[AArch64] Improved lowering for saturating float to int.

[ebevhan]

Summary

Adapted from D54696 by @nikic.

This patch improves the default lowering of saturating
float to int conversions, FP_TO_[SU]INT_SAT, on AArch64.
Since the default FP_TO_INT operations on AArch64 are
already saturating, we can take advantage of this
behavior in the lowering for the saturating operations.

[ebevhan]

Amended comment.

[paulwalker-arm]

Given you are making use of the fact that AArch64 fp_to_int already does the saturation part, I'm wondering if the different-width saturation can be moved from the input to the output? Specially I'm thinking this will result in nicer code as the min/max immediate values will be easier to produce in integer form.

[ebevhan]

In D86078#2233560, @paulwalker-arm wrote:

Given you are making use of the fact that AArch64 fp_to_int already does the saturation part, I'm wondering if the different-width saturation can be moved from the input to the output? Specially I'm thinking this will result in nicer code as the min/max immediate values will be easier to produce in integer form.

Ah, so you mean to emit the select-comparisons as integer comparisons rather than floating point comparisons in the second expansion.

It feels like that would work. @nikic, was there any reason in particular you didn't implement it that way in the original patch or does it sound fine to you?

[nikic]

In D86078#2235475, @ebevhan wrote:

In D86078#2233560, @paulwalker-arm wrote:

Given you are making use of the fact that AArch64 fp_to_int already does the saturation part, I'm wondering if the different-width saturation can be moved from the input to the output? Specially I'm thinking this will result in nicer code as the min/max immediate values will be easier to produce in integer form.

Ah, so you mean to emit the select-comparisons as integer comparisons rather than floating point comparisons in the second expansion.

It feels like that would work. @nikic, was there any reason in particular you didn't implement it that way in the original patch or does it sound fine to you?

Sounds like a good idea to me. Don't think I had a particular reason here beyond "that's what the generic expansion does".

[ebevhan]

Made natively saturating expansions use integer comparisons instead.

[ebevhan]

Rebased.

[ebevhan]

Removed superfluous NaN check and updated tests.

[paulwalker-arm]

Sorry I had hoped to look at this patch properly today but that hasn't worked out. I've got a general comment below as I think it would be nicer to abstract the NativeSaturation into a TLI hook that other targets can implement when useful to them.

I'm also wondering if there's some code reuse opportunities with LowerVectorFP_TO_INT since understandably they're making similar lowering choices. I'll defer that last point until I take a proper look tomorrow.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3026

This seems a bit unnatural to the way lowering is typically done. Can this just return SDValue() and then add a target TLI hook to query the behaviour of the FP convert ISD nodes that expandFP_TO_INT_SAT can call.

[paulwalker-arm]

I'm afraid some of my comments are probably conflicting. I would have experimented a little to understand better how things work, but I'm guessing the patch is based on other work because I couldn't some of the affected functions/nodes.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8069–8074 ↗

(On Diff #290297)

Perhaps I've misread something but with this change it looks like a NaN input to FP_TO_UINT_SAT can result in (unsigned int)MaxFloat rather than the expected zero? because the following ISD::FMINNUM will choose the non-NaN input rather than propagating MinFloat like it did before (because the FMAXNUM has been omitted).

This goes against my previous suggestion but perhaps it will be cleaner to perform all the lowering within LowerFP_TO_INT_SAT as the process will be a uniform:

// This handles native saturation and NaN -> 0 transformations.
A = getNode(FP_TO_UINT // Letting LowerFP_TO_INT handle input promotion, rather than duplicate that handling.
A = getNode(ISD::MIN, A, SAT_HI)
if (isSigned)
  A = getNode(ISD::MAX, A, SAT_LO)
return A

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3029–3032

The DstVT.getScalarSizeInBits().getFixedSize() != SatWidth case feels like something we should catch and transform as early as possible to enable other optimisation opportunities. Perhaps worth a DAGCombine using the same target TLI hook mentioned before.

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

78–88

This test backs up the performance side of what I'm saying in expandFP_TO_INT_SAT. Using the knowledge that the saturation value is exactly representable as a float is not the only thing you care about for AArch64. You also care about "what's the most efficient way to perform the clamping operations".

Assuming (mainly because I haven't yet found documented proof) that a native FP_TO_INT operation on AArch64 implements the NaN->0 requirement, then I'm wondering if there's ever a good reason to perform the clamping at the input stage. Perhaps it's really a question of scalar vs vector with regards to the availability of MIN/MAX instructions.

[ebevhan]

In D86078#2260930, @paulwalker-arm wrote:

I would have experimented a little to understand better how things work, but I'm guessing the patch is based on other work because I couldn't some of the affected functions/nodes.

I forgot to add the parent revision of this to Phab, sorry. It's added now.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8069–8074 ↗

(On Diff #290297)

I suspect you may be right. Your suggested pattern might be cleaner.

Should I just drop the NativeSaturation parameter altogether and only handle the expansion explicitly in Lowering?

Should I add more types to Custom lowering of these nodes on AArch64?

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3029–3032

What sort of combines do you have in mind here?

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

78–88

So perhaps we should just skip the standard expansion for these cases and only expand to the pattern you specified there. It's probably not safe to do it for all cases if we can't guarantee the saturating behavior of other FP_TO_INT operations.

Assuming (mainly because I haven't yet found documented proof) that a native FP_TO_INT operation on AArch64 implements the NaN->0 requirement,

That is interesting, I can't find it either. I simply adapted this from the previous patchset by nikic, andI presumed that that was correct.
Perhaps it's an undocumented behavior.

[ebevhan]

Followup to removing vector expansion in the parent patch.

[ebevhan]

Redid lowering.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8098 ↗

(On Diff #290752)

Please don't abuse the semantics of target-independent opcodes. If the replacement operation is saturating, we should use FP_TO_SINT_SAT. (I assume this doesn't form an infinite loop because the saturation width would be different.)

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8850

Is this change related somhow?

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

78–88

It's documented in the AArch64 reference manual, it's just sort of buried. The conversion is described in FPToFixed(), which calls FPUnpackBase().

[efriedma]

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

173

This should probably just be "fcvtzs v0.2d, v0.2d; sqxtn v0.2s, v0.2d".

[ebevhan]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8098 ↗

(On Diff #290752)

I don't think saturation width is used to determine legality, so I don't think I can emit a _SAT here, unless I've misunderstood how legalization operates.

I think I would be more inclined to simply remove NativeSaturation and do everything in Lower.

If I can't use FP_TO_INT, should there be patterns in AArch64 for selecting FP_TO_INT_SAT nodes in that case?

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8850

I got an issue here with some of the vector emissions since getNode with a BUILD_VECTOR can actually manage to optimize away the BUILD_VECTOR node and we end up getting something else. Then the rest of the code in this function breaks, because it assumes that Op is a BUILD_VECTOR.

Even if I change the patch after this so we don't end up with that pattern any more, I might keep this in because it's a pitfall waiting to happen.

[ebevhan]

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

173

Is sqxtn ever selected without intrinsics? I would assume that a simple minmax and trunc pattern would catch it, but that doesn't happen.

[ebevhan]

Removed NativeSaturation parameter and made all lowering happen in Lower.

We only use fminnum/fmaxnum on vector-same-width saturation, and otherwise we use integer comparisons. This improves some emitted code.

[ebevhan]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3067

Do you think it's still wrong to use FP_TO_INT in these lowerings?

[ebevhan]

Use default expansion for f128 conversions; they aren't native so we can't be sure that they saturate.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8098 ↗

(On Diff #290752)

If you've marked the legality of a node "Custom", the target determines whether it's legal. If the custom lowering hook just returns the input node, that will tell the legalizer that the node is legal.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3067

My concern is that you're making assumptions that doesn't match the specified semantics of FP_TO_SINT. This is confusing, and some code could see this operation and perform some illegal transform on it. (This sort of usage has caused miscompiles in the past.)

int_aarch64_neon_fcvtzs has the right semantics, or you could introduce a new target-specific node, or you could generate another FP_TO_SINT_SAT. I guess I'd slightly prefer a new node.

8850

Oh, hmm, strange that nobody else has hit it. I guess it's fine.

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

173

Not sure off the top of my head, but I wouldn't be surprised if the answer is no. Nobody has spent much time on saturation patterns.

The current patch generates xtn? That isn't saturating, I think?

[ebevhan]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3067

Hm, I agree with what you're saying, so I opted for emitting FP_TO_INT_SAT nodes with DstWidth == SatWidth.

However, while implementing I'm finding that I need to reimplement all of the custom vector lowering for FP_TO_INT for these as well, which seems a bit superfluous.

Would it be wrong to construct an FP_TO_INT node and then just immediately manually call LowerFP_TO_INT?

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

173

xtn doesn't saturate, no... It just seems to truncate.

But... Doesn't this actually mean that it's wrong? This is supposed to saturate to i32, but it's actually converting to i64 and then truncating. That can't be right.

You weren't wrong about assumptions on node behavior, lowering this to FP_TO_INT clearly didn't do the right thing. So this means that vector FP_TO_INT only saturates if the scalar types are the same bit width? I wonder if the same applies to f16.

[efriedma]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3067

Would it be wrong to construct an FP_TO_INT node and then just immediately manually call LowerFP_TO_INT?

I think I'd prefer to just make LowerVectorFP_TO_INT work on both FP_TO_INT and FP_TO_INT_SAT nodes.

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

173

ISD::FP_TO_SINT always has the same semantics as the IR fptosi, regardless of what the actual underlying instructions do.

[ebevhan]

Now only uses FP_TO_INT_SAT nodes for lowering. The nodes are selected in isel.

LowerVectorFP_TO_INT was extended to also handle the _SAT nodes.

[ebevhan]

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

173

Ah, certainly. I really meant FCVTZ, not FP_TO_INT.

[ebevhan]

Fix clang-format warnings.

[efriedma]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3916

(v8i16 (to_int v8f16:$Rn, (i32 64)))? The 64 seems weird.

[ebevhan]

Fixed typos.

[ebevhan]

Ping. The build failures don't seem related to the patch.

[ebevhan]

Rebased.

[uabelho]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3054

We explicitly did

if (DstWidth == SatWidth)
  return Op;

at line 3105 above, so the

DstWidth != SatWidth

comparison should always be true here?

3076

Always false since we already did

if (DstWidth == SatWidth)
  return Op;

at 3105?

llvm/lib/Target/AArch64/AArch64ISelLowering.h

private:
   SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
                         RTLIB::Libcall Call) const;
   SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
 
+  // These are equivalent to FP_TO_[SU]INT if the saturation width matches
+  // the result width, otherwise they require expansion.
+  setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
+  setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
+  setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
+  setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
+
   // Variable arguments.
   setOperationAction(ISD::VASTART, MVT::Other, Custom);
   setOperationAction(ISD::VAARG, MVT::Other, Custom);
   setOperationAction(ISD::VACOPY, MVT::Other, Custom);
   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 
   // Variable-sized objects.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
if (Subtarget->hasNEON()) {
     setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
     setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
     setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
     setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
 
     setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
     setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
+    setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v1i64, Expand);
+    setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v1i64, Expand);
     setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
     setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
     setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
 
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);
 
     // AArch64 doesn't have a direct vector ->f32 conversion instructions for
     // elements smaller than i32, so promote the input to i32 first.
void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
   setOperationAction(ISD::UDIV, VT, Expand);
   setOperationAction(ISD::SDIV, VT, Expand);
   setOperationAction(ISD::UREM, VT, Expand);
   setOperationAction(ISD::SREM, VT, Expand);
   setOperationAction(ISD::FREM, VT, Expand);
 
   setOperationAction(ISD::FP_TO_SINT, VT, Custom);
   setOperationAction(ISD::FP_TO_UINT, VT, Custom);
+  setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
+  setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
 
   if (!VT.isFloatingPoint())
     setOperationAction(ISD::ABS, VT, Legal);
 
   // [SU][MIN|MAX] are available for all NEON types apart from i64.
   if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
     for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
       setOperationAction(Opcode, VT, Legal);

 SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
                                                     SelectionDAG &DAG) const {
   // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
   // Any additional optimization in this function should be recorded
   // in the cost tables.
   EVT InVT = Op.getOperand(0).getValueType();
   EVT VT = Op.getValueType();
   unsigned NumElts = InVT.getVectorNumElements();
+  bool IsSat = Op.getOpcode() == ISD::FP_TO_SINT_SAT ||
+               Op.getOpcode() == ISD::FP_TO_UINT_SAT;
 
   // f16 conversions are promoted to f32 when full fp16 is not supported.
   if (InVT.getVectorElementType() == MVT::f16 &&
       !Subtarget->hasFullFP16()) {
     MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts);
     SDLoc dl(Op);
+    if (IsSat)
+      return DAG.getNode(
+          Op.getOpcode(), dl, Op.getValueType(),
+          DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)),
+          Op.getOperand(1));
+    else
       return DAG.getNode(
           Op.getOpcode(), dl, Op.getValueType(),
           DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
   }
 
   if (VT.getSizeInBits() < InVT.getSizeInBits()) {
     SDLoc dl(Op);
-    SDValue Cv =
-        DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
+    SDValue Cv;
+    if (IsSat)
+      Cv = DAG.getNode(Op.getOpcode(), dl,
+                       InVT.changeVectorElementTypeToInteger(),
+                       Op.getOperand(0), Op.getOperand(1));
+    else
+      Cv = DAG.getNode(Op.getOpcode(), dl,
+                       InVT.changeVectorElementTypeToInteger(),
                        Op.getOperand(0));
     return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
   }
 
   if (VT.getSizeInBits() > InVT.getSizeInBits()) {
     SDLoc dl(Op);
     MVT ExtVT =
         MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
                          VT.getVectorNumElements());
     SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
+    if (IsSat)
+      return DAG.getNode(Op.getOpcode(), dl, VT, Ext, Op.getOperand(1));
+    else
       return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
   }
 
   // Type changing conversions are illegal.
   return Op;
 }
 
 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
                                               SelectionDAG &DAG) const {
if (VT.getSizeInBits() > InVT.getSizeInBits()) {
     EVT CastVT = VT.changeVectorElementTypeToInteger();
     In = DAG.getNode(CastOpc, dl, CastVT, In);
     return DAG.getNode(Op.getOpcode(), dl, VT, In);
   }
 
   return Op;
 }
 
+SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SDValue Src = Op.getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  EVT DstVT = Op.getValueType();
+  unsigned SatWidth = Op.getConstantOperandVal(1);
+  unsigned DstWidth = DstVT.getScalarSizeInBits().getFixedSize();
+  SDLoc dl(Op);
+
+  if (SrcVT.isVector()) {
+    SDValue Vec = LowerVectorFP_TO_INT(Op, DAG);
+    if (Vec != Op)
+      return Vec;
+  }
+
+  // f16 conversions are promoted to f32 when full fp16 is not supported.
+  if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16()) {
+    SDValue Extend = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Src);
+    return DAG.getNode(Op.getOpcode(), dl, DstVT, Extend, Op.getOperand(1));
+  }
+
+  // f128 conversions are not native, so we can't trust that they saturate.
+  // Use the default expansion.
+  if (SrcVT == MVT::f128)
+    return SDValue();
+
+  // The below expansion is mostly lifted from expandFP_TO_INT_SAT with
+  // modifications to take advantage of AArch64's natively saturating conversion
+  // instructions.
+  if (DstWidth == SatWidth)
+    return Op;
+
+  bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
+  APInt MinInt, MaxInt;
+  if (IsSigned) {
+    MinInt = APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth);
+    MaxInt = APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth);
+  } else {
+    MinInt = APInt::getMinValue(SatWidth).zextOrSelf(DstWidth);
+    MaxInt = APInt::getMaxValue(SatWidth).zextOrSelf(DstWidth);
+  }
+
+  SDValue MinIntNode = DAG.getConstant(MinInt, dl, DstVT);
+  SDValue MaxIntNode = DAG.getConstant(MaxInt, dl, DstVT);
+
+  APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT));
+  APFloat MaxFloat(DAG.EVTToAPFloatSemantics(SrcVT));
+
+  APFloat::opStatus MinStatus =
+      MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero);
+  APFloat::opStatus MaxStatus =
+      MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero);
+  bool AreExactFloatBounds = !(MinStatus & APFloat::opStatus::opInexact) &&
+                             !(MaxStatus & APFloat::opStatus::opInexact);
+
+  SDValue MinFloatNode = DAG.getConstantFP(MinFloat, dl, SrcVT);
+  SDValue MaxFloatNode = DAG.getConstantFP(MaxFloat, dl, SrcVT);
+
+  // If the integer bounds are exactly representable as floats and min/max are
+  // legal, emit a min+max+fptoi sequence. Otherwise we have to use a sequence
+  // of comparisons and selects.
+  bool MinMaxLegal = isOperationLegal(ISD::FMINNUM, SrcVT) &&
+                     isOperationLegal(ISD::FMAXNUM, SrcVT);
+
+  // We want the fmin/fmax pattern for vectors since those operations have
+  // vector support and the min/max integer pattern does not.
+  if (DstWidth != SatWidth && SrcVT.isVector() && AreExactFloatBounds &&
+      MinMaxLegal) {
+    SDValue Clamped = Src;
+    // Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
+    Clamped = DAG.getNode(ISD::FMAXNUM, dl, SrcVT, Clamped, MinFloatNode);
+    // Clamp by MaxFloat from above. NaN cannot occur.
+    Clamped = DAG.getNode(ISD::FMINNUM, dl, SrcVT, Clamped, MaxFloatNode);
+    // Convert clamped value to integer.
+    SDValue FpToInt =
+        DAG.getNode(IsSigned ? ISD::FP_TO_SINT_SAT : ISD::FP_TO_UINT_SAT, dl,
+                    DstVT, Clamped, DAG.getConstant(DstWidth, dl, MVT::i32));
+    return FpToInt;
+  }
+
+  // The native fp to int conversions are already saturating, lower to them.
+  SDValue Select =
+      DAG.getNode(IsSigned ? ISD::FP_TO_SINT_SAT : ISD::FP_TO_UINT_SAT, dl,
+                  DstVT, Src, DAG.getConstant(DstWidth, dl, MVT::i32));
+
+  // If the saturation width is the same as the destination width, we don't
+  // need to emit explicit saturation. However, the vector ops only saturate
+  // when the scalar size of the type is the same (e.g. f32 -> i32).
+  if (DstWidth == SatWidth &&
+      (!SrcVT.isVector() ||
+       SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits()))
+    return Select;
+
+  if (IsSigned)
+    Select = DAG.getSelectCC(dl, Select, MinIntNode, MinIntNode, Select,
+                             ISD::CondCode::SETLT);
+  Select =
+      DAG.getSelectCC(dl, Select, MaxIntNode, MaxIntNode, Select,
+                      IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT);
+  return Select;
+}
+
 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
                                             SelectionDAG &DAG) const {
   if (Op.getValueType().isVector())
     return LowerVectorINT_TO_FP(Op, DAG);
 
   bool IsStrict = Op->isStrictFPOpcode();
   SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
 
SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::STRICT_SINT_TO_FP:
   case ISD::STRICT_UINT_TO_FP:
     return LowerINT_TO_FP(Op, DAG);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::STRICT_FP_TO_SINT:
   case ISD::STRICT_FP_TO_UINT:
     return LowerFP_TO_INT(Op, DAG);
+  case ISD::FP_TO_SINT_SAT:
+  case ISD::FP_TO_UINT_SAT:
+    return LowerFP_TO_INT_SAT(Op, DAG);
   case ISD::FSINCOS:
     return LowerFSINCOS(Op, DAG);
   case ISD::FLT_ROUNDS_:
     return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::MUL:
     return LowerMUL(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);

 }
 
 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
                                                  SelectionDAG &DAG) const {
   EVT VT = Op.getValueType();
 
   // Try to build a simple constant vector.
   Op = NormalizeBuildVector(Op, DAG);
+  if (!isa<BuildVectorSDNode>(Op.getNode()))
+    return Op;
   if (VT.isInteger()) {
     // Certain vector constants, used to express things like logical NOT and
     // arithmetic NEG, are passed through unmodified.  This allows special
     // patterns for these operations to match, which will lower these constants
     // to whatever is proven necessary.
     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
     if (BVN->isConstant())
       if (ConstantSDNode *Const = BVN->getConstantSplatNode()) {

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm : FPToIntegerPats<fp_to_uint, fceil,  "FCVTPU">;
 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
 
+multiclass FPToIntegerSatPats<SDNode to_int, string INST> {
+  def : Pat<(i32 (to_int f16:$Rn, (i32 32))),
+            (!cast<Instruction>(INST # UWHr) $Rn)>;
+  def : Pat<(i64 (to_int f16:$Rn, (i32 64))),
+            (!cast<Instruction>(INST # UXHr) $Rn)>;
+  def : Pat<(i32 (to_int f32:$Rn, (i32 32))),
+            (!cast<Instruction>(INST # UWSr) $Rn)>;
+  def : Pat<(i64 (to_int f32:$Rn, (i32 64))),
+            (!cast<Instruction>(INST # UXSr) $Rn)>;
+  def : Pat<(i32 (to_int f64:$Rn, (i32 32))),
+            (!cast<Instruction>(INST # UWDr) $Rn)>;
+  def : Pat<(i64 (to_int f64:$Rn, (i32 64))),
+            (!cast<Instruction>(INST # UXDr) $Rn)>;
+}
+
+defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
+defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
+
 let Predicates = [HasFullFP16] in {
   def : Pat<(i32 (lround f16:$Rn)),
             (!cast<Instruction>(FCVTASUWHr) f16:$Rn)>;
   def : Pat<(i64 (lround f16:$Rn)),
             (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
   def : Pat<(i64 (llround f16:$Rn)),
             (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
 }
def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))),
           (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
                                         int_aarch64_neon_fcvtxn>;
 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
 
+multiclass SIMDTwoVectorFPToIntSatPats<SDNode to_int, string INST> {
+  def : Pat<(v4i16 (to_int v4f16:$Rn, (i32 32))),
+            (!cast<Instruction>(INST # v4f16) $Rn)>;
+  def : Pat<(v8i16 (to_int v8f16:$Rn, (i32 64))),
+            (!cast<Instruction>(INST # v8f16) $Rn)>;
+  def : Pat<(v2i32 (to_int v2f32:$Rn, (i32 32))),
+            (!cast<Instruction>(INST # v2f32) $Rn)>;
+  def : Pat<(v4i32 (to_int v4f32:$Rn, (i32 32))),
+            (!cast<Instruction>(INST # v4f32) $Rn)>;
+  def : Pat<(v2i64 (to_int v2f64:$Rn, (i32 64))),
+            (!cast<Instruction>(INST # v2f64) $Rn)>;
+}
+
+defm : SIMDTwoVectorFPToIntSatPats<fp_to_sint_sat, "FCVTZS">;
+defm : SIMDTwoVectorFPToIntSatPats<fp_to_uint_sat, "FCVTZU">;
+
 def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>;
 def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>;
 def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>;
 def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>;
 def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>;
 
 def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>;
 def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>;

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

 declare  i50 @llvm.fptosi.sat.i50.f32 (float)
 declare  i64 @llvm.fptosi.sat.i64.f32 (float)
 declare i100 @llvm.fptosi.sat.i100.f32(float)
 declare i128 @llvm.fptosi.sat.i128.f32(float)
 
 define i1 @test_signed_i1_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i1_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov s1, #-1.00000000
-; CHECK-NEXT:    fmov s2, wzr
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    cmn w8, #1 // =1
+; CHECK-NEXT:    csinv w8, w8, wzr, ge
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csel w8, wzr, w8, gt
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
     ret i1 %x
 }
 
 define i8 @test_signed_i8_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i8_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1023410176
-; CHECK-NEXT:    mov w9, #1123942400
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov w9, #-128
+; CHECK-NEXT:    cmn w8, #128 // =128
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #127 // =127
+; CHECK-NEXT:    mov w9, #127
+; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
     ret i8 %x
 }
 
 define i13 @test_signed_i13_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i13_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-981467136
-; CHECK-NEXT:    mov w9, #61440
-; CHECK-NEXT:    movk w9, #17791, lsl #16
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov w9, #-4096
+; CHECK-NEXT:    cmn w8, #1, lsl #12 // =4096
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #4095 // =4095
+; CHECK-NEXT:    mov w9, #4095
+; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptosi.sat.i13.f32(float %f)
     ret i13 %x
 }
 
 define i16 @test_signed_i16_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i16_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-956301312
-; CHECK-NEXT:    mov w9, #65024
-; CHECK-NEXT:    movk w9, #18175, lsl #16
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #8, lsl #12 // =32768
+; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    csel w0, w9, w8, ge
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
     ret i16 %x
 }
 
 define i19 @test_signed_i19_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i19_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-931135488
-; CHECK-NEXT:    mov w9, #65472
-; CHECK-NEXT:    movk w9, #18559, lsl #16
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov w9, #-262144
+; CHECK-NEXT:    cmn w8, #64, lsl #12 // =262144
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #64, lsl #12 // =262144
+; CHECK-NEXT:    mov w9, #262143
+; CHECK-NEXT:    csel w0, w9, w8, ge
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f32(float %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-671088640
-; CHECK-NEXT:    mov w11, #1476395007
-; CHECK-NEXT:    fmov s1, w9
 ; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    mov x10, #-562949953421312
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    mov x12, #562949953421311
-; CHECK-NEXT:    csel x8, x10, x8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel x8, x12, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    mov x9, #-562949953421312
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x8, x9, x8, lt
+; CHECK-NEXT:    mov x9, #562949953421311
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x0, x9, x8, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f32(float %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-553648128
-; CHECK-NEXT:    mov w11, #1593835519
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    mov x10, #-9223372036854775808
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    mov x12, #9223372036854775807
-; CHECK-NEXT:    csel x8, x10, x8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel x8, x12, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    fcvtzs x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f32:
 ; CHECK:       // %bb.0:

 declare  i50 @llvm.fptosi.sat.i50.f64 (double)
 declare  i64 @llvm.fptosi.sat.i64.f64 (double)
 declare i100 @llvm.fptosi.sat.i100.f64(double)
 declare i128 @llvm.fptosi.sat.i128.f64(double)
 
 define i1 @test_signed_i1_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i1_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov d1, #-1.00000000
-; CHECK-NEXT:    fmov d2, xzr
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
+; CHECK-NEXT:    cmn w8, #1 // =1
+; CHECK-NEXT:    csinv w8, w8, wzr, ge
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csel w8, wzr, w8, gt
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
     ret i1 %x
 }
 
 define i8 @test_signed_i8_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i8_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4584664420663164928
-; CHECK-NEXT:    mov x9, #211106232532992
-; CHECK-NEXT:    movk x9, #16479, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
+; CHECK-NEXT:    mov w9, #-128
+; CHECK-NEXT:    cmn w8, #128 // =128
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #127 // =127
+; CHECK-NEXT:    mov w9, #127
+; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
     ret i8 %x
 }
 
 define i13 @test_signed_i13_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i13_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4562146422526312448
-; CHECK-NEXT:    mov x9, #279275953455104
-; CHECK-NEXT:    movk x9, #16559, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
+; CHECK-NEXT:    mov w9, #-4096
+; CHECK-NEXT:    cmn w8, #1, lsl #12 // =4096
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #4095 // =4095
+; CHECK-NEXT:    mov w9, #4095
+; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptosi.sat.i13.f64(double %f)
     ret i13 %x
 }
 
 define i16 @test_signed_i16_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i16_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4548635623644200960
-; CHECK-NEXT:    mov x9, #281200098803712
-; CHECK-NEXT:    movk x9, #16607, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
+; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #8, lsl #12 // =32768
+; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    csel w0, w9, w8, ge
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
     ret i16 %x
 }
 
 define i19 @test_signed_i19_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i19_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4535124824762089472
-; CHECK-NEXT:    mov x9, #281440616972288
-; CHECK-NEXT:    movk x9, #16655, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
+; CHECK-NEXT:    mov w9, #-262144
+; CHECK-NEXT:    cmn w8, #64, lsl #12 // =262144
+; CHECK-NEXT:    csel w8, w9, w8, lt
+; CHECK-NEXT:    cmp w8, #64, lsl #12 // =262144
+; CHECK-NEXT:    mov w9, #262143
+; CHECK-NEXT:    csel w0, w9, w8, ge
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f64(double %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w0, d0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4395513236313604096
-; CHECK-NEXT:    mov x9, #-16
-; CHECK-NEXT:    movk x9, #17151, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs x8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    fcvtzs x8, d0
+; CHECK-NEXT:    mov x9, #-562949953421312
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x8, x9, x8, lt
+; CHECK-NEXT:    mov x9, #562949953421311
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x0, x9, x8, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f64(double %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x9, #-4332462841530417152
-; CHECK-NEXT:    mov x11, #4890909195324358655
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    mov x10, #-9223372036854775808
-; CHECK-NEXT:    fcmp d0, d1
-; CHECK-NEXT:    fmov d1, x11
-; CHECK-NEXT:    mov x12, #9223372036854775807
-; CHECK-NEXT:    csel x8, x10, x8, lt
-; CHECK-NEXT:    fcmp d0, d1
-; CHECK-NEXT:    csel x8, x12, x8, gt
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    fcvtzs x0, d0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f64:
 ; CHECK:       // %bb.0:

 declare  i64 @llvm.fptosi.sat.i64.f16 (half)
 declare i100 @llvm.fptosi.sat.i100.f16(half)
 declare i128 @llvm.fptosi.sat.i128.f16(half)
 
 define i1 @test_signed_i1_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i1_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, #-1.00000000
-; CHECK-NEXT:    fmov s2, wzr
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    cmn w8, #1 // =1
+; CHECK-NEXT:    csinv w8, w8, wzr, ge
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csel w8, wzr, w8, gt
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
     ret i1 %x
 }
 
 define i8 @test_signed_i8_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i8_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1023410176
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w9, #1123942400
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w9, s0
+; CHECK-NEXT:    mov w8, #-128
+; CHECK-NEXT:    cmn w9, #128 // =128
+; CHECK-NEXT:    csel w8, w8, w9, lt
+; CHECK-NEXT:    cmp w8, #127 // =127
+; CHECK-NEXT:    mov w9, #127
+; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
     ret i8 %x
 }
 
 define i13 @test_signed_i13_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i13_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-981467136
-; CHECK-NEXT:    mov w9, #61440
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    movk w9, #17791, lsl #16
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w9, s0
+; CHECK-NEXT:    mov w8, #-4096
+; CHECK-NEXT:    cmn w9, #1, lsl #12 // =4096
+; CHECK-NEXT:    csel w8, w8, w9, lt
+; CHECK-NEXT:    cmp w8, #4095 // =4095
+; CHECK-NEXT:    mov w9, #4095
+; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptosi.sat.i13.f16(half %f)
     ret i13 %x
 }
 
 define i16 @test_signed_i16_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i16_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-956301312
-; CHECK-NEXT:    mov w9, #65024
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    movk w9, #18175, lsl #16
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w9, s0
+; CHECK-NEXT:    mov w8, #-32768
+; CHECK-NEXT:    cmn w9, #8, lsl #12 // =32768
+; CHECK-NEXT:    csel w8, w8, w9, lt
+; CHECK-NEXT:    cmp w8, #8, lsl #12 // =32768
+; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    csel w0, w9, w8, ge
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
     ret i16 %x
 }
 
 define i19 @test_signed_i19_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i19_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-931135488
-; CHECK-NEXT:    mov w9, #65472
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    movk w9, #18559, lsl #16
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmaxnm s1, s0, s1
-; CHECK-NEXT:    fmov s2, w9
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w9, s0
+; CHECK-NEXT:    mov w8, #-262144
+; CHECK-NEXT:    cmn w9, #64, lsl #12 // =262144
+; CHECK-NEXT:    csel w8, w8, w9, lt
+; CHECK-NEXT:    cmp w8, #64, lsl #12 // =262144
+; CHECK-NEXT:    mov w9, #262143
+; CHECK-NEXT:    csel w0, w9, w8, ge
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f16(half %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1325400063
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-671088640
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1476395007
-; CHECK-NEXT:    mov x9, #-562949953421312
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    csel x8, x9, x8, lt
+; CHECK-NEXT:    mov x8, #-562949953421312
+; CHECK-NEXT:    fcvtzs x9, s0
+; CHECK-NEXT:    cmp x9, x8
+; CHECK-NEXT:    csel x8, x8, x9, lt
 ; CHECK-NEXT:    mov x9, #562949953421311
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel x8, x9, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x0, x9, x8, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f16(half %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-553648128
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1593835519
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    mov x9, #9223372036854775807
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel x8, x9, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    fcvtzs x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f16:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

 declare <5 x i32> @llvm.fptosi.sat.v5f32.v5i32 (<5 x float>)
 declare <6 x i32> @llvm.fptosi.sat.v6f32.v6i32 (<6 x float>)
 declare <7 x i32> @llvm.fptosi.sat.v7f32.v7i32 (<7 x float>)
 declare <8 x i32> @llvm.fptosi.sat.v8f32.v8i32 (<8 x float>)
 
 define <1 x i32> @test_signed_v1f32_v1i32(<1 x float> %f) {
 ; CHECK-LABEL: test_signed_v1f32_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f32.v1i32(<1 x float> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f32_v2i32(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) {
 ; CHECK-LABEL: test_signed_v3f32_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov s1, v0.s[3]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) {
 ; CHECK-LABEL: test_signed_v4f32_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov s1, v0.s[3]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
 ; CHECK-LABEL: test_signed_v5f32_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s5, w9
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fmov s6, w11
-; CHECK-NEXT:    fcmp s0, s5
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s0, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fcvtzs w13, s1
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s5
-; CHECK-NEXT:    csel w8, w10, w13, lt
-; CHECK-NEXT:    fcmp s1, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w14, s2
-; CHECK-NEXT:    csel w1, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s5
-; CHECK-NEXT:    csel w8, w10, w14, lt
-; CHECK-NEXT:    fcmp s2, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fcvtzs w9, s3
-; CHECK-NEXT:    csel w2, wzr, w8, vs
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w8, w10, w9, lt
-; CHECK-NEXT:    fcmp s3, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w8, w10, w11, lt
-; CHECK-NEXT:    fcmp s4, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    csel w4, wzr, w8, vs
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzs v4.4s, v4.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w4, s4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
 ; CHECK-LABEL: test_signed_v6f32_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s6, w9
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fcmp s5, s6
-; CHECK-NEXT:    fmov s7, w11
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s5, s7
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    fcvtzs w13, s4
-; CHECK-NEXT:    csel w5, wzr, w8, vs
-; CHECK-NEXT:    fcmp s4, s6
-; CHECK-NEXT:    csel w8, w10, w13, lt
-; CHECK-NEXT:    fcmp s4, s7
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvtzs w14, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s6
-; CHECK-NEXT:    csel w13, w10, w14, lt
-; CHECK-NEXT:    fcmp s0, s7
-; CHECK-NEXT:    csel w13, w12, w13, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w0, wzr, w13, vs
-; CHECK-NEXT:    fcmp s1, s6
-; CHECK-NEXT:    csel w9, w10, w9, lt
-; CHECK-NEXT:    fcmp s1, s7
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w11, s2
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s6
-; CHECK-NEXT:    csel w9, w10, w11, lt
-; CHECK-NEXT:    fcmp s2, s7
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    csel w2, wzr, w9, vs
-; CHECK-NEXT:    fcmp s3, s6
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s3, s7
-; CHECK-NEXT:    mov v4.s[1], w5
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzs v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
 ; CHECK-LABEL: test_signed_v7f32_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s7, w9
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fcmp s5, s7
-; CHECK-NEXT:    fmov s16, w11
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s5, s16
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    fcvtzs w13, s4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s4, s7
-; CHECK-NEXT:    csel w11, w10, w13, lt
-; CHECK-NEXT:    fcmp s4, s16
-; CHECK-NEXT:    csel w11, w12, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvtzs w14, s6
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s6, s7
-; CHECK-NEXT:    csel w14, w10, w14, lt
-; CHECK-NEXT:    fcmp s6, s16
-; CHECK-NEXT:    csel w14, w12, w14, gt
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    csel w6, wzr, w14, vs
-; CHECK-NEXT:    fcmp s0, s7
-; CHECK-NEXT:    csel w9, w10, w9, lt
-; CHECK-NEXT:    fcmp s0, s16
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fcvtzs w13, s1
-; CHECK-NEXT:    csel w0, wzr, w9, vs
-; CHECK-NEXT:    fcmp s1, s7
-; CHECK-NEXT:    csel w9, w10, w13, lt
-; CHECK-NEXT:    fcmp s1, s16
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmov s4, w11
-; CHECK-NEXT:    fcvtzs w11, s2
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s7
-; CHECK-NEXT:    csel w9, w10, w11, lt
-; CHECK-NEXT:    fcmp s2, s16
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v4.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    csel w2, wzr, w9, vs
-; CHECK-NEXT:    fcmp s3, s7
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s3, s16
-; CHECK-NEXT:    mov v4.s[2], w6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    mov w5, v4.s[1]
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s6 killed $s6 def $q6
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[2], v6.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzs v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w6, v1.s[2]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
 ; CHECK-LABEL: test_signed_v8f32_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w10, #-822083584
-; CHECK-NEXT:    mov s3, v0.s[1]
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s2, w10
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s5, w11
-; CHECK-NEXT:    fcvtzs w11, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fcvtzs w10, s0
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s0, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    mov s4, v0.s[2]
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    mov s3, v0.s[3]
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v0.s[1], w11
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    fcvtzs w10, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov s4, v1.s[1]
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    mov v0.s[3], w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvtzs w11, s1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s1, s5
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov s3, v1.s[2]
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    mov s4, v1.s[3]
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fcvtzs w11, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov v1.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w8, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v1.s[2], w11
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; Double to signed 32-bit -- Vector size variation
 ;
 
 declare <1 x i32> @llvm.fptosi.sat.v1f64.v1i32 (<1 x double>)
 declare <2 x i32> @llvm.fptosi.sat.v2f64.v2i32 (<2 x double>)
 declare <3 x i32> @llvm.fptosi.sat.v3f64.v3i32 (<3 x double>)
 declare <4 x i32> @llvm.fptosi.sat.v4f64.v4i32 (<4 x double>)
 declare <5 x i32> @llvm.fptosi.sat.v5f64.v5i32 (<5 x double>)
 declare <6 x i32> @llvm.fptosi.sat.v6f64.v6i32 (<6 x double>)
 
 define <1 x i32> @test_signed_v1f64_v1i32(<1 x double> %f) {
 ; CHECK-LABEL: test_signed_v1f64_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f64.v1i32(<1 x double> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f64_v2i32(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4476578029606273024
 ; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) {
 ; CHECK-LABEL: test_signed_v3f64_v3i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d1, d3
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fmaxnm d5, d0, d3
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fminnm d5, d5, d4
-; CHECK-NEXT:    fcvtzs w9, d5
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d1, d2, d3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmaxnm d3, d3, d0
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fminnm d3, d3, d4
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fcvtzs w8, d3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    dup v3.2d, x8
+; CHECK-NEXT:    mov x8, #281474972516352
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    movk x8, #16863, lsl #48
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT:    fmaxnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fminnm v1.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-NEXT:    xtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f64.v3i32(<3 x double> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f64_v4i32(<4 x double> %f) {
 ; CHECK-LABEL: test_signed_v4f64_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4476578029606273024
 ; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    mov d2, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d4, x8
-; CHECK-NEXT:    fmaxnm d5, d2, d4
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d5, d5, d2
-; CHECK-NEXT:    fcvtzs w8, d5
-; CHECK-NEXT:    fmaxnm d5, d0, d4
-; CHECK-NEXT:    fminnm d5, d5, d2
-; CHECK-NEXT:    mov d3, v1.d[1]
-; CHECK-NEXT:    fcvtzs w9, d5
-; CHECK-NEXT:    fmaxnm d5, d1, d4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d4, d3, d4
-; CHECK-NEXT:    fminnm d5, d5, d2
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fminnm d2, d4, d2
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzs w9, d5
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp d3, d3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    dup v2.2d, x8
+; CHECK-NEXT:    dup v3.2d, x9
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v2.2d
+; CHECK-NEXT:    fmaxnm v1.2d, v1.2d, v2.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT:    fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-NEXT:    xtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f64.v4i32(<4 x double> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
 ; CHECK-LABEL: test_signed_v5f64_v5i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov x8, #-4476578029606273024
 ; CHECK-NEXT:    mov x9, #281474972516352
+; CHECK-NEXT:    // kill: def $d3 killed $d3 def $q3
 ; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d5, x8
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d0, d0, d5
-; CHECK-NEXT:    fmov d6, x9
-; CHECK-NEXT:    fmaxnm d7, d1, d5
-; CHECK-NEXT:    fminnm d0, d0, d6
-; CHECK-NEXT:    fmaxnm d16, d2, d5
-; CHECK-NEXT:    fminnm d7, d7, d6
-; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    fmaxnm d17, d3, d5
-; CHECK-NEXT:    fminnm d16, d16, d6
-; CHECK-NEXT:    fcvtzs w9, d7
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d5, d4, d5
-; CHECK-NEXT:    fminnm d17, d17, d6
-; CHECK-NEXT:    fcvtzs w10, d16
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fminnm d5, d5, d6
-; CHECK-NEXT:    fcvtzs w11, d17
-; CHECK-NEXT:    csel w2, wzr, w10, vs
-; CHECK-NEXT:    fcmp d3, d3
-; CHECK-NEXT:    fcvtzs w12, d5
-; CHECK-NEXT:    csel w3, wzr, w11, vs
-; CHECK-NEXT:    fcmp d4, d4
-; CHECK-NEXT:    csel w4, wzr, w12, vs
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    mov v2.d[1], v3.d[0]
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT:    dup v3.2d, x9
+; CHECK-NEXT:    fmaxnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fmaxnm v1.2d, v4.2d, v1.2d
+; CHECK-NEXT:    fminnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT:    fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT:    fcvtzs v2.2d, v2.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-NEXT:    xtn v2.2s, v2.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w3, v2.s[1]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w2, s2
+; CHECK-NEXT:    fmov w4, s1
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f64.v5i32(<5 x double> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f64_v6i32(<6 x double> %f) {
 ; CHECK-LABEL: test_signed_v6f64_v6i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov x8, #-4476578029606273024
 ; CHECK-NEXT:    mov x9, #281474972516352
+; CHECK-NEXT:    // kill: def $d5 killed $d5 def $q5
+; CHECK-NEXT:    // kill: def $d3 killed $d3 def $q3
 ; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d6, x8
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d0, d0, d6
-; CHECK-NEXT:    fmov d7, x9
-; CHECK-NEXT:    fmaxnm d16, d1, d6
-; CHECK-NEXT:    fminnm d0, d0, d7
-; CHECK-NEXT:    fmaxnm d17, d2, d6
-; CHECK-NEXT:    fminnm d16, d16, d7
-; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    fmaxnm d18, d3, d6
-; CHECK-NEXT:    fminnm d17, d17, d7
-; CHECK-NEXT:    fcvtzs w9, d16
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d19, d4, d6
-; CHECK-NEXT:    fminnm d18, d18, d7
-; CHECK-NEXT:    fcvtzs w10, d17
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fmaxnm d6, d5, d6
-; CHECK-NEXT:    fminnm d19, d19, d7
-; CHECK-NEXT:    fcvtzs w11, d18
-; CHECK-NEXT:    csel w2, wzr, w10, vs
-; CHECK-NEXT:    fcmp d3, d3
-; CHECK-NEXT:    fminnm d6, d6, d7
-; CHECK-NEXT:    fcvtzs w12, d19
-; CHECK-NEXT:    csel w3, wzr, w11, vs
-; CHECK-NEXT:    fcmp d4, d4
-; CHECK-NEXT:    fcvtzs w13, d6
-; CHECK-NEXT:    csel w4, wzr, w12, vs
-; CHECK-NEXT:    fcmp d5, d5
-; CHECK-NEXT:    csel w5, wzr, w13, vs
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    mov v2.d[1], v3.d[0]
+; CHECK-NEXT:    mov v4.d[1], v5.d[0]
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    dup v3.2d, x9
+; CHECK-NEXT:    fmaxnm v4.2d, v4.2d, v1.2d
+; CHECK-NEXT:    fmaxnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fminnm v1.2d, v4.2d, v3.2d
+; CHECK-NEXT:    fminnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v2.2d, v2.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v2.2s, v2.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w3, v2.s[1]
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w2, s2
+; CHECK-NEXT:    fmov w4, s1
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f64.v6i32(<6 x double> %f)
     ret <6 x i32> %x
 }
 
 ;
 ; FP128 to signed 32-bit -- Vector size variation
 ;

 declare <5 x i32> @llvm.fptosi.sat.v5f16.v5i32 (<5 x half>)
 declare <6 x i32> @llvm.fptosi.sat.v6f16.v6i32 (<6 x half>)
 declare <7 x i32> @llvm.fptosi.sat.v7f16.v7i32 (<7 x half>)
 declare <8 x i32> @llvm.fptosi.sat.v8f16.v8i32 (<8 x half>)
 
 define <1 x i32> @test_signed_v1f16_v1i32(<1 x half> %f) {
 ; CHECK-LABEL: test_signed_v1f16_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1325400063
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f16.v1i32(<1 x half> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f16_v2i32(<2 x half> %f) {
 ; CHECK-LABEL: test_signed_v2f16_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f16.v2i32(<2 x half> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f16_v3i32(<3 x half> %f) {
 ; CHECK-LABEL: test_signed_v3f16_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f16.v3i32(<3 x half> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f16_v4i32(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) {
 ; CHECK-LABEL: test_signed_v5f16_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fcvtzs w12, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w12, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w1, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w2, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w12, s0
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w12, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w4, wzr, w8, vs
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) {
 ; CHECK-LABEL: test_signed_v6f16_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov h2, v1.h[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w5, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w12, s1
-; CHECK-NEXT:    csel w0, wzr, w10, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    csel w10, w9, w12, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w13, s2
-; CHECK-NEXT:    csel w1, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    csel w10, w9, w13, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w2, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    mov v1.s[1], w5
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) {
 ; CHECK-LABEL: test_signed_v7f16_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov w10, #-822083584
-; CHECK-NEXT:    mov h4, v3.h[1]
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s2, w10
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s4, h3
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    mov h3, v3.h[2]
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvtzs w12, s3
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w12, w8, w12, lt
-; CHECK-NEXT:    fcmp s3, s1
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    csel w12, w9, w12, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fcvtzs w13, s4
-; CHECK-NEXT:    csel w6, wzr, w12, vs
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    csel w12, w8, w13, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    csel w12, w9, w12, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvtzs w13, s3
-; CHECK-NEXT:    csel w0, wzr, w12, vs
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    csel w12, w8, w13, lt
-; CHECK-NEXT:    fcmp s3, s1
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    csel w12, w9, w12, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fmov s3, w11
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w1, wzr, w12, vs
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v3.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s0
-; CHECK-NEXT:    csel w2, wzr, w11, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w8, w10, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    mov v3.s[2], w6
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    mov w5, v3.s[1]
-; CHECK-NEXT:    fmov w4, s3
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w6, v0.s[2]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) {
 ; CHECK-LABEL: test_signed_v8f16_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w10, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s2, w11
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    ext v6.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fmov s0, w11
-; CHECK-NEXT:    fcvtzs w11, s5
-; CHECK-NEXT:    fcmp s5, s3
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s5, s2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h4, v6.h[1]
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    mov v0.s[2], w11
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    fcvt s1, h6
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v0.s[3], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov h4, v6.h[2]
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fmov s1, w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    mov h5, v6.h[3]
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v1.s[1], w11
-; CHECK-NEXT:    fcvtzs w11, s5
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s5, s3
-; CHECK-NEXT:    csel w8, w8, w11, lt
-; CHECK-NEXT:    fcmp s5, s2
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v1.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; 2-Vector float to signed integer -- result size variation
 ;
 
 declare <2 x   i1> @llvm.fptosi.sat.v2f32.v2i1  (<2 x float>)
 declare <2 x   i8> @llvm.fptosi.sat.v2f32.v2i8  (<2 x float>)
 declare <2 x  i13> @llvm.fptosi.sat.v2f32.v2i13 (<2 x float>)
 declare <2 x  i16> @llvm.fptosi.sat.v2f32.v2i16 (<2 x float>)
 declare <2 x  i19> @llvm.fptosi.sat.v2f32.v2i19 (<2 x float>)
 declare <2 x  i50> @llvm.fptosi.sat.v2f32.v2i50 (<2 x float>)
 declare <2 x  i64> @llvm.fptosi.sat.v2f32.v2i64 (<2 x float>)
 declare <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float>)
 declare <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float>)
 
 define <2 x i1> @test_signed_v2f32_v2i1(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s2, #-1.00000000
-; CHECK-NEXT:    fmov s3, wzr
-; CHECK-NEXT:    fmaxnm s4, s1, s2
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmaxnm s1, s0, s2
-; CHECK-NEXT:    fminnm s2, s4, s3
-; CHECK-NEXT:    fminnm s1, s1, s3
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmov v1.2s, #-1.00000000
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    movi d1, #0000000000000000
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i1> @llvm.fptosi.sat.v2f32.v2i1(<2 x float> %f)
     ret <2 x i1> %x
 }
 
 define <2 x i8> @test_signed_v2f32_v2i8(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1023410176
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w9, #1123942400
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fmaxnm s3, s1, s2
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmaxnm s1, s0, s2
-; CHECK-NEXT:    fminnm s2, s3, s4
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    movi v1.2s, #195, lsl #24
+; CHECK-NEXT:    mov w8, #1123942400
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i8> @llvm.fptosi.sat.v2f32.v2i8(<2 x float> %f)
     ret <2 x i8> %x
 }
 
 define <2 x i13> @test_signed_v2f32_v2i13(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i13:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-981467136
 ; CHECK-NEXT:    mov w9, #61440
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    movk w9, #17791, lsl #16
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fmaxnm s3, s1, s2
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmaxnm s1, s0, s2
-; CHECK-NEXT:    fminnm s2, s3, s4
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w9
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i13> @llvm.fptosi.sat.v2f32.v2i13(<2 x float> %f)
     ret <2 x i13> %x
 }
 
 define <2 x i16> @test_signed_v2f32_v2i16(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-956301312
-; CHECK-NEXT:    mov w9, #65024
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    movk w9, #18175, lsl #16
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fmaxnm s3, s1, s2
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmaxnm s1, s0, s2
-; CHECK-NEXT:    fminnm s2, s3, s4
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    mov w8, #65024
+; CHECK-NEXT:    movi v1.2s, #199, lsl #24
+; CHECK-NEXT:    movk w8, #18175, lsl #16
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i16> @llvm.fptosi.sat.v2f32.v2i16(<2 x float> %f)
     ret <2 x i16> %x
 }
 
 define <2 x i19> @test_signed_v2f32_v2i19(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i19:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-931135488
 ; CHECK-NEXT:    mov w9, #65472
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    movk w9, #18559, lsl #16
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fmaxnm s3, s1, s2
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmaxnm s1, s0, s2
-; CHECK-NEXT:    fminnm s2, s3, s4
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w9
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptosi.sat.v2f32.v2i19(<2 x float> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_signed_v2f32_v2i32_duplicate(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f32_v2i50(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i50:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-671088640
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1476395007
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov x9, #-562949953421312
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs x10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov x11, #562949953421311
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x8, xzr, x8, vs
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov v0.d[1], x10
+; CHECK-NEXT:    mov x8, #-4395513236313604096
+; CHECK-NEXT:    mov x9, #-16
+; CHECK-NEXT:    fcvtl v0.2d, v0.2s
+; CHECK-NEXT:    movk x9, #17151, lsl #48
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptosi.sat.v2f32.v2i50(<2 x float> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_signed_v2f32_v2i64(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-553648128
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1593835519
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs x10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov x11, #9223372036854775807
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x8, xzr, x8, vs
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov v0.d[1], x10
+; CHECK-NEXT:    fcvtl v0.2d, v0.2s
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptosi.sat.v2f32.v2i64(<2 x float> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_signed_v2f32_v2i100(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i100:
 ; CHECK:       // %bb.0:

 declare <2 x  i50> @llvm.fptosi.sat.v2f64.v2i50 (<2 x double>)
 declare <2 x  i64> @llvm.fptosi.sat.v2f64.v2i64 (<2 x double>)
 declare <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double>)
 declare <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double>)
 
 define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    fmov d2, #-1.00000000
-; CHECK-NEXT:    fmov d3, xzr
-; CHECK-NEXT:    fmaxnm d4, d1, d2
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d4, d3
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmov v1.2d, #-1.00000000
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i1> @llvm.fptosi.sat.v2f64.v2i1(<2 x double> %f)
     ret <2 x i1> %x
 }
 
 define <2 x i8> @test_signed_v2f64_v2i8(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4584664420663164928
 ; CHECK-NEXT:    mov x9, #211106232532992
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16479, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i8> @llvm.fptosi.sat.v2f64.v2i8(<2 x double> %f)
     ret <2 x i8> %x
 }
 
 define <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i13:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4562146422526312448
 ; CHECK-NEXT:    mov x9, #279275953455104
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16559, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i13> @llvm.fptosi.sat.v2f64.v2i13(<2 x double> %f)
     ret <2 x i13> %x
 }
 
 define <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4548635623644200960
 ; CHECK-NEXT:    mov x9, #281200098803712
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16607, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i16> @llvm.fptosi.sat.v2f64.v2i16(<2 x double> %f)
     ret <2 x i16> %x
 }
 
 define <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i19:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4535124824762089472
 ; CHECK-NEXT:    mov x9, #281440616972288
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16655, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptosi.sat.v2f64.v2i19(<2 x double> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i32_duplicate:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4476578029606273024
 ; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i50:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4395513236313604096
 ; CHECK-NEXT:    mov x9, #-16
-; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    movk x9, #17151, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs x8, d2
-; CHECK-NEXT:    fcvtzs x9, d1
-; CHECK-NEXT:    csel x8, xzr, x8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel x9, xzr, x9, vs
-; CHECK-NEXT:    fmov d0, x9
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x9
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4332462841530417152
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov x10, #4890909195324358655
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fmov d3, x10
-; CHECK-NEXT:    fcvtzs x10, d1
-; CHECK-NEXT:    fcmp d1, d2
-; CHECK-NEXT:    mov x11, #9223372036854775807
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp d1, d3
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcmp d0, d2
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp d0, d3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel x8, xzr, x8, vs
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov v0.d[1], x10
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i100:
 ; CHECK:       // %bb.0:

 declare <4 x  i50> @llvm.fptosi.sat.v4f16.v4i50 (<4 x half>)
 declare <4 x  i64> @llvm.fptosi.sat.v4f16.v4i64 (<4 x half>)
 declare <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half>)
 declare <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half>)
 
 define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov s2, #-1.00000000
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    fmov s3, wzr
-; CHECK-NEXT:    fmaxnm s5, s4, s2
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fminnm s5, s5, s3
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s6, h0
-; CHECK-NEXT:    fmaxnm s0, s1, s2
-; CHECK-NEXT:    fminnm s0, s0, s3
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    fmaxnm s0, s5, s2
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fmaxnm s1, s6, s2
-; CHECK-NEXT:    fminnm s2, s0, s3
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fminnm s1, s1, s3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.h[1], w9
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, vs
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fmov v1.4s, #-1.00000000
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i1> @llvm.fptosi.sat.v4f16.v4i1(<4 x half> %f)
     ret <4 x i1> %x
 }
 
 define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1023410176
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov w9, #1123942400
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fmaxnm s5, s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fminnm s5, s5, s4
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s6, h0
-; CHECK-NEXT:    fmaxnm s0, s1, s3
-; CHECK-NEXT:    fminnm s0, s0, s4
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    fmaxnm s0, s5, s3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmaxnm s1, s6, s3
-; CHECK-NEXT:    fminnm s3, s0, s4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.h[1], w9
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, vs
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.4s, #195, lsl #24
+; CHECK-NEXT:    mov w8, #1123942400
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i8> @llvm.fptosi.sat.v4f16.v4i8(<4 x half> %f)
     ret <4 x i8> %x
 }
 
 define <4 x i13> @test_signed_v4f16_v4i13(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i13:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-981467136
 ; CHECK-NEXT:    mov w9, #61440
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NEXT:    movk w9, #17791, lsl #16
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fmaxnm s5, s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fminnm s5, s5, s4
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s6, h0
-; CHECK-NEXT:    fmaxnm s0, s1, s3
-; CHECK-NEXT:    fminnm s0, s0, s4
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    fmaxnm s0, s5, s3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmaxnm s1, s6, s3
-; CHECK-NEXT:    fminnm s3, s0, s4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.h[1], w9
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, vs
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w9
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i13> @llvm.fptosi.sat.v4f16.v4i13(<4 x half> %f)
     ret <4 x i13> %x
 }
 
 define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-956301312
-; CHECK-NEXT:    mov w9, #65024
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    movk w9, #18175, lsl #16
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fmaxnm s5, s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fminnm s5, s5, s4
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s6, h0
-; CHECK-NEXT:    fmaxnm s0, s1, s3
-; CHECK-NEXT:    fminnm s0, s0, s4
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    fmaxnm s0, s5, s3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmaxnm s1, s6, s3
-; CHECK-NEXT:    fminnm s3, s0, s4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.h[1], w9
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, vs
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    mov w8, #65024
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.4s, #199, lsl #24
+; CHECK-NEXT:    movk w8, #18175, lsl #16
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i16> @llvm.fptosi.sat.v4f16.v4i16(<4 x half> %f)
     ret <4 x i16> %x
 }
 
 define <4 x i19> @test_signed_v4f16_v4i19(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i19:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-931135488
 ; CHECK-NEXT:    mov w9, #65472
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NEXT:    movk w9, #18559, lsl #16
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fmaxnm s5, s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fminnm s5, s5, s4
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s6, h0
-; CHECK-NEXT:    fmaxnm s0, s1, s3
-; CHECK-NEXT:    fminnm s0, s0, s4
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    fmaxnm s0, s5, s3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmaxnm s1, s6, s3
-; CHECK-NEXT:    fminnm s3, s0, s4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fminnm s1, s1, s4
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.s[1], w9
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w9
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i19> @llvm.fptosi.sat.v4f16.v4i19(<4 x half> %f)
     ret <4 x i19> %x
 }
 
 define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i50:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-671088640
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov w10, #1476395007
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov x9, #-562949953421312
-; CHECK-NEXT:    fcvtzs x12, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    mov x11, #562949953421311
-; CHECK-NEXT:    csel x8, x9, x12, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s1, s1
+; CHECK-NEXT:    mov x8, #-562949953421312
+; CHECK-NEXT:    fcvtzs x10, s1
 ; CHECK-NEXT:    mov h1, v0.h[1]
+; CHECK-NEXT:    cmp x10, x8
+; CHECK-NEXT:    mov x9, #562949953421311
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs x10, s1
-; CHECK-NEXT:    csel x0, xzr, x8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel x8, x9, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s1, s1
+; CHECK-NEXT:    csel x10, x8, x10, lt
+; CHECK-NEXT:    fcvtzs x11, s1
+; CHECK-NEXT:    cmp x10, x9
 ; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    csel x0, x9, x10, gt
+; CHECK-NEXT:    cmp x11, x8
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs x10, s1
-; CHECK-NEXT:    csel x1, xzr, x8, vs
-; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    csel x10, x8, x11, lt
+; CHECK-NEXT:    fcvtzs x12, s1
+; CHECK-NEXT:    cmp x10, x9
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    csel x8, x9, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
+; CHECK-NEXT:    csel x1, x9, x10, gt
+; CHECK-NEXT:    cmp x12, x8
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs x12, s0
-; CHECK-NEXT:    csel x2, xzr, x8, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel x8, x9, x12, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x3, xzr, x8, vs
+; CHECK-NEXT:    csel x10, x8, x12, lt
+; CHECK-NEXT:    fcvtzs x13, s0
+; CHECK-NEXT:    cmp x10, x9
+; CHECK-NEXT:    csel x2, x9, x10, gt
+; CHECK-NEXT:    cmp x13, x8
+; CHECK-NEXT:    csel x8, x8, x13, lt
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x3, x9, x8, gt
 ; CHECK-NEXT:    ret
     %x = call <4 x i50> @llvm.fptosi.sat.v4f16.v4i50(<4 x half> %f)
     ret <4 x i50> %x
 }
 
 define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-553648128
-; CHECK-NEXT:    mov w10, #1593835519
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fmov s4, w10
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
+; CHECK-NEXT:    fcvtzs x8, s1
+; CHECK-NEXT:    fcvt s1, h2
+; CHECK-NEXT:    fmov d2, x8
 ; CHECK-NEXT:    fcvtzs x8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov x11, #9223372036854775807
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs x10, s2
-; CHECK-NEXT:    csel x8, xzr, x8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp s2, s4
+; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcvtzs x12, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h0, v0.h[2]
-; CHECK-NEXT:    csel x12, x9, x12, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s5, h0
-; CHECK-NEXT:    csel x12, x11, x12, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmov d0, x10
-; CHECK-NEXT:    fcvtzs x10, s5
-; CHECK-NEXT:    csel x12, xzr, x12, vs
-; CHECK-NEXT:    fcmp s5, s3
-; CHECK-NEXT:    csel x9, x9, x10, lt
-; CHECK-NEXT:    fcmp s5, s4
-; CHECK-NEXT:    csel x9, x11, x9, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    csel x9, xzr, x9, vs
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    mov v0.d[1], x8
-; CHECK-NEXT:    mov v1.d[1], x12
+; CHECK-NEXT:    mov v2.d[1], x8
+; CHECK-NEXT:    fcvtzs x8, s1
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fcvtzs x8, s0
+; CHECK-NEXT:    mov v1.d[1], x8
+; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
     ret <4 x i64> %x
 }
 
 define <4 x i100> @test_signed_v4f16_v4i100(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i100:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll

 declare  i50 @llvm.fptoui.sat.i50.f32 (float)
 declare  i64 @llvm.fptoui.sat.i64.f32 (float)
 declare i100 @llvm.fptoui.sat.i100.f32(float)
 declare i128 @llvm.fptoui.sat.i128.f32(float)
 
 define i1 @test_unsigned_i1_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i1_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, #1.00000000
-; CHECK-NEXT:    fminnm s0, s0, s1
 ; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    csinc w8, w8, wzr, ls
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptoui.sat.i1.f32(float %f)
     ret i1 %x
 }
 
 define i8 @test_unsigned_i8_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i8_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    mov w8, #1132396544
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #255 // =255
+; CHECK-NEXT:    mov w9, #255
+; CHECK-NEXT:    csel w0, w9, w8, hi
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptoui.sat.i8.f32(float %f)
     ret i8 %x
 }
 
 define i13 @test_unsigned_i13_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i13_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #63488
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    movk w8, #17919, lsl #16
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #2, lsl #12 // =8192
+; CHECK-NEXT:    mov w9, #8191
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptoui.sat.i13.f32(float %f)
     ret i13 %x
 }
 
 define i16 @test_unsigned_i16_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i16_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #65280
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    movk w8, #18303, lsl #16
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #16, lsl #12 // =65536
+; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptoui.sat.i16.f32(float %f)
     ret i16 %x
 }
 
 define i19 @test_unsigned_i19_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i19_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #65504
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    movk w8, #18687, lsl #16
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
+; CHECK-NEXT:    mov w9, #524287
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptoui.sat.i19.f32(float %f)
     ret i19 %x
 }
 
 define i32 @test_unsigned_i32_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i32_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptoui.sat.i32.f32(float %f)
     ret i32 %x
 }
 
 define i50 @test_unsigned_i50_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i50_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1484783615
 ; CHECK-NEXT:    fcvtzu x8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s0, s1
 ; CHECK-NEXT:    mov x9, #1125899906842623
-; CHECK-NEXT:    csel x0, x9, x8, gt
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x0, x9, x8, hi
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptoui.sat.i50.f32(float %f)
     ret i50 %x
 }
 
 define i64 @test_unsigned_i64_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i64_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1602224127
-; CHECK-NEXT:    fcvtzu x8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv x0, x8, xzr, le
+; CHECK-NEXT:    fcvtzu x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptoui.sat.i64.f32(float %f)
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f32:
 ; CHECK:       // %bb.0:

 declare  i50 @llvm.fptoui.sat.i50.f64 (double)
 declare  i64 @llvm.fptoui.sat.i64.f64 (double)
 declare i100 @llvm.fptoui.sat.i100.f64(double)
 declare i128 @llvm.fptoui.sat.i128.f64(double)
 
 define i1 @test_unsigned_i1_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i1_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, #1.00000000
-; CHECK-NEXT:    fminnm d0, d0, d1
 ; CHECK-NEXT:    fcvtzu w8, d0
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    csinc w8, w8, wzr, ls
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptoui.sat.i1.f64(double %f)
     ret i1 %x
 }
 
 define i8 @test_unsigned_i8_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i8_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #246290604621824
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #16495, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w8, d0
+; CHECK-NEXT:    cmp w8, #255 // =255
+; CHECK-NEXT:    mov w9, #255
+; CHECK-NEXT:    csel w0, w9, w8, hi
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptoui.sat.i8.f64(double %f)
     ret i8 %x
 }
 
 define i13 @test_unsigned_i13_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i13_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #280375465082880
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #16575, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w8, d0
+; CHECK-NEXT:    cmp w8, #2, lsl #12 // =8192
+; CHECK-NEXT:    mov w9, #8191
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptoui.sat.i13.f64(double %f)
     ret i13 %x
 }
 
 define i16 @test_unsigned_i16_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i16_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281337537757184
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #16623, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w8, d0
+; CHECK-NEXT:    cmp w8, #16, lsl #12 // =65536
+; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptoui.sat.i16.f64(double %f)
     ret i16 %x
 }
 
 define i19 @test_unsigned_i19_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i19_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281457796841472
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #16671, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w8, d0
+; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
+; CHECK-NEXT:    mov w9, #524287
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptoui.sat.i19.f64(double %f)
     ret i19 %x
 }
 
 define i32 @test_unsigned_i32_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i32_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
 ; CHECK-NEXT:    fcvtzu w0, d0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptoui.sat.i32.f64(double %f)
     ret i32 %x
 }
 
 define i50 @test_unsigned_i50_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i50_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-8
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #17167, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
-; CHECK-NEXT:    fcvtzu x0, d0
+; CHECK-NEXT:    fcvtzu x8, d0
+; CHECK-NEXT:    mov x9, #1125899906842623
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x0, x9, x8, hi
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptoui.sat.i50.f64(double %f)
     ret i50 %x
 }
 
 define i64 @test_unsigned_i64_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i64_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x9, #4895412794951729151
-; CHECK-NEXT:    fcvtzu x8, d0
-; CHECK-NEXT:    fcmp d0, #0.0
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp d0, d1
-; CHECK-NEXT:    csinv x0, x8, xzr, le
+; CHECK-NEXT:    fcvtzu x0, d0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f64:
 ; CHECK:       // %bb.0:

 declare  i64 @llvm.fptoui.sat.i64.f16 (half)
 declare i100 @llvm.fptoui.sat.i100.f16(half)
 declare i128 @llvm.fptoui.sat.i128.f16(half)
 
 define i1 @test_unsigned_i1_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i1_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, #1.00000000
-; CHECK-NEXT:    fminnm s0, s0, s1
 ; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    csinc w8, w8, wzr, ls
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptoui.sat.i1.f16(half %f)
     ret i1 %x
 }
 
 define i8 @test_unsigned_i8_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i8_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    mov w8, #1132396544
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #255 // =255
+; CHECK-NEXT:    mov w9, #255
+; CHECK-NEXT:    csel w0, w9, w8, hi
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptoui.sat.i8.f16(half %f)
     ret i8 %x
 }
 
 define i13 @test_unsigned_i13_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i13_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #63488
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    movk w8, #17919, lsl #16
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #2, lsl #12 // =8192
+; CHECK-NEXT:    mov w9, #8191
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptoui.sat.i13.f16(half %f)
     ret i13 %x
 }
 
 define i16 @test_unsigned_i16_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i16_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #65280
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    movk w8, #18303, lsl #16
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #16, lsl #12 // =65536
+; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptoui.sat.i16.f16(half %f)
     ret i16 %x
 }
 
 define i19 @test_unsigned_i19_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i19_f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #65504
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    movk w8, #18687, lsl #16
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fminnm s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    cmp w8, #128, lsl #12 // =524288
+; CHECK-NEXT:    mov w9, #524287
+; CHECK-NEXT:    csel w0, w9, w8, hs
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptoui.sat.i19.f16(half %f)
     ret i19 %x
 }
 
 define i32 @test_unsigned_i32_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i32_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptoui.sat.i32.f16(half %f)
     ret i32 %x
 }
 
 define i50 @test_unsigned_i50_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i50_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1484783615
-; CHECK-NEXT:    fcvtzu x9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel x8, xzr, x9, lt
-; CHECK-NEXT:    fcmp s0, s1
+; CHECK-NEXT:    fcvtzu x8, s0
 ; CHECK-NEXT:    mov x9, #1125899906842623
-; CHECK-NEXT:    csel x0, x9, x8, gt
+; CHECK-NEXT:    cmp x8, x9
+; CHECK-NEXT:    csel x0, x9, x8, hi
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptoui.sat.i50.f16(half %f)
     ret i50 %x
 }
 
 define i64 @test_unsigned_i64_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i64_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1602224127
-; CHECK-NEXT:    fcvtzu x9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel x8, xzr, x9, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv x0, x8, xzr, le
+; CHECK-NEXT:    fcvtzu x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f16:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

 declare <5 x i32> @llvm.fptoui.sat.v5f32.v5i32 (<5 x float>)
 declare <6 x i32> @llvm.fptoui.sat.v6f32.v6i32 (<6 x float>)
 declare <7 x i32> @llvm.fptoui.sat.v7f32.v7i32 (<7 x float>)
 declare <8 x i32> @llvm.fptoui.sat.v8f32.v8i32 (<8 x float>)
 
 define <1 x i32> @test_unsigned_v1f32_v1i32(<1 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v1f32_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f32.v1i32(<1 x float> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v3f32_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov s1, v0.s[3]
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v4f32_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov s1, v0.s[3]
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v5f32_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s5, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s0, s5
-; CHECK-NEXT:    fcvtzu w10, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w10, lt
-; CHECK-NEXT:    fcmp s1, s5
-; CHECK-NEXT:    fcvtzu w11, s2
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w11, lt
-; CHECK-NEXT:    fcmp s2, s5
-; CHECK-NEXT:    fcvtzu w12, s3
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    fcvtzu w9, s4
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csinv w4, w8, wzr, le
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzu v4.4s, v4.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w4, s4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v6f32_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s5
-; CHECK-NEXT:    fcmp s5, #0.0
-; CHECK-NEXT:    fmov s6, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s5, s6
-; CHECK-NEXT:    fcvtzu w10, s4
-; CHECK-NEXT:    csinv w5, w8, wzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel w8, wzr, w10, lt
-; CHECK-NEXT:    fcmp s4, s6
-; CHECK-NEXT:    fcvtzu w11, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    csel w8, wzr, w11, lt
-; CHECK-NEXT:    fcmp s0, s6
-; CHECK-NEXT:    fcvtzu w12, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s1, s6
-; CHECK-NEXT:    fcvtzu w13, s2
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w13, lt
-; CHECK-NEXT:    fcmp s2, s6
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v4.s[1], w5
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s6
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzu v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v7f32_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s5
-; CHECK-NEXT:    fcmp s5, #0.0
-; CHECK-NEXT:    fmov s7, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s5, s7
-; CHECK-NEXT:    fcvtzu w10, s4
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel w10, wzr, w10, lt
-; CHECK-NEXT:    fcmp s4, s7
-; CHECK-NEXT:    fcvtzu w11, s6
-; CHECK-NEXT:    csinv w10, w10, wzr, le
-; CHECK-NEXT:    fcmp s6, #0.0
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    csel w10, wzr, w11, lt
-; CHECK-NEXT:    fcmp s6, s7
-; CHECK-NEXT:    fcvtzu w12, s0
-; CHECK-NEXT:    csinv w6, w10, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    mov v4.s[1], w8
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s0, s7
-; CHECK-NEXT:    fcvtzu w13, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w13, lt
-; CHECK-NEXT:    fcmp s1, s7
-; CHECK-NEXT:    fcvtzu w14, s2
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w14, lt
-; CHECK-NEXT:    fcmp s2, s7
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v4.s[2], w6
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s7
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    mov w5, v4.s[1]
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s6 killed $s6 def $q6
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[2], v6.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzu v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w6, v1.s[2]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v8f32_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov s2, v0.s[3]
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov s3, v1.s[1]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    mov s2, v1.s[2]
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov s3, v1.s[3]
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov v1.s[1], w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; Double to unsigned 32-bit -- Vector size variation
 ;
 
 declare <1 x i32> @llvm.fptoui.sat.v1f64.v1i32 (<1 x double>)
 declare <2 x i32> @llvm.fptoui.sat.v2f64.v2i32 (<2 x double>)
 declare <3 x i32> @llvm.fptoui.sat.v3f64.v3i32 (<3 x double>)
 declare <4 x i32> @llvm.fptoui.sat.v4f64.v4i32 (<4 x double>)
 declare <5 x i32> @llvm.fptoui.sat.v5f64.v5i32 (<5 x double>)
 declare <6 x i32> @llvm.fptoui.sat.v6f64.v6i32 (<6 x double>)
 
 define <1 x i32> @test_unsigned_v1f64_v1i32(<1 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v1f64_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
 ; CHECK-NEXT:    fcvtzu w8, d0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f64.v1i32(<1 x double> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f64_v2i32(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v3f64_v3i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d3, xzr
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    movi v3.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d3
-; CHECK-NEXT:    fmov d4, x8
-; CHECK-NEXT:    fmaxnm d1, d1, d3
-; CHECK-NEXT:    fmaxnm d2, d2, d3
-; CHECK-NEXT:    fmaxnm d3, d3, d0
-; CHECK-NEXT:    fminnm d0, d0, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d2, d2, d4
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    fminnm d3, d3, d4
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, d2
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, d3
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT:    fmaxnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fminnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    fcvtzu v1.2d, v2.2d
+; CHECK-NEXT:    xtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f64_v4i32(<4 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v4f64_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d2, xzr
+; CHECK-NEXT:    movi v2.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    mov d3, v0.d[1]
-; CHECK-NEXT:    mov d4, v1.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d2
-; CHECK-NEXT:    fmaxnm d3, d3, d2
-; CHECK-NEXT:    fmaxnm d1, d1, d2
-; CHECK-NEXT:    fmaxnm d2, d4, d2
-; CHECK-NEXT:    fmov d4, x8
-; CHECK-NEXT:    fminnm d0, d0, d4
-; CHECK-NEXT:    fminnm d3, d3, d4
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d3
-; CHECK-NEXT:    fminnm d2, d2, d4
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, d2
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v2.2d
+; CHECK-NEXT:    dup v3.2d, x8
+; CHECK-NEXT:    fmaxnm v1.2d, v1.2d, v2.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT:    fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    fcvtzu v1.2d, v1.2d
+; CHECK-NEXT:    xtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v5f64_v5i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d5, xzr
+; CHECK-NEXT:    // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    movi v5.2d, #0000000000000000
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
 ; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d5
-; CHECK-NEXT:    fmov d6, x8
-; CHECK-NEXT:    fmaxnm d1, d1, d5
-; CHECK-NEXT:    fmaxnm d2, d2, d5
-; CHECK-NEXT:    fmaxnm d3, d3, d5
-; CHECK-NEXT:    fmaxnm d4, d4, d5
-; CHECK-NEXT:    fminnm d0, d0, d6
-; CHECK-NEXT:    fminnm d1, d1, d6
-; CHECK-NEXT:    fminnm d2, d2, d6
-; CHECK-NEXT:    fminnm d3, d3, d6
-; CHECK-NEXT:    fminnm d4, d4, d6
-; CHECK-NEXT:    fcvtzu w0, d0
-; CHECK-NEXT:    fcvtzu w1, d1
-; CHECK-NEXT:    fcvtzu w2, d2
-; CHECK-NEXT:    fcvtzu w3, d3
-; CHECK-NEXT:    fcvtzu w4, d4
+; CHECK-NEXT:    mov v2.d[1], v3.d[0]
+; CHECK-NEXT:    // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v3.2d, v4.2d, v5.2d
+; CHECK-NEXT:    fmaxnm v2.2d, v2.2d, v5.2d
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v5.2d
+; CHECK-NEXT:    fminnm v3.2d, v3.2d, v1.2d
+; CHECK-NEXT:    fminnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v1.2d, v3.2d
+; CHECK-NEXT:    fcvtzu v2.2d, v2.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v2.2s, v2.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w3, v2.s[1]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w2, s2
+; CHECK-NEXT:    fmov w4, s1
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f64.v5i32(<5 x double> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f64_v6i32(<6 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v6f64_v6i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d6, xzr
+; CHECK-NEXT:    // kill: def $d5 killed $d5 def $q5
+; CHECK-NEXT:    // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    movi v6.2d, #0000000000000000
+; CHECK-NEXT:    mov v0.d[1], v1.d[0]
 ; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d6
-; CHECK-NEXT:    fmov d7, x8
-; CHECK-NEXT:    fmaxnm d1, d1, d6
-; CHECK-NEXT:    fmaxnm d2, d2, d6
-; CHECK-NEXT:    fmaxnm d3, d3, d6
-; CHECK-NEXT:    fmaxnm d4, d4, d6
-; CHECK-NEXT:    fmaxnm d5, d5, d6
-; CHECK-NEXT:    fminnm d0, d0, d7
-; CHECK-NEXT:    fminnm d1, d1, d7
-; CHECK-NEXT:    fminnm d2, d2, d7
-; CHECK-NEXT:    fminnm d3, d3, d7
-; CHECK-NEXT:    fminnm d4, d4, d7
-; CHECK-NEXT:    fminnm d5, d5, d7
-; CHECK-NEXT:    fcvtzu w0, d0
-; CHECK-NEXT:    fcvtzu w1, d1
-; CHECK-NEXT:    fcvtzu w2, d2
-; CHECK-NEXT:    fcvtzu w3, d3
-; CHECK-NEXT:    fcvtzu w4, d4
-; CHECK-NEXT:    fcvtzu w5, d5
+; CHECK-NEXT:    mov v2.d[1], v3.d[0]
+; CHECK-NEXT:    mov v4.d[1], v5.d[0]
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fmaxnm v3.2d, v4.2d, v6.2d
+; CHECK-NEXT:    fmaxnm v2.2d, v2.2d, v6.2d
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v6.2d
+; CHECK-NEXT:    fminnm v3.2d, v3.2d, v1.2d
+; CHECK-NEXT:    fminnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v1.2d, v3.2d
+; CHECK-NEXT:    fcvtzu v2.2d, v2.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v2.2s, v2.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w3, v2.s[1]
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w2, s2
+; CHECK-NEXT:    fmov w4, s1
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f64.v6i32(<6 x double> %f)
     ret <6 x i32> %x
 }
 
 ;
 ; FP128 to unsigned 32-bit -- Vector size variation
 ;

 declare <6 x i32> @llvm.fptoui.sat.v6f16.v6i32 (<6 x half>)
 declare <7 x i32> @llvm.fptoui.sat.v7f16.v7i32 (<7 x half>)
 declare <8 x i32> @llvm.fptoui.sat.v8f16.v8i32 (<8 x half>)
 
 define <1 x i32> @test_unsigned_v1f16_v1i32(<1 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v1f16_v1i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv w8, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v2f16_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f16.v2i32(<2 x half> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f16_v3i32(<3 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v3f16_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f16.v3i32(<3 x half> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f16_v4i32(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v5f16_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w10, s0
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w8, wzr, w10, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w4, w8, wzr, le
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v6f16_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov h2, v1.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w5, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    fcvtzu w10, s1
-; CHECK-NEXT:    csinv w0, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csel w9, wzr, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu w11, s2
-; CHECK-NEXT:    csinv w1, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel w8, wzr, w11, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvtzu w12, s0
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    mov v1.s[1], w5
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v7f16_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov h2, v1.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s2, h1
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v1.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w10, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w10, wzr, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvtzu w11, s2
-; CHECK-NEXT:    csinv w6, w10, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w10, wzr, w11, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    fcvtzu w11, s1
-; CHECK-NEXT:    csinv w0, w10, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csel w10, wzr, w11, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu w12, s2
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csinv w1, w10, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvtzu w13, s0
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    mov v1.s[2], w6
-; CHECK-NEXT:    csel w8, wzr, w13, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    mov w5, v1.s[1]
-; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w6, v0.s[2]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v8f16_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h3, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    mov h2, v5.h[1]
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fcvt s1, h5
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov v0.s[3], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    mov h2, v5.h[2]
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov h3, v5.h[3]
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov v1.s[1], w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; 2-Vector float to unsigned integer -- result size variation
 ;
 
 declare <2 x   i1> @llvm.fptoui.sat.v2f32.v2i1  (<2 x float>)
 declare <2 x   i8> @llvm.fptoui.sat.v2f32.v2i8  (<2 x float>)
 declare <2 x  i13> @llvm.fptoui.sat.v2f32.v2i13 (<2 x float>)
 declare <2 x  i16> @llvm.fptoui.sat.v2f32.v2i16 (<2 x float>)
 declare <2 x  i19> @llvm.fptoui.sat.v2f32.v2i19 (<2 x float>)
 declare <2 x  i50> @llvm.fptoui.sat.v2f32.v2i50 (<2 x float>)
 declare <2 x  i64> @llvm.fptoui.sat.v2f32.v2i64 (<2 x float>)
 declare <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float>)
 declare <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float>)
 
 define <2 x i1> @test_unsigned_v2f32_v2i1(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov s1, wzr
-; CHECK-NEXT:    fmov s2, #1.00000000
-; CHECK-NEXT:    mov s3, v0.s[1]
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmaxnm s1, s3, s1
-; CHECK-NEXT:    fminnm s0, s0, s2
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    movi d1, #0000000000000000
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fmov v1.2s, #1.00000000
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i1> @llvm.fptoui.sat.v2f32.v2i1(<2 x float> %f)
     ret <2 x i1> %x
 }
 
 define <2 x i8> @test_unsigned_v2f32_v2i8(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov s1, wzr
+; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    mov w8, #1132396544
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmaxnm s1, s2, s1
-; CHECK-NEXT:    fminnm s0, s0, s3
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fminnm s1, s1, s3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i8> @llvm.fptoui.sat.v2f32.v2i8(<2 x float> %f)
     ret <2 x i8> %x
 }
 
 define <2 x i13> @test_unsigned_v2f32_v2i13(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i13:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #63488
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov s1, wzr
+; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    movk w8, #17919, lsl #16
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmaxnm s1, s2, s1
-; CHECK-NEXT:    fminnm s0, s0, s3
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fminnm s1, s1, s3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i13> @llvm.fptoui.sat.v2f32.v2i13(<2 x float> %f)
     ret <2 x i13> %x
 }
 
 define <2 x i16> @test_unsigned_v2f32_v2i16(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #65280
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov s1, wzr
+; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    movk w8, #18303, lsl #16
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmaxnm s1, s2, s1
-; CHECK-NEXT:    fminnm s0, s0, s3
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fminnm s1, s1, s3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i16> @llvm.fptoui.sat.v2f32.v2i16(<2 x float> %f)
     ret <2 x i16> %x
 }
 
 define <2 x i19> @test_unsigned_v2f32_v2i19(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i19:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #65504
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov s1, wzr
+; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    movk w8, #18687, lsl #16
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    fmaxnm s0, s0, s1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmaxnm s1, s2, s1
-; CHECK-NEXT:    fminnm s0, s0, s3
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fminnm s1, s1, s3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_unsigned_v2f32_v2i50(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i50:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1484783615
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu x8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    mov x9, #1125899906842623
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu x10, s0
-; CHECK-NEXT:    csel x8, x9, x8, gt
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel x10, xzr, x10, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel x9, x9, x10, gt
-; CHECK-NEXT:    fmov d0, x9
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    mov x8, #-8
+; CHECK-NEXT:    fcvtl v0.2d, v0.2s
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
+; CHECK-NEXT:    movk x8, #17167, lsl #48
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptoui.sat.v2f32.v2i50(<2 x float> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_unsigned_v2f32_v2i64(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1602224127
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu x8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu x9, s0
-; CHECK-NEXT:    csinv x8, x8, xzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fmov d0, x9
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    fcvtl v0.2d, v0.2s
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i100:
 ; CHECK:       // %bb.0:

 declare <2 x  i50> @llvm.fptoui.sat.v2f64.v2i50 (<2 x double>)
 declare <2 x  i64> @llvm.fptoui.sat.v2f64.v2i64 (<2 x double>)
 declare <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double>)
 declare <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double>)
 
 define <2 x i1> @test_unsigned_v2f64_v2i1(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov d1, xzr
-; CHECK-NEXT:    fmov d2, #1.00000000
-; CHECK-NEXT:    mov d3, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmaxnm d1, d3, d1
-; CHECK-NEXT:    fminnm d0, d0, d2
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fmov v1.2d, #1.00000000
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i1> @llvm.fptoui.sat.v2f64.v2i1(<2 x double> %f)
     ret <2 x i1> %x
 }
 
 define <2 x i8> @test_unsigned_v2f64_v2i8(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #246290604621824
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16495, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i8> @llvm.fptoui.sat.v2f64.v2i8(<2 x double> %f)
     ret <2 x i8> %x
 }
 
 define <2 x i13> @test_unsigned_v2f64_v2i13(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i13:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #280375465082880
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16575, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i13> @llvm.fptoui.sat.v2f64.v2i13(<2 x double> %f)
     ret <2 x i13> %x
 }
 
 define <2 x i16> @test_unsigned_v2f64_v2i16(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #281337537757184
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16623, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i16> @llvm.fptoui.sat.v2f64.v2i16(<2 x double> %f)
     ret <2 x i16> %x
 }
 
 define <2 x i19> @test_unsigned_v2f64_v2i19(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i19:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #281457796841472
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16671, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i32_duplicate:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_unsigned_v2f64_v2i50(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i50:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-8
-; CHECK-NEXT:    fmov d1, xzr
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk x8, #17167, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
-; CHECK-NEXT:    fcvtzu x8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    fcvtzu x8, d1
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov x8, #4895412794951729151
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fcvtzu x8, d1
-; CHECK-NEXT:    fcmp d1, #0.0
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp d1, d2
-; CHECK-NEXT:    fcvtzu x9, d0
-; CHECK-NEXT:    csinv x8, x8, xzr, le
-; CHECK-NEXT:    fcmp d0, #0.0
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp d0, d2
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fmov d0, x9
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i100:
 ; CHECK:       // %bb.0:

 declare <4 x  i50> @llvm.fptoui.sat.v4f16.v4i50 (<4 x half>)
 declare <4 x  i64> @llvm.fptoui.sat.v4f16.v4i64 (<4 x half>)
 declare <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half>)
 declare <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half>)
 
 define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fmov s2, wzr
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmaxnm s1, s1, s2
-; CHECK-NEXT:    fmaxnm s3, s3, s2
-; CHECK-NEXT:    fmaxnm s4, s4, s2
-; CHECK-NEXT:    fmaxnm s0, s0, s2
-; CHECK-NEXT:    fmov s2, #1.00000000
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fminnm s1, s3, s2
-; CHECK-NEXT:    fminnm s3, s4, s2
-; CHECK-NEXT:    fminnm s2, s0, s2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.h[1], w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fmov v1.4s, #1.00000000
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
     ret <4 x i1> %x
 }
 
 define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fmov s2, wzr
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    mov w8, #1132396544
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmaxnm s1, s1, s2
-; CHECK-NEXT:    fmaxnm s3, s3, s2
-; CHECK-NEXT:    fmaxnm s4, s4, s2
-; CHECK-NEXT:    fmaxnm s0, s0, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fminnm s1, s3, s2
-; CHECK-NEXT:    fminnm s3, s4, s2
-; CHECK-NEXT:    fminnm s2, s0, s2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.h[1], w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
     ret <4 x i8> %x
 }
 
 define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i13:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
 ; CHECK-NEXT:    mov w8, #63488
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fmov s2, wzr
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk w8, #17919, lsl #16
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmaxnm s1, s1, s2
-; CHECK-NEXT:    fmaxnm s3, s3, s2
-; CHECK-NEXT:    fmaxnm s4, s4, s2
-; CHECK-NEXT:    fmaxnm s0, s0, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fminnm s1, s3, s2
-; CHECK-NEXT:    fminnm s3, s4, s2
-; CHECK-NEXT:    fminnm s2, s0, s2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.h[1], w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i13> @llvm.fptoui.sat.v4f16.v4i13(<4 x half> %f)
     ret <4 x i13> %x
 }
 
 define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
 ; CHECK-NEXT:    mov w8, #65280
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fmov s2, wzr
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk w8, #18303, lsl #16
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmaxnm s1, s1, s2
-; CHECK-NEXT:    fmaxnm s3, s3, s2
-; CHECK-NEXT:    fmaxnm s4, s4, s2
-; CHECK-NEXT:    fmaxnm s0, s0, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fminnm s1, s3, s2
-; CHECK-NEXT:    fminnm s3, s4, s2
-; CHECK-NEXT:    fminnm s2, s0, s2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.h[1], w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v0.h[3], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i16> @llvm.fptoui.sat.v4f16.v4i16(<4 x half> %f)
     ret <4 x i16> %x
 }
 
 define <4 x i19> @test_unsigned_v4f16_v4i19(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i19:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
 ; CHECK-NEXT:    mov w8, #65504
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fmov s2, wzr
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-NEXT:    movk w8, #18687, lsl #16
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmaxnm s1, s1, s2
-; CHECK-NEXT:    fmaxnm s3, s3, s2
-; CHECK-NEXT:    fmaxnm s4, s4, s2
-; CHECK-NEXT:    fmaxnm s0, s0, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fminnm s1, s3, s2
-; CHECK-NEXT:    fminnm s3, s4, s2
-; CHECK-NEXT:    fminnm s2, s0, s2
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i19> @llvm.fptoui.sat.v4f16.v4i19(<4 x half> %f)
     ret <4 x i19> %x
 }
 
 define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_unsigned_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i50:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov w8, #1484783615
-; CHECK-NEXT:    fcvtzu x10, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    csel x8, xzr, x10, lt
-; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    fcvtzu x9, s1
 ; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov x9, #1125899906842623
 ; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    mov x8, #1125899906842623
 ; CHECK-NEXT:    fcvtzu x10, s1
-; CHECK-NEXT:    csel x0, x9, x8, gt
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel x8, xzr, x10, lt
-; CHECK-NEXT:    fcmp s1, s2
 ; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    fcvt s1, h1
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu x10, s1
-; CHECK-NEXT:    csel x1, x9, x8, gt
-; CHECK-NEXT:    fcmp s1, #0.0
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    cmp x9, x8
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel x8, xzr, x10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu x11, s0
-; CHECK-NEXT:    csel x2, x9, x8, gt
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel x8, xzr, x11, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel x3, x9, x8, gt
+; CHECK-NEXT:    fcvtzu x11, s1
+; CHECK-NEXT:    csel x0, x8, x9, hi
+; CHECK-NEXT:    cmp x10, x8
+; CHECK-NEXT:    fcvtzu x12, s0
+; CHECK-NEXT:    csel x1, x8, x10, hi
+; CHECK-NEXT:    cmp x11, x8
+; CHECK-NEXT:    csel x2, x8, x11, hi
+; CHECK-NEXT:    cmp x12, x8
+; CHECK-NEXT:    csel x3, x8, x12, hi
 ; CHECK-NEXT:    ret
     %x = call <4 x i50> @llvm.fptoui.sat.v4f16.v4i50(<4 x half> %f)
     ret <4 x i50> %x
 }
 
 define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1602224127
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzu x8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    fcvtzu x9, s2
-; CHECK-NEXT:    csinv x8, x8, xzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
+; CHECK-NEXT:    fcvt s1, h2
+; CHECK-NEXT:    fmov d2, x8
+; CHECK-NEXT:    fcvtzu x8, s1
+; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h0, v0.h[2]
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fcvtzu x10, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    csel x10, xzr, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fmov d0, x9
-; CHECK-NEXT:    fcvtzu x9, s4
-; CHECK-NEXT:    csinv x10, x10, xzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    mov v0.d[1], x8
-; CHECK-NEXT:    mov v1.d[1], x10
+; CHECK-NEXT:    mov v2.d[1], x8
+; CHECK-NEXT:    fcvtzu x8, s1
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fcvtzu x8, s0
+; CHECK-NEXT:    mov v1.d[1], x8
+; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
     ret <4 x i64> %x
 }
 
 define <4 x i100> @test_unsigned_v4f16_v4i100(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i100:
 ; CHECK:       // %bb.0: