[ARM][FPEnv] Lowering of {get,set,reset}_fpenv

[sepavloff]

Summary

The change implements lowering of get_fpenv, set_fpenv and
reset_fpenv. The lowering is based on the intrinsic arm_get_fpscr.

[arsenm]

llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp

273

Addr.getValueType()

[sepavloff]

Simplified address type calculation

[sepavloff]

Updated patch as its dependency changed

[sepavloff]

llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp

273

Fixed.

[sepavloff]

Update after update of dependency

[sepavloff]

Ping.

[sepavloff]

Ping.

[john.brawn]

llvm/lib/Target/ARM/ARMISelLowering.cpp

6444–6472 ↗

(On Diff #523051)

This could be done more simply by setting these nodes to Legal having tablegen patterns instead, e.g.

def : Pat<(get_fpenv), (VMRS)>;
def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
def : Pat<(reset_fpenv), (VMSR 0)>;

(though it requires get_fpenv etc. nodes being added to TargetSelectionDAG.td).

[sepavloff]

Rebase and simplify implementation

[sepavloff]

llvm/lib/Target/ARM/ARMISelLowering.cpp

6444–6472 ↗

(On Diff #523051)

Indeed, this is much better.
Thank you!

[john.brawn]

LGTM

[sepavloff]

Thanks!

[sepavloff]

The patch was reverted because it caused fail on a buildbot with expensive checks. It detected that vmsr does not allow immediate as a source. I am going to modify this commit:

diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 7898972ee278..9b1224c7e1e3 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2673,7 +2673,7 @@ def : Pat<(f32 (vfp_f32f16imm:$imm)),
 // Floating-point environment management.
 def : Pat<(get_fpenv), (VMRS)>;
 def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
-def : Pat<(reset_fpenv), (VMSR 0)>;
+def : Pat<(reset_fpenv), (VMSR (MOVi 0))>;
 
 //===----------------------------------------------------------------------===//
 // Assembler aliases.
diff --git a/llvm/test/CodeGen/ARM/fpenv.ll b/llvm/test/CodeGen/ARM/fpenv.ll
index f5c6a9608bac..40db627ebb3c 100644
--- a/llvm/test/CodeGen/ARM/fpenv.ll
+++ b/llvm/test/CodeGen/ARM/fpenv.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 --verify-machineinstrs %s -o - | FileCheck %s
 
 define void @func_02(i32 %rm) {
 ; CHECK-LABEL: func_02:
@@ -134,7 +134,8 @@ entry:
 define void @reset_fpenv_02() nounwind {
 ; CHECK-LABEL: reset_fpenv_02:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr fpscr, #0
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    vmsr fpscr, r0
 ; CHECK-NEXT:    mov pc, lr
 entry:
   call void @llvm.reset.fpenv()

If there are no objections, I will commit the modified patch.

[john.brawn]

That would cause an invalid instruction to be emitted when compiling for thumb. I think you need one pattern using MOVi marked with Requires<[IsARM]>, and another using tMOVi8 marked with Requires<[IsThumb]>.

[sepavloff]

In D81843#4656796, @john.brawn wrote:

That would cause an invalid instruction to be emitted when compiling for thumb. I think you need one pattern using MOVi marked with Requires<[IsARM]>, and another using tMOVi8 marked with Requires<[IsThumb]>.

Thank you for advice! Now the problem place looks like:

--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2673,7 +2673,8 @@ def : Pat<(f32 (vfp_f32f16imm:$imm)),
 // Floating-point environment management.
 def : Pat<(get_fpenv), (VMRS)>;
 def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
-def : Pat<(reset_fpenv), (VMSR 0)>;
+def : Pat<(reset_fpenv), (VMSR (MOVi 0))>, Requires<[IsARM]>;
+def : Pat<(reset_fpenv), (VMSR (tMOVi8 0))>, Requires<[IsThumb]>;

llvm/lib/Target/ARM/ARMSelectionDAGInfo.h

SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
                                   SDValue Chain, SDValue Op1, SDValue Op2,
                                   SDValue Op3, unsigned Align, bool isVolatile,
                                   MachinePointerInfo DstPtrInfo) const override;
 
   SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl,
                                  SDValue Chain, SDValue Dst, SDValue Src,
                                  SDValue Size, unsigned Align,
                                  RTLIB::Libcall LC) const;
+
+  SDValue emitTargetCodeForGetFPEnv(SelectionDAG &DAG, const SDLoc &DL,
+                                    SDValue Chain, SDValue Addr,
+                                    MachinePointerInfo PtrInfo) const override;
+
+  SDValue emitTargetCodeForSetFPEnv(SelectionDAG &DAG, const SDLoc &DL,
+                                    SDValue Chain, SDValue Addr,
+                                    MachinePointerInfo PtrInfo) const override;
+
+  SDValue emitTargetCodeForResetFPEnv(SelectionDAG &DAG, const SDLoc &DL,
+                                      SDValue Chain) const override;
 };
 
 }
 
 #endif

llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp

 
 SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemset(
     SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
     SDValue Size, unsigned Align, bool isVolatile,
     MachinePointerInfo DstPtrInfo) const {
   return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align,
                                 RTLIB::MEMSET);
 }
+
+SDValue ARMSelectionDAGInfo::emitTargetCodeForGetFPEnv(
+    SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Addr,
+    MachinePointerInfo PtrInfo) const {
+  SDValue Ops[] = {Chain,
+                   DAG.getConstant(Intrinsic::arm_get_fpscr, DL, MVT::i32)};
+  SDValue FPSCR =
+      DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i32, MVT::Other}, Ops);
+  Chain = FPSCR.getValue(1);
+  Chain = DAG.getStore(Chain, DL, FPSCR.getValue(0), Addr, PtrInfo,
+                       DAG.InferPtrAlign(Addr), MachineMemOperand::MOStore);
+  return Chain;
+}
+
+SDValue ARMSelectionDAGInfo::emitTargetCodeForSetFPEnv(
+    SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Addr,
+    MachinePointerInfo PtrInfo) const {
+  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
+  SDValue Load =
+      DAG.getLoad(PtrVT, DL, Chain, Addr, PtrInfo, DAG.InferPtrAlign(Addr));
+  SDValue Ops[] = {
+      Chain, DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32), Load};
+  return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops);
+}
+
+SDValue ARMSelectionDAGInfo::emitTargetCodeForResetFPEnv(SelectionDAG &DAG,
+                                                         const SDLoc &DL,
+                                                         SDValue Chain) const {
+  SDValue Ops[] = {Chain,
+                   DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32),
+                   DAG.getConstant(0, DL, MVT::i32)};
+  return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops);
+}

llvm/test/CodeGen/ARM/fpenv.ll

+; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 -o - %s | FileCheck %s
+
+define void @func_01(i8* %fpenv) {
+entry:
+  call void @llvm.get.fpenv(i8* %fpenv)
+  ret void
+}
+; CHECK-LABEL: func_01:
+; CHECK:       vmrs [[REG:r[0-9]+]], fpscr
+; CHECK-NEXT:  str  [[REG]], [r0]
+; CHECK-NEXT:  mov  pc, lr
+
+
+define void @func_02(i8* %fpenv) {
+entry:
+  call void @llvm.set.fpenv(i8* %fpenv)
+  ret void
+}
+; CHECK-LABEL: func_02:
+; CHECK:       ldr  [[REG:r[0-9]+]], [r0]
+; CHECK-NEXT:  vmsr fpscr, [[REG]]
+; CHECK-NEXT:  mov  pc, lr
+
+
+define void @func_03() {
+entry:
+  call void @llvm.reset.fpenv()
+  ret void
+}
+; CHECK-LABEL: func_03:
+; CHECK:       mov  [[REG:r[0-9]+]], #0
+; CHECK-NEXT:  vmsr fpscr, [[REG]]
+; CHECK-NEXT:  mov  pc, lr
+
+
+; Check that in the sequence (get_fpenv, set_fpenv) memory is not used.
+define void @func_04() {
+entry:
+  %fpenv = alloca i32
+  %fptr = bitcast i32* %fpenv to i8*
+  call void @llvm.get.fpenv(i8* %fptr)
+  call void @llvm.set.fpenv(i8* %fptr)
+  ret void
+}
+; CHECK-LABEL: func_04:
+; CHECK:       vmrs [[REG:r[0-9]+]], fpscr
+; CHECK:       vmsr fpscr, [[REG]]
+
+
+; Check that in the sequence (get_fpenv, state modification, set_fpenv) memory
+; is not used.
+define void @func_05() {
+entry:
+  %fpenv = alloca i32
+  %fptr = bitcast i32* %fpenv to i8*
+  call void @llvm.get.fpenv(i8* %fptr)
+  %fpenv2 = load i32, i32* %fpenv
+  %fpenv3 = and i32 %fpenv2, 12582912
+  store i32 %fpenv3, i32* %fpenv, align 4
+  call void @llvm.set.fpenv(i8* %fptr)
+  ret void
+}
+; CHECK-LABEL: func_05:
+; CHECK:       vmrs [[REG1:r[0-9]+]], fpscr
+; CHECK:       and  [[REG2:r[0-0]+]], [[REG1]], #12582912
+; CHECK:       vmsr fpscr, [[REG2]]
+
+
+declare void @llvm.get.fpenv(i8* %fpenv)
+declare void @llvm.set.fpenv(i8* %fpenv)
+declare void @llvm.reset.fpenv()