[ARM][FPEnv] Lowering of {get,set,reset}_fpenv

[sepavloff]

Summary

The change implements lowering of get_fpenv, set_fpenv and
reset_fpenv. The lowering is based on the intrinsic arm_get_fpscr.

[arsenm]

llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp

273 ↗

(On Diff #270750)

Addr.getValueType()

[sepavloff]

Simplified address type calculation

[sepavloff]

Updated patch as its dependency changed

[sepavloff]

llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp

273 ↗

(On Diff #270750)

Fixed.

[sepavloff]

Update after update of dependency

[sepavloff]

Ping.

[sepavloff]

Ping.

[john.brawn]

llvm/lib/Target/ARM/ARMISelLowering.cpp

6449–6477

This could be done more simply by setting these nodes to Legal having tablegen patterns instead, e.g.

def : Pat<(get_fpenv), (VMRS)>;
def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
def : Pat<(reset_fpenv), (VMSR 0)>;

(though it requires get_fpenv etc. nodes being added to TargetSelectionDAG.td).

[sepavloff]

Rebase and simplify implementation

[sepavloff]

llvm/lib/Target/ARM/ARMISelLowering.cpp

6449–6477

Indeed, this is much better.
Thank you!

[john.brawn]

LGTM

[sepavloff]

Thanks!

[sepavloff]

The patch was reverted because it caused fail on a buildbot with expensive checks. It detected that vmsr does not allow immediate as a source. I am going to modify this commit:

diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 7898972ee278..9b1224c7e1e3 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2673,7 +2673,7 @@ def : Pat<(f32 (vfp_f32f16imm:$imm)),
 // Floating-point environment management.
 def : Pat<(get_fpenv), (VMRS)>;
 def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
-def : Pat<(reset_fpenv), (VMSR 0)>;
+def : Pat<(reset_fpenv), (VMSR (MOVi 0))>;
 
 //===----------------------------------------------------------------------===//
 // Assembler aliases.
diff --git a/llvm/test/CodeGen/ARM/fpenv.ll b/llvm/test/CodeGen/ARM/fpenv.ll
index f5c6a9608bac..40db627ebb3c 100644
--- a/llvm/test/CodeGen/ARM/fpenv.ll
+++ b/llvm/test/CodeGen/ARM/fpenv.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 --verify-machineinstrs %s -o - | FileCheck %s
 
 define void @func_02(i32 %rm) {
 ; CHECK-LABEL: func_02:
@@ -134,7 +134,8 @@ entry:
 define void @reset_fpenv_02() nounwind {
 ; CHECK-LABEL: reset_fpenv_02:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr fpscr, #0
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    vmsr fpscr, r0
 ; CHECK-NEXT:    mov pc, lr
 entry:
   call void @llvm.reset.fpenv()

If there are no objections, I will commit the modified patch.

[john.brawn]

That would cause an invalid instruction to be emitted when compiling for thumb. I think you need one pattern using MOVi marked with Requires<[IsARM]>, and another using tMOVi8 marked with Requires<[IsThumb]>.

[sepavloff]

In D81843#4656796, @john.brawn wrote:

That would cause an invalid instruction to be emitted when compiling for thumb. I think you need one pattern using MOVi marked with Requires<[IsARM]>, and another using tMOVi8 marked with Requires<[IsThumb]>.

Thank you for advice! Now the problem place looks like:

--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2673,7 +2673,8 @@ def : Pat<(f32 (vfp_f32f16imm:$imm)),
 // Floating-point environment management.
 def : Pat<(get_fpenv), (VMRS)>;
 def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
-def : Pat<(reset_fpenv), (VMSR 0)>;
+def : Pat<(reset_fpenv), (VMSR (MOVi 0))>, Requires<[IsARM]>;
+def : Pat<(reset_fpenv), (VMSR (tMOVi8 0))>, Requires<[IsThumb]>;

llvm/include/llvm/Target/TargetSelectionDAG.td

def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT",
                                SDTFPToIntOp, [SDNPHasChain]>;
 def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP",
                                SDTIntToFPOp, [SDNPHasChain]>;
 def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP",
                                SDTIntToFPOp, [SDNPHasChain]>;
 def strict_fsetcc  : SDNode<"ISD::STRICT_FSETCC",  SDTSetCC, [SDNPHasChain]>;
 def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
 
+def get_fpenv      : SDNode<"ISD::GET_FPENV", SDTGetFPStateOp, [SDNPHasChain]>;
+def set_fpenv      : SDNode<"ISD::SET_FPENV", SDTSetFPStateOp, [SDNPHasChain]>;
+def reset_fpenv    : SDNode<"ISD::RESET_FPENV", SDTNone, [SDNPHasChain]>;
 def get_fpmode     : SDNode<"ISD::GET_FPMODE", SDTGetFPStateOp, [SDNPHasChain]>;
 def set_fpmode     : SDNode<"ISD::SET_FPMODE", SDTSetFPStateOp, [SDNPHasChain]>;
 def reset_fpmode   : SDNode<"ISD::RESET_FPMODE", SDTNone, [SDNPHasChain]>;
 
 def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
 def select     : SDNode<"ISD::SELECT"     , SDTSelect>;
 def vselect    : SDNode<"ISD::VSELECT"    , SDTVSelect>;
 def selectcc   : SDNode<"ISD::SELECT_CC"  , SDTSelectCC>;

llvm/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
 
   if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
       !Subtarget->isThumb1Only()) {
     // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
     // iff target supports vfp2.
     setOperationAction(ISD::BITCAST, MVT::i64, Custom);
     setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom);
     setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
+    setOperationAction(ISD::GET_FPENV, MVT::i32, Legal);
+    setOperationAction(ISD::SET_FPENV, MVT::i32, Legal);
+    setOperationAction(ISD::RESET_FPENV, MVT::Other, Legal);
   }
 
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
   setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
   if (Subtarget->useSjLjEH())
SDValue ARMTargetLowering::LowerSET_ROUNDING(SDValue Op,
   FPSCR = DAG.getNode(ISD::AND, DL, MVT::i32, FPSCR,
                       DAG.getConstant(RMMask, DL, MVT::i32));
   FPSCR = DAG.getNode(ISD::OR, DL, MVT::i32, FPSCR, RMValue);
   SDValue Ops2[] = {
       Chain, DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32), FPSCR};
   return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
 }
 
 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
                          const ARMSubtarget *ST) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
   if (VT.isVector() && ST->hasNEON()) {
 
     // Compute the least significant set bit: LSB = X & -X
     SDValue X = N->getOperand(0);
     SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
     SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
 
     EVT ElemTy = VT.getVectorElementType();
 
     if (ElemTy == MVT::i8) {
       // Compute with: cttz(x) = ctpop(lsb - 1)
       SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
                                 DAG.getTargetConstant(1, dl, ElemTy));
       SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
       return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
     }
 
     if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
         (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
       // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
       unsigned NumBits = ElemTy.getSizeInBits();
       SDValue WidthMinus1 =
           DAG.getNode(ARMISD::VMOVIMM, dl, VT,
                       DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
       SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
       return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
     }
 
     // Compute with: cttz(x) = ctpop(lsb - 1)
 
     // Compute LSB - 1.
     SDValue Bits;
     if (ElemTy == MVT::i64) {

llvm/lib/Target/ARM/ARMInstrVFP.td

 }
 }
 
 def : Pat<(f32 (vfp_f32f16imm:$imm)),
           (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> {
   let Predicates = [HasFullFP16];
 }
 
+// Floating-point environment management.
+def : Pat<(get_fpenv), (VMRS)>;
+def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
+def : Pat<(reset_fpenv), (VMSR 0)>;
+
 //===----------------------------------------------------------------------===//
 // Assembler aliases.
 //
 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
 // support them all, but supporting at least some of the basics is
 // good to be friendly.
 def : VFP2MnemonicAlias<"flds", "vldr">;
 def : VFP2MnemonicAlias<"fldd", "vldr">;

llvm/test/CodeGen/ARM/fpenv.ll

 ; CHECK-NEXT:    add sp, sp, #8
 ; CHECK-NEXT:    pop {r11, lr}
 ; CHECK-NEXT:    mov pc, lr
 entry:
   %fpenv = call i32 @llvm.get.fpenv.i32()
   ret i32 %fpenv
 }
 
+define i32 @get_fpenv_02() nounwind {
+; CHECK-LABEL: get_fpenv_02:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmrs r0, fpscr
+; CHECK-NEXT:    mov pc, lr
+entry:
+  %fpenv = call i32 @llvm.get.fpenv.i32()
+  ret i32 %fpenv
+}
+
 define void @set_fpenv_01(i32 %fpenv) #0 {
 ; CHECK-LABEL: set_fpenv_01:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r11, lr}
 ; CHECK-NEXT:    push {r11, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, sp, #8
 ; CHECK-NEXT:    str r0, [sp, #4]
 ; CHECK-NEXT:    add r0, sp, #4
 ; CHECK-NEXT:    bl fesetenv
 ; CHECK-NEXT:    add sp, sp, #8
 ; CHECK-NEXT:    pop {r11, lr}
 ; CHECK-NEXT:    mov pc, lr
 entry:
   call void @llvm.set.fpenv.i32(i32 %fpenv)
   ret void
 }
 
+define void @set_fpenv_02(i32 %fpenv) nounwind {
+; CHECK-LABEL: set_fpenv_02:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr fpscr, r0
+; CHECK-NEXT:    mov pc, lr
+entry:
+  call void @llvm.set.fpenv.i32(i32 %fpenv)
+  ret void
+}
+
 define void @reset_fpenv_01() #0 {
 ; CHECK-LABEL: reset_fpenv_01:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r11, lr}
 ; CHECK-NEXT:    push {r11, lr}
 ; CHECK-NEXT:    mvn r0, #0
 ; CHECK-NEXT:    bl fesetenv
 ; CHECK-NEXT:    pop {r11, lr}
 ; CHECK-NEXT:    mov pc, lr
 entry:
   call void @llvm.reset.fpenv()
   ret void
 }
 
+define void @reset_fpenv_02() nounwind {
+; CHECK-LABEL: reset_fpenv_02:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr fpscr, #0
+; CHECK-NEXT:    mov pc, lr
+entry:
+  call void @llvm.reset.fpenv()
+  ret void
+}
+
 attributes #0 = { nounwind "use-soft-float"="true" }
 
 declare void @llvm.set.rounding(i32)
 declare i32 @llvm.get.fpenv.i32()
 declare void @llvm.set.fpenv.i32(i32 %fpenv)
 declare void @llvm.reset.fpenv()