[CodeGen,AArch64] Fix up warnings in splitStores

[david-arm]

Summary

The code for trying to split up stores is designed for NEON vectors,
where we support arbitrary alignments. It's an optimisation designed
to improve performance by using smaller, aligned stores. However,
we currently only support 16 byte alignments for SVE vectors anyway
so we may as well bail out early.

This change fixes up remaining warnings in a couple of tests:

CodeGen/AArch64/sve-callbyref-notailcall.ll
CodeGen/AArch64/sve-calling-convention-byref.ll

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

12039

VT.isScalableVector() ?

12041

It's a bit odd to assert !VT.isScalableVector() here given the condition above, but I also don't really see why you're asserting the alignment here in this function. What was the motivation for adding it?

[david-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

12039

The original code bailed out if it wasn't a vector, now we want to bail if it's not a fixed length vector. That's why I can't just use

if (VT.isScalableVector())

as it would then allow non-vector types in.

12041

So we can get here for two cases:

1. It's not a vector at all, hence the assert(!VT.isScalableVector() || ..)
2. It's a scalable vector. This function has been specifically written to optimise cases of NEON vector stores to addresses with terrible alignments, i.e. not 16 bytes. It's hard to split up stores for SVE, although not impossible - and the cost of doing so probably makes it not worth it. However, we shouldn't even have to worry about mis-alignments for SVE vectors at all because they are always supposed to be aligned to 16 bytes. That's why I put the assert in, although I admit it may be unnecessary. I can remove it if you want?

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

12039

Okay that makes sense, thanks for clarifying!

12041

We indeed require an alignment of 16 for scalable vectors allocated on the stack, it's more that given that this code is not doing anything with scalable vectors other than bailing out, having the assert here seems unnecessary. There are already asserts in FrameLowering to cover this.

[sdesmalen]

LGTM!

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                            const AArch64Subtarget *Subtarget) {
 
   StoreSDNode *S = cast<StoreSDNode>(N);
   if (S->isVolatile() || S->isIndexed())
     return SDValue();
 
   SDValue StVal = S->getValue();
   EVT VT = StVal.getValueType();
-  if (!VT.isVector())
+  // All SVE vectors should be aligned to 16 bytes
+  if (!VT.isVector() || VT.isScalableVector())
     return SDValue();
 
   // If we get a splat of zeros, convert this vector store to a store of
   // scalars. They will be merged into store pairs of xzr thereby removing one
   // instruction and one register.
   if (SDValue ReplacedZeroSplat = replaceZeroVectorStore(DAG, *S))
     return ReplacedZeroSplat;
 
   // FIXME: The logic for deciding if an unaligned store should be split should
   // be included in TLI.allowsMisalignedMemoryAccesses(), and there should be

llvm/test/CodeGen/AArch64/sve-callbyref-notailcall.ll

 ; Because some arguments are passed by reference (through stack),
 ; the compiler should not do tail-call optimization.
-; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: warning
 
 ; CHECK-LABEL: caller:
 ; CHECK:       addvl sp, sp, #-[[STACKSIZE:[0-9]+]]
 ; CHECK-NOT:   addvl sp
 ; CHECK:       bl callee
 ; CHECK:       addvl sp, sp, #[[STACKSIZE]]
 ; CHECK:       ret
 define <vscale x 16 x i8> @caller(<vscale x 16 x i8> %v) {

llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll

-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: warning
 
 ; Test that z8 and z9, passed in by reference, are correctly loaded from x0 and x1.
 ; i.e. z0 =  %z0
 ;         :
 ;      z7 =  %z7
 ;      x0 = &%z8
 ;      x1 = &%z9
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 4 x i32> %z8, <vscale x 4 x i32> %z9) {