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[MC][Bugfix] Remove redundant parameter for relaxInstruction
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Authored by skan on Apr 17 2020, 6:28 AM.

Details

Summary

Before this patch, relaxInstruction takes three arguments, the first
argument refers to the instruction before relaxation and the third
argument is the output instruction after relaxation. There are two quite
strange things:

  1. The first argument's type is const MCInst &, the third argument's type is MCInst &, but they may be aliased to the same variable
  2. The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third argument is a fresh uninitialized MCInst even if relaxInstruction may be called like relaxInstruction(Relaxed, STI, Relaxed) in a loop.

In this patch, we drop the thrid argument, and let relaxInstruction
directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, and
breaks the assumption of ARM, AMDGPU, RISC-V, Hexagon.

Diff Detail

Event Timeline

skan created this revision.Apr 17 2020, 6:28 AM
skan edited the summary of this revision. (Show Details)Apr 17 2020, 6:35 AM
skan added a subscriber: annita.zhang.

Just as an FYI, this fixes the issue I reported here: https://bugs.llvm.org/show_bug.cgi?id=45580

It would be cool to add a test for RISCV that way we can ensure we don't regress this again. I think @nathanchance 's test case was quite minimal.

skan added a comment.Apr 17 2020, 7:09 PM

Feel free to add yourself as a reviewer if you'd like to.

skan updated this revision to Diff 258475.Apr 17 2020, 9:19 PM

Add test for RISCV to prevent future regression

skan edited the summary of this revision. (Show Details)Apr 17 2020, 11:05 PM
skan added a reviewer: asb.Apr 17 2020, 11:33 PM
MaskRay added inline comments.Apr 18 2020, 12:15 AM
llvm/test/MC/RISCV/rv64-relaxation-encoding.s
1 ↗(On Diff #258475)

#

9 ↗(On Diff #258475)

Omit encodings.

skan updated this revision to Diff 258503.Apr 18 2020, 2:47 AM

Address review comments (only test file changes)

luismarques added inline comments.Apr 18 2020, 3:34 AM
llvm/test/MC/RISCV/rv64-relax-all.s
10–12

I'm confused about this. When you relax the instruction it goes from a compressed instruction to an uncompressed one?

luismarques marked an inline comment as done.Apr 18 2020, 3:53 AM
luismarques added inline comments.
llvm/test/MC/RISCV/rv64-relax-all.s
10–12

Ah, I see which patch this came from. When I think of RISC-V relaxations I associate with going from the more general code pattern to the more restricted one, such as the ones requested by RISC-V relaxation relocations, so I was surprised by this.

Seems reasonable. I've only got some nits about using move assignments.

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
63

Inst = std::move(Res);

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
353

Inst = std::move(Res);

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
684

Inst = std::move(Res);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
176

Inst = std::move(Res);

jrtc27 added inline comments.Apr 19 2020, 3:46 PM
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
353

Also please make Res scoped to the if. I also note that it would be nice for the code to use ARMCC::AL rather than the hard-coded 14, but that's unrelated to this patch...

skan updated this revision to Diff 258643.Apr 19 2020, 7:28 PM
skan marked 6 inline comments as done.

Address review comments

MaskRay accepted this revision.EditedApr 19 2020, 9:46 PM

LGTM. As both a bugfix and a cleanup, this looks quite reasonable to me. Probably give RISC-V/Hexagon people one or two days to confirm.

This revision is now accepted and ready to land.Apr 19 2020, 9:46 PM
Razer6 accepted this revision.Apr 20 2020, 6:28 AM

LGTM. Tested the patch for RISC-V.

bcain added a subscriber: bcain.Apr 20 2020, 2:12 PM
bcain accepted this revision.Apr 20 2020, 6:20 PM

LGTM. Tested with Hexagon.

This revision was automatically updated to reflect the committed changes.