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rtaylor (Ryan Taylor)
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User Since
Jan 9 2018, 7:56 AM (79 w, 4 d)

Recent Activity

Today

rtaylor updated the diff for D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable.

Added IntToPtrInst to case statement in Value::getPointerDereferenceableBytes

Sat, Jul 20, 12:44 PM · Restricted Project
rtaylor updated the diff for D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable.

Changed LangRef.rst to reflect !dereferenceable is applicable to pointer types not
just load types.

Sat, Jul 20, 12:31 PM · Restricted Project
rtaylor added inline comments to D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.
Sat, Jul 20, 10:36 AM · Restricted Project
rtaylor updated the diff for D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.

Updated error comment and case error test

Sat, Jul 20, 10:36 AM · Restricted Project

Yesterday

rtaylor updated the diff for D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.

Changed error message in AnalyzeFormalArguments to be more generic.
Added comments.

Fri, Jul 19, 3:08 PM · Restricted Project
rtaylor added inline comments to D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.
Fri, Jul 19, 2:58 PM · Restricted Project
rtaylor added inline comments to D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.
Fri, Jul 19, 2:55 PM · Restricted Project
rtaylor updated the diff for D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable.

Fixed test to use llvm-as and to just check for passing.

Fri, Jul 19, 2:55 PM · Restricted Project
rtaylor updated the diff for D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable.

Added !dereferenceable_or_null to syntax of inttoptr in LangRef

Fri, Jul 19, 2:44 PM · Restricted Project
rtaylor updated the diff for D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable.

Added tests and updated LangRef

Fri, Jul 19, 2:32 PM · Restricted Project
rtaylor updated the diff for D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.

Added test case. Changed assert to report_fatal_error when checking
arguments and returns.

Fri, Jul 19, 1:39 PM · Restricted Project

Thu, Jul 18

rtaylor added reviewers for D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable: nhaehnle, dstuttard, arsenm, apilipenko.
Thu, Jul 18, 3:45 PM · Restricted Project
rtaylor created D64954: [IR][Verifier] Allow IntToPtrInst to be !dereferenceable.
Thu, Jul 18, 3:38 PM · Restricted Project
rtaylor added reviewers for D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention: arsenm, nhaehnle.
Thu, Jul 18, 9:57 AM · Restricted Project
rtaylor created D64933: [AMDGPU] Adjust number of SGPRs available in Calling Convention.
Thu, Jul 18, 9:56 AM · Restricted Project

Wed, Jun 26

rtaylor committed rG9ab812d4752b: [AMDGPU] Fix for branch offset hardware workaround (authored by rtaylor).
[AMDGPU] Fix for branch offset hardware workaround
Wed, Jun 26, 10:37 AM

Sat, Jun 22

rtaylor updated the diff for D63494: [AMDGPU] Fix for branch offset hardware workaround.

Fixed suggestions

Sat, Jun 22, 6:31 AM · Restricted Project

Jun 20 2019

rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 20 2019, 5:16 PM · Restricted Project
rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 20 2019, 4:52 PM · Restricted Project
rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 20 2019, 3:03 PM · Restricted Project
rtaylor updated the diff for D63494: [AMDGPU] Fix for branch offset hardware workaround.

Fixed idents.

Jun 20 2019, 3:03 PM · Restricted Project
rtaylor updated the diff for D63494: [AMDGPU] Fix for branch offset hardware workaround.

Suggested changes: Added InstrMapping. Three test files. Lower-cased suffixes for MI defs. Changed multiclass suffix.

Jun 20 2019, 1:10 PM · Restricted Project
rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 20 2019, 11:18 AM · Restricted Project
rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 20 2019, 5:48 AM · Restricted Project

Jun 19 2019

rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 19 2019, 11:16 AM · Restricted Project
rtaylor updated the diff for D63494: [AMDGPU] Fix for branch offset hardware workaround.

Changes per suggestions

Jun 19 2019, 10:29 AM · Restricted Project

Jun 18 2019

rtaylor added a comment to D63494: [AMDGPU] Fix for branch offset hardware workaround.

Can we have a disasm test? I want to see that we do not mess with decoding.

Something other than the -disassemble checks?

Ah, missed it. Thanks, this is sufficient.

Jun 18 2019, 12:20 PM · Restricted Project
rtaylor added a comment to D63494: [AMDGPU] Fix for branch offset hardware workaround.

Can we have a disasm test? I want to see that we do not mess with decoding.

Jun 18 2019, 12:06 PM · Restricted Project
rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 18 2019, 8:41 AM · Restricted Project
rtaylor added inline comments to D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 18 2019, 8:16 AM · Restricted Project
rtaylor added reviewers for D63494: [AMDGPU] Fix for branch offset hardware workaround: dstuttard, tpr, nhaehnle, rampitec, arsenm.
Jun 18 2019, 7:23 AM · Restricted Project
rtaylor created D63494: [AMDGPU] Fix for branch offset hardware workaround.
Jun 18 2019, 7:19 AM · Restricted Project

May 15 2019

rtaylor committed rG29257eb76c8d: [AMDGPU] Increases available SGPR for Calling Convention (authored by rtaylor).
[AMDGPU] Increases available SGPR for Calling Convention
May 15 2019, 7:42 AM

May 10 2019

rtaylor updated the diff for D61261: [AMDGPU] Increases available SGPR for Calling Convention.

Added test for SGPR tuple

May 10 2019, 10:49 AM · Restricted Project

May 7 2019

rtaylor updated the diff for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

More detailed explanation of why LCSSA is needed

May 7 2019, 7:55 AM · Restricted Project

May 6 2019

rtaylor updated the diff for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

Added StackProtectorID and changed LCSSA to use it instead of StackProtector directly.

May 6 2019, 9:11 AM · Restricted Project

May 2 2019

rtaylor added inline comments to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.
May 2 2019, 3:37 PM · Restricted Project
rtaylor added inline comments to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.
May 2 2019, 11:24 AM · Restricted Project
rtaylor updated the diff for D61261: [AMDGPU] Increases available SGPR for Calling Convention.

Fixed 105 SGPR to 106 SGPR, increased limit count for allocateSGPRTuple

May 2 2019, 10:33 AM · Restricted Project
rtaylor added a reviewer for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent: chandlerc.
May 2 2019, 10:07 AM · Restricted Project
rtaylor updated the diff for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

Preserving StackProtector in LCSSA to avoid pass scheduling conflict
Removed explicit call of LCSSA in AMDGPUTargetMachine

May 2 2019, 10:01 AM · Restricted Project
rtaylor added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

Scratch that last commit, this is still broken.

May 2 2019, 8:17 AM · Restricted Project
rtaylor updated the diff for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

I was misunderstanding the dependency issues, this should fix it.

May 2 2019, 8:16 AM · Restricted Project

Apr 30 2019

rtaylor updated the diff for D61261: [AMDGPU] Increases available SGPR for Calling Convention.

[AMDGPU] Increased SGPR Count for Calling Convention

Apr 30 2019, 10:01 AM · Restricted Project

Apr 29 2019

rtaylor created D61261: [AMDGPU] Increases available SGPR for Calling Convention.
Apr 29 2019, 7:14 AM · Restricted Project
rtaylor added reviewers for D61261: [AMDGPU] Increases available SGPR for Calling Convention: arsenm, nhaehnle, dstuttard, tpr, mareko.
Apr 29 2019, 7:14 AM · Restricted Project

Apr 25 2019

rtaylor added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

Also needs a comment explaining why LCSSA is needed

Apr 25 2019, 8:04 AM · Restricted Project

Apr 23 2019

rtaylor updated the diff for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

Moved LCSSA call to after the sinking pass.

Apr 23 2019, 6:44 AM · Restricted Project

Apr 17 2019

rtaylor added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

It sort of intuitively makes sense to me that the control flow lowering would like LCSSA. However, this should not be handled by adding it directly to the pass pipeline. You can add this as a dependency, e.g. AU.addRequiredID(LCSSAID);

I would also like to see the an IR->IR testcase showing LCSSA was implicitly run

Actually, what really requires LCSSA? Is it DivergenceAnalysis or StructurizeCFG directly?

Apr 17 2019, 3:36 PM · Restricted Project
rtaylor added reviewers for D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent: dstuttard, nhaehnle, tpr.
Apr 17 2019, 1:21 PM · Restricted Project
rtaylor added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

This is a workaround. The structurizer / annotator must be correct without relying on another pass to hide situations they don't handle correctly

Apr 17 2019, 1:21 PM · Restricted Project
rtaylor added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

We have a test case such that a value that is uniform in the loop is used outside the loop where threads might have diverged.

Apr 17 2019, 1:15 PM · Restricted Project
rtaylor created D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.
Apr 17 2019, 12:56 PM · Restricted Project

Mar 20 2019

rtaylor closed D42885: [AMDGPU] intrintrics for byte/short load/store.
Mar 20 2019, 7:12 AM · Restricted Project

Mar 19 2019

rtaylor committed rG00e063ab9234: [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics (authored by rtaylor).
[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
Mar 19 2019, 9:10 AM

Mar 12 2019

rtaylor updated the diff for D42885: [AMDGPU] intrintrics for byte/short load/store.

Requested Changes

Mar 12 2019, 3:29 PM · Restricted Project
rtaylor updated the diff for D42885: [AMDGPU] intrintrics for byte/short load/store.

Add requested changes

Mar 12 2019, 9:50 AM · Restricted Project
rtaylor commandeered D42885: [AMDGPU] intrintrics for byte/short load/store.

Changing ownership

Mar 12 2019, 9:50 AM · Restricted Project

Mar 11 2019

rtaylor added inline comments to D42885: [AMDGPU] intrintrics for byte/short load/store.
Mar 11 2019, 1:57 PM · Restricted Project
rtaylor added inline comments to D42885: [AMDGPU] intrintrics for byte/short load/store.
Mar 11 2019, 10:05 AM · Restricted Project

Mar 6 2019

rtaylor committed rG67f36903ae97: [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions (authored by rtaylor).
[AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions
Mar 6 2019, 9:04 AM

Mar 5 2019

rtaylor added inline comments to D42885: [AMDGPU] intrintrics for byte/short load/store.
Mar 5 2019, 8:44 AM · Restricted Project

Mar 4 2019

rtaylor updated the summary of D58918: [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions.
Mar 4 2019, 3:36 PM · Restricted Project
rtaylor updated the diff for D58918: [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions.
Mar 4 2019, 3:36 PM · Restricted Project
rtaylor added reviewers for D58918: [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions: nhaehnle, dstuttard, tpr, arsenm.
Mar 4 2019, 12:31 PM · Restricted Project
rtaylor created D58918: [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions.
Mar 4 2019, 12:28 PM · Restricted Project
rtaylor added a comment to D42885: [AMDGPU] intrintrics for byte/short load/store.

Ping.

Mar 4 2019, 8:09 AM · Restricted Project

Feb 27 2019

rtaylor updated the diff for D42885: [AMDGPU] intrintrics for byte/short load/store.

Rename function to better reflect what it does

Feb 27 2019, 12:17 PM · Restricted Project
rtaylor updated the diff for D42885: [AMDGPU] intrintrics for byte/short load/store.

Request changes

Feb 27 2019, 12:09 PM · Restricted Project

Feb 22 2019

rtaylor added inline comments to D42885: [AMDGPU] intrintrics for byte/short load/store.
Feb 22 2019, 8:02 AM · Restricted Project
rtaylor added inline comments to D42885: [AMDGPU] intrintrics for byte/short load/store.
Feb 22 2019, 7:30 AM · Restricted Project

Feb 21 2019

rtaylor added a reviewer for D42885: [AMDGPU] intrintrics for byte/short load/store: nhaehnle.
Feb 21 2019, 10:59 AM · Restricted Project
rtaylor updated the diff for D42885: [AMDGPU] intrintrics for byte/short load/store.

Updating to include requested changes

Feb 21 2019, 10:54 AM · Restricted Project

Aug 28 2018

rtaylor added a comment to D50575: [AMDGPU] Add support for a16 modifier for gfx9.

Thanks for the changes.

Sorry to be a stickler about this, but the formatting of the odd gradients check in lowerImage is still wrong, please adjust this according to clang-format-diff before you commit.

No need to re-upload here, the rest of the changes looks good to me.

Aug 28 2018, 10:45 AM

Aug 27 2018

rtaylor updated the diff for D50575: [AMDGPU] Add support for a16 modifier for gfx9.

Realized that I had updated clang-format runs of of SIISelLowering.h/.cpp and this caused a lot of re-formatting.

Aug 27 2018, 8:22 AM

Aug 23 2018

rtaylor updated the diff for D50575: [AMDGPU] Add support for a16 modifier for gfx9.

Made suggested changes.

Aug 23 2018, 4:12 PM

Aug 17 2018

rtaylor added a comment to D50575: [AMDGPU] Add support for a16 modifier for gfx9.

Ping.

Aug 17 2018, 7:38 AM

Aug 14 2018

rtaylor added a reviewer for D50575: [AMDGPU] Add support for a16 modifier for gfx9: arsenm.
Aug 14 2018, 11:30 AM
rtaylor updated the diff for D50575: [AMDGPU] Add support for a16 modifier for gfx9.

Made changes according to suggestions. Reduced redundancy and simplified code structure.

Aug 14 2018, 9:26 AM

Aug 13 2018

rtaylor added inline comments to D50575: [AMDGPU] Add support for a16 modifier for gfx9.
Aug 13 2018, 4:33 PM
rtaylor added inline comments to D50575: [AMDGPU] Add support for a16 modifier for gfx9.
Aug 13 2018, 6:06 AM

Aug 10 2018

rtaylor retitled D50575: [AMDGPU] Add support for a16 modifier for gfx9 from [AMDGPU] Add support for a16 modifiear for gfx9 to [AMDGPU] Add support for a16 modifier for gfx9.
Aug 10 2018, 11:07 AM
rtaylor added reviewers for D50575: [AMDGPU] Add support for a16 modifier for gfx9: nhaehnle, tpr, dstuttard, timcorringham.
Aug 10 2018, 11:06 AM
rtaylor created D50575: [AMDGPU] Add support for a16 modifier for gfx9.
Aug 10 2018, 11:05 AM

Jul 30 2018

rtaylor updated the diff for D49483: [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero.

Added gather4 test cases.
Added 'isNegative' to _L to _LZ check to include <= 0.0

Jul 30 2018, 7:42 AM

Jul 25 2018

rtaylor added a comment to D49483: [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero.

Ping.

Jul 25 2018, 8:20 AM

Jul 18 2018

rtaylor added a comment to D49483: [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero.

Should this be done in an IR pass instead?

Jul 18 2018, 8:30 AM
rtaylor added reviewers for D49483: [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero: nhaehnle, arsenm, tpr, dstuttard.
Jul 18 2018, 7:00 AM
rtaylor created D49483: [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero.
Jul 18 2018, 6:59 AM

Jun 29 2018

rtaylor updated the diff for D48772: [AMDGPU] Add VALU to V_INTERP Instructions.

Adding GCN-NEXT in test case

Jun 29 2018, 10:59 AM
rtaylor updated the diff for D48772: [AMDGPU] Add VALU to V_INTERP Instructions.

Removed empty line insert in SIInstructions.td

Jun 29 2018, 10:43 AM
rtaylor updated the diff for D48772: [AMDGPU] Add VALU to V_INTERP Instructions.

Changed VALU to be set in base instruction class.

Jun 29 2018, 10:41 AM
rtaylor updated the diff for D48772: [AMDGPU] Add VALU to V_INTERP Instructions.

Moved VALU=1 to the base instruction defs.

Jun 29 2018, 8:53 AM
rtaylor added reviewers for D48772: [AMDGPU] Add VALU to V_INTERP Instructions: tpr, dstuttard, arsenm, nhaehnle.
Jun 29 2018, 7:27 AM
rtaylor created D48772: [AMDGPU] Add VALU to V_INTERP Instructions.
Jun 29 2018, 7:25 AM