Clean up usages of asserting vector getters in Type

[ctetreau]

Summary

Remove usages of asserting vector getters in Type in preparation for the
VectorType refactor. The existence of these functions complicates the
refactor while adding little value.

[ctetreau]

Update to mention that this is NFC

[ctetreau]

rebase, mention SystemZ in commit message

[sdesmalen]

LGTM

rebase, mention SystemZ in commit message

this still needs to happen?

[ctetreau]

this still needs to happen?

Apparently Arc is not a great tool and doesn't actually update the commit message in the diff... Better commit messages are being used for future commits.

llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp

static unsigned getScalarSizeInBits(Type *Ty) {
   return Size;
 }
 
 // getNumberOfParts() calls getTypeLegalizationCost() which splits the vector
 // type until it is legal. This would e.g. return 4 for <6 x i64>, instead of
 // 3.
 static unsigned getNumVectorRegs(Type *Ty) {
   assert(Ty->isVectorTy() && "Expected vector type");
-  unsigned WideBits = getScalarSizeInBits(Ty) * Ty->getVectorNumElements();
+  unsigned WideBits =
+      getScalarSizeInBits(Ty) * cast<VectorType>(Ty)->getNumElements();
   assert(WideBits > 0 && "Could not compute size of vector");
   return ((WideBits % 128U) ? ((WideBits / 128U) + 1) : (WideBits / 128U));
 }
 
 int SystemZTTIImpl::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
     TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
if (!Ty->isVectorTy()) {
     if (DivRemConstPow2)
       return (SignedDivRem ? SDivPow2Cost : 1);
     if (DivRemConst)
       return DivMulSeqCost;
     if (SignedDivRem || UnsignedDivRem)
       return DivInstrCost;
   }
   else if (ST->hasVector()) {
-    unsigned VF = Ty->getVectorNumElements();
+    unsigned VF = cast<VectorType>(Ty)->getNumElements();
     unsigned NumVectors = getNumVectorRegs(Ty);
 
     // These vector operations are custom handled, but are still supported
     // with one instruction per vector, regardless of element size.
     if (Opcode == Instruction::Shl || Opcode == Instruction::LShr ||
         Opcode == Instruction::AShr) {
       return NumVectors;
     }

 }
 
 // Return the number of instructions needed to truncate SrcTy to DstTy.
 unsigned SystemZTTIImpl::
 getVectorTruncCost(Type *SrcTy, Type *DstTy) {
   assert (SrcTy->isVectorTy() && DstTy->isVectorTy());
   assert (SrcTy->getPrimitiveSizeInBits() > DstTy->getPrimitiveSizeInBits() &&
           "Packing must reduce size of vector type.");
-  assert (SrcTy->getVectorNumElements() == DstTy->getVectorNumElements() &&
-          "Packing should not change number of elements.");
+  assert(cast<VectorType>(SrcTy)->getNumElements() ==
+             cast<VectorType>(DstTy)->getNumElements() &&
 
   // TODO: Since fp32 is expanded, the extract cost should always be 0.
 
   unsigned NumParts = getNumVectorRegs(SrcTy);
   if (NumParts <= 2)
     // Up to 2 vector registers can be truncated efficiently with pack or
     // permute. The latter requires an immediate mask to be loaded, which
     // typically gets hoisted out of a loop.  TODO: return a good value for
     // BB-VECTORIZER that includes the immediate loads, which we do not want
     // to count for the loop vectorizer.
     return 1;
 
   unsigned Cost = 0;
   unsigned Log2Diff = getElSizeLog2Diff(SrcTy, DstTy);
-  unsigned VF = SrcTy->getVectorNumElements();
+  unsigned VF = cast<VectorType>(SrcTy)->getNumElements();
   for (unsigned P = 0; P < Log2Diff; ++P) {
     if (NumParts > 1)
       NumParts /= 2;
     Cost += NumParts;
   }
 
   // Currently, a general mix of permutes and pack instructions is output by
   // isel, which follow the cost computation above except for this case which

 }
 
 // Get the cost of converting a boolean vector to a vector with same width
 // and element size as Dst, plus the cost of zero extending if needed.
 unsigned SystemZTTIImpl::
 getBoolVecToIntConversionCost(unsigned Opcode, Type *Dst,
                               const Instruction *I) {
   assert (Dst->isVectorTy());
-  unsigned VF = Dst->getVectorNumElements();
+  unsigned VF = cast<VectorType>(Dst)->getNumElements();
   unsigned Cost = 0;
   // If we know what the widths of the compared operands, get any cost of
   // converting it to match Dst. Otherwise assume same widths.
   Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I, VF) : nullptr);
   if (CmpOpTy != nullptr)
     Cost = getVectorBitmaskConversionCost(CmpOpTy, Dst);
   if (Opcode == Instruction::ZExt || Opcode == Instruction::UIToFP)
     // One 'vn' per dst vector with an immediate mask.
if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
       if (CmpOpTy != nullptr && CmpOpTy->isFloatingPointTy())
         // If operands of an fp-type was compared, this costs +1.
         Cost++;
       return Cost;
     }
   }
   else if (ST->hasVector()) {
     assert (Dst->isVectorTy());
-    unsigned VF = Src->getVectorNumElements();
+    unsigned VF = cast<VectorType>(Src)->getNumElements();
     unsigned NumDstVectors = getNumVectorRegs(Dst);
     unsigned NumSrcVectors = getNumVectorRegs(Src);
 
     if (Opcode == Instruction::Trunc) {
       if (Src->getScalarSizeInBits() == Dst->getScalarSizeInBits())
         return 0; // Check for NOOP conversions.
       return getVectorTruncCost(Src, Dst);
     }
if (!ValTy->isVectorTy()) {
     }
     case Instruction::Select:
       if (ValTy->isFloatingPointTy())
         return 4; // No load on condition for FP - costs a conditional jump.
       return 1; // Load On Condition / Select Register.
     }
   }
   else if (ST->hasVector()) {
-    unsigned VF = ValTy->getVectorNumElements();
+    unsigned VF = cast<VectorType>(ValTy)->getNumElements();
 
     // Called with a compare instruction.
     if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) {
       unsigned PredicateExtraCost = 0;
       if (I != nullptr) {
         // Some predicates cost one or two extra instructions.
         switch (cast<CmpInst>(I)->getPredicate()) {
         case CmpInst::Predicate::ICMP_NE:
return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                              Alignment, AddressSpace,
                                              UseMaskForCond, UseMaskForGaps);
   assert(isa<VectorType>(VecTy) &&
          "Expect a vector type for interleaved memory op");
 
   // Return the ceiling of dividing A by B.
   auto ceil = [](unsigned A, unsigned B) { return (A + B - 1) / B; };
 
-  unsigned NumElts = VecTy->getVectorNumElements();
+  unsigned NumElts = cast<VectorType>(VecTy)->getNumElements();
   assert(Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor");
   unsigned VF = NumElts / Factor;
   unsigned NumEltsPerVecReg = (128U / getScalarSizeInBits(VecTy));
   unsigned NumVectorMemOps = getNumVectorRegs(VecTy);
   unsigned NumPermutes = 0;
 
   if (Opcode == Instruction::Load) {
     // Loading interleave groups may have gaps, which may mean fewer