[PowerPC][Future] Add initial support for PC Relative addressing to get jump table base address

[NeHuang]

Summary

Add initial support for PCRelative addressing to get jump table base address instead of using TOC.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2913

I think it would be good if we can put a comment above briefly saying what happens when we have PC relative mem ops.

[nemanjai]

LGTM aside from a couple of nits. Feel free to address those on the commit.

llvm/test/CodeGen/PowerPC/jump-table.ll

13 ↗

(On Diff #250805)

I think it would be useful to show how the base address is used as well. Please add checks for at least all the instructions until the bctr

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2913

Also, remove this from the AIX block as there is no PC-Rel on AIX.

[anil9]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2598–2599

The naming of the SDNodes is not consistent

ConstPoolNode/ GSDN / JT

[NeHuang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2598–2599

SDNodes GSDN and JT were following the same name convention in "PPCTargetLowering::LowerGlobalAddress" and "PPCTargetLowering::LowerJumpTable", however "ConstPoolNode" is different from the name in "LowerConstantPool"

As the code design here has been updated based on nemanja's suggestion in https://reviews.llvm.org/D76294, we can either change the naming for "ConstPoolNode" or apply similar new design here.

[NeHuang]

Addressed review comment.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 
 /// Returns true if this address is a PC Relative address.
 /// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
 /// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
 bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
   // This is a materialize PC Relative node. Always select this as PC Relative.
   Base = N;
   if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
     return true;
   if (ConstantPoolSDNode *CPN = dyn_cast<ConstantPoolSDNode>(N))
     if (CPN->getTargetFlags() & PPCII::MO_PCREL_FLAG)
       return true;
   if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(N))
     if (GAN->getTargetFlags() & PPCII::MO_PCREL_FLAG)
       return true;
+  if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(N))
+    if (JT->getTargetFlags() & PPCII::MO_PCREL_FLAG)
+      return true;
   return false;
 }
 
 /// Returns true if we should use a direct load into vector instruction
 /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
 static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
 
   // If there are any other uses other than scalar to vector, then we should
default:
     return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
   }
 }
 
 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
 
+  // isUsingPCRelativeCalls() returns true when PCRelative is enabled
+  if (Subtarget.isUsingPCRelativeCalls()) {
+    SDLoc DL(JT);
+    EVT Ty = getPointerTy(DAG.getDataLayout());
+    SDValue GA =
+        DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
+    SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
+    return MatAddr;
+  }
+
   // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
     return getTOCEntry(DAG, SDLoc(JT), GA);
   }
 
   unsigned MOHiFlag, MOLoFlag;
   bool IsPIC = isPositionIndependent();
   getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
 

llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-R
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-use-absolute-jumptables \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-A
+
+; This test checks for getting relative and absolute jump table base address
+; using PC Relative addressing.
+
+define dso_local signext i32 @jumptable(i32 signext %param) {
+; CHECK-R-LABEL: jumptable:
+; CHECK-R:       # %bb.1: # %entry
+; CHECK-R-NEXT:    rldic r4, r4
+; CHECK-R-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
+; CHECK-R-NEXT:    lwax r4, r4, r5
+; CHECK-R-NEXT:    add r4, r4, r5
+; CHECK-R-NEXT:    mtctr r4
+; CHECK-R-NEXT:    bctr
+; CHECK-A-LABEL: jumptable:
+; CHECK-A:       # %bb.1: # %entry
+; CHECK-A-NEXT:    rldic r4, r4
+; CHECK-A-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
+; CHECK-A-NEXT:    ldx r4, r4, r5
+; CHECK-A-NEXT:    mtctr r4
+; CHECK-A-NEXT:    bctr
+
+entry:
+  switch i32 %param, label %sw.default [
+    i32 1, label %return
+    i32 2, label %sw.bb1
+    i32 3, label %sw.bb2
+    i32 4, label %sw.bb3
+    i32 20, label %sw.bb4
+  ]
+
+sw.bb1:                                           ; preds = %entry
+  br label %return
+
+sw.bb2:                                           ; preds = %entry
+  br label %return
+
+sw.bb3:                                           ; preds = %entry
+  br label %return
+
+sw.bb4:                                           ; preds = %entry
+  br label %return
+
+sw.default:                                       ; preds = %entry
+  br label %return
+
+return:  ; preds = %entry, %sw.default, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1
+  %retval.0 = phi i32 [ -1, %sw.default ], [ 400, %sw.bb4 ], [ 16, %sw.bb3 ],
+                      [ 9, %sw.bb2 ], [ 4, %sw.bb1 ], [ %param, %entry ]
+  ret i32 %retval.0
+}