[PowerPC][Future] Add initial support for PC Relative addressing to get block address

[NeHuang]

Summary

Add initial support for PCRelative addressing to get block address instead of using TOC.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2953

I think it would be good if we can put a comment above briefly saying what happens when we have PC relative mem ops.

[nemanjai]

LGTM aside from some nits that should be easily addressable on the commit.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2601

This is starting to get unnecessary. There is no reason to have all the different bool variables.
Something like this might be more readable:

  bool ValidPCRelNode = false;
#define VALIDATE_PCREL_NODE(TYPE)                                              \
  {                                                                            \
    TYPE *PCRelCand = dyn_cast<TYPE>(N);                                       \
    if (PCRelCand && PCRelCand->getTargetFlags() == PPCII::MO_PCREL_FLAG)      \
      ValidPCRelNode = true;                                                   \
  }
  VALIDATE_PCREL_NODE(ConstantPoolSDNode);
  VALIDATE_PCREL_NODE(GlobalAddressSDNode);
  VALIDATE_PCREL_NODE(JumpTableSDNode);
  VALIDATE_PCREL_NODE(BlockAddressSDNode);
  if (ValidPCRelNode) {
    Base = N;
    return true;
  }
  return false;
#undef VALIDATE_PCREL_NODE

Or define a template such as:

template <typename Ty> static bool isValidPCRelNode(SDValue N) {
  Ty *PCRelCand = dyn_cast<Ty>(N);
  return PCRelCand && PCRelCand->getTargetFlags() == PPCII::MO_PCREL_FLAG;
}

And then this function is just:

if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
    isValidPCRelNode<GlobalAddressSDNode>(N) ||
    isValidPCRelNode<JumpTableSDNode>(N) ||
    isValidPCRelNode<BlockAddressSDNode>(N)) {
  Base = N;
  return true;
}
return false;

My preference being for the latter.

2953

Remove this from the AIX block as there is no PC-Rel on AIX.

[NeHuang]

Address review comment

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
 
   // Otherwise, do it the hard way, using R0 as the base register.
   Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
                          N.getValueType());
   Index = N;
   return true;
 }
 
+template <typename Ty> static bool isValidPCRelNode(SDValue N) {
+  Ty *PCRelCand = dyn_cast<Ty>(N);
+  return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
+}
+
 /// Returns true if this address is a PC Relative address.
 /// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
 /// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
 bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
   // This is a materialize PC Relative node. Always select this as PC Relative.
   Base = N;
   if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
     return true;
-  if (ConstantPoolSDNode *CPN = dyn_cast<ConstantPoolSDNode>(N))
-    if (CPN->getTargetFlags() & PPCII::MO_PCREL_FLAG)
-      return true;
-  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(N))
-    if (GAN->getTargetFlags() & PPCII::MO_PCREL_FLAG)
-      return true;
-  if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(N))
-    if (JT->getTargetFlags() & PPCII::MO_PCREL_FLAG)
-      return true;
+  if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
+      isValidPCRelNode<GlobalAddressSDNode>(N) ||
+      isValidPCRelNode<JumpTableSDNode>(N) ||
+      isValidPCRelNode<BlockAddressSDNode>(N))
   return false;
 }
 
 /// Returns true if we should use a direct load into vector instruction
 /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
 static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
 
   // If there are any other uses other than scalar to vector, then we should

 }
 
 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
                                              SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
   const BlockAddress *BA = BASDN->getBlockAddress();
 
+  // isUsingPCRelativeCalls() returns true when PCRelative is enabled
+  if (Subtarget.isUsingPCRelativeCalls()) {
+    SDLoc DL(BASDN);
+    EVT Ty = getPointerTy(DAG.getDataLayout());
+    SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
+                                           PPCII::MO_PCREL_FLAG);
+    SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
+    return MatAddr;
+  }
+
   // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
   // The actual BlockAddress is stored in the TOC.
   if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
     return getTOCEntry(DAG, SDLoc(BASDN), GA);
   }
 
   // 32-bit position-independent ELF stores the BlockAddress in the .got.
   if (Subtarget.is32BitELFABI() && isPositionIndependent())
     return getTOCEntry(
         DAG, SDLoc(BASDN),

llvm/test/CodeGen/PowerPC/pcrel-block-address.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s
+define dso_local void @blockaddress() {
+; CHECK-LABEL: blockaddress:
+; CHECK:       # %bb.0: # %entry
+; CHECK:       paddi r3, 0, .Ltmp0@PCREL, 1
+; CHECK:       bl helper@notoc
+entry:
+  tail call void @helper(i8* blockaddress(@blockaddress, %label))
+  br label %label
+
+label:                                            ; preds = %entry
+  ret void
+}
+
+declare void @helper(i8*)