[RISCV] Correct the CallPreservedMask for the function call in an interrupt handler

[shiva0217]

Summary

The patch fix the issue mentioned in https://bugs.llvm.org/show_bug.cgi?id=42984.

CallPreservedMask is used to describe the register liveness after a function call. The function call in an interrupt handler should use the same CallPreservedMask as normal functions. So that only callee save registers can live through the function call.

[lenary]

LGTM. it now makes more sense why getCallPreservedMask and getCalleeSavedRegs are not direct inverses of each other.

[lenary]

@shiva0217 This is probably a fix that needs backporting to the 10.0 branch. I'll let alex make the final call on that though.

[luismarques]

llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll

10

Typo "funciton".

[shiva0217]

Update the patch to fix the typo.

[shiva0217]

Hi @lenary and @luismarques,
Thanks for the review.

[lenary]

@shiva0217 I see you've closed this revision - has it landed, or not yet?

[shiva0217]

Hi @lenary,

The patch has landed with https://github.com/llvm/llvm-project/commit/1cae2f9d192c69833e22684ca338660942ab464e. I forgot to add the "Differential Revision:" in the commit message, so I closed the revision manually. Sorry for the inconvenience.

[asb]

@hans this patch fixes a reported bug https://bugs.llvm.org/show_bug.cgi?id=42984 and is non-invasive. I'd be in favour of cherry-picking for 10.0 if you're ok with that.

[hans]

In D74596#1884474, @asb wrote:

@hans this patch fixes a reported bug https://bugs.llvm.org/show_bug.cgi?id=42984 and is non-invasive. I'd be in favour of cherry-picking for 10.0 if you're ok with that.

Sounds good, pushed as 4bcdac8d762794d822819eb6d207a0630c345d0b.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
 const uint32_t *
 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID /*CC*/) const {
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
-  if (MF.getFunction().hasFnAttribute("interrupt")) {
-    if (Subtarget.hasStdExtD())
-      return CSR_XLEN_F64_Interrupt_RegMask;
-    if (Subtarget.hasStdExtF())
-      return CSR_XLEN_F32_Interrupt_RegMask;
-    return CSR_Interrupt_RegMask;
-  }
 
   switch (Subtarget.getTargetABI()) {
   default:
     llvm_unreachable("Unrecognized ABI");
   case RISCVABI::ABI_ILP32:
   case RISCVABI::ABI_LP64:
     return CSR_ILP32_LP64_RegMask;
   case RISCVABI::ABI_ILP32F:
   case RISCVABI::ABI_LP64F:
     return CSR_ILP32F_LP64F_RegMask;
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:
     return CSR_ILP32D_LP64D_RegMask;
   }
 }

llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-F
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-FD
+;
+; The test case check that the function call in an interrupt handler will use
+; the correct CallPreservedMask as normal function. So only callee saved
+; registers could live through the function call.
+
+define dso_local void @handler() nounwind {
+; CHECK-RV32-LABEL: handler:
+; CHECK-RV32:       # %bb.0: # %entry
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw ra, 12(sp)
+; CHECK-RV32-NEXT:    sw s0, 8(sp)
+; CHECK-RV32-NEXT:    lui a0, 2
+; CHECK-RV32-NEXT:    addi a0, a0, 4
+; CHECK-RV32-NEXT:    call read
+; CHECK-RV32-NEXT:    mv s0, a0
+; CHECK-RV32-NEXT:    call callee
+; CHECK-RV32-NEXT:    mv a0, s0
+; CHECK-RV32-NEXT:    lw s0, 8(sp)
+; CHECK-RV32-NEXT:    lw ra, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    tail write
+;
+; CHECK-RV32-F-LABEL: handler:
+; CHECK-RV32-F:       # %bb.0: # %entry
+; CHECK-RV32-F-NEXT:    addi sp, sp, -16
+; CHECK-RV32-F-NEXT:    sw ra, 12(sp)
+; CHECK-RV32-F-NEXT:    sw s0, 8(sp)
+; CHECK-RV32-F-NEXT:    lui a0, 2
+; CHECK-RV32-F-NEXT:    addi a0, a0, 4
+; CHECK-RV32-F-NEXT:    call read
+; CHECK-RV32-F-NEXT:    mv s0, a0
+; CHECK-RV32-F-NEXT:    call callee
+; CHECK-RV32-F-NEXT:    mv a0, s0
+; CHECK-RV32-F-NEXT:    lw s0, 8(sp)
+; CHECK-RV32-F-NEXT:    lw ra, 12(sp)
+; CHECK-RV32-F-NEXT:    addi sp, sp, 16
+; CHECK-RV32-F-NEXT:    tail write
+;
+; CHECK-RV32-FD-LABEL: handler:
+; CHECK-RV32-FD:       # %bb.0: # %entry
+; CHECK-RV32-FD-NEXT:    addi sp, sp, -16
+; CHECK-RV32-FD-NEXT:    sw ra, 12(sp)
+; CHECK-RV32-FD-NEXT:    sw s0, 8(sp)
+; CHECK-RV32-FD-NEXT:    lui a0, 2
+; CHECK-RV32-FD-NEXT:    addi a0, a0, 4
+; CHECK-RV32-FD-NEXT:    call read
+; CHECK-RV32-FD-NEXT:    mv s0, a0
+; CHECK-RV32-FD-NEXT:    call callee
+; CHECK-RV32-FD-NEXT:    mv a0, s0
+; CHECK-RV32-FD-NEXT:    lw s0, 8(sp)
+; CHECK-RV32-FD-NEXT:    lw ra, 12(sp)
+; CHECK-RV32-FD-NEXT:    addi sp, sp, 16
+; CHECK-RV32-FD-NEXT:    tail write
+entry:
+  %call = tail call i32 @read(i32 8196)
+  tail call void bitcast (void (...)* @callee to void ()*)()
+  tail call void @write(i32 %call)
+  ret void
+}
+
+declare i32 @read(i32)
+declare void @callee(...)
+declare void @write(i32)