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This LG to me.
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
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18568–18587 | Can you precommit this NFC part? | |
18580–18581 | I'm guessing the order doesn't matter? |
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
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18580–18581 | Unfortunately it matters. ARM makes legal v1i32 but does worse job for i32. If I change the order that leads to obvious regression in ARM Neon. |
llvm/test/CodeGen/ARM/vext.ll | ||
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277 | Please can pre-commit this regenerated file to fix the whitespace changes separately? |
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
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18580–18581 | Sorry, it is aarch64, not arm. |
I'm guessing the order doesn't matter?
If ISD::EXTRACT_VECTOR_ELT is legal, we'll transform
single-element ISD::EXTRACT_SUBVECTOR into ISD::EXTRACT_VECTOR_ELT later anyway?