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Allow combining of extract_subvector to extract element
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Authored by rampitec on Jan 21 2020, 12:39 PM.

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rampitec created this revision.Jan 21 2020, 12:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 21 2020, 12:39 PM
lebedev.ri accepted this revision.Jan 22 2020, 12:23 AM
lebedev.ri added reviewers: spatel, deadalnix.
lebedev.ri added a subscriber: lebedev.ri.

This LG to me.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
18572–18590

Can you precommit this NFC part?

18591–18592

I'm guessing the order doesn't matter?
If ISD::EXTRACT_VECTOR_ELT is legal, we'll transform
single-element ISD::EXTRACT_SUBVECTOR into ISD::EXTRACT_VECTOR_ELT later anyway?

This revision is now accepted and ready to land.Jan 22 2020, 12:23 AM
rampitec marked an inline comment as done.Jan 22 2020, 12:30 AM
rampitec added inline comments.
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
18591–18592

Unfortunately it matters. ARM makes legal v1i32 but does worse job for i32. If I change the order that leads to obvious regression in ARM Neon.

RKSimon added inline comments.Jan 22 2020, 12:58 AM
llvm/test/CodeGen/ARM/vext.ll
294

Please can pre-commit this regenerated file to fix the whitespace changes separately?

rampitec marked an inline comment as done.Jan 22 2020, 8:11 AM
rampitec added inline comments.
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
18591–18592

Sorry, it is aarch64, not arm.

rampitec updated this revision to Diff 239622.Jan 22 2020, 9:21 AM
rampitec marked 2 inline comments as done.

Pre-commited NFC changes and rebased.

RKSimon accepted this revision.Jan 23 2020, 2:28 AM

LGTM, cheers

This revision was automatically updated to reflect the committed changes.