[X86] Insert wait instruction after X87 instructions which could raise float-point exception.

[LiuChen3]

Summary

This patch insert wait after X87 instruction to make sure floating-point exceptions synchronized.

The rule is simple:

1. If the X87 instruction don't raise float exception nor is a load/store instruction, or is a x87 control instruction, don't insert wait.
2. If the X87 instruction is an instruction which the following instruction is an X87 exception synchronizing X87 instruction, don't insert wait.
3. For other situations, insert wait instruction.

FNINIT, FNSTENV, FNSAVE, FNSTSW, FNSTCW, and FNCLEX instructions don't check for pending unmasked
exceptions, they don't synchronize exceptions.

This patch also modify some mayRaiseFPException flag which set in D68854. In D68854, we set mayRaiseFPException =1
in each X87 instruction which could raise Floating-Point Exceptions. Now, we don't set this flag to 1 in instruction which
only have #IS float-point Exceptions.

[LiuChen3]

Fix format problems.

[craig.topper]

llvm/lib/Target/X86/X86InsertWait.cpp

25

This is unused

26

This is unused

40

This is unused. Those were just the obvious ones. Please prune to just what's necessary.

[LiuChen3]

llvm/lib/Target/X86/X86InsertWait.cpp

40

Sorry for adding redundant header files. Thanks to point out.

[LiuChen3]

remove redundant header files.

[craig.topper]

LGTM

llvm/lib/Target/X86/CMakeLists.txt

set(sources
   X86SpeculativeLoadHardening.cpp
   X86Subtarget.cpp
   X86TargetMachine.cpp
   X86TargetObjectFile.cpp
   X86TargetTransformInfo.cpp
   X86VZeroUpper.cpp
   X86WinAllocaExpander.cpp
   X86WinEHState.cpp
+  X86InsertWait.cpp
   )
 
 add_llvm_target(X86CodeGen ${sources})
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)

llvm/lib/Target/X86/X86.h

 
 /// This pass ensures instructions featuring a memory operand
 /// have distinctive <LineNumber, Discriminator> (with respect to eachother)
 FunctionPass *createX86DiscriminateMemOpsPass();
 
 /// This pass applies profiling information to insert cache prefetches.
 FunctionPass *createX86InsertPrefetchPass();
 
+/// This pass insert wait instruction after X87 instructions which could raise
+/// fp exceptions when strict-fp enabled.
+FunctionPass *createX86InsertX87waitPass();
+
 InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
                                                   X86Subtarget &,
                                                   X86RegisterBankInfo &);
 
 FunctionPass *createX86SpeculativeLoadHardeningPass();
 
 void initializeEvexToVexInstPassPass(PassRegistry &);
 void initializeFixupBWInstPassPass(PassRegistry &);

llvm/lib/Target/X86/X86FloatingPoint.cpp

void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
 
   // NotTOS - The register which is not on the top of stack...
   unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
 
   // Replace the old instruction with a new instruction
   MBB->remove(&*I++);
   I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
 
+  if (!MI.mayRaiseFPException())
+    I->setFlag(MachineInstr::MIFlag::NoFPExcept);
+
   // If both operands are killed, pop one off of the stack in addition to
   // overwriting the other one.
   if (KillsOp0 && KillsOp1 && Op0 != Op1) {
     assert(!updateST0 && "Should have updated other operand!");
     popStackAfter(I);   // Pop the top of stack
   }
 
   // Update stack information so that we know the destination register is now on

llvm/lib/Target/X86/X86InsertWait.cpp

+//- X86Insertwait.cpp - Insert wait instruction after constrained X87
+//instruction -//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the pass which insert x86 wait instructions after each
+// X87 instructions when strict float is enabled.
+//
+// The logic to insert a wait instruction after an X87 instruction is as below:
+// 1. If the X87 instruction don't raise float exception nor is a load/store
+//    instruction, or is a x87 control instruction, don't insert wait.
+// 2. If the X87 instruction is an instruction which the following instruction
+//    is an X87 exception synchronizing X87 instruction, don't insert wait.
+// 3. For other situations, insert wait instruction.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include "X86InstrInfo.h"
+#include "X86Subtarget.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/Function.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+
+using namespace llvm;
+
+#define DEBUG_TYPE "x86-insert-wait"
+
+namespace {
+
+class WaitInsert : public MachineFunctionPass {
+public:
+  static char ID;
+
+  WaitInsert() : MachineFunctionPass(ID) {}
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override {
+    return "X86 insert wait instruction";
+  }
+
+private:
+  const TargetInstrInfo *TII; // Machine instruction info.
+};
+
+} // namespace
+
+char WaitInsert::ID = 0;
+
+FunctionPass *llvm::createX86InsertX87waitPass() { return new WaitInsert(); }
+
+/// Return true if the Reg is X87 register.
+static bool isX87Reg(unsigned Reg) {
+  return (Reg == X86::FPCW || Reg == X86::FPSW ||
+          (Reg >= X86::ST0 && Reg <= X86::ST7));
+}
+
+/// check if the instruction is X87 instruction
+static bool isX87Instruction(MachineInstr &MI) {
+  for (const MachineOperand &MO : MI.operands()) {
+    if (!MO.isReg())
+      continue;
+    if (isX87Reg(MO.getReg()))
+      return true;
+  }
+  return false;
+}
+
+static bool isX87ControlInstruction(MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  case X86::FNINIT:
+  case X86::FLDCW16m:
+  case X86::FNSTCW16m:
+  case X86::FNSTSW16r:
+  case X86::FNSTSWm:
+  case X86::FNCLEX:
+  case X86::FLDENVm:
+  case X86::FSTENVm:
+  case X86::FRSTORm:
+  case X86::FSAVEm:
+  case X86::FINCSTP:
+  case X86::FDECSTP:
+  case X86::FFREE:
+  case X86::FFREEP:
+  case X86::FNOP:
+  case X86::WAIT:
+    return true;
+  default:
+    return false;
+  }
+}
+
+static bool isX87NonWaitingControlInstruction(MachineInstr &MI) {
+  // a few special control instructions don't perform a wait operation
+  switch (MI.getOpcode()) {
+  case X86::FNINIT:
+  case X86::FNSTSW16r:
+  case X86::FNSTSWm:
+  case X86::FNSTCW16m:
+  case X86::FNCLEX:
+    return true;
+  default:
+    return false;
+  }
+}
+
+bool WaitInsert::runOnMachineFunction(MachineFunction &MF) {
+  if (!MF.getFunction().hasFnAttribute(Attribute::StrictFP))
+    return false;
+
+  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
+  TII = ST.getInstrInfo();
+  bool Changed = false;
+
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
+      // Jump non X87 instruction.
+      if (!isX87Instruction(*MI))
+        continue;
+      // If the instruction instruction neither has float exception
+      // nor is a load instruction, or the instruction is x87 control
+      // instruction, do not insert wait.
+      if (!(MI->mayRaiseFPException() || MI->mayLoadOrStore()) ||
+          isX87ControlInstruction(*MI))
+        continue;
+      // If the following instruction is an X87 instruction and isn't an X87
+      // non-waiting control instruction, we can omit insert wait instruction.
+      MachineBasicBlock::iterator AfterMI = std::next(MI);
+      if (AfterMI != MBB.end() && isX87Instruction(*AfterMI) &&
+          !isX87NonWaitingControlInstruction(*AfterMI))
+        continue;
+
+      BuildMI(MBB, AfterMI, MI->getDebugLoc(), TII->get(X86::WAIT));
+      LLVM_DEBUG(dbgs() << "\nInsert wait after:\t" << *MI);
+      // Jump the newly inserting wait
+      ++MI;
+      Changed = true;
+    }
+  }
+  return Changed;
+}

llvm/lib/Target/X86/X86InstrFPStack.td

 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
 }
 
 // FP Stack manipulation instructions.
 let SchedRW = [WriteMove], Uses = [FPCW] in {
 def LD_Frr   : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
 def ST_Frr   : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;
 def ST_FPrr  : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">;
+let mayRaiseFPException = 0 in
 def XCH_F    : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;
 }
 
 // Floating point constant loads.
 let SchedRW = [WriteZero], Uses = [FPCW] in {
 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
                 [(set RFP32:$dst, fpimm0)]>;
 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
                 [(set RFP32:$dst, fpimm1)]>;
 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
                 [(set RFP64:$dst, fpimm0)]>;
 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
                 [(set RFP64:$dst, fpimm1)]>;
 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
                 [(set RFP80:$dst, fpimm0)]>;
 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
                 [(set RFP80:$dst, fpimm1)]>;
 }
 
-let SchedRW = [WriteFLD0], Uses = [FPCW] in
+let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in
 def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
 
-let SchedRW = [WriteFLD1], Uses = [FPCW] in
+let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in
 def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
 
-let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW] in {
+let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in {
 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;
 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
 } // SchedRW
 
 // Floating point compares.

llvm/lib/Target/X86/X86TargetMachine.cpp

void X86PassConfig::addPreEmitPass() {
   if (getOptLevel() != CodeGenOpt::None) {
     addPass(createX86FixupBWInsts());
     addPass(createX86PadShortFunctions());
     addPass(createX86FixupLEAs());
     addPass(createX86EvexToVexInsts());
   }
   addPass(createX86DiscriminateMemOpsPass());
   addPass(createX86InsertPrefetchPass());
+  addPass(createX86InsertX87waitPass());
 }
 
 void X86PassConfig::addPreEmitPass2() {
   const Triple &TT = TM->getTargetTriple();
   const MCAsmInfo *MAI = TM->getMCAsmInfo();
 
   addPass(createX86RetpolineThunksPass());
 

llvm/test/CodeGen/X86/O0-pipeline.ll

 ; CHECK-NEXT:       Prologue/Epilogue Insertion & Frame Finalization
 ; CHECK-NEXT:       Post-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       X86 pseudo instruction expansion pass
 ; CHECK-NEXT:       Analyze Machine Code For Garbage Collection
 ; CHECK-NEXT:       X86 Indirect Branch Tracking
 ; CHECK-NEXT:       X86 vzeroupper inserter
 ; CHECK-NEXT:       X86 Discriminate Memory Operands
 ; CHECK-NEXT:       X86 Insert Cache Prefetches
+; CHECK-NEXT:       X86 insert wait instruction
 ; CHECK-NEXT:       Contiguously Lay Out Funclets
 ; CHECK-NEXT:       StackMap Liveness Analysis
 ; CHECK-NEXT:       Live DEBUG_VALUE analysis
 ; CHECK-NEXT:       Insert fentry calls
 ; CHECK-NEXT:       Insert XRay ops
 ; CHECK-NEXT:       Implement the 'patchable-function' attribute
 ; CHECK-NEXT:       X86 Retpoline Thunks
 ; CHECK-NEXT:       Check CFA info and insert CFI instructions if needed
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       X86 Assembly Printer
 ; CHECK-NEXT:       Free MachineFunction
 
 define void @f() {
   ret void
 }

llvm/test/CodeGen/X86/O3-pipeline.ll

 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       X86 Byte/Word Instruction Fixup
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       X86 Atom pad short functions
 ; CHECK-NEXT:       X86 LEA Fixup
 ; CHECK-NEXT:       Compressing EVEX instrs to VEX encoding when possible
 ; CHECK-NEXT:       X86 Discriminate Memory Operands
 ; CHECK-NEXT:       X86 Insert Cache Prefetches
+; CHECK-NEXT:       X86 insert wait instruction
 ; CHECK-NEXT:       Contiguously Lay Out Funclets
 ; CHECK-NEXT:       StackMap Liveness Analysis
 ; CHECK-NEXT:       Live DEBUG_VALUE analysis
 ; CHECK-NEXT:       Insert fentry calls
 ; CHECK-NEXT:       Insert XRay ops
 ; CHECK-NEXT:       Implement the 'patchable-function' attribute
 ; CHECK-NEXT:       X86 Retpoline Thunks
 ; CHECK-NEXT:       Check CFA info and insert CFI instructions if needed
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       X86 Assembly Printer
 ; CHECK-NEXT:       Free MachineFunction
 
 define void @f() {
   ret void
 }

llvm/test/CodeGen/X86/constrained-fp80-trunc-ext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O3 -mtriple=x86_64-gnu-linux < %s | FileCheck %s
 
 define x86_fp80 @constrained_fpext_f32_as_fp80(float %mem) #0 {
 ; CHECK-LABEL: constrained_fpext_f32_as_fp80:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movss %xmm0, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    flds -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 entry:
   %ext = call x86_fp80 @llvm.experimental.constrained.fpext.f80.f32(
             float %mem,
             metadata !"fpexcept.strict") #0
   ret x86_fp80 %ext
 }
 
 define float @constrained_fptrunc_f80_to_f32(x86_fp80 %reg) #0 {
 ; CHECK-LABEL: constrained_fptrunc_f80_to_f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fstps -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    retq
   %trunc = call float @llvm.experimental.constrained.fptrunc.f32.f80(
              x86_fp80 %reg,
              metadata !"round.dynamic",
              metadata !"fpexcept.strict") #0
   ret float %trunc
 }
 
 define x86_fp80 @constrained_fpext_f64_to_f80(double %mem) #0 {
 ; CHECK-LABEL: constrained_fpext_f64_to_f80:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movsd %xmm0, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 entry:
   %ext = call x86_fp80 @llvm.experimental.constrained.fpext.f80.f64(
             double %mem,
             metadata !"fpexcept.strict") #0
   ret x86_fp80 %ext
 }
 
 define double @constrained_fptrunc_f80_to_f64(x86_fp80 %reg) #0 {
 ; CHECK-LABEL: constrained_fptrunc_f80_to_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fstpl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    retq
   %trunc = call double @llvm.experimental.constrained.fptrunc.f64.f80(
              x86_fp80 %reg,
              metadata !"round.dynamic",
              metadata !"fpexcept.strict") #0
   ret double %trunc
 }
 
 attributes #0 = { strictfp }
 
 declare x86_fp80 @llvm.experimental.constrained.fpext.f80.f32(float, metadata)
 declare x86_fp80 @llvm.experimental.constrained.fpext.f80.f64(double, metadata)
 declare float @llvm.experimental.constrained.fptrunc.f32.f80(x86_fp80, metadata, metadata)
 declare double @llvm.experimental.constrained.fptrunc.f64.f80(x86_fp80, metadata, metadata)

llvm/test/CodeGen/X86/fp-intrinsics.ll

 ;   return 1.0/10.0;
 ; }
 ;
 define double @f1() #0 {
 ; X87-LABEL: f1:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fld1
 ; X87-NEXT:    fdivs {{\.LCPI.*}}
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f1:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    divsd {{\.LCPI.*}}, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f1:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    divsd {{.*}}(%rip), %xmm0

 ;   return a - 0;
 ; }
 ;
 define double @f2(double %a) #0 {
 ; X87-LABEL: f2:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fldz
 ; X87-NEXT:    fsubrl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f2:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    xorpd %xmm1, %xmm1
 ; X86-SSE-NEXT:    subsd %xmm1, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f2:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    xorpd %xmm1, %xmm1
 ; SSE-NEXT:    subsd %xmm1, %xmm0

 ; X87-LABEL: f3:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fldz
 ; X87-NEXT:    fchs
 ; X87-NEXT:    fld %st(0)
 ; X87-NEXT:    fsubl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fmull {{[0-9]+}}(%esp)
 ; X87-NEXT:    fsubrp %st, %st(1)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f3:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    movapd %xmm0, %xmm1
 ; X86-SSE-NEXT:    subsd {{[0-9]+}}(%esp), %xmm1
 ; X86-SSE-NEXT:    mulsd {{[0-9]+}}(%esp), %xmm1
 ; X86-SSE-NEXT:    subsd %xmm1, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f3:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
 ; SSE-NEXT:    movapd %xmm2, %xmm3

 ;   return a;
 ; }
 ;
 ;
 define double @f4(i32 %n, double %a) #0 {
 ; X87-LABEL: f4:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X87-NEXT:    jle .LBB3_2
 ; X87-NEXT:  # %bb.1: # %if.then
 ; X87-NEXT:    fld1
 ; X87-NEXT:    faddp %st, %st(1)
+; X87-NEXT:    wait
 ; X87-NEXT:  .LBB3_2: # %if.end
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f4:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    jle .LBB3_2
 ; X86-SSE-NEXT:  # %bb.1: # %if.then
 ; X86-SSE-NEXT:    addsd {{\.LCPI.*}}, %xmm0
 ; X86-SSE-NEXT:  .LBB3_2: # %if.end
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f4:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    testl %edi, %edi
 ; SSE-NEXT:    jle .LBB3_2

 }
 
 ; Verify that sqrt(42.0) isn't simplified when the rounding mode is unknown.
 define double @f5() #0 {
 ; X87-LABEL: f5:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fsqrt
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f5:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    sqrtsd %xmm0, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f5:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    sqrtsd %xmm0, %xmm0

 ; X87-LABEL: f6:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $28, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 32
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll pow
 ; X87-NEXT:    addl $28, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f6:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $28, %esp

 ; Verify that powi(42.1, 3) isn't simplified when the rounding mode is unknown.
 define double @f7() #0 {
 ; X87-LABEL: f7:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    movl $3, {{[0-9]+}}(%esp)
 ; X87-NEXT:    calll __powidf2
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f7:
 ; X86-SSE:       # %bb.0: # %entry

 ; Verify that sin(42.0) isn't simplified when the rounding mode is unknown.
 define double @f8() #0 {
 ; X87-LABEL: f8:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll sin
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f8:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that cos(42.0) isn't simplified when the rounding mode is unknown.
 define double @f9() #0 {
 ; X87-LABEL: f9:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll cos
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f9:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that exp(42.0) isn't simplified when the rounding mode is unknown.
 define double @f10() #0 {
 ; X87-LABEL: f10:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll exp
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f10:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that exp2(42.1) isn't simplified when the rounding mode is unknown.
 define double @f11() #0 {
 ; X87-LABEL: f11:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll exp2
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f11:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that log(42.0) isn't simplified when the rounding mode is unknown.
 define double @f12() #0 {
 ; X87-LABEL: f12:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll log
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f12:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that log10(42.0) isn't simplified when the rounding mode is unknown.
 define double @f13() #0 {
 ; X87-LABEL: f13:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll log10
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f13:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that log2(42.0) isn't simplified when the rounding mode is unknown.
 define double @f14() #0 {
 ; X87-LABEL: f14:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll log2
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f14:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; Verify that rint(42.1) isn't simplified when the rounding mode is unknown.
 define double @f15() #0 {
 ; X87-LABEL: f15:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll rint
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f15:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 ; unknown.
 define double @f16() #0 {
 ; X87-LABEL: f16:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{\.LCPI.*}}
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll nearbyint
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f16:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define double @f19() #0 {
 ; X87-LABEL: f19:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $28, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 32
 ; X87-NEXT:    flds {{\.LCPI.*}}
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    movl $1072693248, {{[0-9]+}}(%esp) # imm = 0x3FF00000
 ; X87-NEXT:    movl $0, (%esp)
 ; X87-NEXT:    calll fmod
 ; X87-NEXT:    addl $28, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f19:

 ; FIXME: The SSE/AVX code does not raise an invalid exception for all values
 ; that don't fit in i8.
 define i8 @f20s8(double %x) #0 {
 ; X87-LABEL: f20s8:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 12
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; FIXME: The SSE/AVX code does not raise an invalid exception for all values
 ; that don't fit in i16.
 define i16 @f20s16(double %x) #0 {
 ; X87-LABEL: f20s16:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 12
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax

 ; unknown.
 ; Verify that no gross errors happen.
 define i32 @f20s(double %x) #0 {
 ; X87-LABEL: f20s:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 12
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw (%esp)
 ; X87-NEXT:    movzwl (%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw (%esp)
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; Verify that no gross errors happen.
 ; FIXME: This code generates spurious inexact exceptions.
 define i64 @f20s64(double %x) #0 {
 ; X87-LABEL: f20s64:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $20, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 24
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X87-NEXT:    addl $20, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f20s64:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $20, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 24
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-SSE-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; X87-LABEL: f20s128:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %edi
 ; X87-NEXT:    pushl %esi
 ; X87-NEXT:    subl $36, %esp
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    calll __fixdfti
 ; X87-NEXT:    subl $4, %esp
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %edi

 ; FIXME: The SSE/AVX code does not raise an invalid exception for all values
 ; that don't fit in i8.
 define i8 @f20u8(double %x) #0 {
 ; X87-LABEL: f20u8:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 12
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; FIXME: The SSE/AVX code does not raise an invalid exception for all values
 ; that don't fit in i16.
 define i16 @f20u16(double %x) #0 {
 ; X87-LABEL: f20u16:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 12
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw (%esp)
 ; X87-NEXT:    movzwl (%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw (%esp)
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; FIXME: The X87/SSE/AVX1 code does not raise an invalid exception for all
 ; values that don't fit in i32. The AVX512 code does.
 define i32 @f20u(double %x) #0 {
 ; X87-LABEL: f20u:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $20, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 24
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; FIXME: This code generates spurious inexact exceptions.
 define i64 @f20u64(double %x) #0 {
 ; X87-LABEL: f20u64:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $20, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 24
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{\.LCPI.*}}
+; X87-NEXT:    wait
 ; X87-NEXT:    xorl %edx, %edx
 ; X87-NEXT:    fcomi %st(1), %st
+; X87-NEXT:    wait
 ; X87-NEXT:    setbe %dl
 ; X87-NEXT:    fldz
 ; X87-NEXT:    fxch %st(1)
 ; X87-NEXT:    fcmovnbe %st(1), %st
 ; X87-NEXT:    fstp %st(1)
 ; X87-NEXT:    fsubrp %st, %st(1)
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X87-NEXT:    shll $31, %edx

 ; X86-SSE-NEXT:    ja .LBB25_2
 ; X86-SSE-NEXT:  # %bb.1: # %entry
 ; X86-SSE-NEXT:    movapd %xmm2, %xmm1
 ; X86-SSE-NEXT:  .LBB25_2: # %entry
 ; X86-SSE-NEXT:    subsd %xmm1, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    setbe %al
 ; X86-SSE-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-SSE-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; X86-SSE-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    movzbl %al, %edx

 ; X87-LABEL: f20u128:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %edi
 ; X87-NEXT:    pushl %esi
 ; X87-NEXT:    subl $36, %esp
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    calll __fixunsdfti
 ; X87-NEXT:    subl $4, %esp
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %edi

 define float @f21() #0 {
 ; X87-LABEL: f21:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    fldl {{\.LCPI.*}}
 ; X87-NEXT:    fstps (%esp)
 ; X87-NEXT:    flds (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f21:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    cvtsd2ss %xmm0, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f21:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    cvtsd2ss %xmm0, %xmm0
%result = call float @llvm.experimental.constrained.fptrunc.f32.f64(
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define double @f22(float %x) #0 {
 ; X87-LABEL: f22:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f22:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; X86-SSE-NEXT:    cvtss2sd %xmm0, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: f22:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    cvtss2sd %xmm0, %xmm0
 ; SSE-NEXT:    retq

 
 define i32 @f23(double %x) #0 {
 ; X87-LABEL: f23:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll lrint
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f23:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define i32 @f24(float %x) #0 {
 ; X87-LABEL: f24:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstps (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll lrintf
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f24:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define i64 @f25(double %x) #0 {
 ; X87-LABEL: f25:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll llrint
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f25:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define i32 @f27(double %x) #0 {
 ; X87-LABEL: f27:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll lround
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f27:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define i32 @f28(float %x) #0 {
 ; X87-LABEL: f28:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstps (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll lroundf
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f28:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define i64 @f29(double %x) #0 {
 ; X87-LABEL: f29:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll llround
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f29:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 
 define i64 @f30(float %x) #0 {
 ; X87-LABEL: f30:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstps (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll llroundf
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: f30:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp

 define double @sifdb(i8 %x) #0 {
 ; X87-LABEL: sifdb:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: sifdb:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2sd %eax, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: sifdb:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsbl %dil, %eax
 ; SSE-NEXT:    cvtsi2sd %eax, %xmm0

 define double @sifdw(i16 %x) #0 {
 ; X87-LABEL: sifdw:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: sifdw:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2sd %eax, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: sifdw:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movswl %di, %eax
 ; SSE-NEXT:    cvtsi2sd %eax, %xmm0

 define double @sifdi(i32 %x) #0 {
 ; X87-LABEL: sifdi:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: sifdi:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    cvtsi2sdl {{[0-9]+}}(%esp), %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: sifdi:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    cvtsi2sd %edi, %xmm0
 ; SSE-NEXT:    retq

 define float @siffb(i8 %x) #0 {
 ; X87-LABEL: siffb:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: siffb:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2ss %eax, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: siffb:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsbl %dil, %eax
 ; SSE-NEXT:    cvtsi2ss %eax, %xmm0

 define float @siffw(i16 %x) #0 {
 ; X87-LABEL: siffw:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: siffw:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2ss %eax, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: siffw:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movswl %di, %eax
 ; SSE-NEXT:    cvtsi2ss %eax, %xmm0

 define float @siffi(i32 %x) #0 {
 ; X87-LABEL: siffi:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: siffi:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    cvtsi2ssl {{[0-9]+}}(%esp), %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: siffi:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    cvtsi2ss %edi, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: siffi:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtsi2ss %edi, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %result = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define double @sifdl(i64 %x) #0 {
 ; X87-LABEL: sifdl:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fildll {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: sifdl:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fstpl (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: sifdl:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    cvtsi2sd %rdi, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: sifdl:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %result = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define float @siffl(i64 %x) #0 {
 ; X87-LABEL: siffl:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fildll {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: siffl:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fstps (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: siffl:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    cvtsi2ss %rdi, %xmm0
 ; SSE-NEXT:    retq

 define double @uifdb(i8 %x) #0 {
 ; X87-LABEL: uifdb:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uifdb:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2sd %eax, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uifdb:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movzbl %dil, %eax
 ; SSE-NEXT:    cvtsi2sd %eax, %xmm0

 define double @uifdw(i16 %x) #0 {
 ; X87-LABEL: uifdw:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uifdw:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2sd %eax, %xmm0
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uifdw:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movzwl %di, %eax
 ; SSE-NEXT:    cvtsi2sd %eax, %xmm0

 ; X87-LABEL: uifdi:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fildll (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uifdi:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X86-SSE-NEXT:    orpd %xmm0, %xmm1
 ; X86-SSE-NEXT:    subsd %xmm0, %xmm1
 ; X86-SSE-NEXT:    movsd %xmm1, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uifdi:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movl %edi, %eax
 ; SSE-NEXT:    cvtsi2sd %rax, %xmm0

 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    shrl $31, %ecx
 ; X87-NEXT:    fildll (%esp)
 ; X87-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    addl $20, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uifdl:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; X86-SSE-NEXT:    subpd {{\.LCPI.*}}, %xmm0
 ; X86-SSE-NEXT:    movapd %xmm0, %xmm1
 ; X86-SSE-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; X86-SSE-NEXT:    addpd %xmm0, %xmm1
 ; X86-SSE-NEXT:    movlpd %xmm1, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uifdl:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movq %rdi, %xmm1
 ; SSE-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]

 define float @uiffb(i8 %x) #0 {
 ; X87-LABEL: uiffb:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uiffb:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2ss %eax, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uiffb:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movzbl %dil, %eax
 ; SSE-NEXT:    cvtsi2ss %eax, %xmm0

 define float @uiffw(i16 %x) #0 {
 ; X87-LABEL: uiffw:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uiffw:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    cvtsi2ss %eax, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uiffw:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movzwl %di, %eax
 ; SSE-NEXT:    cvtsi2ss %eax, %xmm0

 ; X87-LABEL: uiffi:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 16
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fildll (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uiffi:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X86-SSE-NEXT:    orpd %xmm0, %xmm1
 ; X86-SSE-NEXT:    subsd %xmm0, %xmm1
 ; X86-SSE-NEXT:    xorps %xmm0, %xmm0
 ; X86-SSE-NEXT:    cvtsd2ss %xmm1, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uiffi:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movl %edi, %eax
 ; SSE-NEXT:    cvtsi2ss %rax, %xmm0

 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    shrl $31, %ecx
 ; X87-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X87-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
 ; X87-NEXT:    fstps {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    addl $20, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uiffl:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $20, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 24
 ; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    movlps %xmm0, {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    shrl $31, %eax
 ; X86-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-SSE-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; X86-SSE-NEXT:    fstps {{[0-9]+}}(%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
+; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $20, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uiffl:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movq %rdi, %rax
 ; SSE-NEXT:    shrq %rax

llvm/test/CodeGen/X86/fp-strict-libcalls-msvc32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O3 -mtriple=i686-pc-windows-msvc -mattr=+cmov < %s | FileCheck %s
 
 define float @ceil(float %x) #0 {
 ; CHECK-LABEL: ceil:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _ceil
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.ceil.f32(float %x, metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @cos(float %x) #0 {
 ; CHECK-LABEL: cos:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _cos
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.cos.f32(float %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @exp(float %x) #0 {
 ; CHECK-LABEL: exp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _exp
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.exp.f32(float %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @floor(float %x) #0 {
 ; CHECK-LABEL: floor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _floor
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.floor.f32(float %x, metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @frem(float %x, float %y) #0 {
 ; CHECK-LABEL: frem:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $20, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _fmod
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $20, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.frem.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @log(float %x) #0 {
 ; CHECK-LABEL: log:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _log
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.log.f32(float %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @log10(float %x) #0 {
 ; CHECK-LABEL: log10:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _log10
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.log10.f32(float %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @pow(float %x, float %y) #0 {
 ; CHECK-LABEL: pow:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $20, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _pow
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $20, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.pow.f32(float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @sin(float %x) #0 {
 ; CHECK-LABEL: sin:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    calll _sin
 ; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
   %result = call float @llvm.experimental.constrained.sin.f32(float %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 attributes #0 = { strictfp }
 

llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_oeq_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB0_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB0_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB0_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_oeq_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"oeq",

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ogt_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB1_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB1_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ogt_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_oge_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB2_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB2_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_oge_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_olt_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB3_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB3_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_olt_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ole_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB4_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB4_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ole_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_one_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jne .LBB5_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB5_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_one_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ord_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jnp .LBB6_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB6_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ord_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovnel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ueq_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    je .LBB7_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB7_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ueq_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ugt_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB8_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB8_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ugt_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_uge_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB9_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB9_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_uge_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ult_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB10_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB10_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ult_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ule_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB11_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB11_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ule_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %edi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_une_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB12_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB12_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB12_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_une_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"une",

 ; AVX-64-NEXT:    cmovnpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_uno_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jp .LBB13_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB13_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_uno_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_oeq_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB14_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB14_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB14_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_oeq_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"oeq",

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ogt_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB15_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB15_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ogt_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_oge_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB16_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB16_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_oge_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_olt_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB17_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB17_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_olt_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ole_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB18_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB18_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ole_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_one_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jne .LBB19_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB19_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_one_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ord_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jnp .LBB20_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB20_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ord_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovnel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ueq_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    je .LBB21_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB21_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ueq_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ugt_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB22_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB22_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ugt_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_uge_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB23_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB23_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_uge_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ult_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB24_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB24_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ult_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ule_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB25_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB25_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ule_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %edi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_une_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB26_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB26_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB26_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_une_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"une",

 ; AVX-64-NEXT:    cmovnpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_uno_q:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fucompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jp .LBB27_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB27_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_uno_q:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fucompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_oeq_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB28_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB28_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB28_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_oeq_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"oeq",

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ogt_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB29_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB29_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ogt_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_oge_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB30_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB30_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_oge_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_olt_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB31_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB31_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_olt_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ole_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB32_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB32_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ole_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_one_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jne .LBB33_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB33_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_one_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ord_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jnp .LBB34_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB34_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ord_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovnel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ueq_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    je .LBB35_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB35_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ueq_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ugt_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB36_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB36_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ugt_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_uge_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB37_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB37_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_uge_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ult_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB38_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB38_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ult_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_ule_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB39_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB39_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_ule_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %edi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_une_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB40_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB40_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB40_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_une_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"une",

 ; AVX-64-NEXT:    cmovnpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f32_uno_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jp .LBB41_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB41_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f32_uno_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_oeq_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB42_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB42_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB42_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_oeq_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"oeq",

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ogt_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB43_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB43_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ogt_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_oge_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB44_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB44_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_oge_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_olt_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    ja .LBB45_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB45_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_olt_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmoval %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovbl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ole_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jae .LBB46_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB46_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ole_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovael %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_one_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jne .LBB47_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB47_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_one_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ord_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jnp .LBB48_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB48_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ord_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovnel %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ueq_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    je .LBB49_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB49_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ueq_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ugt_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB50_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB50_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ugt_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_uge_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB51_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB51_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_uge_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovael %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ult_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jb .LBB52_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB52_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ult_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmoval %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_ule_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jbe .LBB53_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB53_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_ule_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovbel %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0

 ; AVX-64-NEXT:    cmovpl %edi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_une_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    jne .LBB54_3
 ; X87-NEXT:  # %bb.1:
 ; X87-NEXT:    jp .LBB54_3
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:  .LBB54_3:
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_une_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovnel %eax, %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"une",

 ; AVX-64-NEXT:    cmovnpl %esi, %eax
 ; AVX-64-NEXT:    retq
 ;
 ; X87-LABEL: test_f64_uno_s:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fcompp
+; X87-NEXT:    wait
 ; X87-NEXT:    fnstsw %ax
 ; X87-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-NEXT:    sahf
 ; X87-NEXT:    jp .LBB55_1
 ; X87-NEXT:  # %bb.2:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ; X87-NEXT:  .LBB55_1:
 ; X87-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl (%eax), %eax
 ; X87-NEXT:    retl
 ;
 ; X87-CMOV-LABEL: test_f64_uno_s:
 ; X87-CMOV:       # %bb.0:
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-CMOV-NEXT:    fcompi %st(1), %st
 ; X87-CMOV-NEXT:    fstp %st(0)
+; X87-CMOV-NEXT:    wait
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; X87-CMOV-NEXT:    cmovpl %eax, %ecx
 ; X87-CMOV-NEXT:    movl (%ecx), %eax
 ; X87-CMOV-NEXT:    retl
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0

llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f32toi1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f32toi8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f32toi16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax

 ; AVX-X64-NEXT:    vcvttss2si %xmm0, %eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f32toi32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw (%esp)
 ; CHECK-NEXT:    movzwl (%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw (%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $16, %esp
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
 ; AVX-X86-NEXT:    fisttpll (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl (%esp), %eax
 ; AVX-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fptosi_f32toi64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvttss2si %xmm0, %rax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f32toi64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    flds 8(%ebp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptoui_f32toi1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptoui_f32toi8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptoui_f32toi16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw (%esp)
 ; CHECK-NEXT:    movzwl (%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw (%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; AVX1-X86-NEXT:    movl %esp, %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX1-X86-NEXT:    andl $-8, %esp
 ; AVX1-X86-NEXT:    subl $8, %esp
 ; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX1-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX1-X86-NEXT:    flds (%esp)
 ; AVX1-X86-NEXT:    fisttpll (%esp)
+; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    movl (%esp), %eax
 ; AVX1-X86-NEXT:    movl %ebp, %esp
 ; AVX1-X86-NEXT:    popl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX1-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: fptoui_f32toi32:
 ; AVX1-X64:       # %bb.0:

 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    flds 8(%ebp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; SSE-X86-NEXT:    ja .LBB9_2
 ; SSE-X86-NEXT:  # %bb.1:
 ; SSE-X86-NEXT:    movaps %xmm2, %xmm1
 ; SSE-X86-NEXT:  .LBB9_2:
 ; SSE-X86-NEXT:    subss %xmm1, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    setbe %al
 ; SSE-X86-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; SSE-X86-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; SSE-X86-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movzbl %al, %edx

 ; AVX1-X86-NEXT:    ja .LBB9_2
 ; AVX1-X86-NEXT:  # %bb.1:
 ; AVX1-X86-NEXT:    vmovaps %xmm1, %xmm2
 ; AVX1-X86-NEXT:  .LBB9_2:
 ; AVX1-X86-NEXT:    vsubss %xmm2, %xmm0, %xmm0
 ; AVX1-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX1-X86-NEXT:    flds (%esp)
 ; AVX1-X86-NEXT:    fisttpll (%esp)
+; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    setbe %al
 ; AVX1-X86-NEXT:    movzbl %al, %edx
 ; AVX1-X86-NEXT:    shll $31, %edx
 ; AVX1-X86-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX1-X86-NEXT:    movl (%esp), %eax
 ; AVX1-X86-NEXT:    movl %ebp, %esp
 ; AVX1-X86-NEXT:    popl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4

 ; AVX512-X86-NEXT:    seta %al
 ; AVX512-X86-NEXT:    kmovw %eax, %k1
 ; AVX512-X86-NEXT:    vxorps %xmm2, %xmm2, %xmm2
 ; AVX512-X86-NEXT:    vmovss %xmm2, %xmm1, %xmm1 {%k1}
 ; AVX512-X86-NEXT:    vsubss %xmm1, %xmm0, %xmm0
 ; AVX512-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX512-X86-NEXT:    flds (%esp)
 ; AVX512-X86-NEXT:    fisttpll (%esp)
+; AVX512-X86-NEXT:    wait
 ; AVX512-X86-NEXT:    setbe %dl
 ; AVX512-X86-NEXT:    shll $31, %edx
 ; AVX512-X86-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512-X86-NEXT:    movl (%esp), %eax
 ; AVX512-X86-NEXT:    movl %ebp, %esp
 ; AVX512-X86-NEXT:    popl %ebp
 ; AVX512-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512-X86-NEXT:    retl

 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    flds 8(%ebp)
 ; CHECK-NEXT:    flds {{\.LCPI.*}}
 ; CHECK-NEXT:    fcom %st(1)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstsw %ax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    # kill: def $ah killed $ah killed $ax
 ; CHECK-NEXT:    sahf
 ; CHECK-NEXT:    setbe %al
 ; CHECK-NEXT:    fldz
 ; CHECK-NEXT:    ja .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    fldz
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    fstp %st(1)
 ; CHECK-NEXT:    fsubrp %st, %st(1)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; CHECK-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb %al, %dl

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f64toi8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f64toi16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax

 ; AVX-X64-NEXT:    vcvttsd2si %xmm0, %eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f64toi32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw (%esp)
 ; CHECK-NEXT:    movzwl (%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw (%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $16, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    fisttpll (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl (%esp), %eax
 ; AVX-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fptosi_f64toi64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvttsd2si %xmm0, %rax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptosi_f64toi64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    fldl 8(%ebp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptoui_f64toi1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptoui_f64toi8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistps {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al

 ; AVX-X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; AVX-X64-NEXT:    retq
 ;
 ; CHECK-LABEL: fptoui_f64toi16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw (%esp)
 ; CHECK-NEXT:    movzwl (%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw (%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; AVX1-X86-NEXT:    movl %esp, %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX1-X86-NEXT:    andl $-8, %esp
 ; AVX1-X86-NEXT:    subl $8, %esp
 ; AVX1-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX1-X86-NEXT:    fldl (%esp)
 ; AVX1-X86-NEXT:    fisttpll (%esp)
+; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    movl (%esp), %eax
 ; AVX1-X86-NEXT:    movl %ebp, %esp
 ; AVX1-X86-NEXT:    popl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX1-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: fptoui_f64toi32:
 ; AVX1-X64:       # %bb.0:

 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    fldl 8(%ebp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    orl $3072, %eax # imm = 0xC00
 ; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax

 ; SSE-X86-NEXT:    ja .LBB18_2
 ; SSE-X86-NEXT:  # %bb.1:
 ; SSE-X86-NEXT:    movapd %xmm2, %xmm1
 ; SSE-X86-NEXT:  .LBB18_2:
 ; SSE-X86-NEXT:    subsd %xmm1, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    setbe %al
 ; SSE-X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; SSE-X86-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; SSE-X86-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movzbl %al, %edx

 ; AVX1-X86-NEXT:    ja .LBB18_2
 ; AVX1-X86-NEXT:  # %bb.1:
 ; AVX1-X86-NEXT:    vmovapd %xmm1, %xmm2
 ; AVX1-X86-NEXT:  .LBB18_2:
 ; AVX1-X86-NEXT:    vsubsd %xmm2, %xmm0, %xmm0
 ; AVX1-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX1-X86-NEXT:    fldl (%esp)
 ; AVX1-X86-NEXT:    fisttpll (%esp)
+; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    setbe %al
 ; AVX1-X86-NEXT:    movzbl %al, %edx
 ; AVX1-X86-NEXT:    shll $31, %edx
 ; AVX1-X86-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX1-X86-NEXT:    movl (%esp), %eax
 ; AVX1-X86-NEXT:    movl %ebp, %esp
 ; AVX1-X86-NEXT:    popl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4

 ; AVX512-X86-NEXT:    seta %al
 ; AVX512-X86-NEXT:    kmovw %eax, %k1
 ; AVX512-X86-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
 ; AVX512-X86-NEXT:    vmovsd %xmm2, %xmm1, %xmm1 {%k1}
 ; AVX512-X86-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; AVX512-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512-X86-NEXT:    fldl (%esp)
 ; AVX512-X86-NEXT:    fisttpll (%esp)
+; AVX512-X86-NEXT:    wait
 ; AVX512-X86-NEXT:    setbe %dl
 ; AVX512-X86-NEXT:    shll $31, %edx
 ; AVX512-X86-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512-X86-NEXT:    movl (%esp), %eax
 ; AVX512-X86-NEXT:    movl %ebp, %esp
 ; AVX512-X86-NEXT:    popl %ebp
 ; AVX512-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512-X86-NEXT:    retl

 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    fldl 8(%ebp)
 ; CHECK-NEXT:    flds {{\.LCPI.*}}
 ; CHECK-NEXT:    fcom %st(1)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstsw %ax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    # kill: def $ah killed $ah killed $ax
 ; CHECK-NEXT:    sahf
 ; CHECK-NEXT:    setbe %al
 ; CHECK-NEXT:    fldz
 ; CHECK-NEXT:    ja .LBB18_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    fldz
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:  .LBB18_2:
 ; CHECK-NEXT:    fstp %st(1)
 ; CHECK-NEXT:    fsubrp %st, %st(1)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; CHECK-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movb %al, %dl

llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll

 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; SSE-X86-NEXT:    andb $1, %al
 ; SSE-X86-NEXT:    negb %al
 ; SSE-X86-NEXT:    movsbl %al, %eax
 ; SSE-X86-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i1tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    andb $1, %dil
 ; SSE-X64-NEXT:    negb %dil
 ; SSE-X64-NEXT:    movsbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i1tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; AVX-X86-NEXT:    andb $1, %al
 ; AVX-X86-NEXT:    negb %al
 ; AVX-X86-NEXT:    movsbl %al, %eax
 ; AVX-X86-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i1tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    andb $1, %dil
 ; AVX-X64-NEXT:    negb %dil
 ; AVX-X64-NEXT:    movsbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i1tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X87-NEXT:    andb $1, %al
 ; X87-NEXT:    negb %al
 ; X87-NEXT:    movsbl %al, %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.sitofp.f32.i1(i1 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @sitofp_i8tof32(i8 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i8tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i8tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movsbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i8tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i8tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movsbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i8tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.sitofp.f32.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @sitofp_i16tof32(i16 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i16tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i16tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movswl %di, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i16tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i16tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movswl %di, %eax
 ; AVX-X64-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i16tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @sitofp_i32tof32(i32 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i32tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    cvtsi2ssl {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i32tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    cvtsi2ss %edi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i32tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    vcvtsi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i32tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvtsi2ss %edi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i32tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @sitofp_i64tof32(i64 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i64tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fstps (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i64tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    cvtsi2ss %rdi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i64tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-X86-NEXT:    fstps (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i64tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvtsi2ss %rdi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i64tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fildll {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @uitofp_i1tof32(i1 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i1tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; SSE-X86-NEXT:    andb $1, %al
 ; SSE-X86-NEXT:    movzbl %al, %eax
 ; SSE-X86-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i1tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    andl $1, %edi
 ; SSE-X64-NEXT:    cvtsi2ss %edi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i1tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; AVX-X86-NEXT:    andb $1, %al
 ; AVX-X86-NEXT:    movzbl %al, %eax
 ; AVX-X86-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i1tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    andl $1, %edi
 ; AVX-X64-NEXT:    vcvtsi2ss %edi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i1tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X87-NEXT:    andb $1, %al
 ; X87-NEXT:    movzbl %al, %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.uitofp.f32.i1(i1 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @uitofp_i8tof32(i8 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i8tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i8tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movzbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i8tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i8tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movzbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i8tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.uitofp.f32.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @uitofp_i16tof32(i16 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i16tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i16tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movzwl %di, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i16tof32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i16tof32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movzwl %di, %eax
 ; AVX-X64-NEXT:    vcvtsi2ss %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i16tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.uitofp.f32.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define float @uitofp_i32tof32(i32 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i32tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    orpd %xmm0, %xmm1
 ; SSE-X86-NEXT:    subsd %xmm0, %xmm1
 ; SSE-X86-NEXT:    xorps %xmm0, %xmm0
 ; SSE-X86-NEXT:    cvtsd2ss %xmm1, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i32tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movl %edi, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %rax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX1-X86-LABEL: uitofp_i32tof32:
 ; AVX1-X86:       # %bb.0:
 ; AVX1-X86-NEXT:    pushl %eax
 ; AVX1-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX1-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX1-X86-NEXT:    vorpd %xmm0, %xmm1, %xmm1
 ; AVX1-X86-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
 ; AVX1-X86-NEXT:    vcvtsd2ss %xmm0, %xmm0, %xmm0
 ; AVX1-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX1-X86-NEXT:    flds (%esp)
+; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    popl %eax
 ; AVX1-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX1-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: uitofp_i32tof32:
 ; AVX1-X64:       # %bb.0:
 ; AVX1-X64-NEXT:    movl %edi, %eax
 ; AVX1-X64-NEXT:    vcvtsi2ss %rax, %xmm0, %xmm0
 ; AVX1-X64-NEXT:    retq
 ;
 ; AVX512-X86-LABEL: uitofp_i32tof32:
 ; AVX512-X86:       # %bb.0:
 ; AVX512-X86-NEXT:    pushl %eax
 ; AVX512-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX512-X86-NEXT:    vcvtusi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX512-X86-NEXT:    flds (%esp)
+; AVX512-X86-NEXT:    wait
 ; AVX512-X86-NEXT:    popl %eax
 ; AVX512-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512-X86-NEXT:    retl
 ;
 ; AVX512-X64-LABEL: uitofp_i32tof32:
 ; AVX512-X64:       # %bb.0:
 ; AVX512-X64-NEXT:    vcvtusi2ss %edi, %xmm0, %xmm0
 ; AVX512-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i32tof32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %ebp
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    .cfi_offset %ebp, -8
 ; X87-NEXT:    movl %esp, %ebp
 ; X87-NEXT:    .cfi_def_cfa_register %ebp
 ; X87-NEXT:    andl $-8, %esp
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    movl 8(%ebp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fildll (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    movl %ebp, %esp
 ; X87-NEXT:    popl %ebp
 ; X87-NEXT:    .cfi_def_cfa %esp, 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result

 ; SSE-X86-NEXT:    subl $16, %esp
 ; SSE-X86-NEXT:    movl 12(%ebp), %eax
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movlps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    shrl $31, %eax
 ; SSE-X86-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; SSE-X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i64tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movq %rdi, %rax

 ; AVX-X86-NEXT:    subl $16, %esp
 ; AVX-X86-NEXT:    movl 12(%ebp), %eax
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-X86-NEXT:    shrl $31, %eax
 ; AVX-X86-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-X86-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: uitofp_i64tof32:
 ; AVX1-X64:       # %bb.0:
 ; AVX1-X64-NEXT:    movq %rdi, %rax

 ; X87-NEXT:    movl 12(%ebp), %ecx
 ; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    shrl $31, %ecx
 ; X87-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X87-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
 ; X87-NEXT:    fstps {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    movl %ebp, %esp
 ; X87-NEXT:    popl %ebp
 ; X87-NEXT:    .cfi_def_cfa %esp, 4
 ; X87-NEXT:    retl
   %result = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define double @sitofp_i8tof64(i8 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i8tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsbl 8(%ebp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i8tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movsbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i8tof64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    movsbl 8(%ebp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i8tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movsbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i8tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @sitofp_i16tof64(i16 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i16tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movswl 8(%ebp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i16tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movswl %di, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i16tof64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    movswl 8(%ebp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i16tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movswl %di, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i16tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @sitofp_i32tof64(i32 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i32tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    cvtsi2sdl 8(%ebp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i32tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    cvtsi2sd %edi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i32tof64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vcvtsi2sdl 8(%ebp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i32tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i32tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @sitofp_i64tof64(i64 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i64tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    fildll 8(%ebp)
 ; SSE-X86-NEXT:    fstpl (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i64tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    cvtsi2sd %rdi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i64tof64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    fildll 8(%ebp)
 ; AVX-X86-NEXT:    fstpl (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i64tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i64tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fildll {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i1tof64(i1 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i1tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movb 8(%ebp), %al
 ; SSE-X86-NEXT:    andb $1, %al
 ; SSE-X86-NEXT:    movzbl %al, %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i1tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    andl $1, %edi

 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    movb 8(%ebp), %al
 ; AVX-X86-NEXT:    andb $1, %al
 ; AVX-X86-NEXT:    movzbl %al, %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i1tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    andl $1, %edi
 ; AVX-X64-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i1tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X87-NEXT:    andb $1, %al
 ; X87-NEXT:    movzbl %al, %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.uitofp.f64.i1(i1 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i8tof64(i8 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i8tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movzbl 8(%ebp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i8tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movzbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i8tof64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    movzbl 8(%ebp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i8tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movzbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i8tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X87-NEXT:    filds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.uitofp.f64.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i16tof64(i16 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i16tof64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movzwl 8(%ebp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i16tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movzwl %di, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i16tof64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    movzwl 8(%ebp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i16tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movzwl %di, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i16tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    fildl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.uitofp.f64.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }

 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    orpd %xmm0, %xmm1
 ; SSE-X86-NEXT:    subsd %xmm0, %xmm1
 ; SSE-X86-NEXT:    movsd %xmm1, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i32tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movl %edi, %eax

 ; AVX1-X86-NEXT:    andl $-8, %esp
 ; AVX1-X86-NEXT:    subl $8, %esp
 ; AVX1-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX1-X86-NEXT:    vorpd %xmm0, %xmm1, %xmm1
 ; AVX1-X86-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
 ; AVX1-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX1-X86-NEXT:    fldl (%esp)
+; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    movl %ebp, %esp
 ; AVX1-X86-NEXT:    popl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX1-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: uitofp_i32tof64:
 ; AVX1-X64:       # %bb.0:
 ; AVX1-X64-NEXT:    movl %edi, %eax
 ; AVX1-X64-NEXT:    vcvtsi2sd %rax, %xmm0, %xmm0
 ; AVX1-X64-NEXT:    retq
 ;
 ; AVX512-X86-LABEL: uitofp_i32tof64:
 ; AVX512-X86:       # %bb.0:
 ; AVX512-X86-NEXT:    pushl %ebp
 ; AVX512-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX512-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX512-X86-NEXT:    movl %esp, %ebp
 ; AVX512-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX512-X86-NEXT:    andl $-8, %esp
 ; AVX512-X86-NEXT:    subl $8, %esp
 ; AVX512-X86-NEXT:    vcvtusi2sdl 8(%ebp), %xmm0, %xmm0
 ; AVX512-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512-X86-NEXT:    fldl (%esp)
+; AVX512-X86-NEXT:    wait
 ; AVX512-X86-NEXT:    movl %ebp, %esp
 ; AVX512-X86-NEXT:    popl %ebp
 ; AVX512-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512-X86-NEXT:    retl
 ;
 ; AVX512-X64-LABEL: uitofp_i32tof64:
 ; AVX512-X64:       # %bb.0:
 ; AVX512-X64-NEXT:    vcvtusi2sd %edi, %xmm0, %xmm0
 ; AVX512-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i32tof64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %ebp
 ; X87-NEXT:    .cfi_def_cfa_offset 8
 ; X87-NEXT:    .cfi_offset %ebp, -8
 ; X87-NEXT:    movl %esp, %ebp
 ; X87-NEXT:    .cfi_def_cfa_register %ebp
 ; X87-NEXT:    andl $-8, %esp
 ; X87-NEXT:    subl $8, %esp
 ; X87-NEXT:    movl 8(%ebp), %eax
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X87-NEXT:    fildll (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    movl %ebp, %esp
 ; X87-NEXT:    popl %ebp
 ; X87-NEXT:    .cfi_def_cfa %esp, 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result

 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; SSE-X86-NEXT:    subpd {{\.LCPI.*}}, %xmm0
 ; SSE-X86-NEXT:    movapd %xmm0, %xmm1
 ; SSE-X86-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; SSE-X86-NEXT:    addpd %xmm0, %xmm1
 ; SSE-X86-NEXT:    movlpd %xmm1, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i64tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movq %rdi, %xmm1

 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; AVX-X86-NEXT:    vsubpd {{\.LCPI.*}}, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; AVX-X86-NEXT:    vaddpd %xmm0, %xmm1, %xmm0
 ; AVX-X86-NEXT:    vmovlpd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: uitofp_i64tof64:
 ; AVX1-X64:       # %bb.0:
 ; AVX1-X64-NEXT:    vmovq %rdi, %xmm0

 ; X87-NEXT:    movl 12(%ebp), %ecx
 ; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X87-NEXT:    movl %eax, (%esp)
 ; X87-NEXT:    shrl $31, %ecx
 ; X87-NEXT:    fildll (%esp)
 ; X87-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    movl %ebp, %esp
 ; X87-NEXT:    popl %ebp
 ; X87-NEXT:    .cfi_def_cfa %esp, 4
 ; X87-NEXT:    retl
   %result = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 attributes #0 = { strictfp }

llvm/test/CodeGen/X86/fp-strict-scalar-round.ll

 ; SSE41-X86-LABEL: fceil32:
 ; SSE41-X86:       # %bb.0:
 ; SSE41-X86-NEXT:    pushl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE41-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-X86-NEXT:    roundss $10, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE41-X86-NEXT:    flds (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    popl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: fceil32:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundss $10, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fceil32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vroundss $10, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fceil32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundss $10, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq

 ; SSE41-X86-NEXT:    movl %esp, %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $10, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    movl %ebp, %esp
 ; SSE41-X86-NEXT:    popl %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: fceilf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $10, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fceilf64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $10, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fceilf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $10, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.ceil.f64(
                         double %f, metadata !"fpexcept.strict")
   ret double %res
 }
 
 define float @ffloor32(float %f) #0 {
 ; SSE41-X86-LABEL: ffloor32:
 ; SSE41-X86:       # %bb.0:
 ; SSE41-X86-NEXT:    pushl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE41-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-X86-NEXT:    roundss $9, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE41-X86-NEXT:    flds (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    popl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: ffloor32:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundss $9, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: ffloor32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vroundss $9, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: ffloor32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundss $9, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq

 ; SSE41-X86-NEXT:    movl %esp, %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $9, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    movl %ebp, %esp
 ; SSE41-X86-NEXT:    popl %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: ffloorf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $9, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: ffloorf64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $9, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: ffloorf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $9, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.floor.f64(
                         double %f, metadata !"fpexcept.strict")
   ret double %res
 }
 
 define float @ftrunc32(float %f) #0 {
 ; SSE41-X86-LABEL: ftrunc32:
 ; SSE41-X86:       # %bb.0:
 ; SSE41-X86-NEXT:    pushl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE41-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-X86-NEXT:    roundss $11, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE41-X86-NEXT:    flds (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    popl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: ftrunc32:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundss $11, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: ftrunc32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vroundss $11, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: ftrunc32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundss $11, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq

 ; SSE41-X86-NEXT:    movl %esp, %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $11, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    movl %ebp, %esp
 ; SSE41-X86-NEXT:    popl %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: ftruncf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $11, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: ftruncf64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: ftruncf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.trunc.f64(
                         double %f, metadata !"fpexcept.strict")
   ret double %res
 }
 
 define float @frint32(float %f) #0 {
 ; SSE41-X86-LABEL: frint32:
 ; SSE41-X86:       # %bb.0:
 ; SSE41-X86-NEXT:    pushl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE41-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-X86-NEXT:    roundss $4, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE41-X86-NEXT:    flds (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    popl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: frint32:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundss $4, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: frint32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vroundss $4, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: frint32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundss $4, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq

 ; SSE41-X86-NEXT:    movl %esp, %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $4, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    movl %ebp, %esp
 ; SSE41-X86-NEXT:    popl %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: frintf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $4, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: frintf64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $4, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: frintf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $4, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.rint.f64(
                         double %f,
                         metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret double %res
 }
 
 define float @fnearbyint32(float %f) #0 {
 ; SSE41-X86-LABEL: fnearbyint32:
 ; SSE41-X86:       # %bb.0:
 ; SSE41-X86-NEXT:    pushl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE41-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-X86-NEXT:    roundss $12, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE41-X86-NEXT:    flds (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    popl %eax
 ; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: fnearbyint32:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundss $12, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fnearbyint32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vroundss $12, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fnearbyint32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundss $12, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq

 ; SSE41-X86-NEXT:    movl %esp, %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $12, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
+; SSE41-X86-NEXT:    wait
 ; SSE41-X86-NEXT:    movl %ebp, %esp
 ; SSE41-X86-NEXT:    popl %ebp
 ; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: fnearbyintf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $12, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fnearbyintf64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fnearbyintf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.nearbyint.f64(
                         double %f,
                         metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret double %res
 }
 
 attributes #0 = { strictfp }

llvm/test/CodeGen/X86/fp-strict-scalar.ll

 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    addsd 16(%ebp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fadd_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    addsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fadd_f64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vaddsd 16(%ebp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fadd_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fadd_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    faddl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call double @llvm.experimental.constrained.fadd.f64(double %a, double %b,
                                                              metadata !"round.dynamic",
                                                              metadata !"fpexcept.strict") #0
   ret double %ret
 }
 
 define float @fadd_f32(float %a, float %b) nounwind strictfp {
 ; SSE-X86-LABEL: fadd_f32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    addss {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fadd_f32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    addss %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fadd_f32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vaddss {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fadd_f32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vaddss %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fadd_f32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fadds {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fsub_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fsub_f64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    subsd 16(%ebp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fsub_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    subsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fsub_f64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vsubsd 16(%ebp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fsub_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fsub_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fsubl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call double @llvm.experimental.constrained.fsub.f64(double %a, double %b,
                                                              metadata !"round.dynamic",
                                                              metadata !"fpexcept.strict") #0
   ret double %ret
 }
 
 define float @fsub_f32(float %a, float %b) nounwind strictfp {
 ; SSE-X86-LABEL: fsub_f32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    subss {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fsub_f32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    subss %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fsub_f32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vsubss {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fsub_f32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vsubss %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fsub_f32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fsubs {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call float @llvm.experimental.constrained.fsub.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fmul_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fmul_f64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    mulsd 16(%ebp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fmul_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    mulsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fmul_f64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vmulsd 16(%ebp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fmul_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fmul_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fmull {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call double @llvm.experimental.constrained.fmul.f64(double %a, double %b,
                                                              metadata !"round.dynamic",
                                                              metadata !"fpexcept.strict") #0
   ret double %ret
 }
 
 define float @fmul_f32(float %a, float %b) nounwind strictfp {
 ; SSE-X86-LABEL: fmul_f32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    mulss {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fmul_f32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    mulss %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fmul_f32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vmulss {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fmul_f32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vmulss %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fmul_f32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fmuls {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call float @llvm.experimental.constrained.fmul.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fdiv_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fdiv_f64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    divsd 16(%ebp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fdiv_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    divsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fdiv_f64:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %ebp
 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vdivsd 16(%ebp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fdiv_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fdiv_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fdivl {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b,
                                                              metadata !"round.dynamic",
                                                              metadata !"fpexcept.strict") #0
   ret double %ret
 }
 
 define float @fdiv_f32(float %a, float %b) nounwind strictfp {
 ; SSE-X86-LABEL: fdiv_f32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    divss {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fdiv_f32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    divss %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fdiv_f32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vdivss {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fdiv_f32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vdivss %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fdiv_f32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fdivs {{[0-9]+}}(%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %ret = call float @llvm.experimental.constrained.fdiv.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define void @fpext_f32_to_f64(float* %val, double* %ret) nounwind strictfp {

 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fpext_f32_to_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X87-NEXT:    flds (%ecx)
 ; X87-NEXT:    fstpl (%eax)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %1 = load float, float* %val, align 4
   %res = call double @llvm.experimental.constrained.fpext.f64.f32(float %1,
                                                                   metadata !"fpexcept.strict") #0
   store double %res, double* %ret, align 8
   ret void
 }
 

 ; X87:       # %bb.0:
 ; X87-NEXT:    pushl %eax
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X87-NEXT:    fldl (%ecx)
 ; X87-NEXT:    fstps (%esp)
 ; X87-NEXT:    flds (%esp)
 ; X87-NEXT:    fstps (%eax)
+; X87-NEXT:    wait
 ; X87-NEXT:    popl %eax
 ; X87-NEXT:    retl
   %1 = load double, double* %val, align 8
   %res = call float @llvm.experimental.constrained.fptrunc.f32.f64(double %1,
                                                                    metadata !"round.dynamic",
                                                                    metadata !"fpexcept.strict") #0
   store float %res, float* %ret, align 4
   ret void

 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fsqrt_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    fldl (%eax)
 ; X87-NEXT:    fsqrt
 ; X87-NEXT:    fstpl (%eax)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %1 = load double, double* %a, align 8
   %res = call double @llvm.experimental.constrained.sqrt.f64(double %1,
                                                              metadata !"round.dynamic",
                                                              metadata !"fpexcept.strict") #0
   store double %res, double* %a, align 8
   ret void
 }

 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fsqrt_f32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X87-NEXT:    flds (%eax)
 ; X87-NEXT:    fsqrt
 ; X87-NEXT:    fstps (%eax)
+; X87-NEXT:    wait
 ; X87-NEXT:    retl
   %1 = load float, float* %a, align 4
   %res = call float @llvm.experimental.constrained.sqrt.f32(float %1,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   store float %res, float* %a, align 4
   ret void
 }

 ; AVX-X86-NEXT:    movl %esp, %ebp
 ; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
 ; AVX-X86-NEXT:    vfmadd213sd {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
 ; AVX-X86-NEXT:    vmovsd %xmm1, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    movl %ebp, %esp
 ; AVX-X86-NEXT:    popl %ebp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fma_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fma_f64:
 ; X87:       # %bb.0:
 ; X87-NEXT:    subl $24, %esp
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstpl (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll fma
 ; X87-NEXT:    addl $24, %esp
 ; X87-NEXT:    retl
   %res = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %c,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret double %res
 }

 ; AVX-X86-LABEL: fma_f32:
 ; AVX-X86:       # %bb.0:
 ; AVX-X86-NEXT:    pushl %eax
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX-X86-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
 ; AVX-X86-NEXT:    vmovss %xmm1, (%esp)
 ; AVX-X86-NEXT:    flds (%esp)
+; AVX-X86-NEXT:    wait
 ; AVX-X86-NEXT:    popl %eax
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fma_f32:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fma_f32:
 ; X87:       # %bb.0:
 ; X87-NEXT:    subl $12, %esp
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    flds {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstps {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstps {{[0-9]+}}(%esp)
 ; X87-NEXT:    fstps (%esp)
+; X87-NEXT:    wait
 ; X87-NEXT:    calll fmaf
 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    retl
   %res = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c,
                                                            metadata !"round.dynamic",
                                                            metadata !"fpexcept.strict") #0
   ret float %res
 }
 
 attributes #0 = { strictfp }

llvm/test/CodeGen/X86/fp128-cast-strict.ll

 ; X64-AVX-NEXT:    retq
 ;
 ; X86-LABEL: TestFPExtF32_F128:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    subl $24, %esp
 ; X86-NEXT:    flds vf32
 ; X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    calll __extendsftf2
 ; X86-NEXT:    subl $4, %esp
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi

 ; X64-AVX-NEXT:    retq
 ;
 ; X86-LABEL: TestFPExtF64_F128:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    subl $40, %esp
 ; X86-NEXT:    fldl vf64
 ; X86-NEXT:    fstpl {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    calll __extenddftf2
 ; X86-NEXT:    subl $4, %esp
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi

 }
 
 define void @TestFPExtF80_F128() nounwind strictfp {
 ; X64-SSE-LABEL: TestFPExtF80_F128:
 ; X64-SSE:       # %bb.0: # %entry
 ; X64-SSE-NEXT:    subq $24, %rsp
 ; X64-SSE-NEXT:    fldt {{.*}}(%rip)
 ; X64-SSE-NEXT:    fstpt (%rsp)
+; X64-SSE-NEXT:    wait
 ; X64-SSE-NEXT:    callq __extendxftf2
 ; X64-SSE-NEXT:    movaps %xmm0, {{.*}}(%rip)
 ; X64-SSE-NEXT:    addq $24, %rsp
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX-LABEL: TestFPExtF80_F128:
 ; X64-AVX:       # %bb.0: # %entry
 ; X64-AVX-NEXT:    subq $24, %rsp
 ; X64-AVX-NEXT:    fldt {{.*}}(%rip)
 ; X64-AVX-NEXT:    fstpt (%rsp)
+; X64-AVX-NEXT:    wait
 ; X64-AVX-NEXT:    callq __extendxftf2
 ; X64-AVX-NEXT:    vmovaps %xmm0, {{.*}}(%rip)
 ; X64-AVX-NEXT:    addq $24, %rsp
 ; X64-AVX-NEXT:    retq
 ;
 ; X86-LABEL: TestFPExtF80_F128:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    subl $40, %esp
 ; X86-NEXT:    fldt vf80
 ; X86-NEXT:    fstpt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    calll __extendxftf2
 ; X86-NEXT:    subl $4, %esp
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi

 ; X86-NEXT:    subl $12, %esp
 ; X86-NEXT:    pushl vf128+12
 ; X86-NEXT:    pushl vf128+8
 ; X86-NEXT:    pushl vf128+4
 ; X86-NEXT:    pushl vf128
 ; X86-NEXT:    calll __trunctfsf2
 ; X86-NEXT:    addl $16, %esp
 ; X86-NEXT:    fstps vf32
+; X86-NEXT:    wait
 ; X86-NEXT:    addl $12, %esp
 ; X86-NEXT:    retl
 entry:
   %0 = load fp128, fp128* @vf128, align 16
   %conv = call float @llvm.experimental.constrained.fptrunc.f32.f128(fp128 %0, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   store float %conv, float* @vf32, align 4
   ret void
 }

 ; X86-NEXT:    subl $12, %esp
 ; X86-NEXT:    pushl vf128+12
 ; X86-NEXT:    pushl vf128+8
 ; X86-NEXT:    pushl vf128+4
 ; X86-NEXT:    pushl vf128
 ; X86-NEXT:    calll __trunctfdf2
 ; X86-NEXT:    addl $16, %esp
 ; X86-NEXT:    fstpl vf64
+; X86-NEXT:    wait
 ; X86-NEXT:    addl $12, %esp
 ; X86-NEXT:    retl
 entry:
   %0 = load fp128, fp128* @vf128, align 16
   %conv = call double @llvm.experimental.constrained.fptrunc.f64.f128(fp128 %0, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   store double %conv, double* @vf64, align 8
   ret void
 }
 
 define void @TestFPTruncF128_F80() nounwind strictfp {
 ; X64-SSE-LABEL: TestFPTruncF128_F80:
 ; X64-SSE:       # %bb.0: # %entry
 ; X64-SSE-NEXT:    pushq %rax
 ; X64-SSE-NEXT:    movaps {{.*}}(%rip), %xmm0
 ; X64-SSE-NEXT:    callq __trunctfxf2
 ; X64-SSE-NEXT:    fstpt {{.*}}(%rip)
+; X64-SSE-NEXT:    wait
 ; X64-SSE-NEXT:    popq %rax
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX-LABEL: TestFPTruncF128_F80:
 ; X64-AVX:       # %bb.0: # %entry
 ; X64-AVX-NEXT:    pushq %rax
 ; X64-AVX-NEXT:    vmovaps {{.*}}(%rip), %xmm0
 ; X64-AVX-NEXT:    callq __trunctfxf2
 ; X64-AVX-NEXT:    fstpt {{.*}}(%rip)
+; X64-AVX-NEXT:    wait
 ; X64-AVX-NEXT:    popq %rax
 ; X64-AVX-NEXT:    retq
 ;
 ; X86-LABEL: TestFPTruncF128_F80:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    subl $12, %esp
 ; X86-NEXT:    pushl vf128+12
 ; X86-NEXT:    pushl vf128+8
 ; X86-NEXT:    pushl vf128+4
 ; X86-NEXT:    pushl vf128
 ; X86-NEXT:    calll __trunctfxf2
 ; X86-NEXT:    addl $16, %esp
 ; X86-NEXT:    fstpt vf80
+; X86-NEXT:    wait
 ; X86-NEXT:    addl $12, %esp
 ; X86-NEXT:    retl
 entry:
   %0 = load fp128, fp128* @vf128, align 16
   %conv = call x86_fp80 @llvm.experimental.constrained.fptrunc.f80.f128(fp128 %0, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   store x86_fp80 %conv, x86_fp80* @vf80, align 8
   ret void
 }

llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=CHECK,X87-32
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -O3 | FileCheck %s --check-prefixes=CHECK,X87-64
 
 define i32 @test_oeq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_oeq_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    jne .LBB0_3
 ; X87-32-NEXT:  # %bb.1:
 ; X87-32-NEXT:    jp .LBB0_3
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:  .LBB0_3:
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_oeq_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnel %esi, %eax
 ; X87-64-NEXT:    cmovpl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ogt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ogt_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    ja .LBB1_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB1_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ogt_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_oge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_oge_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jae .LBB2_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB2_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_oge_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_olt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_olt_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    ja .LBB3_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB3_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_olt_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ole_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ole_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jae .LBB4_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB4_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ole_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_one_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_one_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jne .LBB5_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB5_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_one_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ord_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ord_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jnp .LBB6_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB6_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ord_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovpl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ueq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ueq_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    je .LBB7_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB7_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ueq_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ugt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ugt_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jb .LBB8_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB8_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ugt_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovael %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_uge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_uge_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jbe .LBB9_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB9_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_uge_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmoval %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ult_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ult_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jb .LBB10_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB10_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ult_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovael %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ule_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ule_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jbe .LBB11_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB11_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ule_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmoval %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_une_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_une_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    jne .LBB12_3
 ; X87-32-NEXT:  # %bb.1:
 ; X87-32-NEXT:    jp .LBB12_3
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:  .LBB12_3:
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_une_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %esi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnel %edi, %eax
 ; X87-64-NEXT:    cmovpl %edi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_uno_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_uno_q:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fucompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jp .LBB13_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB13_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_uno_q:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fucompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnpl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_oeq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_oeq_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    jne .LBB14_3
 ; X87-32-NEXT:  # %bb.1:
 ; X87-32-NEXT:    jp .LBB14_3
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:  .LBB14_3:
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_oeq_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnel %esi, %eax
 ; X87-64-NEXT:    cmovpl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ogt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ogt_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    ja .LBB15_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB15_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ogt_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_oge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_oge_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jae .LBB16_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB16_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_oge_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_olt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_olt_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    ja .LBB17_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB17_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_olt_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ole_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ole_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jae .LBB18_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB18_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ole_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovbl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_one_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_one_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jne .LBB19_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB19_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_one_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ord_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ord_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jnp .LBB20_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB20_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ord_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovpl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ueq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ueq_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    je .LBB21_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB21_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ueq_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnel %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ugt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ugt_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jb .LBB22_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB22_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ugt_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovael %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_uge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_uge_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jbe .LBB23_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB23_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_uge_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmoval %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ult_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ult_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jb .LBB24_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB24_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ult_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovael %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_ule_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_ule_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jbe .LBB25_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB25_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_ule_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmoval %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_une_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_une_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    jne .LBB26_3
 ; X87-32-NEXT:  # %bb.1:
 ; X87-32-NEXT:    jp .LBB26_3
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:  .LBB26_3:
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_une_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %esi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnel %edi, %eax
 ; X87-64-NEXT:    cmovpl %edi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_uno_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
 ; X87-32-LABEL: test_uno_s:
 ; X87-32:       # %bb.0:
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-32-NEXT:    fcompp
+; X87-32-NEXT:    wait
 ; X87-32-NEXT:    fnstsw %ax
 ; X87-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X87-32-NEXT:    sahf
 ; X87-32-NEXT:    jp .LBB27_1
 ; X87-32-NEXT:  # %bb.2:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ; X87-32-NEXT:  .LBB27_1:
 ; X87-32-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X87-32-NEXT:    movl (%eax), %eax
 ; X87-32-NEXT:    retl
 ;
 ; X87-64-LABEL: test_uno_s:
 ; X87-64:       # %bb.0:
 ; X87-64-NEXT:    movl %edi, %eax
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X87-64-NEXT:    fcompi %st(1), %st
 ; X87-64-NEXT:    fstp %st(0)
+; X87-64-NEXT:    wait
 ; X87-64-NEXT:    cmovnpl %esi, %eax
 ; X87-64-NEXT:    retq
   %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
                                                x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 attributes #0 = { strictfp }
 
 declare i1 @llvm.experimental.constrained.fcmp.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
 declare i1 @llvm.experimental.constrained.fcmps.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

 declare x86_fp80 @llvm.experimental.constrained.uitofp.x86_fp80.i64(i64, metadata, metadata)
 
 define x86_fp80 @fadd_fp80(x86_fp80 %a, x86_fp80 %b) nounwind strictfp {
 ; X86-LABEL: fadd_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    faddp %st, %st(1)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fadd_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    faddp %st, %st(1)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fadd.x86_fp80(x86_fp80 %a, x86_fp80 %b,
                                                                     metadata !"round.dynamic",
                                                                     metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define x86_fp80 @fsub_fp80(x86_fp80 %a, x86_fp80 %b) nounwind strictfp {
 ; X86-LABEL: fsub_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fsubp %st, %st(1)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fsub_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fsubp %st, %st(1)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fsub.x86_fp80(x86_fp80 %a, x86_fp80 %b,
                                                                     metadata !"round.dynamic",
                                                                     metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define x86_fp80 @fmul_fp80(x86_fp80 %a, x86_fp80 %b) nounwind strictfp {
 ; X86-LABEL: fmul_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fmulp %st, %st(1)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fmul_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fmulp %st, %st(1)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fmul.x86_fp80(x86_fp80 %a, x86_fp80 %b,
                                                                     metadata !"round.dynamic",
                                                                     metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define x86_fp80 @fdiv_fp80(x86_fp80 %a, x86_fp80 %b) nounwind strictfp {
 ; X86-LABEL: fdiv_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fdivp %st, %st(1)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fdiv_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fdivp %st, %st(1)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fdiv.x86_fp80(x86_fp80 %a, x86_fp80 %b,
                                                                     metadata !"round.dynamic",
                                                                     metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define x86_fp80 @fpext_f32_to_fp80(float %a) nounwind strictfp {
 ; X86-LABEL: fpext_f32_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fpext_f32_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movss %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    flds -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fpext.x86_fp80.f32(float %a,
                                                                          metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define x86_fp80 @fpext_f64_to_fp80(double %a) nounwind strictfp {
 ; X86-LABEL: fpext_f64_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fpext_f64_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movsd %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fpext.x86_fp80.f64(double %a,
                                                                          metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define float @fptrunc_fp80_to_f32(x86_fp80 %a) nounwind strictfp {
 ; X86-LABEL: fptrunc_fp80_to_f32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fstps (%esp)
 ; X86-NEXT:    flds (%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fptrunc_fp80_to_f32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fstps -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; X64-NEXT:    retq
   %ret = call float @llvm.experimental.constrained.fptrunc.f32.x86_fp80(x86_fp80 %a,
                                                                         metadata !"round.dynamic",
                                                                         metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fptrunc_fp80_to_f64(x86_fp80 %a) nounwind strictfp {
 ; X86-LABEL: fptrunc_fp80_to_f64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    fldt 8(%ebp)
 ; X86-NEXT:    fstpl (%esp)
 ; X86-NEXT:    fldl (%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fptrunc_fp80_to_f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fstpl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X64-NEXT:    retq
   %ret = call double @llvm.experimental.constrained.fptrunc.f64.x86_fp80(x86_fp80 %a,
                                                                          metadata !"round.dynamic",
                                                                          metadata !"fpexcept.strict") #0
   ret double %ret
 }
 
 define x86_fp80 @fsqrt_fp80(x86_fp80 %a) nounwind strictfp {
 ; X86-LABEL: fsqrt_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fsqrt
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fsqrt_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fsqrt
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.sqrt.x86_fp80(x86_fp80 %a,
                                                                     metadata !"round.dynamic",
                                                                     metadata !"fpexcept.strict") #0
   ret x86_fp80 %ret
 }
 
 define i1 @fp80_to_sint1(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_sint1:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_sint1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistps -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movb -{{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    retq
   %result = call i1 @llvm.experimental.constrained.fptosi.i1.x86_fp80(x86_fp80 %x,
                                                metadata !"fpexcept.strict") #0
   ret i1 %result
 }
 
 define i8 @fp80_to_sint8(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_sint8:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_sint8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistps -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movb -{{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    retq
   %result = call i8 @llvm.experimental.constrained.fptosi.i8.x86_fp80(x86_fp80 %x,
                                                metadata !"fpexcept.strict") #0
   ret i8 %result
 }
 
 define i16 @fp80_to_sint16(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_sint16:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_sint16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistps -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    retq
   %result = call i16 @llvm.experimental.constrained.fptosi.i16.x86_fp80(x86_fp80 %x,
                                                metadata !"fpexcept.strict") #0
   ret i16 %result
 }
 
 define i32 @fp80_to_sint32(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_sint32:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw (%esp)
 ; X86-NEXT:    movzwl (%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw (%esp)
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_sint32:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistpl -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movl -{{[0-9]+}}(%rsp), %eax

 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    .cfi_def_cfa_register %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $16, %esp
 ; X86-NEXT:    fldt 8(%ebp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_sint64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistpll -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X64-NEXT:    retq
   %result = call i64 @llvm.experimental.constrained.fptosi.i64.x86_fp80(x86_fp80 %x,
                                                metadata !"fpexcept.strict") #0
   ret i64 %result
 }
 
 define i1 @fp80_to_uint1(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_uint1:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_uint1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistps -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movb -{{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    retq
   %result = call i1 @llvm.experimental.constrained.fptoui.i1.x86_fp80(x86_fp80 %x,
                                                metadata !"fpexcept.strict") #0
   ret i1 %result
 }
 
 define i8 @fp80_to_uint8(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_uint8:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistps {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_uint8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistps -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movb -{{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    retq
   %result = call i8 @llvm.experimental.constrained.fptoui.i8.x86_fp80(x86_fp80 %x,
                                                metadata !"fpexcept.strict") #0
   ret i8 %result
 }
 
 define i16 @fp80_to_uint16(x86_fp80 %x) #0 {
 ; X86-LABEL: fp80_to_uint16:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw (%esp)
 ; X86-NEXT:    movzwl (%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistpl {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw (%esp)
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_uint16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistpl -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movl -{{[0-9]+}}(%rsp), %eax

 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    .cfi_def_cfa_register %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $16, %esp
 ; X86-NEXT:    fldt 8(%ebp)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_uint32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    orl $3072, %eax # imm = 0xC00
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistpll -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movl -{{[0-9]+}}(%rsp), %eax

 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    .cfi_def_cfa_register %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $16, %esp
 ; X86-NEXT:    fldt 8(%ebp)
 ; X86-NEXT:    flds {{\.LCPI.*}}
 ; X86-NEXT:    fcom %st(1)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstsw %ax
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    # kill: def $ah killed $ah killed $ax
 ; X86-NEXT:    sahf
 ; X86-NEXT:    setbe %al
 ; X86-NEXT:    fldz
 ; X86-NEXT:    ja .LBB18_2
 ; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    fstp %st(0)
 ; X86-NEXT:    fldz
 ; X86-NEXT:    fxch %st(1)
 ; X86-NEXT:  .LBB18_2:
 ; X86-NEXT:    fstp %st(1)
 ; X86-NEXT:    fsubrp %st, %st(1)
+; X86-NEXT:    wait
 ; X86-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; X86-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; X86-NEXT:    movb %al, %dl
 ; X86-NEXT:    shll $31, %edx
 ; X86-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fp80_to_uint64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    flds {{.*}}(%rip)
+; X64-NEXT:    wait
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    fcomi %st(1), %st
+; X64-NEXT:    wait
 ; X64-NEXT:    setbe %al
 ; X64-NEXT:    fldz
 ; X64-NEXT:    fxch %st(1)
 ; X64-NEXT:    fcmovnbe %st(1), %st
 ; X64-NEXT:    fstp %st(1)
 ; X64-NEXT:    fsubrp %st, %st(1)
+; X64-NEXT:    wait
 ; X64-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movzwl -{{[0-9]+}}(%rsp), %ecx
 ; X64-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; X64-NEXT:    movw %cx, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fistpll -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldcw -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    shlq $63, %rax

 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    andb $1, %al
 ; X86-NEXT:    negb %al
 ; X86-NEXT:    movsbl %al, %eax
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    filds {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sint1_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    andb $1, %dil
 ; X64-NEXT:    negb %dil
 ; X64-NEXT:    movsbl %dil, %eax
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.sitofp.x86_fp80.i1(i1 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @sint8_to_fp80(i8 %x) #0 {
 ; X86-LABEL: sint8_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    filds {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sint8_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movsbl %dil, %eax
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.sitofp.x86_fp80.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @sint16_to_fp80(i16 %x) #0 {
 ; X86-LABEL: sint16_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    filds {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sint16_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.sitofp.x86_fp80.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @sint32_to_fp80(i32 %x) #0 {
 ; X86-LABEL: sint32_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    fildl (%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sint32_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fildl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.sitofp.x86_fp80.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @sint64_to_fp80(i64 %x) #0 {
 ; X86-LABEL: sint64_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fildll {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sint64_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fildll -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.sitofp.x86_fp80.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @uint1_to_fp80(i1 %x) #0 {
 ; X86-LABEL: uint1_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    andb $1, %al
 ; X86-NEXT:    movzbl %al, %eax
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    filds {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: uint1_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    andl $1, %edi
 ; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.uitofp.x86_fp80.i1(i1 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @uint8_to_fp80(i8 %x) #0 {
 ; X86-LABEL: uint8_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; X86-NEXT:    filds {{[0-9]+}}(%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: uint8_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzbl %dil, %eax
 ; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.uitofp.x86_fp80.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @uint16_to_fp80(i16 %x) #0 {
 ; X86-LABEL: uint16_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    fildl (%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: uint16_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzwl %di, %eax
 ; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fildl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.uitofp.x86_fp80.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @uint32_to_fp80(i32 %x) #0 {
 ; X86-LABEL: uint32_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    .cfi_def_cfa_register %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    movl 8(%ebp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fildll (%esp)
+; X86-NEXT:    wait
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: uint32_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fildll -{{[0-9]+}}(%rsp)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.uitofp.x86_fp80.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
 ; X86-LABEL: uint64_to_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    .cfi_def_cfa_register %ebp
 ; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    movl 8(%ebp), %eax
 ; X86-NEXT:    movl 12(%ebp), %ecx
 ; X86-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    shrl $31, %ecx
 ; X86-NEXT:    fildll (%esp)
 ; X86-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
+; X86-NEXT:    wait
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: uint64_to_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    testq %rdi, %rdi
 ; X64-NEXT:    sets %al
 ; X64-NEXT:    fildll -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    fadds {{\.LCPI.*}}(,%rax,4)
+; X64-NEXT:    wait
 ; X64-NEXT:    retq
   %result = call x86_fp80 @llvm.experimental.constrained.uitofp.x86_fp80.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret x86_fp80 %result
 }
 
 attributes #0 = { strictfp }

llvm/test/CodeGen/X86/vec-strict-128.ll

 ; SSE-X86-NEXT:    movups %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
 ; SSE-X86-NEXT:    movups %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
 ; SSE-X86-NEXT:    movups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
 ; SSE-X86-NEXT:    movss %xmm2, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movss %xmm1, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    calll fmaf
 ; SSE-X86-NEXT:    fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhlps {{.*#+}} xmm0 = xmm0[1,1]
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhlps {{.*#+}} xmm0 = xmm0[1,1]
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhlps {{.*#+}} xmm0 = xmm0[1,1]
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    calll fmaf
 ; SSE-X86-NEXT:    fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    calll fmaf
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-X86-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    fstps {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
 ; SSE-X86-NEXT:    fstps {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
 ; SSE-X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    calll fmaf
 ; SSE-X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
 ; SSE-X86-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; SSE-X86-NEXT:    addl $108, %esp

 ; SSE-X86-NEXT:    calll fma
 ; SSE-X86-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhps %xmm0, (%esp)
 ; SSE-X86-NEXT:    fstpl {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    calll fma
 ; SSE-X86-NEXT:    fstpl {{[0-9]+}}(%esp)
+; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: f14:

llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll

 ; SSE-32-NEXT:    .cfi_offset %ebp, -8
 ; SSE-32-NEXT:    movl %esp, %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-32-NEXT:    andl $-8, %esp
 ; SSE-32-NEXT:    subl $24, %esp
 ; SSE-32-NEXT:    movhps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movlps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero

 ; AVX-32-NEXT:    andl $-8, %esp
 ; AVX-32-NEXT:    subl $16, %esp
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vmovhps %xmm0, (%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl

 ; AVX512F-32-NEXT:    andl $-8, %esp
 ; AVX512F-32-NEXT:    subl $16, %esp
 ; AVX512F-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    vmovhps %xmm0, (%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    movl %ebp, %esp
 ; AVX512F-32-NEXT:    popl %ebp
 ; AVX512F-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512F-32-NEXT:    retl

 ; AVX512VL-32-NEXT:    andl $-8, %esp
 ; AVX512VL-32-NEXT:    subl $16, %esp
 ; AVX512VL-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    vmovhps %xmm0, (%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    movl %ebp, %esp
 ; AVX512VL-32-NEXT:    popl %ebp
 ; AVX512VL-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512VL-32-NEXT:    retl

 ; SSE-32-NEXT:  # %bb.1:
 ; SSE-32-NEXT:    movapd %xmm2, %xmm3
 ; SSE-32-NEXT:  .LBB1_2:
 ; SSE-32-NEXT:    movapd %xmm0, %xmm4
 ; SSE-32-NEXT:    subsd %xmm3, %xmm4
 ; SSE-32-NEXT:    movsd %xmm4, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %al
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; SSE-32-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; SSE-32-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
 ; SSE-32-NEXT:    comisd %xmm2, %xmm0
 ; SSE-32-NEXT:    jb .LBB1_4
 ; SSE-32-NEXT:  # %bb.3:
 ; SSE-32-NEXT:    movapd %xmm2, %xmm1
 ; SSE-32-NEXT:  .LBB1_4:
 ; SSE-32-NEXT:    subsd %xmm1, %xmm0
 ; SSE-32-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %cl
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %edx
 ; SSE-32-NEXT:    orl $3072, %edx # imm = 0xC00
 ; SSE-32-NEXT:    movw %dx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movzbl %al, %eax

 ; AVX-32-NEXT:    jb .LBB1_2
 ; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB1_2:
 ; AVX-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovsd %xmm3, (%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %al
 ; AVX-32-NEXT:    movzbl %al, %eax
 ; AVX-32-NEXT:    shll $31, %eax
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX-32-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX-32-NEXT:    jb .LBB1_4
 ; AVX-32-NEXT:  # %bb.3:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm2
 ; AVX-32-NEXT:  .LBB1_4:
 ; AVX-32-NEXT:    vsubsd %xmm2, %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0

 ; AVX512F-32-NEXT:    kmovw %ecx, %k1
 ; AVX512F-32-NEXT:    vxorpd %xmm3, %xmm3, %xmm3
 ; AVX512F-32-NEXT:    vmovapd %xmm2, %xmm4
 ; AVX512F-32-NEXT:    vmovsd %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubsd %xmm4, %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vmovsd %xmm1, (%esp)
 ; AVX512F-32-NEXT:    fldl (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %al
 ; AVX512F-32-NEXT:    shll $31, %eax
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    xorl %ecx, %ecx
 ; AVX512F-32-NEXT:    vcomisd %xmm2, %xmm0
 ; AVX512F-32-NEXT:    setb %dl
 ; AVX512F-32-NEXT:    kmovw %edx, %k1
 ; AVX512F-32-NEXT:    vmovsd %xmm3, %xmm2, %xmm2 {%k1}
 ; AVX512F-32-NEXT:    vsubsd %xmm2, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %cl
 ; AVX512F-32-NEXT:    shll $31, %ecx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    movl %ebp, %esp

 ; AVX512VL-32-NEXT:    kmovw %ecx, %k1
 ; AVX512VL-32-NEXT:    vxorpd %xmm3, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovapd %xmm2, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vmovsd %xmm1, (%esp)
 ; AVX512VL-32-NEXT:    fldl (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    xorl %ecx, %ecx
 ; AVX512VL-32-NEXT:    vcomisd %xmm2, %xmm0
 ; AVX512VL-32-NEXT:    setb %dl
 ; AVX512VL-32-NEXT:    kmovw %edx, %k1
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, %xmm2, %xmm2 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm2, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %cl
 ; AVX512VL-32-NEXT:    shll $31, %ecx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    movl %ebp, %esp

 ; SSE-32-NEXT:    movl %esp, %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-32-NEXT:    andl $-8, %esp
 ; SSE-32-NEXT:    subl $24, %esp
 ; SSE-32-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-32-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero

 ; AVX-32-NEXT:    andl $-8, %esp
 ; AVX-32-NEXT:    subl $16, %esp
 ; AVX-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-32-NEXT:    vextractps $1, %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl

 ; AVX512F-32-NEXT:    andl $-8, %esp
 ; AVX512F-32-NEXT:    subl $16, %esp
 ; AVX512F-32-NEXT:    vmovd %xmm0, (%esp)
 ; AVX512F-32-NEXT:    vextractps $1, %xmm0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    movl %ebp, %esp
 ; AVX512F-32-NEXT:    popl %ebp
 ; AVX512F-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512F-32-NEXT:    retl

 ; AVX512VL-32-NEXT:    andl $-8, %esp
 ; AVX512VL-32-NEXT:    subl $16, %esp
 ; AVX512VL-32-NEXT:    vmovd %xmm0, (%esp)
 ; AVX512VL-32-NEXT:    vextractps $1, %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    movl %ebp, %esp
 ; AVX512VL-32-NEXT:    popl %ebp
 ; AVX512VL-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX512VL-32-NEXT:    retl

 ; SSE-32-NEXT:  # %bb.1:
 ; SSE-32-NEXT:    movaps %xmm2, %xmm3
 ; SSE-32-NEXT:  .LBB3_2:
 ; SSE-32-NEXT:    movaps %xmm0, %xmm4
 ; SSE-32-NEXT:    subss %xmm3, %xmm4
 ; SSE-32-NEXT:    movss %xmm4, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %al
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; SSE-32-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; SSE-32-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-32-NEXT:    comiss %xmm2, %xmm0
 ; SSE-32-NEXT:    jb .LBB3_4
 ; SSE-32-NEXT:  # %bb.3:
 ; SSE-32-NEXT:    movaps %xmm2, %xmm1
 ; SSE-32-NEXT:  .LBB3_4:
 ; SSE-32-NEXT:    subss %xmm1, %xmm0
 ; SSE-32-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %cl
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %edx
 ; SSE-32-NEXT:    orl $3072, %edx # imm = 0xC00
 ; SSE-32-NEXT:    movw %dx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movzbl %al, %eax

 ; AVX-32-NEXT:    jb .LBB3_2
 ; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB3_2:
 ; AVX-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %al
 ; AVX-32-NEXT:    movzbl %al, %eax
 ; AVX-32-NEXT:    shll $31, %eax
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX-32-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-32-NEXT:    jb .LBB3_4
 ; AVX-32-NEXT:  # %bb.3:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm2
 ; AVX-32-NEXT:  .LBB3_4:
 ; AVX-32-NEXT:    vsubss %xmm2, %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0

 ; AVX512F-32-NEXT:    kmovw %ecx, %k1
 ; AVX512F-32-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; AVX512F-32-NEXT:    vmovaps %xmm2, %xmm4
 ; AVX512F-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubss %xmm4, %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vmovss %xmm1, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %al
 ; AVX512F-32-NEXT:    shll $31, %eax
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    xorl %ecx, %ecx
 ; AVX512F-32-NEXT:    vcomiss %xmm2, %xmm0
 ; AVX512F-32-NEXT:    setb %dl
 ; AVX512F-32-NEXT:    kmovw %edx, %k1
 ; AVX512F-32-NEXT:    vmovss %xmm3, %xmm2, %xmm2 {%k1}
 ; AVX512F-32-NEXT:    vsubss %xmm2, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX512F-32-NEXT:    flds (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %cl
 ; AVX512F-32-NEXT:    shll $31, %ecx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    movl %ebp, %esp

 ; AVX512VL-32-NEXT:    kmovw %ecx, %k1
 ; AVX512VL-32-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovaps %xmm2, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vmovss %xmm1, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    xorl %ecx, %ecx
 ; AVX512VL-32-NEXT:    vcomiss %xmm2, %xmm0
 ; AVX512VL-32-NEXT:    setb %dl
 ; AVX512VL-32-NEXT:    kmovw %edx, %k1
 ; AVX512VL-32-NEXT:    vmovss %xmm3, %xmm2, %xmm2 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm2, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX512VL-32-NEXT:    flds (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %cl
 ; AVX512VL-32-NEXT:    shll $31, %ecx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    movl %ebp, %esp

 ; AVX-32-NEXT:    andl $-8, %esp
 ; AVX-32-NEXT:    subl $16, %esp
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vmovhps %xmm0, (%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl
 ;
 ; AVX-64-LABEL: strict_vector_fptoui_v2f64_to_v2i32:

 ; AVX-32-NEXT:    andl $-8, %esp
 ; AVX-32-NEXT:    subl $16, %esp
 ; AVX-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-32-NEXT:    vextractps $1, %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl
 ;
 ; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i32:

 ; SSE-32-NEXT:    .cfi_offset %ebp, -8
 ; SSE-32-NEXT:    movl %esp, %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-32-NEXT:    andl $-8, %esp
 ; SSE-32-NEXT:    subl $24, %esp
 ; SSE-32-NEXT:    movhps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movlps %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero

 ; AVX-32-NEXT:    andl $-8, %esp
 ; AVX-32-NEXT:    subl $16, %esp
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vmovhps %xmm0, (%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl

 ; SSE-32-NEXT:  # %bb.1:
 ; SSE-32-NEXT:    movapd %xmm2, %xmm3
 ; SSE-32-NEXT:  .LBB17_2:
 ; SSE-32-NEXT:    movapd %xmm0, %xmm4
 ; SSE-32-NEXT:    subsd %xmm3, %xmm4
 ; SSE-32-NEXT:    movsd %xmm4, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %al
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; SSE-32-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; SSE-32-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
 ; SSE-32-NEXT:    comisd %xmm2, %xmm0
 ; SSE-32-NEXT:    jb .LBB17_4
 ; SSE-32-NEXT:  # %bb.3:
 ; SSE-32-NEXT:    movapd %xmm2, %xmm1
 ; SSE-32-NEXT:  .LBB17_4:
 ; SSE-32-NEXT:    subsd %xmm1, %xmm0
 ; SSE-32-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %cl
 ; SSE-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %edx
 ; SSE-32-NEXT:    orl $3072, %edx # imm = 0xC00
 ; SSE-32-NEXT:    movw %dx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movzbl %al, %eax

 ; AVX-32-NEXT:    jb .LBB17_2
 ; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB17_2:
 ; AVX-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovsd %xmm3, (%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %al
 ; AVX-32-NEXT:    movzbl %al, %eax
 ; AVX-32-NEXT:    shll $31, %eax
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX-32-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX-32-NEXT:    jb .LBB17_4
 ; AVX-32-NEXT:  # %bb.3:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm2
 ; AVX-32-NEXT:  .LBB17_4:
 ; AVX-32-NEXT:    vsubsd %xmm2, %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0

 ; SSE-32-NEXT:    movl %esp, %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-32-NEXT:    andl $-8, %esp
 ; SSE-32-NEXT:    subl $24, %esp
 ; SSE-32-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-32-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %eax
 ; SSE-32-NEXT:    orl $3072, %eax # imm = 0xC00
 ; SSE-32-NEXT:    movw %ax, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero

 ; AVX-32-NEXT:    andl $-8, %esp
 ; AVX-32-NEXT:    subl $16, %esp
 ; AVX-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-32-NEXT:    vextractps $1, %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl

 ; SSE-32-NEXT:  # %bb.1:
 ; SSE-32-NEXT:    movaps %xmm2, %xmm3
 ; SSE-32-NEXT:  .LBB19_2:
 ; SSE-32-NEXT:    movaps %xmm0, %xmm4
 ; SSE-32-NEXT:    subss %xmm3, %xmm4
 ; SSE-32-NEXT:    movss %xmm4, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %al
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; SSE-32-NEXT:    orl $3072, %ecx # imm = 0xC00
 ; SSE-32-NEXT:    movw %cx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-32-NEXT:    comiss %xmm2, %xmm0
 ; SSE-32-NEXT:    jb .LBB19_4
 ; SSE-32-NEXT:  # %bb.3:
 ; SSE-32-NEXT:    movaps %xmm2, %xmm1
 ; SSE-32-NEXT:  .LBB19_4:
 ; SSE-32-NEXT:    subss %xmm1, %xmm0
 ; SSE-32-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    setae %cl
 ; SSE-32-NEXT:    flds {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    fnstcw (%esp)
 ; SSE-32-NEXT:    movzwl (%esp), %edx
 ; SSE-32-NEXT:    orl $3072, %edx # imm = 0xC00
 ; SSE-32-NEXT:    movw %dx, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fldcw (%esp)
 ; SSE-32-NEXT:    movzbl %al, %eax

 ; AVX-32-NEXT:    jb .LBB19_2
 ; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB19_2:
 ; AVX-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %al
 ; AVX-32-NEXT:    movzbl %al, %eax
 ; AVX-32-NEXT:    shll $31, %eax
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX-32-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-32-NEXT:    jb .LBB19_4
 ; AVX-32-NEXT:  # %bb.3:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm2
 ; AVX-32-NEXT:  .LBB19_4:
 ; AVX-32-NEXT:    vsubss %xmm2, %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovss %xmm0, (%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0

llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll

 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX-32-NEXT:    jb .LBB1_2
 ; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB1_2:
 ; AVX-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovsd %xmm3, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %al
 ; AVX-32-NEXT:    movzbl %al, %eax
 ; AVX-32-NEXT:    shll $31, %eax
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX-32-NEXT:    vextractf128 $1, %ymm0, %xmm3
 ; AVX-32-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm3[1,0]
 ; AVX-32-NEXT:    vcomisd %xmm1, %xmm4
 ; AVX-32-NEXT:    vxorpd %xmm5, %xmm5, %xmm5
 ; AVX-32-NEXT:    jb .LBB1_4
 ; AVX-32-NEXT:  # %bb.3:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm5
 ; AVX-32-NEXT:  .LBB1_4:
 ; AVX-32-NEXT:    vsubsd %xmm5, %xmm4, %xmm4
 ; AVX-32-NEXT:    vmovsd %xmm4, (%esp)
 ; AVX-32-NEXT:    fldl (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX-32-NEXT:    vcomisd %xmm1, %xmm3
 ; AVX-32-NEXT:    vxorpd %xmm4, %xmm4, %xmm4
 ; AVX-32-NEXT:    jb .LBB1_6
 ; AVX-32-NEXT:  # %bb.5:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB1_6:
 ; AVX-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovsd %xmm3, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %dl
 ; AVX-32-NEXT:    movzbl %dl, %edx
 ; AVX-32-NEXT:    shll $31, %edx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX-32-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX-32-NEXT:    jb .LBB1_8
 ; AVX-32-NEXT:  # %bb.7:
 ; AVX-32-NEXT:    vmovapd %xmm1, %xmm2
 ; AVX-32-NEXT:  .LBB1_8:
 ; AVX-32-NEXT:    vsubsd %xmm2, %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx

 ; AVX512F-32-NEXT:    kmovw %ecx, %k1
 ; AVX512F-32-NEXT:    vxorpd %xmm3, %xmm3, %xmm3
 ; AVX512F-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512F-32-NEXT:    vmovsd %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubsd %xmm4, %xmm2, %xmm2
 ; AVX512F-32-NEXT:    vmovsd %xmm2, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    movl $0, %eax
 ; AVX512F-32-NEXT:    setae %al
 ; AVX512F-32-NEXT:    shll $31, %eax
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    movl %eax, %esi
 ; AVX512F-32-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; AVX512F-32-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm2[1,0]
 ; AVX512F-32-NEXT:    xorl %ecx, %ecx
 ; AVX512F-32-NEXT:    vcomisd %xmm1, %xmm4
 ; AVX512F-32-NEXT:    setb %dl
 ; AVX512F-32-NEXT:    kmovw %edx, %k1
 ; AVX512F-32-NEXT:    vmovapd %xmm1, %xmm5
 ; AVX512F-32-NEXT:    vmovsd %xmm3, %xmm5, %xmm5 {%k1}
 ; AVX512F-32-NEXT:    vsubsd %xmm5, %xmm4, %xmm4
 ; AVX512F-32-NEXT:    vmovsd %xmm4, (%esp)
 ; AVX512F-32-NEXT:    fldl (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %cl
 ; AVX512F-32-NEXT:    shll $31, %ecx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512F-32-NEXT:    xorl %edx, %edx
 ; AVX512F-32-NEXT:    vcomisd %xmm1, %xmm2
 ; AVX512F-32-NEXT:    setb %bl
 ; AVX512F-32-NEXT:    kmovw %ebx, %k1
 ; AVX512F-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512F-32-NEXT:    vmovsd %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubsd %xmm4, %xmm2, %xmm2
 ; AVX512F-32-NEXT:    vmovsd %xmm2, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %dl
 ; AVX512F-32-NEXT:    shll $31, %edx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    xorl %ebx, %ebx
 ; AVX512F-32-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX512F-32-NEXT:    setb %al
 ; AVX512F-32-NEXT:    kmovw %eax, %k1
 ; AVX512F-32-NEXT:    vmovsd %xmm3, %xmm1, %xmm1 {%k1}
 ; AVX512F-32-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    setae %bl
 ; AVX512F-32-NEXT:    shll $31, %ebx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %ebx
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero

 ; AVX512VL-32-NEXT:    kmovw %ecx, %k1
 ; AVX512VL-32-NEXT:    vxorpd %xmm3, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, %esi
 ; AVX512VL-32-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm2[1,0]
 ; AVX512VL-32-NEXT:    xorl %ecx, %ecx
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    setb %dl
 ; AVX512VL-32-NEXT:    kmovw %edx, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm5
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, %xmm5, %xmm5 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm5, %xmm4, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm4, (%esp)
 ; AVX512VL-32-NEXT:    fldl (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %cl
 ; AVX512VL-32-NEXT:    shll $31, %ecx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512VL-32-NEXT:    xorl %edx, %edx
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm2
 ; AVX512VL-32-NEXT:    setb %bl
 ; AVX512VL-32-NEXT:    kmovw %ebx, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %dl
 ; AVX512VL-32-NEXT:    shll $31, %edx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512VL-32-NEXT:    xorl %ebx, %ebx
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, %xmm1, %xmm1 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    setae %bl
 ; AVX512VL-32-NEXT:    shll $31, %ebx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %ebx
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero

 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX512F-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX-32-NEXT:    jb .LBB3_2
 ; AVX-32-NEXT:  # %bb.1:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB3_2:
 ; AVX-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %al
 ; AVX-32-NEXT:    movzbl %al, %eax
 ; AVX-32-NEXT:    shll $31, %eax
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX-32-NEXT:    vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3]
 ; AVX-32-NEXT:    vcomiss %xmm1, %xmm3
 ; AVX-32-NEXT:    vxorps %xmm4, %xmm4, %xmm4
 ; AVX-32-NEXT:    jb .LBB3_4
 ; AVX-32-NEXT:  # %bb.3:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB3_4:
 ; AVX-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovss %xmm3, (%esp)
 ; AVX-32-NEXT:    flds (%esp)
 ; AVX-32-NEXT:    fisttpll (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX-32-NEXT:    vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
 ; AVX-32-NEXT:    vcomiss %xmm1, %xmm3
 ; AVX-32-NEXT:    vxorps %xmm4, %xmm4, %xmm4
 ; AVX-32-NEXT:    jb .LBB3_6
 ; AVX-32-NEXT:  # %bb.5:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX-32-NEXT:  .LBB3_6:
 ; AVX-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    setae %dl
 ; AVX-32-NEXT:    movzbl %dl, %edx
 ; AVX-32-NEXT:    shll $31, %edx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX-32-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-32-NEXT:    jb .LBB3_8
 ; AVX-32-NEXT:  # %bb.7:
 ; AVX-32-NEXT:    vmovaps %xmm1, %xmm2
 ; AVX-32-NEXT:  .LBB3_8:
 ; AVX-32-NEXT:    vsubss %xmm2, %xmm0, %xmm0
 ; AVX-32-NEXT:    vmovss %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX-32-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
 ; AVX-32-NEXT:    setae %cl
 ; AVX-32-NEXT:    movzbl %cl, %ecx
 ; AVX-32-NEXT:    shll $31, %ecx
 ; AVX-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx

 ; AVX512F-32-NEXT:    kmovw %ecx, %k1
 ; AVX512F-32-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; AVX512F-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512F-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubss %xmm4, %xmm2, %xmm2
 ; AVX512F-32-NEXT:    vmovss %xmm2, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    movl $0, %eax
 ; AVX512F-32-NEXT:    setae %al
 ; AVX512F-32-NEXT:    shll $31, %eax
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    movl %eax, %esi
 ; AVX512F-32-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[3,1,2,3]
 ; AVX512F-32-NEXT:    xorl %ecx, %ecx
 ; AVX512F-32-NEXT:    vcomiss %xmm1, %xmm2
 ; AVX512F-32-NEXT:    setb %dl
 ; AVX512F-32-NEXT:    kmovw %edx, %k1
 ; AVX512F-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512F-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubss %xmm4, %xmm2, %xmm2
 ; AVX512F-32-NEXT:    vmovss %xmm2, (%esp)
 ; AVX512F-32-NEXT:    flds (%esp)
 ; AVX512F-32-NEXT:    fisttpll (%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %cl
 ; AVX512F-32-NEXT:    shll $31, %ecx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512F-32-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
 ; AVX512F-32-NEXT:    xorl %edx, %edx
 ; AVX512F-32-NEXT:    vcomiss %xmm1, %xmm2
 ; AVX512F-32-NEXT:    setb %bl
 ; AVX512F-32-NEXT:    kmovw %ebx, %k1
 ; AVX512F-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512F-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512F-32-NEXT:    vsubss %xmm4, %xmm2, %xmm2
 ; AVX512F-32-NEXT:    vmovss %xmm2, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    setae %dl
 ; AVX512F-32-NEXT:    shll $31, %edx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    xorl %ebx, %ebx
 ; AVX512F-32-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX512F-32-NEXT:    setb %al
 ; AVX512F-32-NEXT:    kmovw %eax, %k1
 ; AVX512F-32-NEXT:    vmovss %xmm3, %xmm1, %xmm1 {%k1}
 ; AVX512F-32-NEXT:    vsubss %xmm1, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vmovss %xmm0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512F-32-NEXT:    wait
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512F-32-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512F-32-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
 ; AVX512F-32-NEXT:    setae %bl
 ; AVX512F-32-NEXT:    shll $31, %ebx
 ; AVX512F-32-NEXT:    xorl {{[0-9]+}}(%esp), %ebx
 ; AVX512F-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero

 ; AVX512VL-32-NEXT:    kmovw %ecx, %k1
 ; AVX512VL-32-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovss %xmm2, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, %esi
 ; AVX512VL-32-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[3,1,2,3]
 ; AVX512VL-32-NEXT:    xorl %ecx, %ecx
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm2
 ; AVX512VL-32-NEXT:    setb %dl
 ; AVX512VL-32-NEXT:    kmovw %edx, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovss %xmm2, (%esp)
 ; AVX512VL-32-NEXT:    flds (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %cl
 ; AVX512VL-32-NEXT:    shll $31, %ecx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
 ; AVX512VL-32-NEXT:    xorl %edx, %edx
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm2
 ; AVX512VL-32-NEXT:    setb %bl
 ; AVX512VL-32-NEXT:    kmovw %ebx, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm3, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovss %xmm2, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %dl
 ; AVX512VL-32-NEXT:    shll $31, %edx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512VL-32-NEXT:    xorl %ebx, %ebx
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovss %xmm3, %xmm1, %xmm1 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm1, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovss %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    setae %bl
 ; AVX512VL-32-NEXT:    shll $31, %ebx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %ebx
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero

llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll

 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; AVX512VL-32-NEXT:    vextractf128 $1, %ymm0, %xmm3
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm3[1,0]
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm5
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm5, %xmm5 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm5, %xmm4, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm4, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; AVX512VL-32-NEXT:    vextractf32x4 $2, %zmm0, %xmm3
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm3[1,0]
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm5
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm5, %xmm5 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm5, %xmm4, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm4, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, %edi
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, %esi
 ; AVX512VL-32-NEXT:    vextractf32x4 $3, %zmm0, %xmm3
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm3[1,0]
 ; AVX512VL-32-NEXT:    xorl %edx, %edx
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm5
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm5, %xmm5 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm5, %xmm4, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm4, (%esp)
 ; AVX512VL-32-NEXT:    fldl (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %dl
 ; AVX512VL-32-NEXT:    shll $31, %edx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512VL-32-NEXT:    xorl %eax, %eax
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %cl
 ; AVX512VL-32-NEXT:    kmovw %ecx, %k1
 ; AVX512VL-32-NEXT:    vmovapd %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovsd %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    xorl %ecx, %ecx
 ; AVX512VL-32-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX512VL-32-NEXT:    setb %bl
 ; AVX512VL-32-NEXT:    kmovw %ebx, %k1
 ; AVX512VL-32-NEXT:    vmovsd %xmm2, %xmm1, %xmm1 {%k1}
 ; AVX512VL-32-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %eax, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, %edx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %esi, %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $3, %edi, %xmm1, %xmm1

 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1

 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vxorps %xmm2, %xmm2, %xmm2
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; AVX512VL-32-NEXT:    vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3]
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; AVX512VL-32-NEXT:    vextractf128 $1, %ymm0, %xmm3
 ; AVX512VL-32-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm3[1,1,3,3]
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm5
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm5, %xmm5 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm5, %xmm4, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm4, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, %edi
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm3, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm4, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    movl $0, %eax
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    movl %eax, %esi
 ; AVX512VL-32-NEXT:    vpermilps {{.*#+}} xmm4 = xmm3[3,1,2,3]
 ; AVX512VL-32-NEXT:    xorl %edx, %edx
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    setb %al
 ; AVX512VL-32-NEXT:    kmovw %eax, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm5
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm5, %xmm5 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm5, %xmm4, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm4, (%esp)
 ; AVX512VL-32-NEXT:    flds (%esp)
 ; AVX512VL-32-NEXT:    fisttpll (%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %dl
 ; AVX512VL-32-NEXT:    shll $31, %edx
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
 ; AVX512VL-32-NEXT:    vpermilpd {{.*#+}} xmm3 = xmm3[1,0]
 ; AVX512VL-32-NEXT:    xorl %eax, %eax
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm3
 ; AVX512VL-32-NEXT:    setb %cl
 ; AVX512VL-32-NEXT:    kmovw %ecx, %k1
 ; AVX512VL-32-NEXT:    vmovaps %xmm1, %xmm4
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm4, %xmm4 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm4, %xmm3, %xmm3
 ; AVX512VL-32-NEXT:    vmovss %xmm3, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    setae %al
 ; AVX512VL-32-NEXT:    shll $31, %eax
 ; AVX512VL-32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
 ; AVX512VL-32-NEXT:    xorl %ecx, %ecx
 ; AVX512VL-32-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX512VL-32-NEXT:    setb %bl
 ; AVX512VL-32-NEXT:    kmovw %ebx, %k1
 ; AVX512VL-32-NEXT:    vmovss %xmm2, %xmm1, %xmm1 {%k1}
 ; AVX512VL-32-NEXT:    vsubss %xmm1, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovss %xmm0, {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    flds {{[0-9]+}}(%esp)
 ; AVX512VL-32-NEXT:    fisttpll {{[0-9]+}}(%esp)
+; AVX512VL-32-NEXT:    wait
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %eax, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $2, (%esp), %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vpinsrd $3, %edx, %xmm0, %xmm0
 ; AVX512VL-32-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX512VL-32-NEXT:    vpinsrd $1, %esi, %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; AVX512VL-32-NEXT:    vpinsrd $3, %edi, %xmm1, %xmm1

llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll

 ; SSE-32-NEXT:    subl $24, %esp
 ; SSE-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fstps (%esp)
 ; SSE-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE-32-NEXT:    movl %ebp, %esp
 ; SSE-32-NEXT:    popl %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-32-NEXT:    retl
 ;

 ; SSE41-32-NEXT:    subl $24, %esp
 ; SSE41-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE41-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fstps (%esp)
 ; SSE41-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE41-32-NEXT:    wait
 ; SSE41-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE41-32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE41-32-NEXT:    movl %ebp, %esp
 ; SSE41-32-NEXT:    popl %ebp
 ; SSE41-32-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-32-NEXT:    retl
 ;

 ; AVX-32-NEXT:    subl $24, %esp
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstps (%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl
 ;
 ; AVX-64-LABEL: sitofp_v2i64_v2f32:

 ; SSE-32-NEXT:    movq %xmm1, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
 ; SSE-32-NEXT:    movd %xmm1, %eax
 ; SSE-32-NEXT:    shrl $31, %eax
 ; SSE-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; SSE-32-NEXT:    fstps (%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE-32-NEXT:    movd %xmm0, %eax
 ; SSE-32-NEXT:    shrl $31, %eax
 ; SSE-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; SSE-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE-32-NEXT:    movl %ebp, %esp
 ; SSE-32-NEXT:    popl %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-32-NEXT:    retl
 ;

 ; SSE41-32-NEXT:    movq %xmm1, {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
 ; SSE41-32-NEXT:    movd %xmm1, %eax
 ; SSE41-32-NEXT:    shrl $31, %eax
 ; SSE41-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; SSE41-32-NEXT:    fstps (%esp)
+; SSE41-32-NEXT:    wait
 ; SSE41-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE41-32-NEXT:    movd %xmm0, %eax
 ; SSE41-32-NEXT:    shrl $31, %eax
 ; SSE41-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; SSE41-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; SSE41-32-NEXT:    wait
 ; SSE41-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE41-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE41-32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE41-32-NEXT:    movl %ebp, %esp
 ; SSE41-32-NEXT:    popl %ebp
 ; SSE41-32-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-32-NEXT:    retl
 ;

 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
 ; AVX-32-NEXT:    vmovlps %xmm1, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vextractps $1, %xmm0, %eax
 ; AVX-32-NEXT:    shrl $31, %eax
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vextractps $3, %xmm0, %eax
 ; AVX-32-NEXT:    shrl $31, %eax
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-32-NEXT:    fstps (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl
 ;
 ; AVX1-64-LABEL: uitofp_v2i64_v2f32:

 ; SSE-32-NEXT:    subl $32, %esp
 ; SSE-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE-32-NEXT:    fstpl (%esp)
+; SSE-32-NEXT:    wait
 ; SSE-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-32-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; SSE-32-NEXT:    movl %ebp, %esp
 ; SSE-32-NEXT:    popl %ebp
 ; SSE-32-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-32-NEXT:    retl
 ;
 ; SSE-64-LABEL: sitofp_v2i64_v2f64:

 ; SSE41-32-NEXT:    subl $32, %esp
 ; SSE41-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE41-32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; SSE41-32-NEXT:    fstpl (%esp)
+; SSE41-32-NEXT:    wait
 ; SSE41-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-32-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; SSE41-32-NEXT:    movl %ebp, %esp
 ; SSE41-32-NEXT:    popl %ebp
 ; SSE41-32-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE41-32-NEXT:    retl
 ;
 ; SSE41-64-LABEL: sitofp_v2i64_v2f64:

 ; AVX-32-NEXT:    subl $32, %esp
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstpl (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-32-NEXT:    vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl
 ;
 ; AVX-64-LABEL: sitofp_v2i64_v2f64:

llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

 ; AVX-32-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; AVX-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstpl {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-32-NEXT:    vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstpl (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
 ; AVX-32-NEXT:    vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
 ; AVX-32-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    retl
 ;

 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fstps (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    vzeroupper

 ; AVX-32-NEXT:    vmovlps %xmm1, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
 ; AVX-32-NEXT:    vmovlps %xmm2, {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    vextractps $1, %xmm0, %eax
 ; AVX-32-NEXT:    shrl $31, %eax
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-32-NEXT:    fstps (%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vextractps $3, %xmm0, %eax
 ; AVX-32-NEXT:    shrl $31, %eax
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vextractps $1, %xmm1, %eax
 ; AVX-32-NEXT:    shrl $31, %eax
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vextractps $3, %xmm1, %eax
 ; AVX-32-NEXT:    shrl $31, %eax
 ; AVX-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; AVX-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; AVX-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; AVX-32-NEXT:    wait
 ; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
 ; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; AVX-32-NEXT:    movl %ebp, %esp
 ; AVX-32-NEXT:    popl %ebp
 ; AVX-32-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX-32-NEXT:    vzeroupper

llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll

 ; NODQ-32-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; NODQ-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; NODQ-32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; NODQ-32-NEXT:    vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl (%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
 ; NODQ-32-NEXT:    vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
 ; NODQ-32-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
 ; NODQ-32-NEXT:    vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstpl {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovsd {{.*#+}} xmm2 = mem[0],zero
 ; NODQ-32-NEXT:    vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1]
 ; NODQ-32-NEXT:    vinsertf128 $1, %xmm2, %ymm1, %ymm1
 ; NODQ-32-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; NODQ-32-NEXT:    movl %ebp, %esp
 ; NODQ-32-NEXT:    popl %ebp
 ; NODQ-32-NEXT:    .cfi_def_cfa %esp, 4
 ; NODQ-32-NEXT:    retl

 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fstps (%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
 ; NODQ-32-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; NODQ-32-NEXT:    movl %ebp, %esp
 ; NODQ-32-NEXT:    popl %ebp
 ; NODQ-32-NEXT:    .cfi_def_cfa %esp, 4

 ; NODQ-32-NEXT:    vmovlps %xmm1, {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    vpermilps {{.*#+}} xmm4 = xmm1[2,3,0,1]
 ; NODQ-32-NEXT:    vmovlps %xmm4, {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    vextractps $1, %xmm0, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps (%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $3, %xmm0, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $1, %xmm3, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $3, %xmm3, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $1, %xmm2, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $3, %xmm2, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $1, %xmm1, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vextractps $3, %xmm1, %eax
 ; NODQ-32-NEXT:    shrl $31, %eax
 ; NODQ-32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; NODQ-32-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
 ; NODQ-32-NEXT:    fstps {{[0-9]+}}(%esp)
+; NODQ-32-NEXT:    wait
 ; NODQ-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; NODQ-32-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
 ; NODQ-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

 ; CHECK-NEXT:    movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
 ; CHECK-NEXT:    divpd {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    divsd {{.*}}(%rip), %xmm1
 ; CHECK-NEXT:    movsd %xmm1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movapd %xmm0, %xmm1
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_fdiv_v3f64:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    vdivsd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vmovapd {{.*#+}} xmm1 = [1.0E+0,2.0E+0]
 ; AVX-NEXT:    vdivpd {{.*}}(%rip), %xmm1, %xmm1

 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq fmod
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq fmod
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
 ; CHECK-NEXT:    mulpd {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    mulsd {{.*}}(%rip), %xmm1
 ; CHECK-NEXT:    movsd %xmm1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movapd %xmm0, %xmm1
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_fmul_v3f64:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    vmulsd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vmovapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308]
 ; AVX-NEXT:    vmulpd {{.*}}(%rip), %xmm1, %xmm1

 ; CHECK-NEXT:    movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
 ; CHECK-NEXT:    addpd {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    xorpd %xmm1, %xmm1
 ; CHECK-NEXT:    addsd {{.*}}(%rip), %xmm1
 ; CHECK-NEXT:    movsd %xmm1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movapd %xmm0, %xmm1
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_fadd_v3f64:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vxorpd %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    vaddsd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vmovapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308]
 ; AVX-NEXT:    vaddpd {{.*}}(%rip), %xmm1, %xmm1

 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    subsd %xmm0, %xmm1
 ; CHECK-NEXT:    movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
 ; CHECK-NEXT:    subpd {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    movsd %xmm1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movapd %xmm0, %xmm1
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_fsub_v3f64:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vxorpd %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
 ; AVX-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    vmovapd {{.*#+}} xmm1 = [-1.7976931348623157E+308,-1.7976931348623157E+308]

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    sqrtsd %xmm0, %xmm1
 ; CHECK-NEXT:    sqrtpd {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    movsd %xmm1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movapd %xmm0, %xmm1
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_sqrt_v3f64:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    vsqrtpd {{.*}}(%rip), %xmm1
 ; AVX-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0

 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq pow
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq pow
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movl $3, %edi
 ; CHECK-NEXT:    callq __powidf2
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movl $3, %edi
 ; CHECK-NEXT:    callq __powidf2
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq sin
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq sin
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq cos
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq cos
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq exp
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq exp
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq exp2
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq exp2
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq log
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq log
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq log10
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq log10
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq log2
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq log2
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq rint
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq rint
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq nearbyint
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq nearbyint
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq fmax
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq fmax
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq fmin
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    callq fmin
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    cvtss2sd %xmm0, %xmm1
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    cvtss2sd %xmm0, %xmm0
 ; CHECK-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    cvtss2sd %xmm2, %xmm2
 ; CHECK-NEXT:    movsd %xmm2, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_fpext_v3f32:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX-NEXT:    vcvtss2sd %xmm1, %xmm1, %xmm1

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq ceil
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq ceil
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq floor
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq floor
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq round
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq round
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq trunc
 ; CHECK-NEXT:    movsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    callq trunc
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movsd (%rsp), %xmm0 # 8-byte Reload
 ; CHECK-NEXT:    # xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero
 ; CHECK-NEXT:    addq $24, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 ;

 ; CHECK-NEXT:    xorps %xmm1, %xmm1
 ; CHECK-NEXT:    cvtsi2sd %eax, %xmm1
 ; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; CHECK-NEXT:    movd %xmm0, %eax
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    cvtsi2sd %eax, %xmm0
 ; CHECK-NEXT:    movsd %xmm0, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movapd %xmm2, %xmm0
 ; CHECK-NEXT:    retq
 ;
 ; AVX-LABEL: constrained_vector_sitofp_v3f64_v3i32:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vextractps $1, %xmm0, %eax
 ; AVX-NEXT:    vcvtsi2sd %eax, %xmm1, %xmm1
 ; AVX-NEXT:    vmovd %xmm0, %eax

 define <3 x double> @constrained_vector_sitofp_v3f64_v3i64(<3 x i64> %x) #0 {
 ; CHECK-LABEL: constrained_vector_sitofp_v3f64_v3i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cvtsi2sd %rsi, %xmm1
 ; CHECK-NEXT:    cvtsi2sd %rdi, %xmm0
 ; CHECK-NEXT:    cvtsi2sd %rdx, %xmm2
 ; CHECK-NEXT:    movsd %xmm2, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX1-LABEL: constrained_vector_sitofp_v3f64_v3i64:
 ; AVX1:       # %bb.0: # %entry
 ; AVX1-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX1-NEXT:    vcvtsi2sd %rax, %xmm1, %xmm1
 ; AVX1-NEXT:    vmovq %xmm0, %rax
 ; AVX1-NEXT:    vcvtsi2sd %rax, %xmm2, %xmm2

 ; CHECK-NEXT:    xorps %xmm1, %xmm1
 ; CHECK-NEXT:    cvtsi2sd %rax, %xmm1
 ; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; CHECK-NEXT:    movd %xmm0, %eax
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    cvtsi2sd %rax, %xmm0
 ; CHECK-NEXT:    movsd %xmm0, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    movapd %xmm2, %xmm0
 ; CHECK-NEXT:    retq
 ;
 ; AVX1-LABEL: constrained_vector_uitofp_v3f64_v3i32:
 ; AVX1:       # %bb.0: # %entry
 ; AVX1-NEXT:    vextractps $1, %xmm0, %eax
 ; AVX1-NEXT:    vcvtsi2sd %rax, %xmm1, %xmm1
 ; AVX1-NEXT:    vmovd %xmm0, %eax

 ; CHECK-NEXT:    movq %rdx, %xmm4
 ; CHECK-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
 ; CHECK-NEXT:    subpd %xmm3, %xmm4
 ; CHECK-NEXT:    movapd %xmm4, %xmm2
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm4[1]
 ; CHECK-NEXT:    addpd %xmm4, %xmm2
 ; CHECK-NEXT:    movlpd %xmm2, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fldl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    wait
 ; CHECK-NEXT:    retq
 ;
 ; AVX1-LABEL: constrained_vector_uitofp_v3f64_v3i64:
 ; AVX1:       # %bb.0: # %entry
 ; AVX1-NEXT:    vmovapd {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
 ; AVX1-NEXT:    vunpcklps {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; AVX1-NEXT:    vmovapd {{.*#+}} xmm3 = [4.503599627370496E+15,1.9342813113834067E+25]
 ; AVX1-NEXT:    vsubpd %xmm3, %xmm2, %xmm2