This is one of the suggestions for eliminating a regression in D63815.
If we are FP extending the high half extract of a vector, we should be able to peek through a bitcast sitting between the extract and extend.
Details
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Event Timeline
llvm/lib/Target/AArch64/AArch64InstrInfo.td | ||
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3639 | This looks correct. Can we generalize this to handle the top half of any 128-bit vector, somehow? Extending the set of special cases to include v2i64 in addition to v4f32 doesn't seem like a complete plan. |
llvm/lib/Target/AArch64/AArch64InstrInfo.td | ||
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3639 | I don't know how to hack this in tablegen, but it seems straightforward in DAGToDAGISel. |
Patch updated:
- Added tests for other casts and half->float. (rGfbaf835c5c51)
- Add a helper to AArch64DAGToDAGISel to deal with all high half extend possibilities.
- Remove redundant tablegen patterns for fcvtl2.
LGTM with one minor nit
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | ||
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3043 | Indentation? |
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | ||
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3043 | Oops - yes, IDE isn't set to comply with clang's switch bracket setting. Will fix on commit. |
Indentation?