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[AArch64] match fcvtl2 with bitcasted extract
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Authored by spatel on Dec 14 2019, 8:29 AM.

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Summary

This is one of the suggestions for eliminating a regression in D63815.
If we are FP extending the high half extract of a vector, we should be able to peek through a bitcast sitting between the extract and extend.

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Event Timeline

spatel created this revision.Dec 14 2019, 8:29 AM
efriedma added inline comments.Dec 16 2019, 6:27 PM
llvm/lib/Target/AArch64/AArch64InstrInfo.td
3651

This looks correct.

Can we generalize this to handle the top half of any 128-bit vector, somehow? Extending the set of special cases to include v2i64 in addition to v4f32 doesn't seem like a complete plan.

spatel marked an inline comment as done.Dec 17 2019, 8:13 AM
spatel added inline comments.
llvm/lib/Target/AArch64/AArch64InstrInfo.td
3651

I don't know how to hack this in tablegen, but it seems straightforward in DAGToDAGISel.

spatel updated this revision to Diff 234310.Dec 17 2019, 8:24 AM
spatel edited the summary of this revision. (Show Details)

Patch updated:

  1. Added tests for other casts and half->float. (rGfbaf835c5c51)
  2. Add a helper to AArch64DAGToDAGISel to deal with all high half extend possibilities.
  3. Remove redundant tablegen patterns for fcvtl2.
efriedma accepted this revision.Dec 17 2019, 4:04 PM

LGTM with one minor nit

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
3043

Indentation?

This revision is now accepted and ready to land.Dec 17 2019, 4:04 PM
spatel marked 2 inline comments as done.Dec 18 2019, 5:44 AM
spatel added inline comments.
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
3043

Oops - yes, IDE isn't set to comply with clang's switch bracket setting. Will fix on commit.

This revision was automatically updated to reflect the committed changes.
spatel marked an inline comment as done.