[AArch64] Save FP for leaf functions when disabling frame pointer elimination

[MaskRay]

Summary

The change allows clang -mno-omit-leaf-frame-pointer to disable frame
pointer elimination. This behavior matches X86 and Mips, and also GCC
AArch64.

[MaskRay]

Fix machine-outliner-regsave.mir. Touch %lr to fix the following -verify-machineinstrs issue

*** Bad machine code: Using an undefined physical register ***                                                                                        
- function:    bar                                       
- basic block: %bb.0  (0x1325e00)                                                                                  
- instruction: early-clobber $sp = STRXpre $lr, $sp(tied-def 0), -16                                                                                  
- operand 1:   $lr

[kamleshbhalui]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

247

MFI.hasCalls() was returning here false, Even for function who has call inside. May be because it is called earlier,before generating Full frame Info . It needs to be removed from here. I could that it is done.

[MaskRay]

Ping:)

[efriedma]

LGTM

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

247

Isn't TargetOptions::DisableFramePointerElim itself calling hasCalls()? I guess we conservatively return true anyway if the frame info isn't computed yet, though, so probably doesn't matter.

[MaskRay]

Ping:)

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

247

TargetOptions::DisableFramePointerElim doesn't call hasCalls(). Deleting hasCalls() will make -frame-pointer=[non-leaf|all] different.

[MaskRay]

Update aarch64-fix-cortex-a53-835769.ll which is sensitive

[efriedma]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

247

TargetOptions::DisableFramePointerElim doesn't call hasCalls()

https://github.com/llvm/llvm-project/blob/11448eeb72e1392f9f4ad072866c2c6dc82d14bc/llvm/lib/CodeGen/TargetOptionsImpl.cpp#L49

[MaskRay]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

247

Thanks for the pointer. It looks there are other cleanup opportunities in TargetOptions::DisableFramePointerElim.

[thakis]

This breaks tests on the "expensive tests" bot: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-debian/builds/514

Please take a look!

[MaskRay]

In D71168#1784724, @thakis wrote:

This breaks tests on the "expensive tests" bot: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-debian/builds/514

Please take a look!

Looking. Where can I find the cmake configuration?

Mine (-DLLVM_ENABLE_ASSERTIONS=On -DLLVM_ENABLE_EXPENSIVE_CHECKS=On) does not build for other reasons:

.../llvm/include/llvm/ADT/PointerUnion.h:93:26: error: constexpr variable 'NumLowBitsAvailable' must be initialized by
 a constant expression                                                                                                                                
    static constexpr int NumLowBitsAvailable = lowBitsAvailable<PTs...>();

[MaskRay]

In D71168#1784849, @MaskRay wrote:

In D71168#1784724, @thakis wrote:

This breaks tests on the "expensive tests" bot: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-debian/builds/514

Please take a look!

Looking. Where can I find the cmake configuration?

Mine (-DLLVM_ENABLE_ASSERTIONS=On -DLLVM_ENABLE_EXPENSIVE_CHECKS=On) does not build for other reasons:

.../llvm/include/llvm/ADT/PointerUnion.h:93:26: error: constexpr variable 'NumLowBitsAvailable' must be initialized by
 a constant expression                                                                                                                                
    static constexpr int NumLowBitsAvailable = lowBitsAvailable<PTs...>();

I find the configuration in https://github.com/llvm/llvm-zorg/blob/master/buildbot/osuosl/master/config/builders.py and reproduce with cmake -GNinja -Hllvm -BExpensive -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_EXPENSIVE_CHECKS=On -DLLVM_ENABLE_WERROR=Off -DCMAKE_CXX_FLAGS=-U_GLIBCXX_DEBUG

Fixed in ccc453eb57b91a4e64ecfd7a9ee8d9415345c6b6

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   // Win64 EH requires a frame pointer if funclets are present, as the locals
   // are accessed off the frame pointer in both the parent function and the
   // funclets.
   if (MF.hasEHFunclets())
     return true;
   // Retain behavior of always omitting the FP for leaf functions when possible.
-  if (MFI.hasCalls() && MF.getTarget().Options.DisableFramePointerElim(MF))
+  if (MF.getTarget().Options.DisableFramePointerElim(MF))
     return true;
   if (MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
       MFI.hasStackMap() || MFI.hasPatchPoint() ||
       RegInfo->needsStackRealignment(MF))
     return true;
   // With large callframes around we may need to use FP to access the scavenging
   // emergency spillslot.
   //

llvm/test/CodeGen/AArch64/GlobalISel/tail-call-no-save-fp-lr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -global-isel-abort=1 -o - 2>&1 | FileCheck %s
+; RUN: llc %s -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -global-isel-abort=1 -frame-pointer=non-leaf -o - 2>&1 | FileCheck %s
 
 ; Check that we get a tail call to foo without saving fp/lr.
 define void @bar(i32 %a) #1 {
 ; CHECK-LABEL: bar:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    b _zoo
 entry:
   tail call void @zoo(i32 undef)
   ret void
 }
 
 define void @zoo(i32 %a) {
+; CHECK-LABEL: zoo:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    ret
 entry:
   ret void
 }
 
 attributes #1 = { "frame-pointer"="all" }
 

llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll

 ; REQUIRES: asserts
 ; The regression tests need to test for order of emitted instructions, and
 ; therefore, the tests are a bit fragile/reliant on instruction scheduling. The
 ; test cases have been minimized as much as possible, but still most of the test
 ; cases could break if instruction scheduling heuristics for cortex-a53 change
-; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=1 -stats 2>&1 \
+; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=1 -frame-pointer=non-leaf -stats 2>&1 \
 ; RUN:  | FileCheck %s
-; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=0 -stats 2>&1 \
+; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=0 -frame-pointer=non-leaf -stats 2>&1 \
 ; RUN:  | FileCheck %s --check-prefix CHECK-NOWORKAROUND
 ; The following run lines are just to verify whether or not this pass runs by
 ; default for given CPUs. Given the fragility of the tests, this is only run on
 ; a test case where the scheduler has not freedom at all to reschedule the
 ; instructions, so the potentially massively different scheduling heuristics
 ; will not break the test case.
-; RUN: llc < %s -mcpu=generic    | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
-; RUN: llc < %s -mcpu=cortex-a53 | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
-; RUN: llc < %s -mcpu=cortex-a57 | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
-; RUN: llc < %s -mcpu=cyclone    | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
+; RUN: llc < %s -mcpu=generic    -frame-pointer=non-leaf | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
+; RUN: llc < %s -mcpu=cortex-a53 -frame-pointer=non-leaf | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
+; RUN: llc < %s -mcpu=cortex-a57 -frame-pointer=non-leaf | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
+; RUN: llc < %s -mcpu=cyclone    -frame-pointer=non-leaf | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 define i64 @f_load_madd_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 {
 entry:
   %0 = load i64, i64* %c, align 8
   %mul = mul nsw i64 %0, %b

llvm/test/CodeGen/AArch64/arm64-large-frame.ll

-; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -frame-pointer=all -disable-post-ra < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -frame-pointer=non-leaf -disable-post-ra < %s | FileCheck %s
 declare void @use_addr(i8*)
 
 @addr = global i8* null
 
 define void @test_bigframe() {
 ; CHECK-LABEL: test_bigframe:
 ; CHECK: .cfi_startproc
 

llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=arm64-apple-ios -enable-shrink-wrap=true -disable-post-ra -frame-pointer=all | FileCheck %s --check-prefix=ENABLE
-; RUN: llc %s -o - -enable-shrink-wrap=false -disable-post-ra -frame-pointer=all | FileCheck %s --check-prefix=DISABLE
+; RUN: llc %s -o - -mtriple=arm64-apple-ios -enable-shrink-wrap=true -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=ENABLE
+; RUN: llc %s -o - -enable-shrink-wrap=false -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=DISABLE
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "arm64-apple-ios"
 
 
 ; Initial motivating example: Simple diamond with a call just on one side.
 define i32 @foo(i32 %a, i32 %b) {
 ; ENABLE-LABEL: foo:
 ; ENABLE:       ; %bb.0:

llvm/test/CodeGen/AArch64/arm64_32.ll

-; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -filetype=obj -o - -disable-post-ra -frame-pointer=all | \
+; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -filetype=obj -o - -disable-post-ra -frame-pointer=non-leaf | \
 ; RUN:     llvm-objdump -private-headers - | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-MACHO
-; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -o - -aarch64-enable-atomic-cfg-tidy=0 -disable-post-ra -frame-pointer=all | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OPT
-; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -o - -fast-isel -aarch64-enable-atomic-cfg-tidy=0 -disable-post-ra -frame-pointer=all | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FAST
+; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -o - -aarch64-enable-atomic-cfg-tidy=0 -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OPT
+; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -o - -fast-isel -aarch64-enable-atomic-cfg-tidy=0 -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FAST
 
 ; CHECK-MACHO: Mach header
 ; CHECK-MACHO: MH_MAGIC ARM64_32 V8
 
 @var64 = global i64 zeroinitializer, align 8
 @var32 = global i32 zeroinitializer, align 4
 
 @var_got = external global i8

llvm/test/CodeGen/AArch64/f16-instructions.ll

-; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -frame-pointer=all | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -frame-pointer=all | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-FP16
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-FP16
 
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple \
-; RUN: -asm-verbose=false -disable-post-ra -frame-pointer=all -global-isel \
+; RUN: -asm-verbose=false -disable-post-ra -frame-pointer=non-leaf -global-isel \
 ; RUN: -global-isel-abort=2 -pass-remarks-missed=gisel-* 2>&1 | FileCheck %s \
 ; RUN: --check-prefixes=FALLBACK,GISEL-CVT,GISEL
 
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 \
 ; RUN: -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra \
-; RUN: -frame-pointer=all -global-isel -global-isel-abort=2 \
+; RUN: -frame-pointer=non-leaf -global-isel -global-isel-abort=2 \
 ; RUN: -pass-remarks-missed=gisel-* 2>&1 | FileCheck %s \
 ; RUN: --check-prefixes=FALLBACK-FP16,GISEL-FP16,GISEL
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
 ; CHECK-CVT-LABEL: test_fadd:
 ; CHECK-CVT-NEXT: fcvt s1, h1
 ; CHECK-CVT-NEXT: fcvt s0, h0

llvm/test/CodeGen/AArch64/fastcc.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -frame-pointer=all -tailcallopt | FileCheck %s -check-prefix CHECK-TAIL
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -frame-pointer=all | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -frame-pointer=all -tailcallopt -aarch64-redzone | FileCheck %s -check-prefix CHECK-TAIL-RZ
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -frame-pointer=non-leaf -tailcallopt | FileCheck %s -check-prefix CHECK-TAIL
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -frame-pointer=non-leaf | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -frame-pointer=non-leaf -tailcallopt -aarch64-redzone | FileCheck %s -check-prefix CHECK-TAIL-RZ
 
 ; Without tailcallopt fastcc still means the caller cleans up the
 ; stack, so try to make sure this is respected.
 
 define fastcc void @func_stack0() {
 ; CHECK-LABEL: func_stack0:
 ; CHECK: sub sp, sp, #48
 ; CHECK: add x29, sp, #32

llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir

 # CHECK: early-clobber $sp = STRXpre $lr, $sp, -16
 # CHECK-NEXT: BL
 # CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16
 name:            bar
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28
+    $lr = ORRXri $xzr, 1
     $w10 = ORRWri $wzr, 1
     $w10 = ORRWri $wzr, 1
     $w10 = ORRWri $wzr, 1
     $w10 = ORRWri $wzr, 1
     $w10 = ORRWri $wzr, 1
     $w12 = ORRWri $wzr, 2
   bb.1:
     liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28

llvm/test/CodeGen/AArch64/machine-outliner.mir

-# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs -frame-pointer=non-leaf %s -o - | FileCheck %s
 --- |
 
   @x = common global i32 0, align 4
 
   define void @baz() #0 {
     ret void
   }
 

llvm/test/DebugInfo/AArch64/line-header.ll

 ; RUN: llc -mtriple=aarch64-none-linux -O0 -fast-isel -filetype=obj - < %S/../Inputs/line.ll | llvm-dwarfdump -v - | FileCheck %s
 ; RUN: llc -mtriple=aarch64_be-none-linux -O0 -fast-isel -filetype=obj - < %S/../Inputs/line.ll | llvm-dwarfdump -v - | FileCheck %s
 
 ; check line table length is correctly calculated for both big and little endian
 CHECK-LABEL: .debug_line contents:
-CHECK: total_length: 0x0000003f
+CHECK: total_length: 0x00000040