Added pattern matching/intrinsics for the following SVE instructions:
- saddv, uaddv
- smaxv, sminv, umaxv, uminv
- orv, eorv, andv
For some instructions (smaxv, sminv, umaxv, uminv, org, eorg, andv) the pattern wasn't implemented for i8 and i16 types.
Since i8 and i16 aren't natural types for the FPR8 and FPR16 register classes, they will need custom lowering and some other modifications in order to function properly. These changes are going to be submitted in a latter patch pending some discussion on what is the best way of implementing it.