[WIP] [AArch64] Pattern-match byte store from a vector register.

[efriedma]

Summary

This is extremely ugly; the right solution is to implement EXTRACT_SUBREG_TO_REGCLASS, and use it here. Just posting this as a proof of concept, in case anyone else was wondering what the issue was in D46655.

[evandro]

Apropos, why is FPR8 defined as untyped and not i8 below?

def FPR8  : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)>

[efriedma]

i8 isn't considered a legal type by the AArch64ISelLowering, so it will never show up in the input to the instruction selector. Given that, I'm not sure it's really meaningful to say i8 maps to any specific register class.

But I guess it wouldn't do any harm to list i8 as part of FPR8? At least, I can't think of any other effects.

[evandro]

In D46851#1098587, @efriedma wrote:

i8 isn't considered a legal type by the AArch64ISelLowering, so it will never show up in the input to the instruction selector. Given that, I'm not sure it's really meaningful to say i8 maps to any specific register class.

But I guess it wouldn't do any harm to list i8 as part of FPR8? At least, I can't think of any other effects.

I'll give it a shot, hoping that I won't go down a rabbit hole...

lib/Target/AArch64/AArch64ISelLowering.h

bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
                                   SelectionDAG &DAG) const override;
 
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
                           SelectionDAG &DAG) const override;
 
   bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
 
   void finalizeLowering(MachineFunction &MF) const override;
+
+  void AdjustInstrPostInstrSelection(MachineInstr &MI,
+                                     SDNode *Node) const override;
 };
 
 namespace AArch64 {
 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                          const TargetLibraryInfo *libInfo);
 } // end namespace AArch64
 
 } // end namespace llvm
 
 #endif

lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::getVaListSizeInBits(const DataLayout &DL) const {
 
   return 3 * getPointerTy(DL).getSizeInBits() + 2 * 32;
 }
 
 void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
   MF.getFrameInfo().computeMaxCallFrameSize(MF);
   TargetLoweringBase::finalizeLowering(MF);
 }
+
+void
+AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
+                                                     SDNode *Node) const {
+  assert(MI.getOpcode() == AArch64::EXTRACT_SUBREG_BYTE);
+  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
+  const MCInstrDesc &MCID = TII->get(TargetOpcode::COPY);
+  MI.setDesc(MCID);
+  MI.getOperand(1).setSubReg(AArch64::bsub);
+}

lib/Target/AArch64/AArch64InstrInfo.td

multiclass VecStoreLane0Pat<Operand UIAddrMode, SDPatternOperator storeop,
                             SubRegIndex SubRegIdx, Operand IndexType,
                             Instruction STR> {
   def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)),
                      (UIAddrMode GPR64sp:$Rn, IndexType:$offset)),
             (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
                  GPR64sp:$Rn, IndexType:$offset)>;
 }
 
+// Lowering byte stores is a bit unusual: we can't use EXTRACT_SUBREG because
+// it can't figure out the right register class.
+// FIXME: Instead of a target-specific node, make a target-independent
+// EXTRACT_SUBREG_TO_REGCLASS.
+let hasNoSchedulingInfo = 1, hasPostISelHook = 1 in
+def EXTRACT_SUBREG_BYTE : Pseudo<(outs FPR8:$Rd), (ins VecListOne128:$Rn), []>;
+let AddedComplexity = 19 in {
+  def : Pat<(truncstorei8 (i32 (vector_extract (v16i8 VecListOne128:$Vt), 0)),
+                          (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
+            (STRBui (EXTRACT_SUBREG_BYTE VecListOne128:$Vt),
+                    GPR64sp:$Rn, uimm12s1:$offset)>;
+}
+
 let AddedComplexity = 19 in {
   defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>;
   defm : VecStoreLane0Pat<am_indexed16,         store, v8f16, f16, hsub, uimm12s2, STRHui>;
   defm : VecStoreLane0Pat<am_indexed32,         store, v4i32, i32, ssub, uimm12s4, STRSui>;
   defm : VecStoreLane0Pat<am_indexed32,         store, v4f32, f32, ssub, uimm12s4, STRSui>;
   defm : VecStoreLane0Pat<am_indexed64,         store, v2i64, i64, dsub, uimm12s8, STRDui>;
   defm : VecStoreLane0Pat<am_indexed64,         store, v2f64, f64, dsub, uimm12s8, STRDui>;
 }

test/CodeGen/AArch64/arm64-collect-loh.ll

 }
 
 ; CHECK-LABEL: _setL
 ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
 ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _L@GOTPAGE
 ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
 ; CHECK-NEXT: ldr [[LDRGOT_REG:x[0-9]+]], {{\[}}[[ADRP_REG]], _L@GOTPAGEOFF]
 ; CHECK-NEXT: ; kill
-; Ultimately we should generate str b0, but right now, we match the vector
-; variant which does not allow to fold the immediate into the store.
-; CHECK-NEXT: st1.b { v0 }[0], {{\[}}[[LDRGOT_REG]]]
+; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
+; CHECK-NEXT: str b0, {{\[}}[[LDRGOT_REG]]]
 ; CHECK-NEXT: ret
-; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]]
+; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
 define void @setL(<1 x i8> %t) {
   store <1 x i8> %t, <1 x i8>* @L, align 4
   ret void
 }
 
 ; Make sure we do not assert when we do not track
 ; all the aliases of a tuple register.
 ; Indeed the tuple register can be tracked because of

test/CodeGen/AArch64/arm64-st1.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
 ; The instruction latencies of Exynos-M1 trigger the transform we see under the Exynos check.
 
 define void @st1lane_16b(<16 x i8> %A, i8* %D) {
 ; CHECK-LABEL: st1lane_16b
 ; CHECK: st1.b
   %tmp = extractelement <16 x i8> %A, i32 1
   store i8 %tmp, i8* %D
   ret void
 }
 
 define void @st1lane0_16b(<16 x i8> %A, i8* %D) {
 ; CHECK-LABEL: st1lane0_16b
-; CHECK: st1.b
+; CHECK: str
   %tmp = extractelement <16 x i8> %A, i32 0
   store i8 %tmp, i8* %D
   ret void
 }
 
 define void @st1lane0u_16b(<16 x i8> %A, i8* %D) {
 ; CHECK-LABEL: st1lane0u_16b
 ; CHECK: st1.b
; CHECK: st1.b { v0 }[1], [x[[XREG]]]
   %tmp = extractelement <16 x i8> %A, i32 1
   store i8 %tmp, i8* %ptr
   ret void
 }
 
 define void @st1lane0_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_16b
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.b { v0 }[0], [x[[XREG]]]
+; CHECK: str b0, [x[[XREG]]]
   %ptr = getelementptr i8, i8* %D, i64 %offset
   %tmp = extractelement <16 x i8> %A, i32 0
   store i8 %tmp, i8* %ptr
   ret void
 }
 
 define void @st1lane_8h(<8 x i16> %A, i16* %D) {
 ; CHECK-LABEL: st1lane_8h
; CHECK: st1.b { v0 }[1], [x[[XREG]]]
   %tmp = extractelement <8 x i8> %A, i32 1
   store i8 %tmp, i8* %ptr
   ret void
 }
 
 define void @st1lane0_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_8b
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.b { v0 }[0], [x[[XREG]]]
+; CHECK: str b0, [x[[XREG]]]
   %ptr = getelementptr i8, i8* %D, i64 %offset
   %tmp = extractelement <8 x i8> %A, i32 0
   store i8 %tmp, i8* %ptr
   ret void
 }
 
 define void @st1lane_4h(<4 x i16> %A, i16* %D) {
 ; CHECK-LABEL: st1lane_4h