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amehsan (Ehsan Amiri)
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Feb 26 2016, 6:34 AM (168 w, 6 d)

Recent Activity

Jan 14 2019

amehsan closed D55264: [Jump Threading] Unfold a select instruction that feeds a switch statement via a phi node.

Committed in rL350931

Jan 14 2019, 11:06 AM

Jan 11 2019

amehsan committed rL350931: [Jump Threading] Unfold a select insn that feeds a switch via a phi node.
[Jump Threading] Unfold a select insn that feeds a switch via a phi node
Jan 11 2019, 7:56 AM

Jan 8 2019

amehsan added a comment to D55264: [Jump Threading] Unfold a select instruction that feeds a switch statement via a phi node.

@amehsan gentle ping. Have you resolved your push access?

Jan 8 2019, 12:37 PM

Dec 14 2018

amehsan committed rL349158: NFC. Adding an empty line to test the updated commit credentials..
NFC. Adding an empty line to test the updated commit credentials.
Dec 14 2018, 8:22 AM

Dec 10 2018

amehsan added a comment to D55264: [Jump Threading] Unfold a select instruction that feeds a switch statement via a phi node.

Thanks @brzycki for careful review. I need to revive my commit access (not used it for two years now), then I will commit this.

Dec 10 2018, 10:51 AM

Dec 7 2018

amehsan updated the diff for D55264: [Jump Threading] Unfold a select instruction that feeds a switch statement via a phi node.
Dec 7 2018, 2:17 PM
amehsan added a comment to D55264: [Jump Threading] Unfold a select instruction that feeds a switch statement via a phi node.

Thanks @brzycki. I believe I have addressed all your comments. Will upload the modified patch shortly.

Dec 7 2018, 10:35 AM

Dec 4 2018

amehsan created D55264: [Jump Threading] Unfold a select instruction that feeds a switch statement via a phi node.
Dec 4 2018, 4:58 AM

Sep 27 2017

amehsan added inline comments to D9401: llvm.noalias - The AA implementaton.
Sep 27 2017, 8:17 AM

Aug 16 2017

amehsan created D36808: [llvm.noalias] add llvm.noalias to pointer use visitor..
Aug 16 2017, 2:00 PM

Jun 12 2017

amehsan added a comment to D32888: TableGen: Add support of Intrinsics with multiple returns.

Hi Hal, can you commit it since I have no commit access?

Jun 12 2017, 12:21 PM

Dec 19 2016

amehsan accepted D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

@echristo explicitly approved this in his last comment, but I think he forgot to change the action box. So I accept just for easier book-keeping. (Eric is in vacation, AFAIK)

Dec 19 2016, 11:54 AM
amehsan closed D26544: [PPC] support for arithmetic builtins in the FE.

https://reviews.llvm.org/rL287872

Dec 19 2016, 11:06 AM
amehsan closed D24525: [Power9] Processor Model for Scheduling.

https://reviews.llvm.org/rL290102

Dec 19 2016, 9:10 AM
amehsan committed rL290102: [Power9] Processor Model for Scheduling.
[Power9] Processor Model for Scheduling
Dec 19 2016, 5:46 AM

Dec 15 2016

amehsan committed rL289900: [PPC] corrections in two testcases.
[PPC] corrections in two testcases
Dec 15 2016, 4:43 PM
amehsan committed rL289869: [PPC] Use CHECK-DAG instead of CHECK in the testcase.
[PPC] Use CHECK-DAG instead of CHECK in the testcase
Dec 15 2016, 1:01 PM
amehsan abandoned D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.

This patch, as is, is incorrect and requires some changes to proceed. Abandoning.

Dec 15 2016, 12:36 PM
amehsan closed D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

rL289813

Dec 15 2016, 12:35 PM
amehsan committed rL289813: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.
[InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp
Dec 15 2016, 4:35 AM

Dec 7 2016

amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

Ping

Dec 7 2016, 12:33 PM

Dec 1 2016

amehsan added a comment to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

You are right (I just tried it :-) If that is the only concern is it possible to approve this and I will remove that line from the switch stmt. (I think it does not hurt to leave the testcases though) and commit.

Yes, it's good to keep the tests to make sure the underlying assumption doesn't break.
LGTM - although I don't think we need a switch for just 2 cases. :)

Dec 1 2016, 11:52 AM
amehsan added a comment to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

Can you just assert that the predicate is not 'ugt' in isAnyBitSet() and simplify that a bit more? Ie, we don't need a switch if we know that eq/ne are the only predicate possibilities for this transform.

"assert" is probably too strong...I've made that mistake before. :)
But I think it's still safe to ignore the 'ugt' case and assume that InstCombine will churn that away sooner or later.

Dec 1 2016, 11:10 AM
amehsan updated the diff for D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.
Dec 1 2016, 5:22 AM

Nov 30 2016

amehsan updated the diff for D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

Added the clean up step that we discussed. Also, made some changes in the comments in the code.

Nov 30 2016, 9:33 AM

Nov 29 2016

amehsan added inline comments to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.
Nov 29 2016, 1:42 PM
amehsan added inline comments to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.
Nov 29 2016, 1:08 PM

Nov 28 2016

amehsan updated the diff for D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.
Nov 28 2016, 4:42 PM
amehsan added a comment to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

Will shortly update the patch.

Nov 28 2016, 3:53 PM

Nov 24 2016

amehsan added inline comments to D26713: [ppc] Legalize the load of MVT::v4i8 into VSX register.
Nov 24 2016, 5:08 AM
amehsan committed rL287872: [PPC] support for arithmetic builtins in the FE.
[PPC] support for arithmetic builtins in the FE
Nov 24 2016, 4:50 AM

Nov 23 2016

amehsan committed rL287796: [PPC] revert r287795.
[PPC] revert r287795
Nov 23 2016, 11:05 AM
amehsan committed rL287795: [PPC] support for arithmetic builtins in the FE.
[PPC] support for arithmetic builtins in the FE
Nov 23 2016, 10:46 AM
amehsan committed rL287775: [PPC] Reverting r287772.
[PPC] Reverting r287772
Nov 23 2016, 9:06 AM
amehsan committed rL287772: [PPC] support for arithmetic builtins in the FE.
[PPC] support for arithmetic builtins in the FE
Nov 23 2016, 8:42 AM

Nov 18 2016

amehsan added a comment to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

@spatel @eli.friedman Could one of you please look at this patch? @majnemer said he is busy and will be even busier next week.

Nov 18 2016, 2:44 PM
amehsan updated subscribers of D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

@spatel @eli.friedman Could one of you please look at this patch? @majnemer said he is busy and will be even busier next week.

Nov 18 2016, 1:58 PM
amehsan closed D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.

https://reviews.llvm.org/rL287329

Nov 18 2016, 8:37 AM
amehsan closed D26551: [Power9] Add patterns for vnegd, vnegw.

https://reviews.llvm.org/rL287334 (fixed the comment in a followup commit though).

Nov 18 2016, 8:36 AM
amehsan committed rL287350: [PPC] limit line width to 80 characters.
[PPC] limit line width to 80 characters
Nov 18 2016, 8:34 AM
amehsan committed rL287334: [Power9] Add patterns for vnegd, vnegw.
[Power9] Add patterns for vnegd, vnegw
Nov 18 2016, 3:15 AM
amehsan committed rL287329: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.
[PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended
Nov 18 2016, 2:51 AM

Nov 17 2016

amehsan added inline comments to D26564: Use PIC relocation mode by default for PowerPC64 ELF.
Nov 17 2016, 9:57 AM
amehsan updated the diff for D26544: [PPC] support for arithmetic builtins in the FE.
Nov 17 2016, 9:53 AM

Nov 16 2016

amehsan added a comment to D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

Could someone take a look at this?

Nov 16 2016, 11:37 AM
amehsan added inline comments to D26544: [PPC] support for arithmetic builtins in the FE.
Nov 16 2016, 6:59 AM

Nov 11 2016

amehsan updated the diff for D26551: [Power9] Add patterns for vnegd, vnegw.
Nov 11 2016, 9:07 AM
amehsan retitled D26551: [Power9] Add patterns for vnegd, vnegw from to [Power9] Add patterns for vnegd, vnegw.
Nov 11 2016, 9:05 AM
amehsan retitled D26544: [PPC] support for arithmetic builtins in the FE from to [PPC] support for arithmetic builtins in the FE.
Nov 11 2016, 5:48 AM

Nov 10 2016

amehsan added inline comments to D26412: [XRay] Support AArch64 in LLVM.
Nov 10 2016, 12:54 PM
amehsan added a comment to D26479: [PowerPC] Implement remaining permute builtins in altivec.h - Clang portion.

I actually wanted to check some surrounding guards.

Nov 10 2016, 7:31 AM
amehsan added a comment to D26479: [PowerPC] Implement remaining permute builtins in altivec.h - Clang portion.

more context?

Nov 10 2016, 7:30 AM

Nov 9 2016

amehsan added inline comments to D26066: [PowerPC] Improvements for BUILD_VECTOR Vol. 4.
Nov 9 2016, 7:22 AM

Nov 8 2016

amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

2- targetSchedulesPostRAScheduling

This seems redundant to me as soon as 1) is implemented.

Maybe I am missing something, but this seems different from (1). Note that addPostRASched is called from addMachinePasses which is not typically overriden by targets. SystemZ has a usecase for targetSchedulesPostRAScheduling which cannot be covered by (1).

Overriding addPostRASched() with an empty function has the same effect as returning true in targetSchedulesPostRAScheduling(), hasn't it?

Correct :)

So we can remove targetSchedulesPostRAScheduling() and replace it with the empty function overload after adding addPostRASched().

That's a reasonable change for this patch. I'll wait to see Eric's comments well, before updating the patch though. Just to save time.

Nov 8 2016, 7:03 AM

Nov 3 2016

amehsan requested review of D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

I put this back in review as Eric wanted to take a look.

Nov 3 2016, 8:41 AM
amehsan updated the diff for D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.

now fully tested with test-suite.

Nov 3 2016, 5:28 AM

Nov 2 2016

amehsan added a comment to D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.

Just finished lnt test and there are some failures. I will update when my investigation of the failures is done.

Nov 2 2016, 2:19 PM
amehsan updated the diff for D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.

Completed the unit test and code. I decided that extending this for signed comparison is not necessary good, because two zero extends that we generate for unsigned comparison, will be sign extension for signed comparison. That means the signed version will have two more instructions. There might be still more useful cases, but I think they are different enough and we don't need to make them part of this patch.

Nov 2 2016, 1:16 PM
amehsan updated the diff for D25200: [InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp.

Thanks David for the review. I have tested this with test-suite. I forgot to do so, after I made first set of changes.

Nov 2 2016, 10:35 AM

Nov 1 2016

amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

2- targetSchedulesPostRAScheduling

This seems redundant to me as soon as 1) is implemented.

Maybe I am missing something, but this seems different from (1). Note that addPostRASched is called from addMachinePasses which is not typically overriden by targets. SystemZ has a usecase for targetSchedulesPostRAScheduling which cannot be covered by (1).

Overriding addPostRASched() with an empty function has the same effect as returning true in targetSchedulesPostRAScheduling(), hasn't it?

Correct :)

So we can remove targetSchedulesPostRAScheduling() and replace it with the empty function overload after adding addPostRASched().

Nov 1 2016, 6:45 PM
amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

2- targetSchedulesPostRAScheduling

This seems redundant to me as soon as 1) is implemented.

Maybe I am missing something, but this seems different from (1). Note that addPostRASched is called from addMachinePasses which is not typically overriden by targets. SystemZ has a usecase for targetSchedulesPostRAScheduling which cannot be covered by (1).

Overriding addPostRASched() with an empty function has the same effect as returning true in targetSchedulesPostRAScheduling(), hasn't it?

Nov 1 2016, 6:29 PM
amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

I opened a PR for this and copied the last couple of comments there. CC'ed Eric and Matt on the PR.

Nov 1 2016, 6:24 PM
amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

2- targetSchedulesPostRAScheduling

This seems redundant to me as soon as 1) is implemented.

Nov 1 2016, 6:10 PM
amehsan updated the diff for D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

Eric, asked for a little more clean up.

Nov 1 2016, 11:18 AM
amehsan updated the diff for D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Nov 1 2016, 10:15 AM
amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Nov 1 2016, 9:24 AM
amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Nov 1 2016, 7:42 AM

Oct 31 2016

amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 31 2016, 4:03 PM
amehsan updated the diff for D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 31 2016, 4:00 PM
amehsan added a comment to D26066: [PowerPC] Improvements for BUILD_VECTOR Vol. 4.

Regarding (2): I think we need to make sure InstCombine and target Independent lowering are doing the right thing for these. Fixing as late as possible does not seem correct to me. But I leave to other reviewers to decide.

Oct 31 2016, 7:18 AM
amehsan added a comment to D26066: [PowerPC] Improvements for BUILD_VECTOR Vol. 4.
Oct 31 2016, 7:08 AM

Oct 30 2016

amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 30 2016, 7:56 PM
amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 30 2016, 7:09 PM

Oct 29 2016

amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 29 2016, 11:00 AM
amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 29 2016, 10:23 AM

Oct 28 2016

amehsan added a comment to D26066: [PowerPC] Improvements for BUILD_VECTOR Vol. 4.

Yeah, when I was implementing some of the P9 instructions that naturally fit the BUILD_VECTOR nodes, I realized that we produce poor code for some patterns. I wanted to see how bad this situation is so I wrote the C test case that is added as a comment to build-vector-tests.ll and examined the assembly. Then I picked off the patterns that produce poor code and fixed them one by one.

Oct 28 2016, 1:46 PM
amehsan added a comment to D26066: [PowerPC] Improvements for BUILD_VECTOR Vol. 4.

Here are some examples of terrible code gen currently (rather than providing code, I'm just illustrating these with pseudo-SDAG nodes):

Oct 28 2016, 11:20 AM
amehsan added inline comments to D26072: [PPC] add absolute difference altivec instructions and matching intrinsics .
Oct 28 2016, 9:26 AM
amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 28 2016, 8:48 AM
amehsan added inline comments to D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.
Oct 28 2016, 6:14 AM
amehsan added a comment to D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.

Thanks Nemanja for comments on the testcase.

Oct 28 2016, 6:04 AM

Oct 27 2016

amehsan added inline comments to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.
Oct 27 2016, 6:07 PM
amehsan added a comment to D25482: [PPC] Allow two post RA schedulers to be in the pipeline and select one depending on the Machine Function's subtarget.

@MatzeB
Do you have further comments on this?

Oct 27 2016, 3:19 PM
amehsan committed rL285333: [PPC] Adding the removed testcase again.
[PPC] Adding the removed testcase again
Oct 27 2016, 12:19 PM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 27 2016, 11:46 AM
amehsan added a comment to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.

There has been many comments here, but only a couple of minor issues has to be addressed. (check indentation, remove whitespace, change some variable names). If you don't mind to approve it, I will fix those before committing.

Oct 27 2016, 1:20 AM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 27 2016, 1:00 AM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 27 2016, 12:57 AM

Oct 26 2016

amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 26 2016, 6:27 PM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 26 2016, 6:22 PM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 26 2016, 6:20 PM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 26 2016, 5:46 PM
amehsan updated the diff for D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.

There is one comment not yet addressed. Size of latest legal integer is currently hardcoded. As I responded to that comment I will fix it. I want to look at this a bit more to see if it makes sense to add some extensions to it.

Oct 26 2016, 2:15 PM
amehsan committed rL285233: [PPC] Remove testcase from incorrect directory.
[PPC] Remove testcase from incorrect directory
Oct 26 2016, 1:26 PM
amehsan added a comment to D23614: [PPC] Generate positive FP zero using xor insn instead of loading from constant area.

Could you move the testcase into the right directory?

Oct 26 2016, 12:53 PM
amehsan added inline comments to D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.
Oct 26 2016, 12:14 PM
amehsan closed D23614: [PPC] Generate positive FP zero using xor insn instead of loading from constant area.

Committed rL284995

Oct 26 2016, 9:24 AM
amehsan closed D24924: [PPC] Better codegen for AND, ANY_EXT, SRL sequence.

Commited 284983

Oct 26 2016, 9:20 AM
amehsan added a comment to D25221: [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extended.
Oct 26 2016, 8:52 AM
amehsan added inline comments to D25991: [PPC] Peephole to remove extra fcmp that checks for NaN.
Oct 26 2016, 8:12 AM