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dancgr (Danilo Carvalho Grael)
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Oct 17 2019, 7:31 AM (13 w, 4 d)

Recent Activity

Thu, Jan 16

dancgr updated the diff for D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.

Tentative changes to address some comments from the reviewers.

Thu, Jan 16, 11:49 AM · Restricted Project
dancgr added a comment to D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.

I'm not sure on some parts, but I have prepared a major update for this patch that I hope will fix most of @sdesmalen concerns.

Thu, Jan 16, 11:39 AM · Restricted Project

Wed, Jan 15

dancgr added a comment to D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.

Can we also also add mul patterns for targets that have SVE, but not SVE2?

That instruction is restricted to SVE2. Do we have unpredicated vector mul instructions for SVE targets as well?

We can synthesize a predicate using ptrue. We do this in a few places currently; for example, to implement bswap.

Wed, Jan 15, 2:06 PM · Restricted Project
dancgr committed rG34ba96a3d49e: [NFC][IndVarSimplify] remove duplicate code in widenWithVariantLoadUseCodegen. (authored by zhongduo).
[NFC][IndVarSimplify] remove duplicate code in widenWithVariantLoadUseCodegen.
Wed, Jan 15, 1:29 PM
dancgr closed D72652: [NFC][IndVarSimplify] remove duplicate code in widenWithVariantLoadUseCodegen.
Wed, Jan 15, 1:29 PM · Restricted Project
dancgr added a comment to D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.

Can we also also add mul patterns for targets that have SVE, but not SVE2?

Wed, Jan 15, 12:32 PM · Restricted Project
dancgr updated the summary of D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.
Wed, Jan 15, 12:15 PM · Restricted Project
dancgr created D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.
Wed, Jan 15, 12:14 PM · Restricted Project

Tue, Jan 14

dancgr committed rG26d96126a0d2: [SVE] Add patterns for MUL immediate instruction. (authored by dancgr).
[SVE] Add patterns for MUL immediate instruction.
Tue, Jan 14, 12:32 PM
dancgr closed D72654: [SVE] Add patterns for MUL immediate instruction..
Tue, Jan 14, 12:30 PM · Restricted Project
dancgr added inline comments to D72654: [SVE] Add patterns for MUL immediate instruction..
Tue, Jan 14, 12:02 PM · Restricted Project
dancgr updated the diff for D72654: [SVE] Add patterns for MUL immediate instruction..

Fix whitespace errors and add a couple negative tests for invalid input.

Tue, Jan 14, 11:12 AM · Restricted Project
dancgr added a comment to D72654: [SVE] Add patterns for MUL immediate instruction..

Do we have any negative tests, for immediates that are outside the range of the sve mul immediate instruction?

Tue, Jan 14, 10:44 AM · Restricted Project

Mon, Jan 13

dancgr created D72654: [SVE] Add patterns for MUL immediate instruction..
Mon, Jan 13, 2:48 PM · Restricted Project
dancgr committed rG2d7e757a836a: [AArch64][SVE] Add patterns for some arith SVE instructions. (authored by dancgr).
[AArch64][SVE] Add patterns for some arith SVE instructions.
Mon, Jan 13, 8:41 AM
dancgr closed D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.
Mon, Jan 13, 8:41 AM · Restricted Project

Thu, Jan 9

dancgr updated subscribers of D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

@efriedma Any other remarks on this patch?

Thu, Jan 9, 1:04 PM · Restricted Project

Tue, Jan 7

dancgr updated the diff for D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

Updated some minor changes.

Tue, Jan 7, 8:39 AM · Restricted Project

Mon, Jan 6

dancgr added inline comments to D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.
Mon, Jan 6, 6:51 AM · Restricted Project

Fri, Dec 27

dancgr committed rG2abda66848e5: [NFC][DA] Remove duplicate code in checkSrcSubscript and checkDstSubscript (authored by dancgr).
[NFC][DA] Remove duplicate code in checkSrcSubscript and checkDstSubscript
Fri, Dec 27, 7:08 AM
dancgr closed D71087: [NFC][DA] Remove duplicate code in checkSrcSubscript and checkDstSubscript.
Fri, Dec 27, 7:08 AM · Restricted Project

Mon, Dec 23

dancgr updated the diff for D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

Update to use default ISD:SMAX variety.

Mon, Dec 23, 12:23 PM · Restricted Project
dancgr added a comment to D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

Wong SMAX; you're referring to VECREDUCE_SMAX, which isn't relevant here. There is no IR intrinsic for ISD::SMAX; it's pattern-matched from select instructions.

Mon, Dec 23, 12:23 PM · Restricted Project
dancgr added a comment to D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

As far as I know the ISD::SMAX only takes one input (https://llvm.org/docs/LangRef.html#llvm-experimental-vector-reduce-smax-intrinsic), in this case we need two inputs so we can do the max between the input vector and the immediate value.

Mon, Dec 23, 7:07 AM · Restricted Project

Dec 20 2019

dancgr created D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.
Dec 20 2019, 11:11 AM · Restricted Project
dancgr retitled D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions from [AArch64][SVE] Add patterns for some int arith instructions to [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.
Dec 20 2019, 11:11 AM · Restricted Project
dancgr committed rG15bfd2cd5438: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant (authored by dancgr).
[AArch64][SVE] Replace integer immediate intrinsics with splat vector variant
Dec 20 2019, 10:51 AM
dancgr closed D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.
Dec 20 2019, 10:51 AM · Restricted Project
dancgr added inline comments to D70450: [AArch64] Teach Load/Store optimizier to rename store operands for pairing..
Dec 20 2019, 10:29 AM · Restricted Project

Dec 18 2019

dancgr requested review of D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.

For llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll it is still not performing the dag combine, however the resulting assembly is different because this matches with the new AArch64dup pattern for logical vector and immediate AND.

Dec 18 2019, 11:45 AM · Restricted Project
dancgr updated the diff for D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.

Fix issues with sve gather scatter test.

Dec 18 2019, 11:45 AM · Restricted Project
dancgr reopened D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.
Dec 18 2019, 11:45 AM · Restricted Project
dancgr committed rGc7abf8841187: Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat vector… (authored by dancgr).
Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat vector…
Dec 18 2019, 11:16 AM
dancgr added a reverting change for rG830e08b98bcb: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant: rGc7abf8841187: Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat vector….
Dec 18 2019, 11:16 AM
dancgr added a reverting change for rGeb1857ce0da4: [AArch64][SVE] Fix gather scatter dag combine test.: rGc7abf8841187: Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat vector….
Dec 18 2019, 11:16 AM
dancgr added a comment to D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.

All changes reverted by commit c7abf8841187c6e2c4169c06226429cdd5650e7f.

Dec 18 2019, 11:16 AM · Restricted Project
dancgr added a comment to D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.

This https://reviews.llvm.org/rGeb1857ce0da481caf82271e6d0c9fc745dfab26f fixes this error for now.

Dec 18 2019, 10:45 AM · Restricted Project
dancgr committed rGeb1857ce0da4: [AArch64][SVE] Fix gather scatter dag combine test. (authored by dancgr).
[AArch64][SVE] Fix gather scatter dag combine test.
Dec 18 2019, 10:38 AM
dancgr committed rG830e08b98bcb: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant (authored by dancgr).
[AArch64][SVE] Replace integer immediate intrinsics with splat vector variant
Dec 18 2019, 10:19 AM
dancgr closed D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.
Dec 18 2019, 10:19 AM · Restricted Project

Dec 17 2019

dancgr updated the diff for D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.

Remove unused intrinsic.

Dec 17 2019, 1:56 PM · Restricted Project
dancgr added inline comments to D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.
Dec 17 2019, 1:56 PM · Restricted Project
dancgr updated the diff for D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.

Moving SUBR from intrinsics to a reverse pattern match with sub IR instruction.

Dec 17 2019, 1:46 PM · Restricted Project
dancgr added inline comments to D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.
Dec 17 2019, 1:25 PM · Restricted Project
dancgr created D71614: [AArch64][SVE] Replace integer immediate intrinsics with splat vector variant.
Dec 17 2019, 9:04 AM · Restricted Project
dancgr added a comment to D71571: [NFC] [AArch64] Adding LLVM_FALLTHROUGH to ISelDAGToDAG..

There are no changes needed after https://reviews.llvm.org/rG002adabb3a251a81ef304353eefb1bf96ec388f6.

Dec 17 2019, 7:49 AM · Restricted Project

Dec 16 2019

dancgr committed rGf933878991a9: [AArch64][SVE] Add patterns for logical immediate operations. (authored by dancgr).
[AArch64][SVE] Add patterns for logical immediate operations.
Dec 16 2019, 1:22 PM
dancgr closed D71483: [AArch64][SVE] Add patterns for logical immediate operations..
Dec 16 2019, 1:21 PM · Restricted Project
dancgr added a comment to D71483: [AArch64][SVE] Add patterns for logical immediate operations..

I will be merging this patch then, and I will submit a short patch for the AArch64dup (SVELogicalImm32 i64:$imm) patterns and the equivalent ones for the add/sub instructions.

Dec 16 2019, 7:20 AM · Restricted Project

Dec 13 2019

dancgr updated the diff for D71483: [AArch64][SVE] Add patterns for logical immediate operations..

Add specific intrinsic for i64.

Dec 13 2019, 12:42 PM · Restricted Project
dancgr added inline comments to D71483: [AArch64][SVE] Add patterns for logical immediate operations..
Dec 13 2019, 12:14 PM · Restricted Project
dancgr added inline comments to D71483: [AArch64][SVE] Add patterns for logical immediate operations..
Dec 13 2019, 12:05 PM · Restricted Project
dancgr added inline comments to D71483: [AArch64][SVE] Add patterns for logical immediate operations..
Dec 13 2019, 11:19 AM · Restricted Project
dancgr created D71483: [AArch64][SVE] Add patterns for logical immediate operations..
Dec 13 2019, 11:01 AM · Restricted Project

Dec 12 2019

dancgr committed rG6bed43f3c40b: [AArch64][SVE] Add integer arithmetic with immediate instructions. (authored by dancgr).
[AArch64][SVE] Add integer arithmetic with immediate instructions.
Dec 12 2019, 3:57 PM
dancgr closed D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
Dec 12 2019, 3:56 PM · Restricted Project
dancgr abandoned D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..
Dec 12 2019, 2:27 PM · Restricted Project
dancgr closed D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

b29916cec3f45e5fb5efff5104acf142f348c724

Dec 12 2019, 12:52 PM · Restricted Project
dancgr updated the diff for D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..

Update minor details.

Dec 12 2019, 12:45 PM · Restricted Project
dancgr added inline comments to D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
Dec 12 2019, 11:23 AM · Restricted Project
dancgr updated the diff for D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..

Add extra check to DAGToDAGISel to avoid invalid immediates.

Dec 12 2019, 11:22 AM · Restricted Project
dancgr added inline comments to D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
Dec 12 2019, 7:45 AM · Restricted Project
dancgr updated the diff for D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..

Fix some formatting and apply suggested changes.

Dec 12 2019, 7:45 AM · Restricted Project

Dec 11 2019

dancgr updated the diff for D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
  • [AArch64][SVE] Update intrinsic to include Immediate option and remove sign handling for i16 immediate for add/sub.
Dec 11 2019, 2:29 PM · Restricted Project
dancgr updated the diff for D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
  • [AArch64][SVE] Update intrinsic to include Immediate option and remove sign handling for i16 immediate for add/sub.
Dec 11 2019, 2:29 PM · Restricted Project
dancgr added inline comments to D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
Dec 11 2019, 2:29 PM · Restricted Project
dancgr created D71370: [AArch64][SVE] Add integer arithmetic with immediate instructions..
Dec 11 2019, 11:19 AM · Restricted Project

Dec 4 2019

dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Dec 4 2019, 11:47 AM · Restricted Project
dancgr updated the diff for D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.
  • [AArch64][SVE] Rename intrinsics to re-use logical SVE intrinsics.
  • [AArch64][SVE] Change bic instrincis to comply with other predicated instructions
  • [AArch64][SVE] Remove trailing backslash from test
Dec 4 2019, 11:08 AM · Restricted Project

Dec 2 2019

dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Dec 2 2019, 12:43 PM · Restricted Project
dancgr added inline comments to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Dec 2 2019, 12:25 PM · Restricted Project

Nov 29 2019

dancgr updated the diff for D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.
  • [AArch64][SVE] Remove trailing backslash from test
Nov 29 2019, 12:00 PM · Restricted Project
dancgr updated the diff for D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.
  • [AArch64][SVE] Change bic instrincis to comply with other predicated instructions
Nov 29 2019, 11:49 AM · Restricted Project
dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

Added final touches.

Nov 29 2019, 10:38 AM · Restricted Project
dancgr added a comment to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

Done all changes suggested by @sdesmalen. I removed the unnecessary changes to AArch64 patterns, did all of the small details and added nxv2i64 sddv mapping to uaddv.

Nov 29 2019, 10:28 AM · Restricted Project
dancgr added a comment to D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.

Added intrinsics re-name before committing as suggested by @sdesmalen.

Nov 29 2019, 7:48 AM · Restricted Project
dancgr updated the diff for D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.
  • [AArch64][SVE] Rename intrinsics to re-use logical SVE intrinsics.
Nov 29 2019, 7:48 AM · Restricted Project

Nov 28 2019

dancgr added inline comments to D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.
Nov 28 2019, 8:53 AM · Restricted Project
dancgr added a comment to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

Do any of the reviewers have other suggestions for this patch?

Nov 28 2019, 8:53 AM · Restricted Project

Nov 27 2019

dancgr created D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions.
Nov 27 2019, 12:47 PM · Restricted Project

Nov 26 2019

dancgr updated the diff for D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..
  • [Transform][InstCombine] Add new test case for the specified scenario.
Nov 26 2019, 12:04 PM · Restricted Project
dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

I think I have addressed all of the comments from the reviewers on this patch. This way we don't have any new legal type and I embedded the insert_subreg in the helper pattern.

Nov 26 2019, 11:26 AM · Restricted Project
dancgr added inline comments to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Nov 26 2019, 10:40 AM · Restricted Project
dancgr updated subscribers of D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..
Nov 26 2019, 7:30 AM · Restricted Project

Nov 25 2019

dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

Add context.

Nov 25 2019, 3:24 PM · Restricted Project
dancgr added inline comments to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Nov 25 2019, 3:24 PM · Restricted Project
dancgr added a comment to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

Also the change on unrelated patterns it to avoid ambiguities in the FPR8 and FPR16 patterns.

Nov 25 2019, 2:19 PM · Restricted Project
dancgr added a comment to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

I have added the FPR8 and FPR16 outputs for the SVE Integer reductions.

Nov 25 2019, 2:11 PM · Restricted Project
dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
  • [AArch64][SVE] Add FPR8 and FPR16 types for SVE integer reduction.
Nov 25 2019, 2:10 PM · Restricted Project

Nov 20 2019

dancgr added a comment to D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..

-1 to adding more artificial one-use restrictions.
I agree there is a general problem of unability to see if
there exists a particular instruction already.

Nov 20 2019, 12:05 PM · Restricted Project

Nov 19 2019

dancgr created D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..
Nov 19 2019, 2:06 PM · Restricted Project
dancgr changed the visibility for D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..
Nov 19 2019, 2:06 PM · Restricted Project
dancgr edited reviewers for D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register., added: majnemer, spatel; removed: amehsan.
Nov 19 2019, 2:06 PM · Restricted Project
dancgr updated the summary of D70462: [InstCombine] Change InstCombineAddSub to not perform constant folding when there is an intermediate use of the source register..
Nov 19 2019, 2:06 PM · Restricted Project

Nov 11 2019

dancgr added a comment to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

@sdesmalen, would you have any objections if I implemented it as @efriedma suggested?

Nov 11 2019, 7:45 AM · Restricted Project

Nov 8 2019

dancgr updated the diff for D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..

Removed unused Intrinsic as requested.

Nov 8 2019, 6:53 AM · Restricted Project
dancgr added inline comments to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Nov 8 2019, 6:53 AM · Restricted Project

Nov 7 2019

dancgr created D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Nov 7 2019, 11:07 AM · Restricted Project

Nov 1 2019

dancgr added a reviewer for D69707: [AArch64][SVE] Implement additional floating-point arithmetic intrinsics: mgudim.
Nov 1 2019, 12:32 PM · Restricted Project

Oct 29 2019

dancgr added a reviewer for D69588: [AArch64][SVE] Add remaining patterns and intrinsics for add/sub/mad patterns: rengolin.
Oct 29 2019, 3:22 PM · Restricted Project