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- Oct 17 2019, 7:31 AM (66 w, 1 d)
Wed, Jan 20
Are there any opinions on this bugfix?
Tue, Jan 19
Dec 17 2020
Sep 30 2020
Sep 22 2020
Sep 15 2020
Sep 4 2020
Sep 2 2020
Aug 26 2020
Jul 13 2020
Jul 2 2020
Jun 9 2020
Jun 3 2020
May 29 2020
@efriedma Thanks Eli, I will close it, as that other patch already fixed that issue.
May 28 2020
Hello David, I have this patch here that I was going to upstream (https://reviews.llvm.org/D80746), but I just realized that it is exactly the same as this one.
Mar 5 2020
Feb 27 2020
Feb 26 2020
Feb 21 2020
Latest commit adds a change to the failing MC tests to be exactly the same as the MC tests for eor3 and bcax.
Will look into that and update this review with the necessary changes.
Feb 20 2020
Feb 19 2020
Merging all instructions into same multiclass.
Feb 18 2020
Feb 12 2020
Feb 10 2020
Jan 31 2020
Add missing i16 tests.
Jan 30 2020
Jan 29 2020
@sdesmalen Hopefully all comments from D73576 were addressed with this patch.
I will make the changes suggested by Sander in a following patch, joined with the saturating multiply-add long intirnsics.
Jan 28 2020
Jan 23 2020
Jan 22 2020
Remove _m from intrinsics, as it is the default behaviour. Also, add unpredicated patterns for SVE2 smulh, umulh.
Jan 20 2020
I'm not sure on some parts, but I have prepared a major update for this patch that I hope will fix most of @sdesmalen concerns.
Jan 16 2020
Tentative changes to address some comments from the reviewers.
I'm not sure on some parts, but I have prepared a major update for this patch that I hope will fix most of @sdesmalen concerns.
Jan 15 2020
Jan 14 2020
Fix whitespace errors and add a couple negative tests for invalid input.
Jan 13 2020
Jan 9 2020
@efriedma Any other remarks on this patch?
Jan 7 2020
Updated some minor changes.
Jan 6 2020
Dec 27 2019
Dec 23 2019
Update to use default ISD:SMAX variety.
As far as I know the ISD::SMAX only takes one input (https://llvm.org/docs/LangRef.html#llvm-experimental-vector-reduce-smax-intrinsic), in this case we need two inputs so we can do the max between the input vector and the immediate value.
Dec 20 2019
Dec 18 2019
For llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll it is still not performing the dag combine, however the resulting assembly is different because this matches with the new AArch64dup pattern for logical vector and immediate AND.
Fix issues with sve gather scatter test.