In D75197#1894971, @c-rhodes wrote:

Thanks for the patch @dancgr but these intrinsics have already been implemented in D74912. @sdesmalen shared a spreadsheet [1] with the mailing list to coordinate the intrinsics upstreaming, it's probably not as useful now given they're almost all implemented but you might find it useful if you haven't seen it already.

[1] https://docs.google.com/spreadsheets/d/1leug3a0eHhi_bWtKJOR0MeZHvfQLoIPtP-um7AWafRM

Latest commit adds a change to the failing MC tests to be exactly the same as the MC tests for eor3 and bcax.

Will look into that and update this review with the necessary changes.

Merging all instructions into same multiclass.

In D73746#1851678, @kmclaughlin wrote:

Thanks for these changes, @dancgr! I just have a couple of comments on the tests in sve2-mla-unpredicated.ll

Add missing i16 tests.

@sdesmalen Hopefully all comments from D73576 were addressed with this patch.

I will make the changes suggested by Sander in a following patch, joined with the saturating multiply-add long intirnsics.

Remove _m from intrinsics, as it is the default behaviour. Also, add unpredicated patterns for SVE2 smulh, umulh.

I'm not sure on some parts, but I have prepared a major update for this patch that I hope will fix most of @sdesmalen concerns.

Tentative changes to address some comments from the reviewers.

I'm not sure on some parts, but I have prepared a major update for this patch that I hope will fix most of @sdesmalen concerns.

In D72799#1822788, @efriedma wrote:

In D72799#1822599, @dancgr wrote:

In D72799#1822588, @efriedma wrote:

Can we also also add mul patterns for targets that have SVE, but not SVE2?

That instruction is restricted to SVE2. Do we have unpredicated vector mul instructions for SVE targets as well?

We can synthesize a predicate using ptrue. We do this in a few places currently; for example, to implement bswap.

In D72799#1822588, @efriedma wrote:

Can we also also add mul patterns for targets that have SVE, but not SVE2?

Fix whitespace errors and add a couple negative tests for invalid input.

In D72654#1818201, @efriedma wrote:

Do we have any negative tests, for immediates that are outside the range of the sve mul immediate instruction?

@efriedma Any other remarks on this patch?

Updated some minor changes.

Update to use default ISD:SMAX variety.

In D71779#1795054, @efriedma wrote:

Wong SMAX; you're referring to VECREDUCE_SMAX, which isn't relevant here. There is no IR intrinsic for ISD::SMAX; it's pattern-matched from select instructions.

As far as I know the ISD::SMAX only takes one input (https://llvm.org/docs/LangRef.html#llvm-experimental-vector-reduce-smax-intrinsic), in this case we need two inputs so we can do the max between the input vector and the immediate value.

For llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll it is still not performing the dag combine, however the resulting assembly is different because this matches with the new AArch64dup pattern for logical vector and immediate AND.

Fix issues with sve gather scatter test.

All changes reverted by commit c7abf8841187c6e2c4169c06226429cdd5650e7f.

This https://reviews.llvm.org/rGeb1857ce0da481caf82271e6d0c9fc745dfab26f fixes this error for now.

Remove unused intrinsic.

Moving SUBR from intrinsics to a reverse pattern match with sub IR instruction.

There are no changes needed after https://reviews.llvm.org/rG002adabb3a251a81ef304353eefb1bf96ec388f6.

I will be merging this patch then, and I will submit a short patch for the AArch64dup (SVELogicalImm32 i64:$imm) patterns and the equivalent ones for the add/sub instructions.

Add specific intrinsic for i64.

b29916cec3f45e5fb5efff5104acf142f348c724

Update minor details.