Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact.
One concern is that some reorderings break relaxable instruction pairs, such as lui/addi with %*hi and %*lo relocations. (Grepping with grep -C1 "%.*hi" *.ll in llvm/test/CodeGen/RISCV shows that in most tests such instructions are still in sequential pairs). We might need a proper machine model to fix that, but that would be a separate patch.
A few tests that had to be manually updated are worth additional review attention:
rv64i-complex-float.ll compress.ll callee-saved-fpr32s.ll callee-saved-fpr64s.ll callee-saved-gprs.ll
This patch does seem to have added some additional mv instructions in this test (and others). It's usually because there's some kind of two-way register copy happening, which now uses a temporary register.