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Differential D66973

[RISCV] Switch to the Machine Scheduler
ClosedPublic

Authored by luismarques on Aug 29 2019, 1:31 PM.

Details

Reviewers
asb
lenary
Commits
rG3d0fbafd0bce: [RISCV] Switch to the Machine Scheduler
rL372106: [RISCV] Switch to the Machine Scheduler
Summary

Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact.

One concern is that some reorderings break relaxable instruction pairs, such as lui/addi with %*hi and %*lo relocations. (Grepping with grep -C1 "%.*hi" *.ll in llvm/test/CodeGen/RISCV shows that in most tests such instructions are still in sequential pairs). We might need a proper machine model to fix that, but that would be a separate patch.

A few tests that had to be manually updated are worth additional review attention:

rv64i-complex-float.ll
compress.ll
callee-saved-fpr32s.ll
callee-saved-fpr64s.ll
callee-saved-gprs.ll

Diff Detail

Event Timeline

luismarques created this revision.Aug 29 2019, 1:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 29 2019, 1:31 PM
Herald added subscribers: llvm-commits, pzheng, s.egerton and 25 others. · View Herald Transcript
luismarques updated this revision to Diff 218111.Aug 30 2019, 8:47 AM

Rebased on master.

jrtc27 added a comment.Aug 30 2019, 12:44 PM

%hi and %lo don't need to be adjacent to relax them; the ABI has been designed with this in mind (and bfd keeps to that) So long as the result of the %hi is always "consumed" by a relaxable %lo, things will work.

lenary added a comment.Sep 10 2019, 7:39 AM
In D66973#1653084, @jrtc27 wrote:

%hi and %lo don't need to be adjacent to relax them; the ABI has been designed with this in mind (and bfd keeps to that) So long as the result of the %hi is always "consumed" by a relaxable %lo, things will work.

Does this apply even if there is another relocation between %hi and %lo?

lenary added a comment.Sep 10 2019, 7:51 AM

Three nits about changes to the testcases that go beyond just reordering.

I don't think this should block the patch from landing, but I do think that we should keep an eye on why they are happening, and hope to get rid of them when we introduce a schedule.

llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
2176

This patch does seem to have added some additional mv instructions in this test (and others). It's usually because there's some kind of two-way register copy happening, which now uses a temporary register.

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
109

I don't know where this came from, but having both flw ... %lo(var)(a0) followed by addi ... %lo(var) does not seem so amenable for linker relaxation, though @jrtc27 would have a better idea about this than me.

llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
46

We seem to have gained a lw; sw pair here. Not entirely sure why. There are a few additions like this in this testcase.

jrtc27 added a comment.EditedSep 10 2019, 5:12 PM
In D66973#1664698, @lenary wrote:
In D66973#1653084, @jrtc27 wrote:

%hi and %lo don't need to be adjacent to relax them; the ABI has been designed with this in mind (and bfd keeps to that) So long as the result of the %hi is always "consumed" by a relaxable %lo, things will work.

Does this apply even if there is another relocation between %hi and %lo?

Yes, it really doesn't matter. So long as the data dependency is there in the assembly (which it will be, because that's what we generate) it makes no difference *where* the instructions are. The relaxations available are: 1. deleting lui rd, %hi(x) and changing the addi rd, rs1, %lo(x) to addi rd, gp, %gprel(x) (if within 2K of gp) or addi rd, x0, %lo(x) (if in first 2K of memory) 2. changing lui rd, %hi(x) to c.lui rd, %hi(x) (but a R_RISCV_RVC_LUI) if rd is a valid register and %hi(x) is a valid immediate for c.lui. None of these care about adjacency or order; they could even be split across object files.

Footnote: I only talk about addi here; any I-type or S-type instruction works in its place.

jrtc27 added inline comments.Sep 10 2019, 5:36 PM
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
46

I assume these were previously scheduled after the addi but have now been hoisted. Note that these check lines do not continue to the end of the function, these are truncated, and manually created rather than using update_llc_test_checks.py for this file.

lenary accepted this revision.Sep 12 2019, 2:53 AM

Ok, I'm happy with the test changes in this patch. Let's get it landed!

This revision is now accepted and ready to land.Sep 12 2019, 2:53 AM
luismarques updated this revision to Diff 220345.Sep 16 2019, 7:59 AM

Refresh patch before committing.

MaskRay closed this revision.Sep 17 2019, 2:57 AM

@luismarques Closed by rL372092 (unfortunately that commit does not include the summary here).

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Diff 220345

llvm/lib/Target/RISCV/RISCVSubtarget.h

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines const RISCVRegisterInfo *getRegisterInfo() const override {
return &RegInfo; return &RegInfo;
} }
const RISCVTargetLowering *getTargetLowering() const override { const RISCVTargetLowering *getTargetLowering() const override {
return &TLInfo; return &TLInfo;
} }
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
bool enableMachineScheduler() const override { return true; }
bool hasStdExtM() const { return HasStdExtM; } bool hasStdExtM() const { return HasStdExtM; }
bool hasStdExtA() const { return HasStdExtA; } bool hasStdExtA() const { return HasStdExtA; }
bool hasStdExtF() const { return HasStdExtF; } bool hasStdExtF() const { return HasStdExtF; }
bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtD() const { return HasStdExtD; }
bool hasStdExtC() const { return HasStdExtC; } bool hasStdExtC() const { return HasStdExtC; }
bool is64Bit() const { return HasRV64; } bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; } bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; } bool enableLinkerRelax() const { return EnableLinkerRelax; }
Show All 21 Lines

llvm/test/CodeGen/RISCV/add-before-shl.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%2 = shl i24 %1, 12 %2 = shl i24 %1, 12
ret i24 %2 ret i24 %2
} }
define i128 @add_wide_operand(i128 %a) nounwind { define i128 @add_wide_operand(i128 %a) nounwind {
; RV32I-LABEL: add_wide_operand: ; RV32I-LABEL: add_wide_operand:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: srli a3, a2, 29 ; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a4, 4(a1) ; RV32I-NEXT: lw a6, 12(a1)
; RV32I-NEXT: slli a5, a4, 3 ; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: or a6, a5, a3 ; RV32I-NEXT: srli a5, a2, 29
; RV32I-NEXT: srli a4, a4, 29 ; RV32I-NEXT: slli a4, a3, 3
; RV32I-NEXT: lw a5, 8(a1) ; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: slli a3, a5, 3 ; RV32I-NEXT: srli a3, a3, 29
; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: slli a5, a1, 3
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: slli a5, a6, 3
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: slli a2, a2, 3 ; RV32I-NEXT: slli a2, a2, 3
; RV32I-NEXT: lui a5, 128
; RV32I-NEXT: add a1, a1, a5
; RV32I-NEXT: sw a2, 0(a0) ; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a3, 8(a0) ; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a6, 4(a0) ; RV32I-NEXT: sw a4, 4(a0)
; RV32I-NEXT: srli a2, a5, 29
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: slli a1, a1, 3
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: lui a2, 128
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: add_wide_operand: ; RV64I-LABEL: add_wide_operand:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: srli a2, a0, 61 ; RV64I-NEXT: srli a2, a0, 61
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 51 ; RV64I-NEXT: slli a2, a2, 51
; RV64I-NEXT: add a1, a1, a2 ; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = add i128 %a, 5192296858534827628530496329220096 %1 = add i128 %a, 5192296858534827628530496329220096
%2 = shl i128 %1, 3 %2 = shl i128 %1, 3
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll

Show All 14 Lines
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = add i64 %a, %b %1 = add i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @subc_sube(i64 %a, i64 %b) nounwind { define i64 @subc_sube(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: subc_sube: ; RV32I-LABEL: subc_sube:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sltu a3, a0, a2 ; RV32I-NEXT: sub a1, a1, a4
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = sub i64 %a, %b %1 = sub i64 %a, %b
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/addcarry.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32
; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY. ; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.
; Signed fixed point multiplication eventually expands down to an ADDCARRY. ; Signed fixed point multiplication eventually expands down to an ADDCARRY.
declare i64 @llvm.smul.fix.i64 (i64, i64, i32) declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
define i64 @addcarry(i64 %x, i64 %y) nounwind { define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-LABEL: addcarry: ; RISCV32-LABEL: addcarry:
; RISCV32: # %bb.0: ; RISCV32: # %bb.0:
; RISCV32-NEXT: mul a4, a0, a3 ; RISCV32-NEXT: mul a4, a0, a3
; RISCV32-NEXT: mulhu a5, a0, a2 ; RISCV32-NEXT: mulhu a7, a0, a2
; RISCV32-NEXT: add a4, a5, a4 ; RISCV32-NEXT: add a4, a7, a4
; RISCV32-NEXT: sltu a6, a4, a5
; RISCV32-NEXT: mulhu a5, a0, a3
; RISCV32-NEXT: add a6, a5, a6
; RISCV32-NEXT: mulhu a5, a1, a2
; RISCV32-NEXT: add a7, a6, a5
; RISCV32-NEXT: mul a5, a1, a2 ; RISCV32-NEXT: mul a5, a1, a2
; RISCV32-NEXT: add a6, a4, a5 ; RISCV32-NEXT: add a6, a4, a5
; RISCV32-NEXT: sltu a4, a6, a4 ; RISCV32-NEXT: sltu t0, a6, a4
; RISCV32-NEXT: add a4, a7, a4 ; RISCV32-NEXT: sltu a4, a4, a7
; RISCV32-NEXT: mulhu a5, a0, a3
; RISCV32-NEXT: add a4, a5, a4
; RISCV32-NEXT: mulhu a5, a1, a2
; RISCV32-NEXT: add a4, a4, a5
; RISCV32-NEXT: add a4, a4, t0
; RISCV32-NEXT: mul a5, a1, a3 ; RISCV32-NEXT: mul a5, a1, a3
; RISCV32-NEXT: add a5, a4, a5 ; RISCV32-NEXT: add a5, a4, a5
; RISCV32-NEXT: bgez a1, .LBB0_2 ; RISCV32-NEXT: bgez a1, .LBB0_2
; RISCV32-NEXT: # %bb.1: ; RISCV32-NEXT: # %bb.1:
; RISCV32-NEXT: sub a5, a5, a2 ; RISCV32-NEXT: sub a5, a5, a2
; RISCV32-NEXT: .LBB0_2: ; RISCV32-NEXT: .LBB0_2:
; RISCV32-NEXT: bgez a3, .LBB0_4 ; RISCV32-NEXT: bgez a3, .LBB0_4
; RISCV32-NEXT: # %bb.3: ; RISCV32-NEXT: # %bb.3:
; RISCV32-NEXT: sub a5, a5, a0 ; RISCV32-NEXT: sub a5, a5, a0
; RISCV32-NEXT: .LBB0_4: ; RISCV32-NEXT: .LBB0_4:
; RISCV32-NEXT: slli a1, a5, 30
; RISCV32-NEXT: srli a3, a6, 2
; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: slli a3, a6, 30
; RISCV32-NEXT: mul a0, a0, a2 ; RISCV32-NEXT: mul a0, a0, a2
; RISCV32-NEXT: srli a0, a0, 2 ; RISCV32-NEXT: srli a0, a0, 2
; RISCV32-NEXT: slli a1, a6, 30 ; RISCV32-NEXT: or a0, a3, a0
; RISCV32-NEXT: or a0, a1, a0
; RISCV32-NEXT: srli a1, a6, 2
; RISCV32-NEXT: slli a2, a5, 30
; RISCV32-NEXT: or a1, a2, a1
; RISCV32-NEXT: ret ; RISCV32-NEXT: ret
%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2); %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);
ret i64 %tmp; ret i64 %tmp;
} }

llvm/test/CodeGen/RISCV/alloca.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: addi a1, zero, 12 ; RV32I-NEXT: addi a1, zero, 12
; RV32I-NEXT: sw a1, 12(sp) ; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: addi a1, zero, 11 ; RV32I-NEXT: addi a1, zero, 11
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, zero, 10 ; RV32I-NEXT: addi a1, zero, 10
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: addi a1, zero, 9 ; RV32I-NEXT: addi t0, zero, 9
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 6 ; RV32I-NEXT: addi a5, zero, 6
; RV32I-NEXT: addi a6, zero, 7 ; RV32I-NEXT: addi a6, zero, 7
; RV32I-NEXT: addi a7, zero, 8 ; RV32I-NEXT: addi a7, zero, 8
; RV32I-NEXT: sw t0, 0(sp)
; RV32I-NEXT: call func ; RV32I-NEXT: call func
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = alloca i8, i32 %n %1 = alloca i8, i32 %n
call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8,
i32 9, i32 10, i32 11, i32 12) i32 9, i32 10, i32 11, i32 12)
ret void ret void
} }

llvm/test/CodeGen/RISCV/alu64.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
define i64 @slli(i64 %a) nounwind { define i64 @slli(i64 %a) nounwind {
; RV64I-LABEL: slli: ; RV64I-LABEL: slli:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 7 ; RV64I-NEXT: slli a0, a0, 7
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32I-LABEL: slli: ; RV32I-LABEL: slli:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a1, 7
; RV32I-NEXT: srli a2, a0, 25 ; RV32I-NEXT: srli a2, a0, 25
; RV32I-NEXT: slli a1, a1, 7
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a0, a0, 7 ; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = shl i64 %a, 7 %1 = shl i64 %a, 7
ret i64 %1 ret i64 %1
} }
define i64 @srli(i64 %a) nounwind { define i64 @srli(i64 %a) nounwind {
; RV64I-LABEL: srli: ; RV64I-LABEL: srli:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32I-LABEL: srli: ; RV32I-LABEL: srli:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: slli a2, a1, 24 ; RV32I-NEXT: slli a2, a1, 24
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = lshr i64 %a, 8 %1 = lshr i64 %a, 8
ret i64 %1 ret i64 %1
} }
define i64 @srai(i64 %a) nounwind { define i64 @srai(i64 %a) nounwind {
; RV64I-LABEL: srai: ; RV64I-LABEL: srai:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srai a0, a0, 9 ; RV64I-NEXT: srai a0, a0, 9
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32I-LABEL: srai: ; RV32I-LABEL: srai:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 9
; RV32I-NEXT: slli a2, a1, 23 ; RV32I-NEXT: slli a2, a1, 23
; RV32I-NEXT: srli a0, a0, 9
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: srai a1, a1, 9 ; RV32I-NEXT: srai a1, a1, 9
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = ashr i64 %a, 9 %1 = ashr i64 %a, 9
ret i64 %1 ret i64 %1
} }
; Register-register instructions ; Register-register instructions
Show All 19 Lines
define i64 @sub(i64 %a, i64 %b) nounwind { define i64 @sub(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sub: ; RV64I-LABEL: sub:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32I-LABEL: sub: ; RV32I-LABEL: sub:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sltu a3, a0, a2 ; RV32I-NEXT: sub a1, a1, a4
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = sub i64 %a, %b %1 = sub i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @sll(i64 %a, i64 %b) nounwind { define i64 @sll(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sll: ; RV64I-LABEL: sll:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32I-LABEL: sll: ; RV32I-LABEL: sll:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB11_2 ; RV32I-NEXT: bltz a3, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a1, a0, a3 ; RV32I-NEXT: sll a1, a0, a3
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: addi a3, zero, 31 ; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2 ; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: srli a4, a0, 1 ; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3 ; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sll a0, a0, a2 ; RV32I-NEXT: sll a2, a0, a2
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = shl i64 %a, %b %1 = shl i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @slt(i64 %a, i64 %b) nounwind { define i64 @slt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: slt: ; RV64I-LABEL: slt:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB15_2 ; RV32I-NEXT: bltz a3, .LBB15_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a0, a1, a3 ; RV32I-NEXT: srl a0, a1, a3
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB15_2: ; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31 ; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2 ; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1 ; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3 ; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: srl a1, a1, a2 ; RV32I-NEXT: srl a2, a1, a2
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = lshr i64 %a, %b %1 = lshr i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @sra(i64 %a, i64 %b) nounwind { define i64 @sra(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sra: ; RV64I-LABEL: sra:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1 ; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32I-LABEL: sra: ; RV32I-LABEL: sra:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB16_2 ; RV32I-NEXT: bltz a3, .LBB16_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sra a0, a1, a3 ; RV32I-NEXT: sra a0, a1, a3
; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB16_2: ; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31 ; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2 ; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1 ; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3 ; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2 ; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = ashr i64 %a, %b %1 = ashr i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @or(i64 %a, i64 %b) nounwind { define i64 @or(i64 %a, i64 %b) nounwind {
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llvm/test/CodeGen/RISCV/arith-with-overflow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b) declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind { define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: sadd: ; RV32I-LABEL: sadd:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: add a3, a0, a1 ; RV32I-NEXT: addi a3, zero, -1
; RV32I-NEXT: sw a3, 0(a2) ; RV32I-NEXT: slt a4, a3, a1
; RV32I-NEXT: addi a2, zero, -1 ; RV32I-NEXT: slt a5, a3, a0
; RV32I-NEXT: slt a1, a2, a1 ; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: slt a0, a2, a0 ; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: slt a2, a2, a3 ; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: slt a0, a3, a1
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a5, a0
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: snez a1, a2 ; RV32I-NEXT: and a0, a4, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) %x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0 %calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1 %ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c store i32 %calc, i32* %c
ret i1 %ovf ret i1 %ovf
} }
define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind { define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: ssub: ; RV32I-LABEL: ssub:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: sub a3, a0, a1 ; RV32I-NEXT: addi a3, zero, -1
; RV32I-NEXT: sw a3, 0(a2) ; RV32I-NEXT: slt a4, a3, a1
; RV32I-NEXT: addi a2, zero, -1 ; RV32I-NEXT: slt a5, a3, a0
; RV32I-NEXT: slt a1, a2, a1 ; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: slt a0, a2, a0 ; RV32I-NEXT: snez a4, a4
; RV32I-NEXT: slt a2, a2, a3 ; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: slt a0, a3, a1
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a5, a0
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: snez a1, a2 ; RV32I-NEXT: and a0, a4, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) %x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0 %calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1 %ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c store i32 %calc, i32* %c
ret i1 %ovf ret i1 %ovf
} }
define i1 @uadd(i32 %a, i32 %b, i32* %c) nounwind { define i1 @uadd(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: uadd: ; RV32I-LABEL: uadd:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: add a1, a0, a1 ; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) %x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0 %calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1 %ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c store i32 %calc, i32* %c
ret i1 %ovf ret i1 %ovf
} }
define i1 @usub(i32 %a, i32 %b, i32* %c) nounwind { define i1 @usub(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: usub: ; RV32I-LABEL: usub:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: sub a1, a0, a1 ; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b) %x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0 %calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1 %ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c store i32 %calc, i32* %c
ret i1 %ovf ret i1 %ovf
} }

llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
; This test ensures that the output of the 'lr.w' instruction is sign-extended. ; This test ensures that the output of the 'lr.w' instruction is sign-extended.
; Previously, the default zero-extension was being used and 'cmp' parameter ; Previously, the default zero-extension was being used and 'cmp' parameter
; higher bits were masked to zero for the comparison. ; higher bits were masked to zero for the comparison.
define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp, define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
i32 signext %val) nounwind {
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: # %entry ; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: .LBB0_1: # %entry ; RV64IA-NEXT: .LBB0_1: # %entry
; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB0_3 ; RV64IA-NEXT: bne a3, a1, .LBB0_3
; RV64IA-NEXT: # %bb.2: # %entry ; RV64IA-NEXT: # %bb.2: # %entry
; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB0_1 ; RV64IA-NEXT: bnez a4, .LBB0_1
; RV64IA-NEXT: .LBB0_3: # %entry ; RV64IA-NEXT: .LBB0_3: # %entry
; RV64IA-NEXT: xor a0, a3, a1 ; RV64IA-NEXT: xor a0, a3, a1
; RV64IA-NEXT: seqz a0, a0 ; RV64IA-NEXT: seqz a0, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
i32 signext %val) nounwind {
entry: entry:
%0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst %0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
%1 = extractvalue { i32, i1 } %0, 1 %1 = extractvalue { i32, i1 } %0, 1
ret i1 %1 ret i1 %1
} }

llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

Show All 18 Lines
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB0_3 ; RV32IA-NEXT: bne a5, a1, .LBB0_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: .LBB0_3: ; RV32IA-NEXT: .LBB0_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB0_3 ; RV64IA-NEXT: bne a5, a1, .LBB0_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB0_1 ; RV64IA-NEXT: bnez a5, .LBB0_1
; RV64IA-NEXT: .LBB0_3: ; RV64IA-NEXT: .LBB0_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB1_3 ; RV32IA-NEXT: bne a5, a1, .LBB1_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: .LBB1_3: ; RV32IA-NEXT: .LBB1_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB1_3 ; RV64IA-NEXT: bne a5, a1, .LBB1_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB1_1 ; RV64IA-NEXT: bnez a5, .LBB1_1
; RV64IA-NEXT: .LBB1_3: ; RV64IA-NEXT: .LBB1_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acquire_acquire: ; RV32I-LABEL: cmpxchg_i8_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB2_3 ; RV32IA-NEXT: bne a5, a1, .LBB2_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: .LBB2_3: ; RV32IA-NEXT: .LBB2_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acquire_acquire: ; RV64I-LABEL: cmpxchg_i8_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB2_3 ; RV64IA-NEXT: bne a5, a1, .LBB2_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB2_1 ; RV64IA-NEXT: bnez a5, .LBB2_1
; RV64IA-NEXT: .LBB2_3: ; RV64IA-NEXT: .LBB2_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_release_monotonic: ; RV32I-LABEL: cmpxchg_i8_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_release_monotonic: ; RV32IA-LABEL: cmpxchg_i8_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB3_3 ; RV32IA-NEXT: bne a5, a1, .LBB3_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: .LBB3_3: ; RV32IA-NEXT: .LBB3_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_release_monotonic: ; RV64I-LABEL: cmpxchg_i8_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_release_monotonic: ; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB3_3 ; RV64IA-NEXT: bne a5, a1, .LBB3_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB3_1 ; RV64IA-NEXT: bnez a5, .LBB3_1
; RV64IA-NEXT: .LBB3_3: ; RV64IA-NEXT: .LBB3_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_release_acquire: ; RV32I-LABEL: cmpxchg_i8_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_release_acquire: ; RV32IA-LABEL: cmpxchg_i8_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB4_3 ; RV32IA-NEXT: bne a5, a1, .LBB4_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: .LBB4_3: ; RV32IA-NEXT: .LBB4_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_release_acquire: ; RV64I-LABEL: cmpxchg_i8_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_release_acquire: ; RV64IA-LABEL: cmpxchg_i8_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB4_3 ; RV64IA-NEXT: bne a5, a1, .LBB4_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB4_1 ; RV64IA-NEXT: bnez a5, .LBB4_1
; RV64IA-NEXT: .LBB4_3: ; RV64IA-NEXT: .LBB4_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
ret void ret void
} }
define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB5_3 ; RV32IA-NEXT: bne a5, a1, .LBB5_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: bnez a5, .LBB5_1
; RV32IA-NEXT: .LBB5_3: ; RV32IA-NEXT: .LBB5_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB5_3 ; RV64IA-NEXT: bne a5, a1, .LBB5_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB5_1 ; RV64IA-NEXT: bnez a5, .LBB5_1
; RV64IA-NEXT: .LBB5_3: ; RV64IA-NEXT: .LBB5_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB6_3 ; RV32IA-NEXT: bne a5, a1, .LBB6_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: bnez a5, .LBB6_1
; RV32IA-NEXT: .LBB6_3: ; RV32IA-NEXT: .LBB6_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB6_3 ; RV64IA-NEXT: bne a5, a1, .LBB6_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB6_1 ; RV64IA-NEXT: bnez a5, .LBB6_1
; RV64IA-NEXT: .LBB6_3: ; RV64IA-NEXT: .LBB6_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB7_3 ; RV32IA-NEXT: bne a5, a1, .LBB7_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: .LBB7_3: ; RV32IA-NEXT: .LBB7_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB7_3 ; RV64IA-NEXT: bne a5, a1, .LBB7_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB7_1 ; RV64IA-NEXT: bnez a5, .LBB7_1
; RV64IA-NEXT: .LBB7_3: ; RV64IA-NEXT: .LBB7_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB8_3 ; RV32IA-NEXT: bne a5, a1, .LBB8_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: .LBB8_3: ; RV32IA-NEXT: .LBB8_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB8_3 ; RV64IA-NEXT: bne a5, a1, .LBB8_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB8_1 ; RV64IA-NEXT: bnez a5, .LBB8_1
; RV64IA-NEXT: .LBB8_3: ; RV64IA-NEXT: .LBB8_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a2, a2, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: andi a2, a2, 255
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a3, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB9_3 ; RV32IA-NEXT: bne a5, a1, .LBB9_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a2 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: .LBB9_3: ; RV32IA-NEXT: .LBB9_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a3 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a2, a2, a3
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: andi a2, a2, 255
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a3, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB9_3 ; RV64IA-NEXT: bne a5, a1, .LBB9_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a2 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB9_1 ; RV64IA-NEXT: bnez a5, .LBB9_1
; RV64IA-NEXT: .LBB9_3: ; RV64IA-NEXT: .LBB9_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB10_3 ; RV32IA-NEXT: bne a4, a1, .LBB10_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB10_1 ; RV32IA-NEXT: bnez a4, .LBB10_1
; RV32IA-NEXT: .LBB10_3: ; RV32IA-NEXT: .LBB10_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB10_3 ; RV64IA-NEXT: bne a4, a1, .LBB10_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB10_1 ; RV64IA-NEXT: bnez a4, .LBB10_1
; RV64IA-NEXT: .LBB10_3: ; RV64IA-NEXT: .LBB10_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB11_3 ; RV32IA-NEXT: bne a4, a1, .LBB11_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB11_1 ; RV32IA-NEXT: bnez a4, .LBB11_1
; RV32IA-NEXT: .LBB11_3: ; RV32IA-NEXT: .LBB11_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB11_3 ; RV64IA-NEXT: bne a4, a1, .LBB11_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB11_1 ; RV64IA-NEXT: bnez a4, .LBB11_1
; RV64IA-NEXT: .LBB11_3: ; RV64IA-NEXT: .LBB11_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acquire_acquire: ; RV32I-LABEL: cmpxchg_i16_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB12_3 ; RV32IA-NEXT: bne a4, a1, .LBB12_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB12_1 ; RV32IA-NEXT: bnez a4, .LBB12_1
; RV32IA-NEXT: .LBB12_3: ; RV32IA-NEXT: .LBB12_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acquire_acquire: ; RV64I-LABEL: cmpxchg_i16_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB12_3 ; RV64IA-NEXT: bne a4, a1, .LBB12_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB12_1 ; RV64IA-NEXT: bnez a4, .LBB12_1
; RV64IA-NEXT: .LBB12_3: ; RV64IA-NEXT: .LBB12_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_release_monotonic: ; RV32I-LABEL: cmpxchg_i16_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_release_monotonic: ; RV32IA-LABEL: cmpxchg_i16_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB13_3 ; RV32IA-NEXT: bne a4, a1, .LBB13_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB13_1 ; RV32IA-NEXT: bnez a4, .LBB13_1
; RV32IA-NEXT: .LBB13_3: ; RV32IA-NEXT: .LBB13_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_release_monotonic: ; RV64I-LABEL: cmpxchg_i16_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_release_monotonic: ; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB13_3 ; RV64IA-NEXT: bne a4, a1, .LBB13_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB13_1 ; RV64IA-NEXT: bnez a4, .LBB13_1
; RV64IA-NEXT: .LBB13_3: ; RV64IA-NEXT: .LBB13_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_release_acquire: ; RV32I-LABEL: cmpxchg_i16_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_release_acquire: ; RV32IA-LABEL: cmpxchg_i16_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB14_3 ; RV32IA-NEXT: bne a4, a1, .LBB14_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB14_1 ; RV32IA-NEXT: bnez a4, .LBB14_1
; RV32IA-NEXT: .LBB14_3: ; RV32IA-NEXT: .LBB14_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_release_acquire: ; RV64I-LABEL: cmpxchg_i16_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_release_acquire: ; RV64IA-LABEL: cmpxchg_i16_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB14_3 ; RV64IA-NEXT: bne a4, a1, .LBB14_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB14_1 ; RV64IA-NEXT: bnez a4, .LBB14_1
; RV64IA-NEXT: .LBB14_3: ; RV64IA-NEXT: .LBB14_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
ret void ret void
} }
define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB15_3 ; RV32IA-NEXT: bne a4, a1, .LBB15_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB15_1 ; RV32IA-NEXT: bnez a4, .LBB15_1
; RV32IA-NEXT: .LBB15_3: ; RV32IA-NEXT: .LBB15_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB15_3 ; RV64IA-NEXT: bne a4, a1, .LBB15_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB15_1 ; RV64IA-NEXT: bnez a4, .LBB15_1
; RV64IA-NEXT: .LBB15_3: ; RV64IA-NEXT: .LBB15_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB16_3 ; RV32IA-NEXT: bne a4, a1, .LBB16_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB16_1 ; RV32IA-NEXT: bnez a4, .LBB16_1
; RV32IA-NEXT: .LBB16_3: ; RV32IA-NEXT: .LBB16_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB16_3 ; RV64IA-NEXT: bne a4, a1, .LBB16_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB16_1 ; RV64IA-NEXT: bnez a4, .LBB16_1
; RV64IA-NEXT: .LBB16_3: ; RV64IA-NEXT: .LBB16_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB17_3 ; RV32IA-NEXT: bne a4, a1, .LBB17_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB17_1 ; RV32IA-NEXT: bnez a4, .LBB17_1
; RV32IA-NEXT: .LBB17_3: ; RV32IA-NEXT: .LBB17_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB17_3 ; RV64IA-NEXT: bne a4, a1, .LBB17_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB17_1 ; RV64IA-NEXT: bnez a4, .LBB17_1
; RV64IA-NEXT: .LBB17_3: ; RV64IA-NEXT: .LBB17_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB18_3 ; RV32IA-NEXT: bne a4, a1, .LBB18_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB18_1 ; RV32IA-NEXT: bnez a4, .LBB18_1
; RV32IA-NEXT: .LBB18_3: ; RV32IA-NEXT: .LBB18_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB18_3 ; RV64IA-NEXT: bne a4, a1, .LBB18_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB18_1 ; RV64IA-NEXT: bnez a4, .LBB18_1
; RV64IA-NEXT: .LBB18_3: ; RV64IA-NEXT: .LBB18_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: and a2, a2, a3 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: slli a4, a0, 3 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: andi a4, a4, 24 ; RV32IA-NEXT: sll a5, a4, a0
; RV32IA-NEXT: sll a3, a3, a4 ; RV32IA-NEXT: and a1, a1, a4
; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: sll a1, a1, a4 ; RV32IA-NEXT: and a2, a2, a4
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a4, a3 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a5, a1, .LBB19_3 ; RV32IA-NEXT: bne a4, a1, .LBB19_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a5, .LBB19_1 ; RV32IA-NEXT: bnez a4, .LBB19_1
; RV32IA-NEXT: .LBB19_3: ; RV32IA-NEXT: .LBB19_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: and a2, a2, a3 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: slli a4, a0, 3 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: andi a4, a4, 24 ; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: sllw a3, a3, a4 ; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: sllw a1, a1, a4 ; RV64IA-NEXT: and a2, a2, a4
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a4, a3 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a5, a1, .LBB19_3 ; RV64IA-NEXT: bne a4, a1, .LBB19_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV64IA-NEXT: bnez a5, .LBB19_1 ; RV64IA-NEXT: bnez a4, .LBB19_1
; RV64IA-NEXT: .LBB19_3: ; RV64IA-NEXT: .LBB19_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic:
▲ Show 20 Lines • Show All 575 Lines • ▼ Show 20 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i64_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
lenaryUnsubmitted
Not Done
ReplyInline Actions

This patch does seem to have added some additional mv instructions in this test (and others). It's usually because there's some kind of two-way register copy happening, which now uses a temporary register.

lenary: This patch does seem to have added some additional `mv` instructions in this test (and others).
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
Show All 22 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acquire_acquire: ; RV32I-LABEL: cmpxchg_i64_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i64_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acquire_acquire: ; RV64I-LABEL: cmpxchg_i64_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 21 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_release_monotonic: ; RV32I-LABEL: cmpxchg_i64_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_release_monotonic: ; RV32IA-LABEL: cmpxchg_i64_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_release_monotonic: ; RV64I-LABEL: cmpxchg_i64_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
Show All 22 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_release_acquire: ; RV32I-LABEL: cmpxchg_i64_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_release_acquire: ; RV32IA-LABEL: cmpxchg_i64_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_release_acquire: ; RV64I-LABEL: cmpxchg_i64_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 21 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
Show All 22 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 21 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
Show All 22 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 21 Lines; RV64IA-NEXT: ret
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 23 Lines

llvm/test/CodeGen/RISCV/atomic-rmw.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show All 15 Lines
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB0_1 ; RV64IA-NEXT: bnez a5, .LBB0_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b monotonic %1 = atomicrmw xchg i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_acquire: ; RV32I-LABEL: atomicrmw_xchg_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_acquire: ; RV64I-LABEL: atomicrmw_xchg_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB1_1 ; RV64IA-NEXT: bnez a5, .LBB1_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b acquire %1 = atomicrmw xchg i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_release: ; RV32I-LABEL: atomicrmw_xchg_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_release: ; RV32IA-LABEL: atomicrmw_xchg_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_release: ; RV64I-LABEL: atomicrmw_xchg_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_release: ; RV64IA-LABEL: atomicrmw_xchg_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB2_1 ; RV64IA-NEXT: bnez a5, .LBB2_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b release %1 = atomicrmw xchg i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB3_1 ; RV64IA-NEXT: bnez a5, .LBB3_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b acq_rel %1 = atomicrmw xchg i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB4_1 ; RV64IA-NEXT: bnez a5, .LBB4_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b seq_cst %1 = atomicrmw xchg i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_monotonic: ; RV32I-LABEL: atomicrmw_add_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_monotonic: ; RV32IA-LABEL: atomicrmw_add_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: bnez a5, .LBB5_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_monotonic: ; RV64I-LABEL: atomicrmw_add_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB5_1 ; RV64IA-NEXT: bnez a5, .LBB5_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b monotonic %1 = atomicrmw add i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_acquire: ; RV32I-LABEL: atomicrmw_add_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_acquire: ; RV32IA-LABEL: atomicrmw_add_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: bnez a5, .LBB6_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_acquire: ; RV64I-LABEL: atomicrmw_add_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_acquire: ; RV64IA-LABEL: atomicrmw_add_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB6_1 ; RV64IA-NEXT: bnez a5, .LBB6_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b acquire %1 = atomicrmw add i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_release: ; RV32I-LABEL: atomicrmw_add_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_release: ; RV32IA-LABEL: atomicrmw_add_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_release: ; RV64I-LABEL: atomicrmw_add_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_release: ; RV64IA-LABEL: atomicrmw_add_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB7_1 ; RV64IA-NEXT: bnez a5, .LBB7_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b release %1 = atomicrmw add i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_acq_rel: ; RV32I-LABEL: atomicrmw_add_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_acq_rel: ; RV64I-LABEL: atomicrmw_add_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB8_1 ; RV64IA-NEXT: bnez a5, .LBB8_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b acq_rel %1 = atomicrmw add i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_seq_cst: ; RV32I-LABEL: atomicrmw_add_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_seq_cst: ; RV64I-LABEL: atomicrmw_add_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB9_1 ; RV64IA-NEXT: bnez a5, .LBB9_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b seq_cst %1 = atomicrmw add i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_monotonic: ; RV32I-LABEL: atomicrmw_sub_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB10_1 ; RV32IA-NEXT: bnez a5, .LBB10_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_monotonic: ; RV64I-LABEL: atomicrmw_sub_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB10_1 ; RV64IA-NEXT: bnez a5, .LBB10_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b monotonic %1 = atomicrmw sub i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_acquire: ; RV32I-LABEL: atomicrmw_sub_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_acquire: ; RV32IA-LABEL: atomicrmw_sub_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB11_1 ; RV32IA-NEXT: bnez a5, .LBB11_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_acquire: ; RV64I-LABEL: atomicrmw_sub_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA-LABEL: atomicrmw_sub_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB11_1 ; RV64IA-NEXT: bnez a5, .LBB11_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b acquire %1 = atomicrmw sub i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_release: ; RV32I-LABEL: atomicrmw_sub_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_release: ; RV32IA-LABEL: atomicrmw_sub_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB12_1 ; RV32IA-NEXT: bnez a5, .LBB12_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_release: ; RV64I-LABEL: atomicrmw_sub_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_release: ; RV64IA-LABEL: atomicrmw_sub_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB12_1 ; RV64IA-NEXT: bnez a5, .LBB12_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b release %1 = atomicrmw sub i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB13_1 ; RV32IA-NEXT: bnez a5, .LBB13_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB13_1 ; RV64IA-NEXT: bnez a5, .LBB13_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b acq_rel %1 = atomicrmw sub i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB14_1 ; RV32IA-NEXT: bnez a5, .LBB14_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB14_1 ; RV64IA-NEXT: bnez a5, .LBB14_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b seq_cst %1 = atomicrmw sub i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_monotonic: ; RV32I-LABEL: atomicrmw_and_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_monotonic: ; RV32IA-LABEL: atomicrmw_and_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sll a1, a1, a2
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: amoand.w a0, a1, (a0) ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_monotonic: ; RV64I-LABEL: atomicrmw_and_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sllw a1, a1, a2
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1 ; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NEXT: amoand.w a0, a1, (a0) ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b monotonic %1 = atomicrmw and i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_acquire: ; RV32I-LABEL: atomicrmw_and_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_acquire: ; RV32IA-LABEL: atomicrmw_and_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sll a1, a1, a2
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_acquire: ; RV64I-LABEL: atomicrmw_and_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_acquire: ; RV64IA-LABEL: atomicrmw_and_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sllw a1, a1, a2
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1 ; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b acquire %1 = atomicrmw and i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_release: ; RV32I-LABEL: atomicrmw_and_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_release: ; RV32IA-LABEL: atomicrmw_and_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sll a1, a1, a2
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_release: ; RV64I-LABEL: atomicrmw_and_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_release: ; RV64IA-LABEL: atomicrmw_and_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sllw a1, a1, a2
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1 ; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b release %1 = atomicrmw and i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_acq_rel: ; RV32I-LABEL: atomicrmw_and_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sll a1, a1, a2
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_acq_rel: ; RV64I-LABEL: atomicrmw_and_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sllw a1, a1, a2
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1 ; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b acq_rel %1 = atomicrmw and i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_seq_cst: ; RV32I-LABEL: atomicrmw_and_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sll a1, a1, a2
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_seq_cst: ; RV64I-LABEL: atomicrmw_and_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sllw a1, a1, a2
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1 ; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b seq_cst %1 = atomicrmw and i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_monotonic: ; RV32I-LABEL: atomicrmw_nand_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a4, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB20_1 ; RV32IA-NEXT: bnez a5, .LBB20_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_monotonic: ; RV64I-LABEL: atomicrmw_nand_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a4, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB20_1 ; RV64IA-NEXT: bnez a5, .LBB20_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b monotonic %1 = atomicrmw nand i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_acquire: ; RV32I-LABEL: atomicrmw_nand_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_acquire: ; RV32IA-LABEL: atomicrmw_nand_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a4, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB21_1 ; RV32IA-NEXT: bnez a5, .LBB21_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_acquire: ; RV64I-LABEL: atomicrmw_nand_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-LABEL: atomicrmw_nand_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a4, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB21_1 ; RV64IA-NEXT: bnez a5, .LBB21_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b acquire %1 = atomicrmw nand i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_release: ; RV32I-LABEL: atomicrmw_nand_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_release: ; RV32IA-LABEL: atomicrmw_nand_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a4, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB22_1 ; RV32IA-NEXT: bnez a5, .LBB22_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_release: ; RV64I-LABEL: atomicrmw_nand_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_release: ; RV64IA-LABEL: atomicrmw_nand_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a4, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB22_1 ; RV64IA-NEXT: bnez a5, .LBB22_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b release %1 = atomicrmw nand i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a4, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB23_1 ; RV32IA-NEXT: bnez a5, .LBB23_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a4, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB23_1 ; RV64IA-NEXT: bnez a5, .LBB23_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b acq_rel %1 = atomicrmw nand i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a4, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB24_1 ; RV32IA-NEXT: bnez a5, .LBB24_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a4, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB24_1 ; RV64IA-NEXT: bnez a5, .LBB24_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b seq_cst %1 = atomicrmw nand i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_monotonic: ; RV32I-LABEL: atomicrmw_or_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_monotonic: ; RV32IA-LABEL: atomicrmw_or_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoor.w a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_monotonic: ; RV64I-LABEL: atomicrmw_or_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoor.w a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b monotonic %1 = atomicrmw or i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_acquire: ; RV32I-LABEL: atomicrmw_or_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_acquire: ; RV32IA-LABEL: atomicrmw_or_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoor.w.aq a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_acquire: ; RV64I-LABEL: atomicrmw_or_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_acquire: ; RV64IA-LABEL: atomicrmw_or_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoor.w.aq a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b acquire %1 = atomicrmw or i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_release: ; RV32I-LABEL: atomicrmw_or_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_release: ; RV32IA-LABEL: atomicrmw_or_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoor.w.rl a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_release: ; RV64I-LABEL: atomicrmw_or_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_release: ; RV64IA-LABEL: atomicrmw_or_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoor.w.rl a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b release %1 = atomicrmw or i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_acq_rel: ; RV32I-LABEL: atomicrmw_or_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_acq_rel: ; RV64I-LABEL: atomicrmw_or_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b acq_rel %1 = atomicrmw or i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_seq_cst: ; RV32I-LABEL: atomicrmw_or_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_seq_cst: ; RV64I-LABEL: atomicrmw_or_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b seq_cst %1 = atomicrmw or i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_monotonic: ; RV32I-LABEL: atomicrmw_xor_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoxor.w a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_monotonic: ; RV64I-LABEL: atomicrmw_xor_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoxor.w a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b monotonic %1 = atomicrmw xor i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_acquire: ; RV32I-LABEL: atomicrmw_xor_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_acquire: ; RV32IA-LABEL: atomicrmw_xor_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_acquire: ; RV64I-LABEL: atomicrmw_xor_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b acquire %1 = atomicrmw xor i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_release: ; RV32I-LABEL: atomicrmw_xor_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_release: ; RV32IA-LABEL: atomicrmw_xor_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_release: ; RV64I-LABEL: atomicrmw_xor_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_release: ; RV64IA-LABEL: atomicrmw_xor_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b release %1 = atomicrmw xor i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b acq_rel %1 = atomicrmw xor i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: srl a0, a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: srlw a0, a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b seq_cst %1 = atomicrmw xor i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_monotonic: ; RV32I-LABEL: atomicrmw_max_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB35_2 ; RV32I-NEXT: j .LBB35_2
; RV32I-NEXT: .LBB35_1: # %atomicrmw.start ; RV32I-NEXT: .LBB35_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB35_4
; RV32I-NEXT: bnez a1, .LBB35_4
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB35_1 ; RV32I-NEXT: blt s0, a0, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: j .LBB35_1
; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB35_3 ; RV32IA-NEXT: bge a3, a1, .LBB35_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 ; RV32IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB35_1 ; RV32IA-NEXT: bnez a2, .LBB35_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: bnez a1, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB35_1 ; RV64I-NEXT: blt s0, a0, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB35_3 ; RV64IA-NEXT: bge a3, a1, .LBB35_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 ; RV64IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB35_1 ; RV64IA-NEXT: bnez a2, .LBB35_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b monotonic %1 = atomicrmw max i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acquire: ; RV32I-LABEL: atomicrmw_max_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB36_2 ; RV32I-NEXT: j .LBB36_2
; RV32I-NEXT: .LBB36_1: # %atomicrmw.start ; RV32I-NEXT: .LBB36_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB36_4
; RV32I-NEXT: bnez a1, .LBB36_4
; RV32I-NEXT: .LBB36_2: # %atomicrmw.start ; RV32I-NEXT: .LBB36_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB36_1 ; RV32I-NEXT: blt s0, a0, .LBB36_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB36_1 ; RV32I-NEXT: j .LBB36_1
; RV32I-NEXT: .LBB36_4: # %atomicrmw.end ; RV32I-NEXT: .LBB36_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acquire: ; RV32IA-LABEL: atomicrmw_max_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB36_3 ; RV32IA-NEXT: bge a3, a1, .LBB36_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1 ; RV32IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB36_1 ; RV32IA-NEXT: bnez a2, .LBB36_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acquire: ; RV64I-LABEL: atomicrmw_max_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB36_2 ; RV64I-NEXT: j .LBB36_2
; RV64I-NEXT: .LBB36_1: # %atomicrmw.start ; RV64I-NEXT: .LBB36_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB36_4
; RV64I-NEXT: bnez a1, .LBB36_4
; RV64I-NEXT: .LBB36_2: # %atomicrmw.start ; RV64I-NEXT: .LBB36_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB36_1 ; RV64I-NEXT: blt s0, a0, .LBB36_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB36_1 ; RV64I-NEXT: j .LBB36_1
; RV64I-NEXT: .LBB36_4: # %atomicrmw.end ; RV64I-NEXT: .LBB36_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-LABEL: atomicrmw_max_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB36_3 ; RV64IA-NEXT: bge a3, a1, .LBB36_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1 ; RV64IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB36_1 ; RV64IA-NEXT: bnez a2, .LBB36_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acquire %1 = atomicrmw max i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_release: ; RV32I-LABEL: atomicrmw_max_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB37_2 ; RV32I-NEXT: j .LBB37_2
; RV32I-NEXT: .LBB37_1: # %atomicrmw.start ; RV32I-NEXT: .LBB37_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB37_4
; RV32I-NEXT: bnez a1, .LBB37_4
; RV32I-NEXT: .LBB37_2: # %atomicrmw.start ; RV32I-NEXT: .LBB37_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB37_1 ; RV32I-NEXT: blt s0, a0, .LBB37_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB37_1 ; RV32I-NEXT: j .LBB37_1
; RV32I-NEXT: .LBB37_4: # %atomicrmw.end ; RV32I-NEXT: .LBB37_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_release: ; RV32IA-LABEL: atomicrmw_max_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB37_3 ; RV32IA-NEXT: bge a3, a1, .LBB37_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1 ; RV32IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB37_1 ; RV32IA-NEXT: bnez a2, .LBB37_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_release: ; RV64I-LABEL: atomicrmw_max_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB37_2 ; RV64I-NEXT: j .LBB37_2
; RV64I-NEXT: .LBB37_1: # %atomicrmw.start ; RV64I-NEXT: .LBB37_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB37_4
; RV64I-NEXT: bnez a1, .LBB37_4
; RV64I-NEXT: .LBB37_2: # %atomicrmw.start ; RV64I-NEXT: .LBB37_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB37_1 ; RV64I-NEXT: blt s0, a0, .LBB37_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB37_1 ; RV64I-NEXT: j .LBB37_1
; RV64I-NEXT: .LBB37_4: # %atomicrmw.end ; RV64I-NEXT: .LBB37_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_release: ; RV64IA-LABEL: atomicrmw_max_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB37_3 ; RV64IA-NEXT: bge a3, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB37_1 ; RV64IA-NEXT: bnez a2, .LBB37_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b release %1 = atomicrmw max i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acq_rel: ; RV32I-LABEL: atomicrmw_max_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB38_2 ; RV32I-NEXT: j .LBB38_2
; RV32I-NEXT: .LBB38_1: # %atomicrmw.start ; RV32I-NEXT: .LBB38_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB38_4
; RV32I-NEXT: bnez a1, .LBB38_4
; RV32I-NEXT: .LBB38_2: # %atomicrmw.start ; RV32I-NEXT: .LBB38_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB38_1 ; RV32I-NEXT: blt s0, a0, .LBB38_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB38_1 ; RV32I-NEXT: j .LBB38_1
; RV32I-NEXT: .LBB38_4: # %atomicrmw.end ; RV32I-NEXT: .LBB38_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB38_3 ; RV32IA-NEXT: bge a3, a1, .LBB38_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1 ; RV32IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB38_1 ; RV32IA-NEXT: bnez a2, .LBB38_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acq_rel: ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB38_2 ; RV64I-NEXT: j .LBB38_2
; RV64I-NEXT: .LBB38_1: # %atomicrmw.start ; RV64I-NEXT: .LBB38_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB38_4
; RV64I-NEXT: bnez a1, .LBB38_4
; RV64I-NEXT: .LBB38_2: # %atomicrmw.start ; RV64I-NEXT: .LBB38_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB38_1 ; RV64I-NEXT: blt s0, a0, .LBB38_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB38_1 ; RV64I-NEXT: j .LBB38_1
; RV64I-NEXT: .LBB38_4: # %atomicrmw.end ; RV64I-NEXT: .LBB38_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB38_3 ; RV64IA-NEXT: bge a3, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB38_1 ; RV64IA-NEXT: bnez a2, .LBB38_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acq_rel %1 = atomicrmw max i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_seq_cst: ; RV32I-LABEL: atomicrmw_max_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB39_2 ; RV32I-NEXT: j .LBB39_2
; RV32I-NEXT: .LBB39_1: # %atomicrmw.start ; RV32I-NEXT: .LBB39_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB39_4
; RV32I-NEXT: bnez a1, .LBB39_4
; RV32I-NEXT: .LBB39_2: # %atomicrmw.start ; RV32I-NEXT: .LBB39_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB39_1 ; RV32I-NEXT: blt s0, a0, .LBB39_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB39_1 ; RV32I-NEXT: j .LBB39_1
; RV32I-NEXT: .LBB39_4: # %atomicrmw.end ; RV32I-NEXT: .LBB39_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a0) ; RV32IA-NEXT: lr.w.aqrl a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB39_3 ; RV32IA-NEXT: bge a3, a1, .LBB39_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 ; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB39_1 ; RV32IA-NEXT: bnez a2, .LBB39_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_seq_cst: ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB39_2 ; RV64I-NEXT: j .LBB39_2
; RV64I-NEXT: .LBB39_1: # %atomicrmw.start ; RV64I-NEXT: .LBB39_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB39_4
; RV64I-NEXT: bnez a1, .LBB39_4
; RV64I-NEXT: .LBB39_2: # %atomicrmw.start ; RV64I-NEXT: .LBB39_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB39_1 ; RV64I-NEXT: blt s0, a0, .LBB39_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB39_1 ; RV64I-NEXT: j .LBB39_1
; RV64I-NEXT: .LBB39_4: # %atomicrmw.end ; RV64I-NEXT: .LBB39_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a0) ; RV64IA-NEXT: lr.w.aqrl a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB39_3 ; RV64IA-NEXT: bge a3, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB39_1 ; RV64IA-NEXT: bnez a2, .LBB39_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b seq_cst %1 = atomicrmw max i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic: ; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB40_2 ; RV32I-NEXT: j .LBB40_2
; RV32I-NEXT: .LBB40_1: # %atomicrmw.start ; RV32I-NEXT: .LBB40_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB40_4
; RV32I-NEXT: bnez a1, .LBB40_4
; RV32I-NEXT: .LBB40_2: # %atomicrmw.start ; RV32I-NEXT: .LBB40_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB40_1 ; RV32I-NEXT: bge s0, a0, .LBB40_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB40_1 ; RV32I-NEXT: j .LBB40_1
; RV32I-NEXT: .LBB40_4: # %atomicrmw.end ; RV32I-NEXT: .LBB40_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB40_3 ; RV32IA-NEXT: bge a1, a3, .LBB40_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1 ; RV32IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB40_1 ; RV32IA-NEXT: bnez a2, .LBB40_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB40_2 ; RV64I-NEXT: j .LBB40_2
; RV64I-NEXT: .LBB40_1: # %atomicrmw.start ; RV64I-NEXT: .LBB40_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB40_4
; RV64I-NEXT: bnez a1, .LBB40_4
; RV64I-NEXT: .LBB40_2: # %atomicrmw.start ; RV64I-NEXT: .LBB40_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB40_1 ; RV64I-NEXT: bge s0, a0, .LBB40_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB40_1 ; RV64I-NEXT: j .LBB40_1
; RV64I-NEXT: .LBB40_4: # %atomicrmw.end ; RV64I-NEXT: .LBB40_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB40_3 ; RV64IA-NEXT: bge a1, a3, .LBB40_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1 ; RV64IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB40_1 ; RV64IA-NEXT: bnez a2, .LBB40_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b monotonic %1 = atomicrmw min i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acquire: ; RV32I-LABEL: atomicrmw_min_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB41_2 ; RV32I-NEXT: j .LBB41_2
; RV32I-NEXT: .LBB41_1: # %atomicrmw.start ; RV32I-NEXT: .LBB41_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB41_4
; RV32I-NEXT: bnez a1, .LBB41_4
; RV32I-NEXT: .LBB41_2: # %atomicrmw.start ; RV32I-NEXT: .LBB41_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB41_1 ; RV32I-NEXT: bge s0, a0, .LBB41_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB41_1 ; RV32I-NEXT: j .LBB41_1
; RV32I-NEXT: .LBB41_4: # %atomicrmw.end ; RV32I-NEXT: .LBB41_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acquire: ; RV32IA-LABEL: atomicrmw_min_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB41_3 ; RV32IA-NEXT: bge a1, a3, .LBB41_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1 ; RV32IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB41_1 ; RV32IA-NEXT: bnez a2, .LBB41_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acquire: ; RV64I-LABEL: atomicrmw_min_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB41_2 ; RV64I-NEXT: j .LBB41_2
; RV64I-NEXT: .LBB41_1: # %atomicrmw.start ; RV64I-NEXT: .LBB41_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB41_4
; RV64I-NEXT: bnez a1, .LBB41_4
; RV64I-NEXT: .LBB41_2: # %atomicrmw.start ; RV64I-NEXT: .LBB41_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB41_1 ; RV64I-NEXT: bge s0, a0, .LBB41_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB41_1 ; RV64I-NEXT: j .LBB41_1
; RV64I-NEXT: .LBB41_4: # %atomicrmw.end ; RV64I-NEXT: .LBB41_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-LABEL: atomicrmw_min_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB41_3 ; RV64IA-NEXT: bge a1, a3, .LBB41_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1 ; RV64IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB41_1 ; RV64IA-NEXT: bnez a2, .LBB41_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acquire %1 = atomicrmw min i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_release: ; RV32I-LABEL: atomicrmw_min_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB42_2 ; RV32I-NEXT: j .LBB42_2
; RV32I-NEXT: .LBB42_1: # %atomicrmw.start ; RV32I-NEXT: .LBB42_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB42_4
; RV32I-NEXT: bnez a1, .LBB42_4
; RV32I-NEXT: .LBB42_2: # %atomicrmw.start ; RV32I-NEXT: .LBB42_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB42_1 ; RV32I-NEXT: bge s0, a0, .LBB42_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB42_1 ; RV32I-NEXT: j .LBB42_1
; RV32I-NEXT: .LBB42_4: # %atomicrmw.end ; RV32I-NEXT: .LBB42_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_release: ; RV32IA-LABEL: atomicrmw_min_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB42_3 ; RV32IA-NEXT: bge a1, a3, .LBB42_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1 ; RV32IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB42_1 ; RV32IA-NEXT: bnez a2, .LBB42_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_release: ; RV64I-LABEL: atomicrmw_min_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB42_2 ; RV64I-NEXT: j .LBB42_2
; RV64I-NEXT: .LBB42_1: # %atomicrmw.start ; RV64I-NEXT: .LBB42_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB42_4
; RV64I-NEXT: bnez a1, .LBB42_4
; RV64I-NEXT: .LBB42_2: # %atomicrmw.start ; RV64I-NEXT: .LBB42_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB42_1 ; RV64I-NEXT: bge s0, a0, .LBB42_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB42_1 ; RV64I-NEXT: j .LBB42_1
; RV64I-NEXT: .LBB42_4: # %atomicrmw.end ; RV64I-NEXT: .LBB42_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_release: ; RV64IA-LABEL: atomicrmw_min_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB42_3 ; RV64IA-NEXT: bge a1, a3, .LBB42_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1 ; RV64IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB42_1 ; RV64IA-NEXT: bnez a2, .LBB42_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b release %1 = atomicrmw min i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acq_rel: ; RV32I-LABEL: atomicrmw_min_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB43_2 ; RV32I-NEXT: j .LBB43_2
; RV32I-NEXT: .LBB43_1: # %atomicrmw.start ; RV32I-NEXT: .LBB43_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB43_4
; RV32I-NEXT: bnez a1, .LBB43_4
; RV32I-NEXT: .LBB43_2: # %atomicrmw.start ; RV32I-NEXT: .LBB43_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB43_1 ; RV32I-NEXT: bge s0, a0, .LBB43_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB43_1 ; RV32I-NEXT: j .LBB43_1
; RV32I-NEXT: .LBB43_4: # %atomicrmw.end ; RV32I-NEXT: .LBB43_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB43_3 ; RV32IA-NEXT: bge a1, a3, .LBB43_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 ; RV32IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB43_1 ; RV32IA-NEXT: bnez a2, .LBB43_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acq_rel: ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB43_2 ; RV64I-NEXT: j .LBB43_2
; RV64I-NEXT: .LBB43_1: # %atomicrmw.start ; RV64I-NEXT: .LBB43_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB43_4
; RV64I-NEXT: bnez a1, .LBB43_4
; RV64I-NEXT: .LBB43_2: # %atomicrmw.start ; RV64I-NEXT: .LBB43_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB43_1 ; RV64I-NEXT: bge s0, a0, .LBB43_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB43_1 ; RV64I-NEXT: j .LBB43_1
; RV64I-NEXT: .LBB43_4: # %atomicrmw.end ; RV64I-NEXT: .LBB43_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB43_3 ; RV64IA-NEXT: bge a1, a3, .LBB43_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 ; RV64IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB43_1 ; RV64IA-NEXT: bnez a2, .LBB43_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acq_rel %1 = atomicrmw min i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_seq_cst: ; RV32I-LABEL: atomicrmw_min_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: srai s0, a0, 24
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s3, sp, 11
; RV32I-NEXT: j .LBB44_2 ; RV32I-NEXT: j .LBB44_2
; RV32I-NEXT: .LBB44_1: # %atomicrmw.start ; RV32I-NEXT: .LBB44_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a1, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB44_4
; RV32I-NEXT: bnez a1, .LBB44_4
; RV32I-NEXT: .LBB44_2: # %atomicrmw.start ; RV32I-NEXT: .LBB44_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a1, a1, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB44_1 ; RV32I-NEXT: bge s0, a0, .LBB44_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_4: # %atomicrmw.end ; RV32I-NEXT: .LBB44_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: addi a4, zero, 255 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 24
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a0) ; RV32IA-NEXT: lr.w.aqrl a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB44_3 ; RV32IA-NEXT: bge a1, a3, .LBB44_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 ; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB44_1 ; RV32IA-NEXT: bnez a2, .LBB44_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_seq_cst: ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: srai s0, a0, 56
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s3, sp, 7
; RV64I-NEXT: j .LBB44_2 ; RV64I-NEXT: j .LBB44_2
; RV64I-NEXT: .LBB44_1: # %atomicrmw.start ; RV64I-NEXT: .LBB44_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a1, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB44_4
; RV64I-NEXT: bnez a1, .LBB44_4
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a1, a1, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB44_1 ; RV64I-NEXT: bge s0, a0, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: j .LBB44_1
; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 56 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: addi a4, zero, 255 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 56
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a0) ; RV64IA-NEXT: lr.w.aqrl a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB44_3 ; RV64IA-NEXT: bge a1, a3, .LBB44_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 ; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB44_1 ; RV64IA-NEXT: bnez a2, .LBB44_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b seq_cst %1 = atomicrmw min i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic: ; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB45_2 ; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start ; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: bnez a1, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start ; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a1, .LBB45_1 ; RV32I-NEXT: bltu s1, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB45_1 ; RV32I-NEXT: j .LBB45_1
; RV32I-NEXT: .LBB45_4: # %atomicrmw.end ; RV32I-NEXT: .LBB45_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a3, a1, .LBB45_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB45_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 ; RV32IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB45_1 ; RV32IA-NEXT: bnez a5, .LBB45_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB45_2 ; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start ; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: bnez a1, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB45_1 ; RV64I-NEXT: bltu s1, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB45_1 ; RV64I-NEXT: j .LBB45_1
; RV64I-NEXT: .LBB45_4: # %atomicrmw.end ; RV64I-NEXT: .LBB45_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a3, a1, .LBB45_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB45_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 ; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB45_1 ; RV64IA-NEXT: bnez a5, .LBB45_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b monotonic %1 = atomicrmw umax i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acquire: ; RV32I-LABEL: atomicrmw_umax_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB46_2 ; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start ; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: bnez a1, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start ; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a1, .LBB46_1 ; RV32I-NEXT: bltu s1, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_4: # %atomicrmw.end ; RV32I-NEXT: .LBB46_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acquire: ; RV32IA-LABEL: atomicrmw_umax_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a3, a1, .LBB46_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB46_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 ; RV32IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB46_1 ; RV32IA-NEXT: bnez a5, .LBB46_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acquire: ; RV64I-LABEL: atomicrmw_umax_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB46_2 ; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start ; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: bnez a1, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB46_1 ; RV64I-NEXT: bltu s1, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a3, a1, .LBB46_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB46_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 ; RV64IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB46_1 ; RV64IA-NEXT: bnez a5, .LBB46_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acquire %1 = atomicrmw umax i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_release: ; RV32I-LABEL: atomicrmw_umax_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB47_2 ; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start ; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: bnez a1, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start ; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a1, .LBB47_1 ; RV32I-NEXT: bltu s1, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB47_1 ; RV32I-NEXT: j .LBB47_1
; RV32I-NEXT: .LBB47_4: # %atomicrmw.end ; RV32I-NEXT: .LBB47_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_release: ; RV32IA-LABEL: atomicrmw_umax_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a3, a1, .LBB47_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB47_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 ; RV32IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB47_1 ; RV32IA-NEXT: bnez a5, .LBB47_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_release: ; RV64I-LABEL: atomicrmw_umax_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB47_2 ; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start ; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: bnez a1, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start ; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB47_1 ; RV64I-NEXT: bltu s1, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB47_1 ; RV64I-NEXT: j .LBB47_1
; RV64I-NEXT: .LBB47_4: # %atomicrmw.end ; RV64I-NEXT: .LBB47_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_release: ; RV64IA-LABEL: atomicrmw_umax_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a3, a1, .LBB47_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB47_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 ; RV64IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB47_1 ; RV64IA-NEXT: bnez a5, .LBB47_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b release %1 = atomicrmw umax i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB48_2 ; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start ; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: bnez a1, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start ; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a1, .LBB48_1 ; RV32I-NEXT: bltu s1, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB48_1 ; RV32I-NEXT: j .LBB48_1
; RV32I-NEXT: .LBB48_4: # %atomicrmw.end ; RV32I-NEXT: .LBB48_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a3, a1, .LBB48_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB48_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 ; RV32IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB48_1 ; RV32IA-NEXT: bnez a5, .LBB48_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB48_2 ; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start ; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: bnez a1, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start ; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB48_1 ; RV64I-NEXT: bltu s1, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB48_1 ; RV64I-NEXT: j .LBB48_1
; RV64I-NEXT: .LBB48_4: # %atomicrmw.end ; RV64I-NEXT: .LBB48_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a3, a1, .LBB48_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB48_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 ; RV64IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB48_1 ; RV64IA-NEXT: bnez a5, .LBB48_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acq_rel %1 = atomicrmw umax i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB49_2 ; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start ; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: bnez a1, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start ; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a1, .LBB49_1 ; RV32I-NEXT: bltu s1, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB49_1 ; RV32I-NEXT: j .LBB49_1
; RV32I-NEXT: .LBB49_4: # %atomicrmw.end ; RV32I-NEXT: .LBB49_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a3, a1, .LBB49_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB49_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB49_1 ; RV32IA-NEXT: bnez a5, .LBB49_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB49_2 ; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start ; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: bnez a1, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start ; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB49_1 ; RV64I-NEXT: bltu s1, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB49_1 ; RV64I-NEXT: j .LBB49_1
; RV64I-NEXT: .LBB49_4: # %atomicrmw.end ; RV64I-NEXT: .LBB49_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a3, a1, .LBB49_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB49_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB49_1 ; RV64IA-NEXT: bnez a5, .LBB49_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b seq_cst %1 = atomicrmw umax i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic: ; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB50_2 ; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start ; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: bnez a1, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a1, .LBB50_1 ; RV32I-NEXT: bgeu s1, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a3, .LBB50_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB50_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 ; RV32IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB50_1 ; RV32IA-NEXT: bnez a5, .LBB50_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB50_2 ; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start ; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: bnez a1, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB50_1 ; RV64I-NEXT: bgeu s1, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a3, .LBB50_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB50_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 ; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB50_1 ; RV64IA-NEXT: bnez a5, .LBB50_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b monotonic %1 = atomicrmw umin i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acquire: ; RV32I-LABEL: atomicrmw_umin_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB51_2 ; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start ; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: bnez a1, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a1, .LBB51_1 ; RV32I-NEXT: bgeu s1, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acquire: ; RV32IA-LABEL: atomicrmw_umin_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a3, .LBB51_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB51_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 ; RV32IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB51_1 ; RV32IA-NEXT: bnez a5, .LBB51_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acquire: ; RV64I-LABEL: atomicrmw_umin_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB51_2 ; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start ; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: bnez a1, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB51_1 ; RV64I-NEXT: bgeu s1, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a3, .LBB51_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB51_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 ; RV64IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB51_1 ; RV64IA-NEXT: bnez a5, .LBB51_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acquire %1 = atomicrmw umin i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_release: ; RV32I-LABEL: atomicrmw_umin_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB52_2 ; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start ; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: bnez a1, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a1, .LBB52_1 ; RV32I-NEXT: bgeu s1, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_release: ; RV32IA-LABEL: atomicrmw_umin_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a3, .LBB52_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB52_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 ; RV32IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB52_1 ; RV32IA-NEXT: bnez a5, .LBB52_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_release: ; RV64I-LABEL: atomicrmw_umin_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB52_2 ; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start ; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: bnez a1, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB52_1 ; RV64I-NEXT: bgeu s1, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_release: ; RV64IA-LABEL: atomicrmw_umin_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a3, .LBB52_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB52_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 ; RV64IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB52_1 ; RV64IA-NEXT: bnez a5, .LBB52_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b release %1 = atomicrmw umin i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB53_2 ; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start ; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: bnez a1, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a1, .LBB53_1 ; RV32I-NEXT: bgeu s1, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a3, .LBB53_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB53_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 ; RV32IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB53_1 ; RV32IA-NEXT: bnez a5, .LBB53_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB53_2 ; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start ; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: bnez a1, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB53_1 ; RV64I-NEXT: bgeu s1, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a3, .LBB53_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB53_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 ; RV64IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB53_1 ; RV64IA-NEXT: bnez a5, .LBB53_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acq_rel %1 = atomicrmw umin i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: lbu a0, 0(a0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: andi s0, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB54_2 ; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start ; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: sb a3, 11(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lb a3, 11(sp)
; RV32I-NEXT: lb a0, 11(sp) ; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: bnez a1, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a1, .LBB54_1 ; RV32I-NEXT: bgeu s1, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4
; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a4, (a6)
; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: and a2, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a3, .LBB54_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB54_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB54_1 ; RV32IA-NEXT: bnez a5, .LBB54_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: lbu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: andi s0, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB54_2 ; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start ; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: sb a3, 7(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lb a3, 7(sp)
; RV64I-NEXT: lb a0, 7(sp) ; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: bnez a1, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a1, a0, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB54_1 ; RV64I-NEXT: bgeu s1, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4
; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a4, (a6)
; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: and a2, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a3, .LBB54_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB54_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB54_1 ; RV64IA-NEXT: bnez a5, .LBB54_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b seq_cst %1 = atomicrmw umin i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB55_1 ; RV32IA-NEXT: bnez a5, .LBB55_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB55_1 ; RV64IA-NEXT: bnez a5, .LBB55_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b monotonic %1 = atomicrmw xchg i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_acquire: ; RV32I-LABEL: atomicrmw_xchg_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB56_1 ; RV32IA-NEXT: bnez a5, .LBB56_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_acquire: ; RV64I-LABEL: atomicrmw_xchg_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB56_1 ; RV64IA-NEXT: bnez a5, .LBB56_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b acquire %1 = atomicrmw xchg i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_release: ; RV32I-LABEL: atomicrmw_xchg_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_release: ; RV32IA-LABEL: atomicrmw_xchg_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB57_1 ; RV32IA-NEXT: bnez a5, .LBB57_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_release: ; RV64I-LABEL: atomicrmw_xchg_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_release: ; RV64IA-LABEL: atomicrmw_xchg_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB57_1 ; RV64IA-NEXT: bnez a5, .LBB57_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b release %1 = atomicrmw xchg i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB58_1 ; RV32IA-NEXT: bnez a5, .LBB58_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB58_1 ; RV64IA-NEXT: bnez a5, .LBB58_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b acq_rel %1 = atomicrmw xchg i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: add a5, zero, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB59_1 ; RV32IA-NEXT: bnez a5, .LBB59_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: add a5, zero, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB59_1 ; RV64IA-NEXT: bnez a5, .LBB59_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b seq_cst %1 = atomicrmw xchg i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_monotonic: ; RV32I-LABEL: atomicrmw_add_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_monotonic: ; RV32IA-LABEL: atomicrmw_add_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB60_1 ; RV32IA-NEXT: bnez a5, .LBB60_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_monotonic: ; RV64I-LABEL: atomicrmw_add_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB60_1 ; RV64IA-NEXT: bnez a5, .LBB60_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b monotonic %1 = atomicrmw add i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_acquire: ; RV32I-LABEL: atomicrmw_add_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_acquire: ; RV32IA-LABEL: atomicrmw_add_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB61_1 ; RV32IA-NEXT: bnez a5, .LBB61_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_acquire: ; RV64I-LABEL: atomicrmw_add_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_acquire: ; RV64IA-LABEL: atomicrmw_add_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB61_1 ; RV64IA-NEXT: bnez a5, .LBB61_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b acquire %1 = atomicrmw add i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_release: ; RV32I-LABEL: atomicrmw_add_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_release: ; RV32IA-LABEL: atomicrmw_add_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB62_1 ; RV32IA-NEXT: bnez a5, .LBB62_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_release: ; RV64I-LABEL: atomicrmw_add_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_release: ; RV64IA-LABEL: atomicrmw_add_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB62_1 ; RV64IA-NEXT: bnez a5, .LBB62_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b release %1 = atomicrmw add i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_acq_rel: ; RV32I-LABEL: atomicrmw_add_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB63_1 ; RV32IA-NEXT: bnez a5, .LBB63_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_acq_rel: ; RV64I-LABEL: atomicrmw_add_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB63_1 ; RV64IA-NEXT: bnez a5, .LBB63_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b acq_rel %1 = atomicrmw add i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_seq_cst: ; RV32I-LABEL: atomicrmw_add_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB64_1 ; RV32IA-NEXT: bnez a5, .LBB64_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_seq_cst: ; RV64I-LABEL: atomicrmw_add_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB64_1 ; RV64IA-NEXT: bnez a5, .LBB64_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b seq_cst %1 = atomicrmw add i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_monotonic: ; RV32I-LABEL: atomicrmw_sub_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB65_1 ; RV32IA-NEXT: bnez a5, .LBB65_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_monotonic: ; RV64I-LABEL: atomicrmw_sub_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB65_1 ; RV64IA-NEXT: bnez a5, .LBB65_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b monotonic %1 = atomicrmw sub i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_acquire: ; RV32I-LABEL: atomicrmw_sub_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_acquire: ; RV32IA-LABEL: atomicrmw_sub_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB66_1 ; RV32IA-NEXT: bnez a5, .LBB66_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_acquire: ; RV64I-LABEL: atomicrmw_sub_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA-LABEL: atomicrmw_sub_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB66_1 ; RV64IA-NEXT: bnez a5, .LBB66_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b acquire %1 = atomicrmw sub i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_release: ; RV32I-LABEL: atomicrmw_sub_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_release: ; RV32IA-LABEL: atomicrmw_sub_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB67_1 ; RV32IA-NEXT: bnez a5, .LBB67_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_release: ; RV64I-LABEL: atomicrmw_sub_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_release: ; RV64IA-LABEL: atomicrmw_sub_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB67_1 ; RV64IA-NEXT: bnez a5, .LBB67_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b release %1 = atomicrmw sub i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB68_1 ; RV32IA-NEXT: bnez a5, .LBB68_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB68_1 ; RV64IA-NEXT: bnez a5, .LBB68_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b acq_rel %1 = atomicrmw sub i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a3, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB69_1 ; RV32IA-NEXT: bnez a5, .LBB69_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a3, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB69_1 ; RV64IA-NEXT: bnez a5, .LBB69_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b seq_cst %1 = atomicrmw sub i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_monotonic: ; RV32I-LABEL: atomicrmw_and_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_monotonic: ; RV32IA-LABEL: atomicrmw_and_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: not a2, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: or a1, a2, a1 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w a0, a1, (a0) ; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_monotonic: ; RV64I-LABEL: atomicrmw_and_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: not a2, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: or a1, a2, a1 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: or a1, a4, a1
; RV64IA-NEXT: amoand.w a0, a1, (a0) ; RV64IA-NEXT: amoand.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b monotonic %1 = atomicrmw and i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_acquire: ; RV32I-LABEL: atomicrmw_and_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_acquire: ; RV32IA-LABEL: atomicrmw_and_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: not a2, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: or a1, a2, a1 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_acquire: ; RV64I-LABEL: atomicrmw_and_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_acquire: ; RV64IA-LABEL: atomicrmw_and_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: not a2, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: or a1, a2, a1 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: or a1, a4, a1
; RV64IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b acquire %1 = atomicrmw and i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_release: ; RV32I-LABEL: atomicrmw_and_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_release: ; RV32IA-LABEL: atomicrmw_and_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: not a2, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: or a1, a2, a1 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_release: ; RV64I-LABEL: atomicrmw_and_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_release: ; RV64IA-LABEL: atomicrmw_and_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: not a2, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: or a1, a2, a1 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: or a1, a4, a1
; RV64IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b release %1 = atomicrmw and i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_acq_rel: ; RV32I-LABEL: atomicrmw_and_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: not a2, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: or a1, a2, a1 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_acq_rel: ; RV64I-LABEL: atomicrmw_and_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: not a2, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: or a1, a2, a1 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: or a1, a4, a1
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b acq_rel %1 = atomicrmw and i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_seq_cst: ; RV32I-LABEL: atomicrmw_and_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: not a2, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: or a1, a2, a1 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_seq_cst: ; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: not a2, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: or a1, a2, a1 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: or a1, a4, a1
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b seq_cst %1 = atomicrmw and i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_monotonic: ; RV32I-LABEL: atomicrmw_nand_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a3, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB75_1 ; RV32IA-NEXT: bnez a5, .LBB75_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_monotonic: ; RV64I-LABEL: atomicrmw_nand_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a3, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB75_1 ; RV64IA-NEXT: bnez a5, .LBB75_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b monotonic %1 = atomicrmw nand i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_acquire: ; RV32I-LABEL: atomicrmw_nand_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_acquire: ; RV32IA-LABEL: atomicrmw_nand_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a3, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB76_1 ; RV32IA-NEXT: bnez a5, .LBB76_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_acquire: ; RV64I-LABEL: atomicrmw_nand_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-LABEL: atomicrmw_nand_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a3, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB76_1 ; RV64IA-NEXT: bnez a5, .LBB76_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b acquire %1 = atomicrmw nand i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_release: ; RV32I-LABEL: atomicrmw_nand_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_release: ; RV32IA-LABEL: atomicrmw_nand_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a3, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB77_1 ; RV32IA-NEXT: bnez a5, .LBB77_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_release: ; RV64I-LABEL: atomicrmw_nand_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_release: ; RV64IA-LABEL: atomicrmw_nand_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a3, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB77_1 ; RV64IA-NEXT: bnez a5, .LBB77_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b release %1 = atomicrmw nand i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a3, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB78_1 ; RV32IA-NEXT: bnez a5, .LBB78_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a3, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB78_1 ; RV64IA-NEXT: bnez a5, .LBB78_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b acq_rel %1 = atomicrmw nand i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a2, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a3, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a2 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB79_1 ; RV32IA-NEXT: bnez a5, .LBB79_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a2, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a3, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a2 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB79_1 ; RV64IA-NEXT: bnez a5, .LBB79_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b seq_cst %1 = atomicrmw nand i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_monotonic: ; RV32I-LABEL: atomicrmw_or_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_monotonic: ; RV32IA-LABEL: atomicrmw_or_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a0, a1, (a0) ; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_monotonic: ; RV64I-LABEL: atomicrmw_or_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a0, a1, (a0) ; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b monotonic %1 = atomicrmw or i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_acquire: ; RV32I-LABEL: atomicrmw_or_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_acquire: ; RV32IA-LABEL: atomicrmw_or_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_acquire: ; RV64I-LABEL: atomicrmw_or_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_acquire: ; RV64IA-LABEL: atomicrmw_or_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b acquire %1 = atomicrmw or i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_release: ; RV32I-LABEL: atomicrmw_or_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_release: ; RV32IA-LABEL: atomicrmw_or_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_release: ; RV64I-LABEL: atomicrmw_or_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_release: ; RV64IA-LABEL: atomicrmw_or_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b release %1 = atomicrmw or i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_acq_rel: ; RV32I-LABEL: atomicrmw_or_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_acq_rel: ; RV64I-LABEL: atomicrmw_or_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b acq_rel %1 = atomicrmw or i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_seq_cst: ; RV32I-LABEL: atomicrmw_or_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_seq_cst: ; RV64I-LABEL: atomicrmw_or_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b seq_cst %1 = atomicrmw or i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_monotonic: ; RV32I-LABEL: atomicrmw_xor_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a0, a1, (a0) ; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_monotonic: ; RV64I-LABEL: atomicrmw_xor_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a0, a1, (a0) ; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b monotonic %1 = atomicrmw xor i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_acquire: ; RV32I-LABEL: atomicrmw_xor_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_acquire: ; RV32IA-LABEL: atomicrmw_xor_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_acquire: ; RV64I-LABEL: atomicrmw_xor_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA-LABEL: atomicrmw_xor_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b acquire %1 = atomicrmw xor i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_release: ; RV32I-LABEL: atomicrmw_xor_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_release: ; RV32IA-LABEL: atomicrmw_xor_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_release: ; RV64I-LABEL: atomicrmw_xor_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_release: ; RV64IA-LABEL: atomicrmw_xor_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b release %1 = atomicrmw xor i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b acq_rel %1 = atomicrmw xor i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b seq_cst %1 = atomicrmw xor i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_monotonic: ; RV32I-LABEL: atomicrmw_max_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB90_2 ; RV32I-NEXT: j .LBB90_2
; RV32I-NEXT: .LBB90_1: # %atomicrmw.start ; RV32I-NEXT: .LBB90_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB90_4
; RV32I-NEXT: bnez a1, .LBB90_4
; RV32I-NEXT: .LBB90_2: # %atomicrmw.start ; RV32I-NEXT: .LBB90_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB90_1 ; RV32I-NEXT: blt s0, a0, .LBB90_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB90_1 ; RV32I-NEXT: j .LBB90_1
; RV32I-NEXT: .LBB90_4: # %atomicrmw.end ; RV32I-NEXT: .LBB90_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA-LABEL: atomicrmw_max_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB90_3 ; RV32IA-NEXT: bge a3, a1, .LBB90_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1 ; RV32IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB90_1 ; RV32IA-NEXT: bnez a2, .LBB90_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB90_2 ; RV64I-NEXT: j .LBB90_2
; RV64I-NEXT: .LBB90_1: # %atomicrmw.start ; RV64I-NEXT: .LBB90_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB90_4
; RV64I-NEXT: bnez a1, .LBB90_4
; RV64I-NEXT: .LBB90_2: # %atomicrmw.start ; RV64I-NEXT: .LBB90_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB90_1 ; RV64I-NEXT: blt s0, a0, .LBB90_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB90_1 ; RV64I-NEXT: j .LBB90_1
; RV64I-NEXT: .LBB90_4: # %atomicrmw.end ; RV64I-NEXT: .LBB90_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB90_3 ; RV64IA-NEXT: bge a3, a1, .LBB90_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1 ; RV64IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB90_1 ; RV64IA-NEXT: bnez a2, .LBB90_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b monotonic %1 = atomicrmw max i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acquire: ; RV32I-LABEL: atomicrmw_max_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB91_2 ; RV32I-NEXT: j .LBB91_2
; RV32I-NEXT: .LBB91_1: # %atomicrmw.start ; RV32I-NEXT: .LBB91_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB91_4
; RV32I-NEXT: bnez a1, .LBB91_4
; RV32I-NEXT: .LBB91_2: # %atomicrmw.start ; RV32I-NEXT: .LBB91_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB91_1 ; RV32I-NEXT: blt s0, a0, .LBB91_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB91_1 ; RV32I-NEXT: j .LBB91_1
; RV32I-NEXT: .LBB91_4: # %atomicrmw.end ; RV32I-NEXT: .LBB91_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acquire: ; RV32IA-LABEL: atomicrmw_max_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB91_3 ; RV32IA-NEXT: bge a3, a1, .LBB91_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1 ; RV32IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB91_1 ; RV32IA-NEXT: bnez a2, .LBB91_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acquire: ; RV64I-LABEL: atomicrmw_max_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB91_2 ; RV64I-NEXT: j .LBB91_2
; RV64I-NEXT: .LBB91_1: # %atomicrmw.start ; RV64I-NEXT: .LBB91_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB91_4
; RV64I-NEXT: bnez a1, .LBB91_4
; RV64I-NEXT: .LBB91_2: # %atomicrmw.start ; RV64I-NEXT: .LBB91_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB91_1 ; RV64I-NEXT: blt s0, a0, .LBB91_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB91_1 ; RV64I-NEXT: j .LBB91_1
; RV64I-NEXT: .LBB91_4: # %atomicrmw.end ; RV64I-NEXT: .LBB91_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-LABEL: atomicrmw_max_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB91_3 ; RV64IA-NEXT: bge a3, a1, .LBB91_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1 ; RV64IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB91_1 ; RV64IA-NEXT: bnez a2, .LBB91_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acquire %1 = atomicrmw max i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_release: ; RV32I-LABEL: atomicrmw_max_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB92_2 ; RV32I-NEXT: j .LBB92_2
; RV32I-NEXT: .LBB92_1: # %atomicrmw.start ; RV32I-NEXT: .LBB92_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB92_4
; RV32I-NEXT: bnez a1, .LBB92_4
; RV32I-NEXT: .LBB92_2: # %atomicrmw.start ; RV32I-NEXT: .LBB92_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB92_1 ; RV32I-NEXT: blt s0, a0, .LBB92_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB92_1 ; RV32I-NEXT: j .LBB92_1
; RV32I-NEXT: .LBB92_4: # %atomicrmw.end ; RV32I-NEXT: .LBB92_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_release: ; RV32IA-LABEL: atomicrmw_max_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB92_3 ; RV32IA-NEXT: bge a3, a1, .LBB92_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1 ; RV32IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB92_1 ; RV32IA-NEXT: bnez a2, .LBB92_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_release: ; RV64I-LABEL: atomicrmw_max_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB92_2 ; RV64I-NEXT: j .LBB92_2
; RV64I-NEXT: .LBB92_1: # %atomicrmw.start ; RV64I-NEXT: .LBB92_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB92_4
; RV64I-NEXT: bnez a1, .LBB92_4
; RV64I-NEXT: .LBB92_2: # %atomicrmw.start ; RV64I-NEXT: .LBB92_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB92_1 ; RV64I-NEXT: blt s0, a0, .LBB92_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB92_1 ; RV64I-NEXT: j .LBB92_1
; RV64I-NEXT: .LBB92_4: # %atomicrmw.end ; RV64I-NEXT: .LBB92_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_release: ; RV64IA-LABEL: atomicrmw_max_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB92_3 ; RV64IA-NEXT: bge a3, a1, .LBB92_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1 ; RV64IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB92_1 ; RV64IA-NEXT: bnez a2, .LBB92_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b release %1 = atomicrmw max i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acq_rel: ; RV32I-LABEL: atomicrmw_max_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB93_2 ; RV32I-NEXT: j .LBB93_2
; RV32I-NEXT: .LBB93_1: # %atomicrmw.start ; RV32I-NEXT: .LBB93_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB93_4
; RV32I-NEXT: bnez a1, .LBB93_4
; RV32I-NEXT: .LBB93_2: # %atomicrmw.start ; RV32I-NEXT: .LBB93_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB93_1 ; RV32I-NEXT: blt s0, a0, .LBB93_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB93_1 ; RV32I-NEXT: j .LBB93_1
; RV32I-NEXT: .LBB93_4: # %atomicrmw.end ; RV32I-NEXT: .LBB93_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB93_3 ; RV32IA-NEXT: bge a3, a1, .LBB93_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1 ; RV32IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB93_1 ; RV32IA-NEXT: bnez a2, .LBB93_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acq_rel: ; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB93_2 ; RV64I-NEXT: j .LBB93_2
; RV64I-NEXT: .LBB93_1: # %atomicrmw.start ; RV64I-NEXT: .LBB93_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB93_4
; RV64I-NEXT: bnez a1, .LBB93_4
; RV64I-NEXT: .LBB93_2: # %atomicrmw.start ; RV64I-NEXT: .LBB93_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB93_1 ; RV64I-NEXT: blt s0, a0, .LBB93_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB93_1 ; RV64I-NEXT: j .LBB93_1
; RV64I-NEXT: .LBB93_4: # %atomicrmw.end ; RV64I-NEXT: .LBB93_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB93_3 ; RV64IA-NEXT: bge a3, a1, .LBB93_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1 ; RV64IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB93_1 ; RV64IA-NEXT: bnez a2, .LBB93_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acq_rel %1 = atomicrmw max i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_seq_cst: ; RV32I-LABEL: atomicrmw_max_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB94_2 ; RV32I-NEXT: j .LBB94_2
; RV32I-NEXT: .LBB94_1: # %atomicrmw.start ; RV32I-NEXT: .LBB94_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB94_4
; RV32I-NEXT: bnez a1, .LBB94_4
; RV32I-NEXT: .LBB94_2: # %atomicrmw.start ; RV32I-NEXT: .LBB94_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: blt s0, a1, .LBB94_1 ; RV32I-NEXT: blt s0, a0, .LBB94_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB94_1 ; RV32I-NEXT: j .LBB94_1
; RV32I-NEXT: .LBB94_4: # %atomicrmw.end ; RV32I-NEXT: .LBB94_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a0) ; RV32IA-NEXT: lr.w.aqrl a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a4, a1, .LBB94_3 ; RV32IA-NEXT: bge a3, a1, .LBB94_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 ; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB94_1 ; RV32IA-NEXT: bnez a2, .LBB94_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_seq_cst: ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB94_2 ; RV64I-NEXT: j .LBB94_2
; RV64I-NEXT: .LBB94_1: # %atomicrmw.start ; RV64I-NEXT: .LBB94_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB94_4
; RV64I-NEXT: bnez a1, .LBB94_4
; RV64I-NEXT: .LBB94_2: # %atomicrmw.start ; RV64I-NEXT: .LBB94_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: blt s0, a1, .LBB94_1 ; RV64I-NEXT: blt s0, a0, .LBB94_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB94_1 ; RV64I-NEXT: j .LBB94_1
; RV64I-NEXT: .LBB94_4: # %atomicrmw.end ; RV64I-NEXT: .LBB94_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a0) ; RV64IA-NEXT: lr.w.aqrl a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a4, a1, .LBB94_3 ; RV64IA-NEXT: bge a3, a1, .LBB94_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 ; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB94_1 ; RV64IA-NEXT: bnez a2, .LBB94_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b seq_cst %1 = atomicrmw max i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic: ; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB95_2 ; RV32I-NEXT: j .LBB95_2
; RV32I-NEXT: .LBB95_1: # %atomicrmw.start ; RV32I-NEXT: .LBB95_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB95_4
; RV32I-NEXT: bnez a1, .LBB95_4
; RV32I-NEXT: .LBB95_2: # %atomicrmw.start ; RV32I-NEXT: .LBB95_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB95_1 ; RV32I-NEXT: bge s0, a0, .LBB95_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB95_1 ; RV32I-NEXT: j .LBB95_1
; RV32I-NEXT: .LBB95_4: # %atomicrmw.end ; RV32I-NEXT: .LBB95_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA-LABEL: atomicrmw_min_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB95_3 ; RV32IA-NEXT: bge a1, a3, .LBB95_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1 ; RV32IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB95_1 ; RV32IA-NEXT: bnez a2, .LBB95_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB95_2 ; RV64I-NEXT: j .LBB95_2
; RV64I-NEXT: .LBB95_1: # %atomicrmw.start ; RV64I-NEXT: .LBB95_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB95_4
; RV64I-NEXT: bnez a1, .LBB95_4
; RV64I-NEXT: .LBB95_2: # %atomicrmw.start ; RV64I-NEXT: .LBB95_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB95_1 ; RV64I-NEXT: bge s0, a0, .LBB95_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB95_1 ; RV64I-NEXT: j .LBB95_1
; RV64I-NEXT: .LBB95_4: # %atomicrmw.end ; RV64I-NEXT: .LBB95_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB95_3 ; RV64IA-NEXT: bge a1, a3, .LBB95_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1 ; RV64IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB95_1 ; RV64IA-NEXT: bnez a2, .LBB95_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b monotonic %1 = atomicrmw min i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acquire: ; RV32I-LABEL: atomicrmw_min_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB96_2 ; RV32I-NEXT: j .LBB96_2
; RV32I-NEXT: .LBB96_1: # %atomicrmw.start ; RV32I-NEXT: .LBB96_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB96_4
; RV32I-NEXT: bnez a1, .LBB96_4
; RV32I-NEXT: .LBB96_2: # %atomicrmw.start ; RV32I-NEXT: .LBB96_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB96_1 ; RV32I-NEXT: bge s0, a0, .LBB96_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB96_1 ; RV32I-NEXT: j .LBB96_1
; RV32I-NEXT: .LBB96_4: # %atomicrmw.end ; RV32I-NEXT: .LBB96_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acquire: ; RV32IA-LABEL: atomicrmw_min_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB96_3 ; RV32IA-NEXT: bge a1, a3, .LBB96_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1 ; RV32IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB96_1 ; RV32IA-NEXT: bnez a2, .LBB96_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acquire: ; RV64I-LABEL: atomicrmw_min_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB96_2 ; RV64I-NEXT: j .LBB96_2
; RV64I-NEXT: .LBB96_1: # %atomicrmw.start ; RV64I-NEXT: .LBB96_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB96_4
; RV64I-NEXT: bnez a1, .LBB96_4
; RV64I-NEXT: .LBB96_2: # %atomicrmw.start ; RV64I-NEXT: .LBB96_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB96_1 ; RV64I-NEXT: bge s0, a0, .LBB96_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB96_1 ; RV64I-NEXT: j .LBB96_1
; RV64I-NEXT: .LBB96_4: # %atomicrmw.end ; RV64I-NEXT: .LBB96_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-LABEL: atomicrmw_min_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB96_3 ; RV64IA-NEXT: bge a1, a3, .LBB96_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1 ; RV64IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB96_1 ; RV64IA-NEXT: bnez a2, .LBB96_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acquire %1 = atomicrmw min i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_release: ; RV32I-LABEL: atomicrmw_min_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB97_2 ; RV32I-NEXT: j .LBB97_2
; RV32I-NEXT: .LBB97_1: # %atomicrmw.start ; RV32I-NEXT: .LBB97_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB97_4
; RV32I-NEXT: bnez a1, .LBB97_4
; RV32I-NEXT: .LBB97_2: # %atomicrmw.start ; RV32I-NEXT: .LBB97_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB97_1 ; RV32I-NEXT: bge s0, a0, .LBB97_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB97_1 ; RV32I-NEXT: j .LBB97_1
; RV32I-NEXT: .LBB97_4: # %atomicrmw.end ; RV32I-NEXT: .LBB97_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_release: ; RV32IA-LABEL: atomicrmw_min_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a0) ; RV32IA-NEXT: lr.w a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB97_3 ; RV32IA-NEXT: bge a1, a3, .LBB97_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1 ; RV32IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB97_1 ; RV32IA-NEXT: bnez a2, .LBB97_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_release: ; RV64I-LABEL: atomicrmw_min_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB97_2 ; RV64I-NEXT: j .LBB97_2
; RV64I-NEXT: .LBB97_1: # %atomicrmw.start ; RV64I-NEXT: .LBB97_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB97_4
; RV64I-NEXT: bnez a1, .LBB97_4
; RV64I-NEXT: .LBB97_2: # %atomicrmw.start ; RV64I-NEXT: .LBB97_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB97_1 ; RV64I-NEXT: bge s0, a0, .LBB97_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB97_1 ; RV64I-NEXT: j .LBB97_1
; RV64I-NEXT: .LBB97_4: # %atomicrmw.end ; RV64I-NEXT: .LBB97_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_release: ; RV64IA-LABEL: atomicrmw_min_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a0) ; RV64IA-NEXT: lr.w a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB97_3 ; RV64IA-NEXT: bge a1, a3, .LBB97_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1 ; RV64IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB97_1 ; RV64IA-NEXT: bnez a2, .LBB97_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b release %1 = atomicrmw min i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acq_rel: ; RV32I-LABEL: atomicrmw_min_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB98_2 ; RV32I-NEXT: j .LBB98_2
; RV32I-NEXT: .LBB98_1: # %atomicrmw.start ; RV32I-NEXT: .LBB98_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB98_4
; RV32I-NEXT: bnez a1, .LBB98_4
; RV32I-NEXT: .LBB98_2: # %atomicrmw.start ; RV32I-NEXT: .LBB98_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB98_1 ; RV32I-NEXT: bge s0, a0, .LBB98_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB98_1 ; RV32I-NEXT: j .LBB98_1
; RV32I-NEXT: .LBB98_4: # %atomicrmw.end ; RV32I-NEXT: .LBB98_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a0) ; RV32IA-NEXT: lr.w.aq a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB98_3 ; RV32IA-NEXT: bge a1, a3, .LBB98_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1 ; RV32IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB98_1 ; RV32IA-NEXT: bnez a2, .LBB98_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acq_rel: ; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB98_2 ; RV64I-NEXT: j .LBB98_2
; RV64I-NEXT: .LBB98_1: # %atomicrmw.start ; RV64I-NEXT: .LBB98_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB98_4
; RV64I-NEXT: bnez a1, .LBB98_4
; RV64I-NEXT: .LBB98_2: # %atomicrmw.start ; RV64I-NEXT: .LBB98_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB98_1 ; RV64I-NEXT: bge s0, a0, .LBB98_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB98_1 ; RV64I-NEXT: j .LBB98_1
; RV64I-NEXT: .LBB98_4: # %atomicrmw.end ; RV64I-NEXT: .LBB98_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a0) ; RV64IA-NEXT: lr.w.aq a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB98_3 ; RV64IA-NEXT: bge a1, a3, .LBB98_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1 ; RV64IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB98_1 ; RV64IA-NEXT: bnez a2, .LBB98_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acq_rel %1 = atomicrmw min i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_seq_cst: ; RV32I-LABEL: atomicrmw_min_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: srai s0, a0, 16
; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: addi s3, sp, 10
; RV32I-NEXT: j .LBB99_2 ; RV32I-NEXT: j .LBB99_2
; RV32I-NEXT: .LBB99_1: # %atomicrmw.start ; RV32I-NEXT: .LBB99_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: lh a0, 10(sp) ; RV32I-NEXT: bnez a0, .LBB99_4
; RV32I-NEXT: bnez a1, .LBB99_4
; RV32I-NEXT: .LBB99_2: # %atomicrmw.start ; RV32I-NEXT: .LBB99_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bge s0, a1, .LBB99_1 ; RV32I-NEXT: bge s0, a0, .LBB99_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB99_1 ; RV32I-NEXT: j .LBB99_1
; RV32I-NEXT: .LBB99_4: # %atomicrmw.end ; RV32I-NEXT: .LBB99_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: slli a2, a0, 3 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: addi a3, zero, 16 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: sub a6, a3, a2 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: sll a7, a3, a0
; RV32IA-NEXT: sll a7, a4, a2
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: addi a4, zero, 16
; RV32IA-NEXT: sub a4, a4, a0
; RV32IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a0) ; RV32IA-NEXT: lr.w.aqrl a5, (a6)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a3, a5, a7
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a2, a5
; RV32IA-NEXT: sll a4, a4, a6 ; RV32IA-NEXT: sll a3, a3, a4
; RV32IA-NEXT: sra a4, a4, a6 ; RV32IA-NEXT: sra a3, a3, a4
; RV32IA-NEXT: bge a1, a4, .LBB99_3 ; RV32IA-NEXT: bge a1, a3, .LBB99_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV32IA-NEXT: xor a3, a5, a1 ; RV32IA-NEXT: xor a2, a5, a1
; RV32IA-NEXT: and a3, a3, a7 ; RV32IA-NEXT: and a2, a2, a7
; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: xor a2, a5, a2
; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 ; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV32IA-NEXT: bnez a3, .LBB99_1 ; RV32IA-NEXT: bnez a2, .LBB99_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_seq_cst: ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: srai s0, a0, 48
; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: addi s3, sp, 6
; RV64I-NEXT: j .LBB99_2 ; RV64I-NEXT: j .LBB99_2
; RV64I-NEXT: .LBB99_1: # %atomicrmw.start ; RV64I-NEXT: .LBB99_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: lh a0, 6(sp) ; RV64I-NEXT: bnez a0, .LBB99_4
; RV64I-NEXT: bnez a1, .LBB99_4
; RV64I-NEXT: .LBB99_2: # %atomicrmw.start ; RV64I-NEXT: .LBB99_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a1, a1, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bge s0, a1, .LBB99_1 ; RV64I-NEXT: bge s0, a0, .LBB99_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB99_1 ; RV64I-NEXT: j .LBB99_1
; RV64I-NEXT: .LBB99_4: # %atomicrmw.end ; RV64I-NEXT: .LBB99_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: slli a2, a0, 3 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 48 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sub a6, a3, a2 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: sllw a7, a3, a0
; RV64IA-NEXT: sllw a7, a4, a2
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: addi a4, zero, 48
; RV64IA-NEXT: sub a4, a4, a0
; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a0) ; RV64IA-NEXT: lr.w.aqrl a5, (a6)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a3, a5, a7
; RV64IA-NEXT: mv a3, a5 ; RV64IA-NEXT: mv a2, a5
; RV64IA-NEXT: sll a4, a4, a6 ; RV64IA-NEXT: sll a3, a3, a4
; RV64IA-NEXT: sra a4, a4, a6 ; RV64IA-NEXT: sra a3, a3, a4
; RV64IA-NEXT: bge a1, a4, .LBB99_3 ; RV64IA-NEXT: bge a1, a3, .LBB99_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: xor a3, a5, a1 ; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a3, a3, a7 ; RV64IA-NEXT: and a2, a2, a7
; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: xor a2, a5, a2
; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 ; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6)
; RV64IA-NEXT: bnez a3, .LBB99_1 ; RV64IA-NEXT: bnez a2, .LBB99_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b seq_cst %1 = atomicrmw min i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_monotonic: ; RV32I-LABEL: atomicrmw_umax_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB100_2 ; RV32I-NEXT: j .LBB100_2
; RV32I-NEXT: .LBB100_1: # %atomicrmw.start ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB100_4
; RV32I-NEXT: bnez a1, .LBB100_4
; RV32I-NEXT: .LBB100_2: # %atomicrmw.start ; RV32I-NEXT: .LBB100_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a1, .LBB100_1 ; RV32I-NEXT: bltu s1, a0, .LBB100_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB100_1 ; RV32I-NEXT: j .LBB100_1
; RV32I-NEXT: .LBB100_4: # %atomicrmw.end ; RV32I-NEXT: .LBB100_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB100_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB100_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1 ; RV32IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB100_1 ; RV32IA-NEXT: bnez a5, .LBB100_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB100_2 ; RV64I-NEXT: j .LBB100_2
; RV64I-NEXT: .LBB100_1: # %atomicrmw.start ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB100_4
; RV64I-NEXT: bnez a1, .LBB100_4
; RV64I-NEXT: .LBB100_2: # %atomicrmw.start ; RV64I-NEXT: .LBB100_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a1, .LBB100_1 ; RV64I-NEXT: bltu s1, a0, .LBB100_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB100_1 ; RV64I-NEXT: j .LBB100_1
; RV64I-NEXT: .LBB100_4: # %atomicrmw.end ; RV64I-NEXT: .LBB100_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB100_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB100_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1 ; RV64IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB100_1 ; RV64IA-NEXT: bnez a5, .LBB100_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b monotonic %1 = atomicrmw umax i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acquire: ; RV32I-LABEL: atomicrmw_umax_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB101_2 ; RV32I-NEXT: j .LBB101_2
; RV32I-NEXT: .LBB101_1: # %atomicrmw.start ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB101_4
; RV32I-NEXT: bnez a1, .LBB101_4
; RV32I-NEXT: .LBB101_2: # %atomicrmw.start ; RV32I-NEXT: .LBB101_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a1, .LBB101_1 ; RV32I-NEXT: bltu s1, a0, .LBB101_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB101_1 ; RV32I-NEXT: j .LBB101_1
; RV32I-NEXT: .LBB101_4: # %atomicrmw.end ; RV32I-NEXT: .LBB101_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acquire: ; RV32IA-LABEL: atomicrmw_umax_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB101_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB101_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1 ; RV32IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB101_1 ; RV32IA-NEXT: bnez a5, .LBB101_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acquire: ; RV64I-LABEL: atomicrmw_umax_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB101_2 ; RV64I-NEXT: j .LBB101_2
; RV64I-NEXT: .LBB101_1: # %atomicrmw.start ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB101_4
; RV64I-NEXT: bnez a1, .LBB101_4
; RV64I-NEXT: .LBB101_2: # %atomicrmw.start ; RV64I-NEXT: .LBB101_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a1, .LBB101_1 ; RV64I-NEXT: bltu s1, a0, .LBB101_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB101_1 ; RV64I-NEXT: j .LBB101_1
; RV64I-NEXT: .LBB101_4: # %atomicrmw.end ; RV64I-NEXT: .LBB101_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB101_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB101_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1 ; RV64IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB101_1 ; RV64IA-NEXT: bnez a5, .LBB101_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acquire %1 = atomicrmw umax i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_release: ; RV32I-LABEL: atomicrmw_umax_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB102_2 ; RV32I-NEXT: j .LBB102_2
; RV32I-NEXT: .LBB102_1: # %atomicrmw.start ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB102_4
; RV32I-NEXT: bnez a1, .LBB102_4
; RV32I-NEXT: .LBB102_2: # %atomicrmw.start ; RV32I-NEXT: .LBB102_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a1, .LBB102_1 ; RV32I-NEXT: bltu s1, a0, .LBB102_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB102_1 ; RV32I-NEXT: j .LBB102_1
; RV32I-NEXT: .LBB102_4: # %atomicrmw.end ; RV32I-NEXT: .LBB102_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_release: ; RV32IA-LABEL: atomicrmw_umax_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB102_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB102_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1 ; RV32IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB102_1 ; RV32IA-NEXT: bnez a5, .LBB102_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_release: ; RV64I-LABEL: atomicrmw_umax_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB102_2 ; RV64I-NEXT: j .LBB102_2
; RV64I-NEXT: .LBB102_1: # %atomicrmw.start ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB102_4
; RV64I-NEXT: bnez a1, .LBB102_4
; RV64I-NEXT: .LBB102_2: # %atomicrmw.start ; RV64I-NEXT: .LBB102_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a1, .LBB102_1 ; RV64I-NEXT: bltu s1, a0, .LBB102_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB102_1 ; RV64I-NEXT: j .LBB102_1
; RV64I-NEXT: .LBB102_4: # %atomicrmw.end ; RV64I-NEXT: .LBB102_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_release: ; RV64IA-LABEL: atomicrmw_umax_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB102_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB102_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1 ; RV64IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB102_1 ; RV64IA-NEXT: bnez a5, .LBB102_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b release %1 = atomicrmw umax i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB103_2 ; RV32I-NEXT: j .LBB103_2
; RV32I-NEXT: .LBB103_1: # %atomicrmw.start ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB103_4
; RV32I-NEXT: bnez a1, .LBB103_4
; RV32I-NEXT: .LBB103_2: # %atomicrmw.start ; RV32I-NEXT: .LBB103_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a1, .LBB103_1 ; RV32I-NEXT: bltu s1, a0, .LBB103_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB103_1 ; RV32I-NEXT: j .LBB103_1
; RV32I-NEXT: .LBB103_4: # %atomicrmw.end ; RV32I-NEXT: .LBB103_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB103_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB103_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1 ; RV32IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB103_1 ; RV32IA-NEXT: bnez a5, .LBB103_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB103_2 ; RV64I-NEXT: j .LBB103_2
; RV64I-NEXT: .LBB103_1: # %atomicrmw.start ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB103_4
; RV64I-NEXT: bnez a1, .LBB103_4
; RV64I-NEXT: .LBB103_2: # %atomicrmw.start ; RV64I-NEXT: .LBB103_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a1, .LBB103_1 ; RV64I-NEXT: bltu s1, a0, .LBB103_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB103_1 ; RV64I-NEXT: j .LBB103_1
; RV64I-NEXT: .LBB103_4: # %atomicrmw.end ; RV64I-NEXT: .LBB103_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB103_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB103_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1 ; RV64IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB103_1 ; RV64IA-NEXT: bnez a5, .LBB103_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acq_rel %1 = atomicrmw umax i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB104_2 ; RV32I-NEXT: j .LBB104_2
; RV32I-NEXT: .LBB104_1: # %atomicrmw.start ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB104_4
; RV32I-NEXT: bnez a1, .LBB104_4
; RV32I-NEXT: .LBB104_2: # %atomicrmw.start ; RV32I-NEXT: .LBB104_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a1, .LBB104_1 ; RV32I-NEXT: bltu s1, a0, .LBB104_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB104_1 ; RV32I-NEXT: j .LBB104_1
; RV32I-NEXT: .LBB104_4: # %atomicrmw.end ; RV32I-NEXT: .LBB104_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB104_3 ; RV32IA-NEXT: bgeu a2, a1, .LBB104_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 ; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB104_1 ; RV32IA-NEXT: bnez a5, .LBB104_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB104_2 ; RV64I-NEXT: j .LBB104_2
; RV64I-NEXT: .LBB104_1: # %atomicrmw.start ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB104_4
; RV64I-NEXT: bnez a1, .LBB104_4
; RV64I-NEXT: .LBB104_2: # %atomicrmw.start ; RV64I-NEXT: .LBB104_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a1, .LBB104_1 ; RV64I-NEXT: bltu s1, a0, .LBB104_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB104_1 ; RV64I-NEXT: j .LBB104_1
; RV64I-NEXT: .LBB104_4: # %atomicrmw.end ; RV64I-NEXT: .LBB104_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB104_3 ; RV64IA-NEXT: bgeu a2, a1, .LBB104_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 ; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB104_1 ; RV64IA-NEXT: bnez a5, .LBB104_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b seq_cst %1 = atomicrmw umax i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_monotonic: ; RV32I-LABEL: atomicrmw_umin_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB105_2 ; RV32I-NEXT: j .LBB105_2
; RV32I-NEXT: .LBB105_1: # %atomicrmw.start ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB105_4
; RV32I-NEXT: bnez a1, .LBB105_4
; RV32I-NEXT: .LBB105_2: # %atomicrmw.start ; RV32I-NEXT: .LBB105_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a1, .LBB105_1 ; RV32I-NEXT: bgeu s1, a0, .LBB105_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB105_1 ; RV32I-NEXT: j .LBB105_1
; RV32I-NEXT: .LBB105_4: # %atomicrmw.end ; RV32I-NEXT: .LBB105_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB105_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB105_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1 ; RV32IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB105_1 ; RV32IA-NEXT: bnez a5, .LBB105_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB105_2 ; RV64I-NEXT: j .LBB105_2
; RV64I-NEXT: .LBB105_1: # %atomicrmw.start ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB105_4
; RV64I-NEXT: bnez a1, .LBB105_4
; RV64I-NEXT: .LBB105_2: # %atomicrmw.start ; RV64I-NEXT: .LBB105_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a1, .LBB105_1 ; RV64I-NEXT: bgeu s1, a0, .LBB105_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB105_1 ; RV64I-NEXT: j .LBB105_1
; RV64I-NEXT: .LBB105_4: # %atomicrmw.end ; RV64I-NEXT: .LBB105_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB105_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB105_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1 ; RV64IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB105_1 ; RV64IA-NEXT: bnez a5, .LBB105_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b monotonic %1 = atomicrmw umin i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acquire: ; RV32I-LABEL: atomicrmw_umin_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB106_2 ; RV32I-NEXT: j .LBB106_2
; RV32I-NEXT: .LBB106_1: # %atomicrmw.start ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB106_4
; RV32I-NEXT: bnez a1, .LBB106_4
; RV32I-NEXT: .LBB106_2: # %atomicrmw.start ; RV32I-NEXT: .LBB106_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a1, .LBB106_1 ; RV32I-NEXT: bgeu s1, a0, .LBB106_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB106_1 ; RV32I-NEXT: j .LBB106_1
; RV32I-NEXT: .LBB106_4: # %atomicrmw.end ; RV32I-NEXT: .LBB106_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acquire: ; RV32IA-LABEL: atomicrmw_umin_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB106_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB106_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1 ; RV32IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: sc.w a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB106_1 ; RV32IA-NEXT: bnez a5, .LBB106_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acquire: ; RV64I-LABEL: atomicrmw_umin_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB106_2 ; RV64I-NEXT: j .LBB106_2
; RV64I-NEXT: .LBB106_1: # %atomicrmw.start ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB106_4
; RV64I-NEXT: bnez a1, .LBB106_4
; RV64I-NEXT: .LBB106_2: # %atomicrmw.start ; RV64I-NEXT: .LBB106_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a1, .LBB106_1 ; RV64I-NEXT: bgeu s1, a0, .LBB106_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB106_1 ; RV64I-NEXT: j .LBB106_1
; RV64I-NEXT: .LBB106_4: # %atomicrmw.end ; RV64I-NEXT: .LBB106_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB106_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB106_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1 ; RV64IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: sc.w a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB106_1 ; RV64IA-NEXT: bnez a5, .LBB106_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acquire %1 = atomicrmw umin i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_release: ; RV32I-LABEL: atomicrmw_umin_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB107_2 ; RV32I-NEXT: j .LBB107_2
; RV32I-NEXT: .LBB107_1: # %atomicrmw.start ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB107_4
; RV32I-NEXT: bnez a1, .LBB107_4
; RV32I-NEXT: .LBB107_2: # %atomicrmw.start ; RV32I-NEXT: .LBB107_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a1, .LBB107_1 ; RV32I-NEXT: bgeu s1, a0, .LBB107_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB107_1 ; RV32I-NEXT: j .LBB107_1
; RV32I-NEXT: .LBB107_4: # %atomicrmw.end ; RV32I-NEXT: .LBB107_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_release: ; RV32IA-LABEL: atomicrmw_umin_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: lr.w a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB107_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB107_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1 ; RV32IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB107_1 ; RV32IA-NEXT: bnez a5, .LBB107_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_release: ; RV64I-LABEL: atomicrmw_umin_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB107_2 ; RV64I-NEXT: j .LBB107_2
; RV64I-NEXT: .LBB107_1: # %atomicrmw.start ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB107_4
; RV64I-NEXT: bnez a1, .LBB107_4
; RV64I-NEXT: .LBB107_2: # %atomicrmw.start ; RV64I-NEXT: .LBB107_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a1, .LBB107_1 ; RV64I-NEXT: bgeu s1, a0, .LBB107_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB107_1 ; RV64I-NEXT: j .LBB107_1
; RV64I-NEXT: .LBB107_4: # %atomicrmw.end ; RV64I-NEXT: .LBB107_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_release: ; RV64IA-LABEL: atomicrmw_umin_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: lr.w a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB107_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB107_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1 ; RV64IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB107_1 ; RV64IA-NEXT: bnez a5, .LBB107_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b release %1 = atomicrmw umin i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB108_2 ; RV32I-NEXT: j .LBB108_2
; RV32I-NEXT: .LBB108_1: # %atomicrmw.start ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB108_4
; RV32I-NEXT: bnez a1, .LBB108_4
; RV32I-NEXT: .LBB108_2: # %atomicrmw.start ; RV32I-NEXT: .LBB108_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a1, .LBB108_1 ; RV32I-NEXT: bgeu s1, a0, .LBB108_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB108_1 ; RV32I-NEXT: j .LBB108_1
; RV32I-NEXT: .LBB108_4: # %atomicrmw.end ; RV32I-NEXT: .LBB108_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB108_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB108_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1 ; RV32IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: sc.w.rl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB108_1 ; RV32IA-NEXT: bnez a5, .LBB108_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB108_2 ; RV64I-NEXT: j .LBB108_2
; RV64I-NEXT: .LBB108_1: # %atomicrmw.start ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB108_4
; RV64I-NEXT: bnez a1, .LBB108_4
; RV64I-NEXT: .LBB108_2: # %atomicrmw.start ; RV64I-NEXT: .LBB108_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a1, .LBB108_1 ; RV64I-NEXT: bgeu s1, a0, .LBB108_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB108_1 ; RV64I-NEXT: j .LBB108_1
; RV64I-NEXT: .LBB108_4: # %atomicrmw.end ; RV64I-NEXT: .LBB108_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB108_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB108_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1 ; RV64IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: sc.w.rl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB108_1 ; RV64IA-NEXT: bnez a5, .LBB108_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acq_rel %1 = atomicrmw umin i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lhu a0, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB109_2 ; RV32I-NEXT: j .LBB109_2
; RV32I-NEXT: .LBB109_1: # %atomicrmw.start ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: sh a1, 6(sp)
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: lh a1, 6(sp)
; RV32I-NEXT: lh a0, 6(sp) ; RV32I-NEXT: bnez a0, .LBB109_4
; RV32I-NEXT: bnez a1, .LBB109_4
; RV32I-NEXT: .LBB109_2: # %atomicrmw.start ; RV32I-NEXT: .LBB109_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a1, .LBB109_1 ; RV32I-NEXT: bgeu s1, a0, .LBB109_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB109_1 ; RV32I-NEXT: j .LBB109_1
; RV32I-NEXT: .LBB109_4: # %atomicrmw.end ; RV32I-NEXT: .LBB109_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lui a2, 16 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: and a1, a1, a2 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: slli a3, a0, 3 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: andi a3, a3, 24 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a6, a2, a3 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: sll a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a6)
; RV32IA-NEXT: and a2, a4, a6 ; RV32IA-NEXT: and a2, a3, a4
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB109_3 ; RV32IA-NEXT: bgeu a1, a2, .LBB109_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 ; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV32IA-NEXT: bnez a5, .LBB109_1 ; RV32IA-NEXT: bnez a5, .LBB109_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: lhu a0, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB109_2 ; RV64I-NEXT: j .LBB109_2
; RV64I-NEXT: .LBB109_1: # %atomicrmw.start ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: sh a1, 14(sp)
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: lh a0, 14(sp) ; RV64I-NEXT: bnez a0, .LBB109_4
; RV64I-NEXT: bnez a1, .LBB109_4
; RV64I-NEXT: .LBB109_2: # %atomicrmw.start ; RV64I-NEXT: .LBB109_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a1, a0, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a1, .LBB109_1 ; RV64I-NEXT: bgeu s1, a0, .LBB109_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB109_1 ; RV64I-NEXT: j .LBB109_1
; RV64I-NEXT: .LBB109_4: # %atomicrmw.end ; RV64I-NEXT: .LBB109_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lui a2, 16 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: addiw a2, a2, -1 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: and a1, a1, a2 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: slli a3, a0, 3 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a3, a3, 24 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a6, a2, a3 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: sllw a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a6)
; RV64IA-NEXT: and a2, a4, a6 ; RV64IA-NEXT: and a2, a3, a4
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB109_3 ; RV64IA-NEXT: bgeu a1, a2, .LBB109_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 ; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6)
; RV64IA-NEXT: bnez a5, .LBB109_1 ; RV64IA-NEXT: bnez a5, .LBB109_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b seq_cst %1 = atomicrmw umin i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
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define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_monotonic: ; RV32I-LABEL: atomicrmw_max_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB145_3 ; RV32I-NEXT: bge s1, a3, .LBB145_3
; RV32I-NEXT: .LBB145_1: # %atomicrmw.start ; RV32I-NEXT: .LBB145_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB145_4 ; RV32I-NEXT: bnez a0, .LBB145_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB145_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB145_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB145_1 ; RV32I-NEXT: blt s1, a3, .LBB145_1
; RV32I-NEXT: .LBB145_3: # %atomicrmw.start ; RV32I-NEXT: .LBB145_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB145_1 ; RV32I-NEXT: j .LBB145_1
; RV32I-NEXT: .LBB145_4: # %atomicrmw.end ; RV32I-NEXT: .LBB145_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_monotonic: ; RV32IA-LABEL: atomicrmw_max_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w a0, a1, (a0) ; RV32IA-NEXT: amomax.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_monotonic: ; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB145_2 ; RV64I-NEXT: j .LBB145_2
; RV64I-NEXT: .LBB145_1: # %atomicrmw.start ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB145_4
; RV64I-NEXT: bnez a1, .LBB145_4
; RV64I-NEXT: .LBB145_2: # %atomicrmw.start ; RV64I-NEXT: .LBB145_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a1, .LBB145_1 ; RV64I-NEXT: blt s1, a0, .LBB145_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB145_1 ; RV64I-NEXT: j .LBB145_1
; RV64I-NEXT: .LBB145_4: # %atomicrmw.end ; RV64I-NEXT: .LBB145_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_monotonic: ; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w a0, a1, (a0) ; RV64IA-NEXT: amomax.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b monotonic %1 = atomicrmw max i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acquire: ; RV32I-LABEL: atomicrmw_max_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB146_3 ; RV32I-NEXT: bge s1, a3, .LBB146_3
; RV32I-NEXT: .LBB146_1: # %atomicrmw.start ; RV32I-NEXT: .LBB146_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB146_4 ; RV32I-NEXT: bnez a0, .LBB146_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB146_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB146_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB146_1 ; RV32I-NEXT: blt s1, a3, .LBB146_1
; RV32I-NEXT: .LBB146_3: # %atomicrmw.start ; RV32I-NEXT: .LBB146_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB146_1 ; RV32I-NEXT: j .LBB146_1
; RV32I-NEXT: .LBB146_4: # %atomicrmw.end ; RV32I-NEXT: .LBB146_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_acquire: ; RV32IA-LABEL: atomicrmw_max_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_acquire: ; RV64I-LABEL: atomicrmw_max_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB146_2 ; RV64I-NEXT: j .LBB146_2
; RV64I-NEXT: .LBB146_1: # %atomicrmw.start ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB146_4
; RV64I-NEXT: bnez a1, .LBB146_4
; RV64I-NEXT: .LBB146_2: # %atomicrmw.start ; RV64I-NEXT: .LBB146_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a1, .LBB146_1 ; RV64I-NEXT: blt s1, a0, .LBB146_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB146_1 ; RV64I-NEXT: j .LBB146_1
; RV64I-NEXT: .LBB146_4: # %atomicrmw.end ; RV64I-NEXT: .LBB146_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_acquire: ; RV64IA-LABEL: atomicrmw_max_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b acquire %1 = atomicrmw max i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_release: ; RV32I-LABEL: atomicrmw_max_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB147_3 ; RV32I-NEXT: bge s1, a3, .LBB147_3
; RV32I-NEXT: .LBB147_1: # %atomicrmw.start ; RV32I-NEXT: .LBB147_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB147_4 ; RV32I-NEXT: bnez a0, .LBB147_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB147_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB147_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB147_1 ; RV32I-NEXT: blt s1, a3, .LBB147_1
; RV32I-NEXT: .LBB147_3: # %atomicrmw.start ; RV32I-NEXT: .LBB147_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB147_1 ; RV32I-NEXT: j .LBB147_1
; RV32I-NEXT: .LBB147_4: # %atomicrmw.end ; RV32I-NEXT: .LBB147_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_release: ; RV32IA-LABEL: atomicrmw_max_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_release: ; RV64I-LABEL: atomicrmw_max_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB147_2 ; RV64I-NEXT: j .LBB147_2
; RV64I-NEXT: .LBB147_1: # %atomicrmw.start ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB147_4
; RV64I-NEXT: bnez a1, .LBB147_4
; RV64I-NEXT: .LBB147_2: # %atomicrmw.start ; RV64I-NEXT: .LBB147_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a1, .LBB147_1 ; RV64I-NEXT: blt s1, a0, .LBB147_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB147_1 ; RV64I-NEXT: j .LBB147_1
; RV64I-NEXT: .LBB147_4: # %atomicrmw.end ; RV64I-NEXT: .LBB147_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_release: ; RV64IA-LABEL: atomicrmw_max_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b release %1 = atomicrmw max i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acq_rel: ; RV32I-LABEL: atomicrmw_max_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB148_3 ; RV32I-NEXT: bge s1, a3, .LBB148_3
; RV32I-NEXT: .LBB148_1: # %atomicrmw.start ; RV32I-NEXT: .LBB148_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB148_4 ; RV32I-NEXT: bnez a0, .LBB148_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB148_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB148_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB148_1 ; RV32I-NEXT: blt s1, a3, .LBB148_1
; RV32I-NEXT: .LBB148_3: # %atomicrmw.start ; RV32I-NEXT: .LBB148_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB148_1 ; RV32I-NEXT: j .LBB148_1
; RV32I-NEXT: .LBB148_4: # %atomicrmw.end ; RV32I-NEXT: .LBB148_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_acq_rel: ; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB148_2 ; RV64I-NEXT: j .LBB148_2
; RV64I-NEXT: .LBB148_1: # %atomicrmw.start ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB148_4
; RV64I-NEXT: bnez a1, .LBB148_4
; RV64I-NEXT: .LBB148_2: # %atomicrmw.start ; RV64I-NEXT: .LBB148_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a1, .LBB148_1 ; RV64I-NEXT: blt s1, a0, .LBB148_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB148_1 ; RV64I-NEXT: j .LBB148_1
; RV64I-NEXT: .LBB148_4: # %atomicrmw.end ; RV64I-NEXT: .LBB148_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b acq_rel %1 = atomicrmw max i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_seq_cst: ; RV32I-LABEL: atomicrmw_max_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB149_3 ; RV32I-NEXT: bge s1, a3, .LBB149_3
; RV32I-NEXT: .LBB149_1: # %atomicrmw.start ; RV32I-NEXT: .LBB149_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB149_4 ; RV32I-NEXT: bnez a0, .LBB149_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB149_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB149_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB149_1 ; RV32I-NEXT: blt s1, a3, .LBB149_1
; RV32I-NEXT: .LBB149_3: # %atomicrmw.start ; RV32I-NEXT: .LBB149_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB149_1 ; RV32I-NEXT: j .LBB149_1
; RV32I-NEXT: .LBB149_4: # %atomicrmw.end ; RV32I-NEXT: .LBB149_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_seq_cst: ; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB149_2 ; RV64I-NEXT: j .LBB149_2
; RV64I-NEXT: .LBB149_1: # %atomicrmw.start ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB149_4
; RV64I-NEXT: bnez a1, .LBB149_4
; RV64I-NEXT: .LBB149_2: # %atomicrmw.start ; RV64I-NEXT: .LBB149_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a1, .LBB149_1 ; RV64I-NEXT: blt s1, a0, .LBB149_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB149_1 ; RV64I-NEXT: j .LBB149_1
; RV64I-NEXT: .LBB149_4: # %atomicrmw.end ; RV64I-NEXT: .LBB149_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b seq_cst %1 = atomicrmw max i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_monotonic: ; RV32I-LABEL: atomicrmw_min_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB150_3 ; RV32I-NEXT: blt s1, a3, .LBB150_3
; RV32I-NEXT: .LBB150_1: # %atomicrmw.start ; RV32I-NEXT: .LBB150_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB150_4 ; RV32I-NEXT: bnez a0, .LBB150_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB150_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB150_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB150_1 ; RV32I-NEXT: bge s1, a3, .LBB150_1
; RV32I-NEXT: .LBB150_3: # %atomicrmw.start ; RV32I-NEXT: .LBB150_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB150_1 ; RV32I-NEXT: j .LBB150_1
; RV32I-NEXT: .LBB150_4: # %atomicrmw.end ; RV32I-NEXT: .LBB150_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_monotonic: ; RV32IA-LABEL: atomicrmw_min_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w a0, a1, (a0) ; RV32IA-NEXT: amomin.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_monotonic: ; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB150_2 ; RV64I-NEXT: j .LBB150_2
; RV64I-NEXT: .LBB150_1: # %atomicrmw.start ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB150_4
; RV64I-NEXT: bnez a1, .LBB150_4
; RV64I-NEXT: .LBB150_2: # %atomicrmw.start ; RV64I-NEXT: .LBB150_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a1, .LBB150_1 ; RV64I-NEXT: bge s1, a0, .LBB150_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB150_1 ; RV64I-NEXT: j .LBB150_1
; RV64I-NEXT: .LBB150_4: # %atomicrmw.end ; RV64I-NEXT: .LBB150_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_monotonic: ; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w a0, a1, (a0) ; RV64IA-NEXT: amomin.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b monotonic %1 = atomicrmw min i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acquire: ; RV32I-LABEL: atomicrmw_min_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB151_3 ; RV32I-NEXT: blt s1, a3, .LBB151_3
; RV32I-NEXT: .LBB151_1: # %atomicrmw.start ; RV32I-NEXT: .LBB151_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB151_4 ; RV32I-NEXT: bnez a0, .LBB151_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB151_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB151_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB151_1 ; RV32I-NEXT: bge s1, a3, .LBB151_1
; RV32I-NEXT: .LBB151_3: # %atomicrmw.start ; RV32I-NEXT: .LBB151_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB151_1 ; RV32I-NEXT: j .LBB151_1
; RV32I-NEXT: .LBB151_4: # %atomicrmw.end ; RV32I-NEXT: .LBB151_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_acquire: ; RV32IA-LABEL: atomicrmw_min_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_acquire: ; RV64I-LABEL: atomicrmw_min_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB151_2 ; RV64I-NEXT: j .LBB151_2
; RV64I-NEXT: .LBB151_1: # %atomicrmw.start ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB151_4
; RV64I-NEXT: bnez a1, .LBB151_4
; RV64I-NEXT: .LBB151_2: # %atomicrmw.start ; RV64I-NEXT: .LBB151_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a1, .LBB151_1 ; RV64I-NEXT: bge s1, a0, .LBB151_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB151_1 ; RV64I-NEXT: j .LBB151_1
; RV64I-NEXT: .LBB151_4: # %atomicrmw.end ; RV64I-NEXT: .LBB151_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_acquire: ; RV64IA-LABEL: atomicrmw_min_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b acquire %1 = atomicrmw min i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_release: ; RV32I-LABEL: atomicrmw_min_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB152_3 ; RV32I-NEXT: blt s1, a3, .LBB152_3
; RV32I-NEXT: .LBB152_1: # %atomicrmw.start ; RV32I-NEXT: .LBB152_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB152_4 ; RV32I-NEXT: bnez a0, .LBB152_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB152_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB152_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB152_1 ; RV32I-NEXT: bge s1, a3, .LBB152_1
; RV32I-NEXT: .LBB152_3: # %atomicrmw.start ; RV32I-NEXT: .LBB152_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB152_1 ; RV32I-NEXT: j .LBB152_1
; RV32I-NEXT: .LBB152_4: # %atomicrmw.end ; RV32I-NEXT: .LBB152_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_release: ; RV32IA-LABEL: atomicrmw_min_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_release: ; RV64I-LABEL: atomicrmw_min_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB152_2 ; RV64I-NEXT: j .LBB152_2
; RV64I-NEXT: .LBB152_1: # %atomicrmw.start ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB152_4
; RV64I-NEXT: bnez a1, .LBB152_4
; RV64I-NEXT: .LBB152_2: # %atomicrmw.start ; RV64I-NEXT: .LBB152_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a1, .LBB152_1 ; RV64I-NEXT: bge s1, a0, .LBB152_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB152_1 ; RV64I-NEXT: j .LBB152_1
; RV64I-NEXT: .LBB152_4: # %atomicrmw.end ; RV64I-NEXT: .LBB152_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_release: ; RV64IA-LABEL: atomicrmw_min_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b release %1 = atomicrmw min i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acq_rel: ; RV32I-LABEL: atomicrmw_min_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB153_3 ; RV32I-NEXT: blt s1, a3, .LBB153_3
; RV32I-NEXT: .LBB153_1: # %atomicrmw.start ; RV32I-NEXT: .LBB153_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB153_4 ; RV32I-NEXT: bnez a0, .LBB153_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB153_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB153_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB153_1 ; RV32I-NEXT: bge s1, a3, .LBB153_1
; RV32I-NEXT: .LBB153_3: # %atomicrmw.start ; RV32I-NEXT: .LBB153_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB153_1 ; RV32I-NEXT: j .LBB153_1
; RV32I-NEXT: .LBB153_4: # %atomicrmw.end ; RV32I-NEXT: .LBB153_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_acq_rel: ; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB153_2 ; RV64I-NEXT: j .LBB153_2
; RV64I-NEXT: .LBB153_1: # %atomicrmw.start ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB153_4
; RV64I-NEXT: bnez a1, .LBB153_4
; RV64I-NEXT: .LBB153_2: # %atomicrmw.start ; RV64I-NEXT: .LBB153_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a1, .LBB153_1 ; RV64I-NEXT: bge s1, a0, .LBB153_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB153_1 ; RV64I-NEXT: j .LBB153_1
; RV64I-NEXT: .LBB153_4: # %atomicrmw.end ; RV64I-NEXT: .LBB153_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b acq_rel %1 = atomicrmw min i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_seq_cst: ; RV32I-LABEL: atomicrmw_min_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s0, a2, .LBB154_3 ; RV32I-NEXT: blt s1, a3, .LBB154_3
; RV32I-NEXT: .LBB154_1: # %atomicrmw.start ; RV32I-NEXT: .LBB154_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB154_4 ; RV32I-NEXT: bnez a0, .LBB154_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB154_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB154_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s0, a2, .LBB154_1 ; RV32I-NEXT: bge s1, a3, .LBB154_1
; RV32I-NEXT: .LBB154_3: # %atomicrmw.start ; RV32I-NEXT: .LBB154_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB154_1 ; RV32I-NEXT: j .LBB154_1
; RV32I-NEXT: .LBB154_4: # %atomicrmw.end ; RV32I-NEXT: .LBB154_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_seq_cst: ; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB154_2 ; RV64I-NEXT: j .LBB154_2
; RV64I-NEXT: .LBB154_1: # %atomicrmw.start ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB154_4
; RV64I-NEXT: bnez a1, .LBB154_4
; RV64I-NEXT: .LBB154_2: # %atomicrmw.start ; RV64I-NEXT: .LBB154_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a1, .LBB154_1 ; RV64I-NEXT: bge s1, a0, .LBB154_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB154_1 ; RV64I-NEXT: j .LBB154_1
; RV64I-NEXT: .LBB154_4: # %atomicrmw.end ; RV64I-NEXT: .LBB154_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b seq_cst %1 = atomicrmw min i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_monotonic: ; RV32I-LABEL: atomicrmw_umax_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB155_3 ; RV32I-NEXT: bgeu s1, a3, .LBB155_3
; RV32I-NEXT: .LBB155_1: # %atomicrmw.start ; RV32I-NEXT: .LBB155_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB155_4 ; RV32I-NEXT: bnez a0, .LBB155_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB155_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB155_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB155_1 ; RV32I-NEXT: bltu s1, a3, .LBB155_1
; RV32I-NEXT: .LBB155_3: # %atomicrmw.start ; RV32I-NEXT: .LBB155_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB155_1 ; RV32I-NEXT: j .LBB155_1
; RV32I-NEXT: .LBB155_4: # %atomicrmw.end ; RV32I-NEXT: .LBB155_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic: ; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB155_2 ; RV64I-NEXT: j .LBB155_2
; RV64I-NEXT: .LBB155_1: # %atomicrmw.start ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB155_4
; RV64I-NEXT: bnez a1, .LBB155_4
; RV64I-NEXT: .LBB155_2: # %atomicrmw.start ; RV64I-NEXT: .LBB155_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB155_1 ; RV64I-NEXT: bltu s1, a0, .LBB155_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB155_1 ; RV64I-NEXT: j .LBB155_1
; RV64I-NEXT: .LBB155_4: # %atomicrmw.end ; RV64I-NEXT: .LBB155_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b monotonic %1 = atomicrmw umax i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acquire: ; RV32I-LABEL: atomicrmw_umax_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB156_3 ; RV32I-NEXT: bgeu s1, a3, .LBB156_3
; RV32I-NEXT: .LBB156_1: # %atomicrmw.start ; RV32I-NEXT: .LBB156_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB156_4 ; RV32I-NEXT: bnez a0, .LBB156_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB156_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB156_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB156_1 ; RV32I-NEXT: bltu s1, a3, .LBB156_1
; RV32I-NEXT: .LBB156_3: # %atomicrmw.start ; RV32I-NEXT: .LBB156_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB156_1 ; RV32I-NEXT: j .LBB156_1
; RV32I-NEXT: .LBB156_4: # %atomicrmw.end ; RV32I-NEXT: .LBB156_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_acquire: ; RV32IA-LABEL: atomicrmw_umax_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_acquire: ; RV64I-LABEL: atomicrmw_umax_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB156_2 ; RV64I-NEXT: j .LBB156_2
; RV64I-NEXT: .LBB156_1: # %atomicrmw.start ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB156_4
; RV64I-NEXT: bnez a1, .LBB156_4
; RV64I-NEXT: .LBB156_2: # %atomicrmw.start ; RV64I-NEXT: .LBB156_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB156_1 ; RV64I-NEXT: bltu s1, a0, .LBB156_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB156_1 ; RV64I-NEXT: j .LBB156_1
; RV64I-NEXT: .LBB156_4: # %atomicrmw.end ; RV64I-NEXT: .LBB156_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_acquire: ; RV64IA-LABEL: atomicrmw_umax_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b acquire %1 = atomicrmw umax i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_release: ; RV32I-LABEL: atomicrmw_umax_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB157_3 ; RV32I-NEXT: bgeu s1, a3, .LBB157_3
; RV32I-NEXT: .LBB157_1: # %atomicrmw.start ; RV32I-NEXT: .LBB157_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB157_4 ; RV32I-NEXT: bnez a0, .LBB157_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB157_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB157_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB157_1 ; RV32I-NEXT: bltu s1, a3, .LBB157_1
; RV32I-NEXT: .LBB157_3: # %atomicrmw.start ; RV32I-NEXT: .LBB157_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB157_1 ; RV32I-NEXT: j .LBB157_1
; RV32I-NEXT: .LBB157_4: # %atomicrmw.end ; RV32I-NEXT: .LBB157_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_release: ; RV32IA-LABEL: atomicrmw_umax_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_release: ; RV64I-LABEL: atomicrmw_umax_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB157_2 ; RV64I-NEXT: j .LBB157_2
; RV64I-NEXT: .LBB157_1: # %atomicrmw.start ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB157_4
; RV64I-NEXT: bnez a1, .LBB157_4
; RV64I-NEXT: .LBB157_2: # %atomicrmw.start ; RV64I-NEXT: .LBB157_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB157_1 ; RV64I-NEXT: bltu s1, a0, .LBB157_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB157_1 ; RV64I-NEXT: j .LBB157_1
; RV64I-NEXT: .LBB157_4: # %atomicrmw.end ; RV64I-NEXT: .LBB157_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_release: ; RV64IA-LABEL: atomicrmw_umax_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b release %1 = atomicrmw umax i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB158_3 ; RV32I-NEXT: bgeu s1, a3, .LBB158_3
; RV32I-NEXT: .LBB158_1: # %atomicrmw.start ; RV32I-NEXT: .LBB158_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB158_4 ; RV32I-NEXT: bnez a0, .LBB158_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB158_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB158_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB158_1 ; RV32I-NEXT: bltu s1, a3, .LBB158_1
; RV32I-NEXT: .LBB158_3: # %atomicrmw.start ; RV32I-NEXT: .LBB158_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB158_1 ; RV32I-NEXT: j .LBB158_1
; RV32I-NEXT: .LBB158_4: # %atomicrmw.end ; RV32I-NEXT: .LBB158_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB158_2 ; RV64I-NEXT: j .LBB158_2
; RV64I-NEXT: .LBB158_1: # %atomicrmw.start ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB158_4
; RV64I-NEXT: bnez a1, .LBB158_4
; RV64I-NEXT: .LBB158_2: # %atomicrmw.start ; RV64I-NEXT: .LBB158_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB158_1 ; RV64I-NEXT: bltu s1, a0, .LBB158_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB158_1 ; RV64I-NEXT: j .LBB158_1
; RV64I-NEXT: .LBB158_4: # %atomicrmw.end ; RV64I-NEXT: .LBB158_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b acq_rel %1 = atomicrmw umax i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB159_3 ; RV32I-NEXT: bgeu s1, a3, .LBB159_3
; RV32I-NEXT: .LBB159_1: # %atomicrmw.start ; RV32I-NEXT: .LBB159_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB159_4 ; RV32I-NEXT: bnez a0, .LBB159_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB159_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB159_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB159_1 ; RV32I-NEXT: bltu s1, a3, .LBB159_1
; RV32I-NEXT: .LBB159_3: # %atomicrmw.start ; RV32I-NEXT: .LBB159_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB159_1 ; RV32I-NEXT: j .LBB159_1
; RV32I-NEXT: .LBB159_4: # %atomicrmw.end ; RV32I-NEXT: .LBB159_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB159_2 ; RV64I-NEXT: j .LBB159_2
; RV64I-NEXT: .LBB159_1: # %atomicrmw.start ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB159_4
; RV64I-NEXT: bnez a1, .LBB159_4
; RV64I-NEXT: .LBB159_2: # %atomicrmw.start ; RV64I-NEXT: .LBB159_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a1, .LBB159_1 ; RV64I-NEXT: bltu s1, a0, .LBB159_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB159_1 ; RV64I-NEXT: j .LBB159_1
; RV64I-NEXT: .LBB159_4: # %atomicrmw.end ; RV64I-NEXT: .LBB159_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b seq_cst %1 = atomicrmw umax i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_monotonic: ; RV32I-LABEL: atomicrmw_umin_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB160_3 ; RV32I-NEXT: bltu s1, a3, .LBB160_3
; RV32I-NEXT: .LBB160_1: # %atomicrmw.start ; RV32I-NEXT: .LBB160_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB160_4 ; RV32I-NEXT: bnez a0, .LBB160_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB160_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB160_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB160_1 ; RV32I-NEXT: bgeu s1, a3, .LBB160_1
; RV32I-NEXT: .LBB160_3: # %atomicrmw.start ; RV32I-NEXT: .LBB160_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB160_1 ; RV32I-NEXT: j .LBB160_1
; RV32I-NEXT: .LBB160_4: # %atomicrmw.end ; RV32I-NEXT: .LBB160_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w a0, a1, (a0) ; RV32IA-NEXT: amominu.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic: ; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB160_2 ; RV64I-NEXT: j .LBB160_2
; RV64I-NEXT: .LBB160_1: # %atomicrmw.start ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB160_4
; RV64I-NEXT: bnez a1, .LBB160_4
; RV64I-NEXT: .LBB160_2: # %atomicrmw.start ; RV64I-NEXT: .LBB160_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB160_1 ; RV64I-NEXT: bgeu s1, a0, .LBB160_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB160_1 ; RV64I-NEXT: j .LBB160_1
; RV64I-NEXT: .LBB160_4: # %atomicrmw.end ; RV64I-NEXT: .LBB160_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w a0, a1, (a0) ; RV64IA-NEXT: amominu.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b monotonic %1 = atomicrmw umin i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acquire: ; RV32I-LABEL: atomicrmw_umin_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB161_3 ; RV32I-NEXT: bltu s1, a3, .LBB161_3
; RV32I-NEXT: .LBB161_1: # %atomicrmw.start ; RV32I-NEXT: .LBB161_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB161_4 ; RV32I-NEXT: bnez a0, .LBB161_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB161_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB161_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB161_1 ; RV32I-NEXT: bgeu s1, a3, .LBB161_1
; RV32I-NEXT: .LBB161_3: # %atomicrmw.start ; RV32I-NEXT: .LBB161_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB161_1 ; RV32I-NEXT: j .LBB161_1
; RV32I-NEXT: .LBB161_4: # %atomicrmw.end ; RV32I-NEXT: .LBB161_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_acquire: ; RV32IA-LABEL: atomicrmw_umin_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aq a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_acquire: ; RV64I-LABEL: atomicrmw_umin_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB161_2 ; RV64I-NEXT: j .LBB161_2
; RV64I-NEXT: .LBB161_1: # %atomicrmw.start ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB161_4
; RV64I-NEXT: bnez a1, .LBB161_4
; RV64I-NEXT: .LBB161_2: # %atomicrmw.start ; RV64I-NEXT: .LBB161_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB161_1 ; RV64I-NEXT: bgeu s1, a0, .LBB161_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB161_1 ; RV64I-NEXT: j .LBB161_1
; RV64I-NEXT: .LBB161_4: # %atomicrmw.end ; RV64I-NEXT: .LBB161_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_acquire: ; RV64IA-LABEL: atomicrmw_umin_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aq a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b acquire %1 = atomicrmw umin i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_release: ; RV32I-LABEL: atomicrmw_umin_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB162_3 ; RV32I-NEXT: bltu s1, a3, .LBB162_3
; RV32I-NEXT: .LBB162_1: # %atomicrmw.start ; RV32I-NEXT: .LBB162_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB162_4 ; RV32I-NEXT: bnez a0, .LBB162_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB162_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB162_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB162_1 ; RV32I-NEXT: bgeu s1, a3, .LBB162_1
; RV32I-NEXT: .LBB162_3: # %atomicrmw.start ; RV32I-NEXT: .LBB162_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB162_1 ; RV32I-NEXT: j .LBB162_1
; RV32I-NEXT: .LBB162_4: # %atomicrmw.end ; RV32I-NEXT: .LBB162_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_release: ; RV32IA-LABEL: atomicrmw_umin_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.rl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_release: ; RV64I-LABEL: atomicrmw_umin_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB162_2 ; RV64I-NEXT: j .LBB162_2
; RV64I-NEXT: .LBB162_1: # %atomicrmw.start ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB162_4
; RV64I-NEXT: bnez a1, .LBB162_4
; RV64I-NEXT: .LBB162_2: # %atomicrmw.start ; RV64I-NEXT: .LBB162_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB162_1 ; RV64I-NEXT: bgeu s1, a0, .LBB162_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB162_1 ; RV64I-NEXT: j .LBB162_1
; RV64I-NEXT: .LBB162_4: # %atomicrmw.end ; RV64I-NEXT: .LBB162_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_release: ; RV64IA-LABEL: atomicrmw_umin_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.rl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b release %1 = atomicrmw umin i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB163_3 ; RV32I-NEXT: bltu s1, a3, .LBB163_3
; RV32I-NEXT: .LBB163_1: # %atomicrmw.start ; RV32I-NEXT: .LBB163_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB163_4 ; RV32I-NEXT: bnez a0, .LBB163_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB163_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB163_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB163_1 ; RV32I-NEXT: bgeu s1, a3, .LBB163_1
; RV32I-NEXT: .LBB163_3: # %atomicrmw.start ; RV32I-NEXT: .LBB163_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB163_1 ; RV32I-NEXT: j .LBB163_1
; RV32I-NEXT: .LBB163_4: # %atomicrmw.end ; RV32I-NEXT: .LBB163_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB163_2 ; RV64I-NEXT: j .LBB163_2
; RV64I-NEXT: .LBB163_1: # %atomicrmw.start ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB163_4
; RV64I-NEXT: bnez a1, .LBB163_4
; RV64I-NEXT: .LBB163_2: # %atomicrmw.start ; RV64I-NEXT: .LBB163_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB163_1 ; RV64I-NEXT: bgeu s1, a0, .LBB163_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB163_1 ; RV64I-NEXT: j .LBB163_1
; RV64I-NEXT: .LBB163_4: # %atomicrmw.end ; RV64I-NEXT: .LBB163_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b acq_rel %1 = atomicrmw umin i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: addi s2, sp, 12 ; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s0, a2, .LBB164_3 ; RV32I-NEXT: bltu s1, a3, .LBB164_3
; RV32I-NEXT: .LBB164_1: # %atomicrmw.start ; RV32I-NEXT: .LBB164_1: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 12(sp)
; RV32I-NEXT: bnez a0, .LBB164_4 ; RV32I-NEXT: bnez a0, .LBB164_4
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB164_1 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB164_1 Depth=1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s0, a2, .LBB164_1 ; RV32I-NEXT: bgeu s1, a3, .LBB164_1
; RV32I-NEXT: .LBB164_3: # %atomicrmw.start ; RV32I-NEXT: .LBB164_3: # %atomicrmw.start
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB164_1 ; RV32I-NEXT: j .LBB164_1
; RV32I-NEXT: .LBB164_4: # %atomicrmw.end ; RV32I-NEXT: .LBB164_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: sext.w s0, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB164_2 ; RV64I-NEXT: j .LBB164_2
; RV64I-NEXT: .LBB164_1: # %atomicrmw.start ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: sw a0, 4(sp) ; RV64I-NEXT: sw a3, 4(sp)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s3
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: lw a3, 4(sp)
; RV64I-NEXT: lw a0, 4(sp) ; RV64I-NEXT: bnez a0, .LBB164_4
; RV64I-NEXT: bnez a1, .LBB164_4
; RV64I-NEXT: .LBB164_2: # %atomicrmw.start ; RV64I-NEXT: .LBB164_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a1, .LBB164_1 ; RV64I-NEXT: bgeu s1, a0, .LBB164_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s3
; RV64I-NEXT: j .LBB164_1 ; RV64I-NEXT: j .LBB164_1
; RV64I-NEXT: .LBB164_4: # %atomicrmw.end ; RV64I-NEXT: .LBB164_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
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; RV32I-LABEL: atomicrmw_max_i64_monotonic: ; RV32I-LABEL: atomicrmw_max_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB200_3 ; RV32I-NEXT: bne a5, s1, .LBB200_3
; RV32I-NEXT: j .LBB200_4 ; RV32I-NEXT: j .LBB200_4
; RV32I-NEXT: .LBB200_1: # %atomicrmw.start ; RV32I-NEXT: .LBB200_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB200_7 ; RV32I-NEXT: bnez a0, .LBB200_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB200_4 ; RV32I-NEXT: beq a5, s1, .LBB200_4
; RV32I-NEXT: .LBB200_3: # %atomicrmw.start ; RV32I-NEXT: .LBB200_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB200_5 ; RV32I-NEXT: j .LBB200_5
; RV32I-NEXT: .LBB200_4: ; RV32I-NEXT: .LBB200_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB200_5: # %atomicrmw.start ; RV32I-NEXT: .LBB200_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB200_1 ; RV32I-NEXT: bnez a0, .LBB200_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB200_1 ; RV32I-NEXT: j .LBB200_1
; RV32I-NEXT: .LBB200_7: # %atomicrmw.end ; RV32I-NEXT: .LBB200_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_monotonic: ; RV32IA-LABEL: atomicrmw_max_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB200_3 ; RV32IA-NEXT: bne a5, s1, .LBB200_3
; RV32IA-NEXT: j .LBB200_4 ; RV32IA-NEXT: j .LBB200_4
; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB200_7 ; RV32IA-NEXT: bnez a0, .LBB200_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB200_4 ; RV32IA-NEXT: beq a5, s1, .LBB200_4
; RV32IA-NEXT: .LBB200_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB200_5 ; RV32IA-NEXT: j .LBB200_5
; RV32IA-NEXT: .LBB200_4: ; RV32IA-NEXT: .LBB200_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB200_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB200_1 ; RV32IA-NEXT: bnez a0, .LBB200_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB200_1 ; RV32IA-NEXT: j .LBB200_1
; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_monotonic: ; RV64I-LABEL: atomicrmw_max_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB200_3 ; RV64I-NEXT: bge s1, a3, .LBB200_3
; RV64I-NEXT: .LBB200_1: # %atomicrmw.start ; RV64I-NEXT: .LBB200_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB200_4 ; RV64I-NEXT: bnez a0, .LBB200_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB200_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB200_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB200_1 ; RV64I-NEXT: blt s1, a3, .LBB200_1
; RV64I-NEXT: .LBB200_3: # %atomicrmw.start ; RV64I-NEXT: .LBB200_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB200_1 ; RV64I-NEXT: j .LBB200_1
; RV64I-NEXT: .LBB200_4: # %atomicrmw.end ; RV64I-NEXT: .LBB200_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_monotonic: ; RV64IA-LABEL: atomicrmw_max_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d a0, a1, (a0) ; RV64IA-NEXT: amomax.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b monotonic %1 = atomicrmw max i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_acquire: ; RV32I-LABEL: atomicrmw_max_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB201_3 ; RV32I-NEXT: bne a5, s1, .LBB201_3
; RV32I-NEXT: j .LBB201_4 ; RV32I-NEXT: j .LBB201_4
; RV32I-NEXT: .LBB201_1: # %atomicrmw.start ; RV32I-NEXT: .LBB201_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB201_7 ; RV32I-NEXT: bnez a0, .LBB201_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB201_4 ; RV32I-NEXT: beq a5, s1, .LBB201_4
; RV32I-NEXT: .LBB201_3: # %atomicrmw.start ; RV32I-NEXT: .LBB201_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB201_5 ; RV32I-NEXT: j .LBB201_5
; RV32I-NEXT: .LBB201_4: ; RV32I-NEXT: .LBB201_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB201_5: # %atomicrmw.start ; RV32I-NEXT: .LBB201_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB201_1 ; RV32I-NEXT: bnez a0, .LBB201_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB201_1 ; RV32I-NEXT: j .LBB201_1
; RV32I-NEXT: .LBB201_7: # %atomicrmw.end ; RV32I-NEXT: .LBB201_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_acquire: ; RV32IA-LABEL: atomicrmw_max_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB201_3 ; RV32IA-NEXT: bne a5, s1, .LBB201_3
; RV32IA-NEXT: j .LBB201_4 ; RV32IA-NEXT: j .LBB201_4
; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB201_7 ; RV32IA-NEXT: bnez a0, .LBB201_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB201_4 ; RV32IA-NEXT: beq a5, s1, .LBB201_4
; RV32IA-NEXT: .LBB201_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB201_5 ; RV32IA-NEXT: j .LBB201_5
; RV32IA-NEXT: .LBB201_4: ; RV32IA-NEXT: .LBB201_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB201_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB201_1 ; RV32IA-NEXT: bnez a0, .LBB201_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB201_1 ; RV32IA-NEXT: j .LBB201_1
; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_acquire: ; RV64I-LABEL: atomicrmw_max_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB201_3 ; RV64I-NEXT: bge s1, a3, .LBB201_3
; RV64I-NEXT: .LBB201_1: # %atomicrmw.start ; RV64I-NEXT: .LBB201_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB201_4 ; RV64I-NEXT: bnez a0, .LBB201_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB201_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB201_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB201_1 ; RV64I-NEXT: blt s1, a3, .LBB201_1
; RV64I-NEXT: .LBB201_3: # %atomicrmw.start ; RV64I-NEXT: .LBB201_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB201_1 ; RV64I-NEXT: j .LBB201_1
; RV64I-NEXT: .LBB201_4: # %atomicrmw.end ; RV64I-NEXT: .LBB201_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_acquire: ; RV64IA-LABEL: atomicrmw_max_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b acquire %1 = atomicrmw max i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_release: ; RV32I-LABEL: atomicrmw_max_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB202_3 ; RV32I-NEXT: bne a5, s1, .LBB202_3
; RV32I-NEXT: j .LBB202_4 ; RV32I-NEXT: j .LBB202_4
; RV32I-NEXT: .LBB202_1: # %atomicrmw.start ; RV32I-NEXT: .LBB202_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB202_7 ; RV32I-NEXT: bnez a0, .LBB202_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB202_4 ; RV32I-NEXT: beq a5, s1, .LBB202_4
; RV32I-NEXT: .LBB202_3: # %atomicrmw.start ; RV32I-NEXT: .LBB202_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB202_5 ; RV32I-NEXT: j .LBB202_5
; RV32I-NEXT: .LBB202_4: ; RV32I-NEXT: .LBB202_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB202_5: # %atomicrmw.start ; RV32I-NEXT: .LBB202_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB202_1 ; RV32I-NEXT: bnez a0, .LBB202_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB202_1 ; RV32I-NEXT: j .LBB202_1
; RV32I-NEXT: .LBB202_7: # %atomicrmw.end ; RV32I-NEXT: .LBB202_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_release: ; RV32IA-LABEL: atomicrmw_max_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB202_3 ; RV32IA-NEXT: bne a5, s1, .LBB202_3
; RV32IA-NEXT: j .LBB202_4 ; RV32IA-NEXT: j .LBB202_4
; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB202_7 ; RV32IA-NEXT: bnez a0, .LBB202_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB202_4 ; RV32IA-NEXT: beq a5, s1, .LBB202_4
; RV32IA-NEXT: .LBB202_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB202_5 ; RV32IA-NEXT: j .LBB202_5
; RV32IA-NEXT: .LBB202_4: ; RV32IA-NEXT: .LBB202_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB202_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB202_1 ; RV32IA-NEXT: bnez a0, .LBB202_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB202_1 ; RV32IA-NEXT: j .LBB202_1
; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_release: ; RV64I-LABEL: atomicrmw_max_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB202_3 ; RV64I-NEXT: bge s1, a3, .LBB202_3
; RV64I-NEXT: .LBB202_1: # %atomicrmw.start ; RV64I-NEXT: .LBB202_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB202_4 ; RV64I-NEXT: bnez a0, .LBB202_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB202_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB202_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB202_1 ; RV64I-NEXT: blt s1, a3, .LBB202_1
; RV64I-NEXT: .LBB202_3: # %atomicrmw.start ; RV64I-NEXT: .LBB202_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB202_1 ; RV64I-NEXT: j .LBB202_1
; RV64I-NEXT: .LBB202_4: # %atomicrmw.end ; RV64I-NEXT: .LBB202_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_release: ; RV64IA-LABEL: atomicrmw_max_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b release %1 = atomicrmw max i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_acq_rel: ; RV32I-LABEL: atomicrmw_max_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB203_3 ; RV32I-NEXT: bne a5, s1, .LBB203_3
; RV32I-NEXT: j .LBB203_4 ; RV32I-NEXT: j .LBB203_4
; RV32I-NEXT: .LBB203_1: # %atomicrmw.start ; RV32I-NEXT: .LBB203_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB203_7 ; RV32I-NEXT: bnez a0, .LBB203_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB203_4 ; RV32I-NEXT: beq a5, s1, .LBB203_4
; RV32I-NEXT: .LBB203_3: # %atomicrmw.start ; RV32I-NEXT: .LBB203_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB203_5 ; RV32I-NEXT: j .LBB203_5
; RV32I-NEXT: .LBB203_4: ; RV32I-NEXT: .LBB203_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB203_5: # %atomicrmw.start ; RV32I-NEXT: .LBB203_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB203_1 ; RV32I-NEXT: bnez a0, .LBB203_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB203_1 ; RV32I-NEXT: j .LBB203_1
; RV32I-NEXT: .LBB203_7: # %atomicrmw.end ; RV32I-NEXT: .LBB203_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB203_3 ; RV32IA-NEXT: bne a5, s1, .LBB203_3
; RV32IA-NEXT: j .LBB203_4 ; RV32IA-NEXT: j .LBB203_4
; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB203_7 ; RV32IA-NEXT: bnez a0, .LBB203_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB203_4 ; RV32IA-NEXT: beq a5, s1, .LBB203_4
; RV32IA-NEXT: .LBB203_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB203_5 ; RV32IA-NEXT: j .LBB203_5
; RV32IA-NEXT: .LBB203_4: ; RV32IA-NEXT: .LBB203_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB203_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB203_1 ; RV32IA-NEXT: bnez a0, .LBB203_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB203_1 ; RV32IA-NEXT: j .LBB203_1
; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_acq_rel: ; RV64I-LABEL: atomicrmw_max_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB203_3 ; RV64I-NEXT: bge s1, a3, .LBB203_3
; RV64I-NEXT: .LBB203_1: # %atomicrmw.start ; RV64I-NEXT: .LBB203_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB203_4 ; RV64I-NEXT: bnez a0, .LBB203_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB203_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB203_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB203_1 ; RV64I-NEXT: blt s1, a3, .LBB203_1
; RV64I-NEXT: .LBB203_3: # %atomicrmw.start ; RV64I-NEXT: .LBB203_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB203_1 ; RV64I-NEXT: j .LBB203_1
; RV64I-NEXT: .LBB203_4: # %atomicrmw.end ; RV64I-NEXT: .LBB203_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b acq_rel %1 = atomicrmw max i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_seq_cst: ; RV32I-LABEL: atomicrmw_max_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB204_3 ; RV32I-NEXT: bne a5, s1, .LBB204_3
; RV32I-NEXT: j .LBB204_4 ; RV32I-NEXT: j .LBB204_4
; RV32I-NEXT: .LBB204_1: # %atomicrmw.start ; RV32I-NEXT: .LBB204_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB204_7 ; RV32I-NEXT: bnez a0, .LBB204_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB204_4 ; RV32I-NEXT: beq a5, s1, .LBB204_4
; RV32I-NEXT: .LBB204_3: # %atomicrmw.start ; RV32I-NEXT: .LBB204_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB204_5 ; RV32I-NEXT: j .LBB204_5
; RV32I-NEXT: .LBB204_4: ; RV32I-NEXT: .LBB204_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB204_5: # %atomicrmw.start ; RV32I-NEXT: .LBB204_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB204_1 ; RV32I-NEXT: bnez a0, .LBB204_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB204_1 ; RV32I-NEXT: j .LBB204_1
; RV32I-NEXT: .LBB204_7: # %atomicrmw.end ; RV32I-NEXT: .LBB204_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB204_3 ; RV32IA-NEXT: bne a5, s1, .LBB204_3
; RV32IA-NEXT: j .LBB204_4 ; RV32IA-NEXT: j .LBB204_4
; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB204_7 ; RV32IA-NEXT: bnez a0, .LBB204_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB204_4 ; RV32IA-NEXT: beq a5, s1, .LBB204_4
; RV32IA-NEXT: .LBB204_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB204_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB204_5 ; RV32IA-NEXT: j .LBB204_5
; RV32IA-NEXT: .LBB204_4: ; RV32IA-NEXT: .LBB204_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB204_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB204_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB204_1 ; RV32IA-NEXT: bnez a0, .LBB204_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB204_1 ; RV32IA-NEXT: j .LBB204_1
; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_seq_cst: ; RV64I-LABEL: atomicrmw_max_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB204_3 ; RV64I-NEXT: bge s1, a3, .LBB204_3
; RV64I-NEXT: .LBB204_1: # %atomicrmw.start ; RV64I-NEXT: .LBB204_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB204_4 ; RV64I-NEXT: bnez a0, .LBB204_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB204_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB204_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB204_1 ; RV64I-NEXT: blt s1, a3, .LBB204_1
; RV64I-NEXT: .LBB204_3: # %atomicrmw.start ; RV64I-NEXT: .LBB204_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB204_1 ; RV64I-NEXT: j .LBB204_1
; RV64I-NEXT: .LBB204_4: # %atomicrmw.end ; RV64I-NEXT: .LBB204_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b seq_cst %1 = atomicrmw max i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_monotonic: ; RV32I-LABEL: atomicrmw_min_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB205_3 ; RV32I-NEXT: bne a5, s1, .LBB205_3
; RV32I-NEXT: j .LBB205_4 ; RV32I-NEXT: j .LBB205_4
; RV32I-NEXT: .LBB205_1: # %atomicrmw.start ; RV32I-NEXT: .LBB205_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB205_7 ; RV32I-NEXT: bnez a0, .LBB205_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB205_4 ; RV32I-NEXT: beq a5, s1, .LBB205_4
; RV32I-NEXT: .LBB205_3: # %atomicrmw.start ; RV32I-NEXT: .LBB205_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB205_5 ; RV32I-NEXT: j .LBB205_5
; RV32I-NEXT: .LBB205_4: ; RV32I-NEXT: .LBB205_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB205_5: # %atomicrmw.start ; RV32I-NEXT: .LBB205_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB205_1 ; RV32I-NEXT: bnez a0, .LBB205_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB205_1 ; RV32I-NEXT: j .LBB205_1
; RV32I-NEXT: .LBB205_7: # %atomicrmw.end ; RV32I-NEXT: .LBB205_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_monotonic: ; RV32IA-LABEL: atomicrmw_min_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB205_3 ; RV32IA-NEXT: bne a5, s1, .LBB205_3
; RV32IA-NEXT: j .LBB205_4 ; RV32IA-NEXT: j .LBB205_4
; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB205_7 ; RV32IA-NEXT: bnez a0, .LBB205_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB205_4 ; RV32IA-NEXT: beq a5, s1, .LBB205_4
; RV32IA-NEXT: .LBB205_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB205_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB205_5 ; RV32IA-NEXT: j .LBB205_5
; RV32IA-NEXT: .LBB205_4: ; RV32IA-NEXT: .LBB205_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB205_1 ; RV32IA-NEXT: bnez a0, .LBB205_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB205_1 ; RV32IA-NEXT: j .LBB205_1
; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_monotonic: ; RV64I-LABEL: atomicrmw_min_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB205_3 ; RV64I-NEXT: blt s1, a3, .LBB205_3
; RV64I-NEXT: .LBB205_1: # %atomicrmw.start ; RV64I-NEXT: .LBB205_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB205_4 ; RV64I-NEXT: bnez a0, .LBB205_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB205_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB205_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB205_1 ; RV64I-NEXT: bge s1, a3, .LBB205_1
; RV64I-NEXT: .LBB205_3: # %atomicrmw.start ; RV64I-NEXT: .LBB205_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB205_1 ; RV64I-NEXT: j .LBB205_1
; RV64I-NEXT: .LBB205_4: # %atomicrmw.end ; RV64I-NEXT: .LBB205_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_monotonic: ; RV64IA-LABEL: atomicrmw_min_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d a0, a1, (a0) ; RV64IA-NEXT: amomin.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b monotonic %1 = atomicrmw min i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_acquire: ; RV32I-LABEL: atomicrmw_min_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB206_3 ; RV32I-NEXT: bne a5, s1, .LBB206_3
; RV32I-NEXT: j .LBB206_4 ; RV32I-NEXT: j .LBB206_4
; RV32I-NEXT: .LBB206_1: # %atomicrmw.start ; RV32I-NEXT: .LBB206_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB206_7 ; RV32I-NEXT: bnez a0, .LBB206_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB206_4 ; RV32I-NEXT: beq a5, s1, .LBB206_4
; RV32I-NEXT: .LBB206_3: # %atomicrmw.start ; RV32I-NEXT: .LBB206_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB206_5 ; RV32I-NEXT: j .LBB206_5
; RV32I-NEXT: .LBB206_4: ; RV32I-NEXT: .LBB206_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB206_5: # %atomicrmw.start ; RV32I-NEXT: .LBB206_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB206_1 ; RV32I-NEXT: bnez a0, .LBB206_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB206_1 ; RV32I-NEXT: j .LBB206_1
; RV32I-NEXT: .LBB206_7: # %atomicrmw.end ; RV32I-NEXT: .LBB206_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_acquire: ; RV32IA-LABEL: atomicrmw_min_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB206_3 ; RV32IA-NEXT: bne a5, s1, .LBB206_3
; RV32IA-NEXT: j .LBB206_4 ; RV32IA-NEXT: j .LBB206_4
; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB206_7 ; RV32IA-NEXT: bnez a0, .LBB206_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB206_4 ; RV32IA-NEXT: beq a5, s1, .LBB206_4
; RV32IA-NEXT: .LBB206_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB206_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB206_5 ; RV32IA-NEXT: j .LBB206_5
; RV32IA-NEXT: .LBB206_4: ; RV32IA-NEXT: .LBB206_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB206_1 ; RV32IA-NEXT: bnez a0, .LBB206_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB206_1 ; RV32IA-NEXT: j .LBB206_1
; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_acquire: ; RV64I-LABEL: atomicrmw_min_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB206_3 ; RV64I-NEXT: blt s1, a3, .LBB206_3
; RV64I-NEXT: .LBB206_1: # %atomicrmw.start ; RV64I-NEXT: .LBB206_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB206_4 ; RV64I-NEXT: bnez a0, .LBB206_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB206_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB206_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB206_1 ; RV64I-NEXT: bge s1, a3, .LBB206_1
; RV64I-NEXT: .LBB206_3: # %atomicrmw.start ; RV64I-NEXT: .LBB206_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB206_1 ; RV64I-NEXT: j .LBB206_1
; RV64I-NEXT: .LBB206_4: # %atomicrmw.end ; RV64I-NEXT: .LBB206_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_acquire: ; RV64IA-LABEL: atomicrmw_min_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomin.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b acquire %1 = atomicrmw min i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_release: ; RV32I-LABEL: atomicrmw_min_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB207_3 ; RV32I-NEXT: bne a5, s1, .LBB207_3
; RV32I-NEXT: j .LBB207_4 ; RV32I-NEXT: j .LBB207_4
; RV32I-NEXT: .LBB207_1: # %atomicrmw.start ; RV32I-NEXT: .LBB207_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB207_7 ; RV32I-NEXT: bnez a0, .LBB207_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB207_4 ; RV32I-NEXT: beq a5, s1, .LBB207_4
; RV32I-NEXT: .LBB207_3: # %atomicrmw.start ; RV32I-NEXT: .LBB207_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB207_5 ; RV32I-NEXT: j .LBB207_5
; RV32I-NEXT: .LBB207_4: ; RV32I-NEXT: .LBB207_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB207_5: # %atomicrmw.start ; RV32I-NEXT: .LBB207_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB207_1 ; RV32I-NEXT: bnez a0, .LBB207_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB207_1 ; RV32I-NEXT: j .LBB207_1
; RV32I-NEXT: .LBB207_7: # %atomicrmw.end ; RV32I-NEXT: .LBB207_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_release: ; RV32IA-LABEL: atomicrmw_min_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB207_3 ; RV32IA-NEXT: bne a5, s1, .LBB207_3
; RV32IA-NEXT: j .LBB207_4 ; RV32IA-NEXT: j .LBB207_4
; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB207_7 ; RV32IA-NEXT: bnez a0, .LBB207_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB207_4 ; RV32IA-NEXT: beq a5, s1, .LBB207_4
; RV32IA-NEXT: .LBB207_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB207_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB207_5 ; RV32IA-NEXT: j .LBB207_5
; RV32IA-NEXT: .LBB207_4: ; RV32IA-NEXT: .LBB207_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB207_1 ; RV32IA-NEXT: bnez a0, .LBB207_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB207_1 ; RV32IA-NEXT: j .LBB207_1
; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_release: ; RV64I-LABEL: atomicrmw_min_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB207_3 ; RV64I-NEXT: blt s1, a3, .LBB207_3
; RV64I-NEXT: .LBB207_1: # %atomicrmw.start ; RV64I-NEXT: .LBB207_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB207_4 ; RV64I-NEXT: bnez a0, .LBB207_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB207_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB207_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB207_1 ; RV64I-NEXT: bge s1, a3, .LBB207_1
; RV64I-NEXT: .LBB207_3: # %atomicrmw.start ; RV64I-NEXT: .LBB207_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB207_1 ; RV64I-NEXT: j .LBB207_1
; RV64I-NEXT: .LBB207_4: # %atomicrmw.end ; RV64I-NEXT: .LBB207_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_release: ; RV64IA-LABEL: atomicrmw_min_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomin.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b release %1 = atomicrmw min i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_acq_rel: ; RV32I-LABEL: atomicrmw_min_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB208_3 ; RV32I-NEXT: bne a5, s1, .LBB208_3
; RV32I-NEXT: j .LBB208_4 ; RV32I-NEXT: j .LBB208_4
; RV32I-NEXT: .LBB208_1: # %atomicrmw.start ; RV32I-NEXT: .LBB208_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB208_7 ; RV32I-NEXT: bnez a0, .LBB208_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB208_4 ; RV32I-NEXT: beq a5, s1, .LBB208_4
; RV32I-NEXT: .LBB208_3: # %atomicrmw.start ; RV32I-NEXT: .LBB208_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB208_5 ; RV32I-NEXT: j .LBB208_5
; RV32I-NEXT: .LBB208_4: ; RV32I-NEXT: .LBB208_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB208_5: # %atomicrmw.start ; RV32I-NEXT: .LBB208_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB208_1 ; RV32I-NEXT: bnez a0, .LBB208_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB208_1 ; RV32I-NEXT: j .LBB208_1
; RV32I-NEXT: .LBB208_7: # %atomicrmw.end ; RV32I-NEXT: .LBB208_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB208_3 ; RV32IA-NEXT: bne a5, s1, .LBB208_3
; RV32IA-NEXT: j .LBB208_4 ; RV32IA-NEXT: j .LBB208_4
; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB208_7 ; RV32IA-NEXT: bnez a0, .LBB208_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB208_4 ; RV32IA-NEXT: beq a5, s1, .LBB208_4
; RV32IA-NEXT: .LBB208_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB208_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB208_5 ; RV32IA-NEXT: j .LBB208_5
; RV32IA-NEXT: .LBB208_4: ; RV32IA-NEXT: .LBB208_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB208_1 ; RV32IA-NEXT: bnez a0, .LBB208_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB208_1 ; RV32IA-NEXT: j .LBB208_1
; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_acq_rel: ; RV64I-LABEL: atomicrmw_min_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB208_3 ; RV64I-NEXT: blt s1, a3, .LBB208_3
; RV64I-NEXT: .LBB208_1: # %atomicrmw.start ; RV64I-NEXT: .LBB208_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB208_4 ; RV64I-NEXT: bnez a0, .LBB208_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB208_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB208_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB208_1 ; RV64I-NEXT: bge s1, a3, .LBB208_1
; RV64I-NEXT: .LBB208_3: # %atomicrmw.start ; RV64I-NEXT: .LBB208_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB208_1 ; RV64I-NEXT: j .LBB208_1
; RV64I-NEXT: .LBB208_4: # %atomicrmw.end ; RV64I-NEXT: .LBB208_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b acq_rel %1 = atomicrmw min i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_seq_cst: ; RV32I-LABEL: atomicrmw_min_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB209_3 ; RV32I-NEXT: bne a5, s1, .LBB209_3
; RV32I-NEXT: j .LBB209_4 ; RV32I-NEXT: j .LBB209_4
; RV32I-NEXT: .LBB209_1: # %atomicrmw.start ; RV32I-NEXT: .LBB209_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB209_7 ; RV32I-NEXT: bnez a0, .LBB209_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB209_4 ; RV32I-NEXT: beq a5, s1, .LBB209_4
; RV32I-NEXT: .LBB209_3: # %atomicrmw.start ; RV32I-NEXT: .LBB209_3: # %atomicrmw.start
; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB209_5 ; RV32I-NEXT: j .LBB209_5
; RV32I-NEXT: .LBB209_4: ; RV32I-NEXT: .LBB209_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB209_5: # %atomicrmw.start ; RV32I-NEXT: .LBB209_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB209_1 ; RV32I-NEXT: bnez a0, .LBB209_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB209_1 ; RV32I-NEXT: j .LBB209_1
; RV32I-NEXT: .LBB209_7: # %atomicrmw.end ; RV32I-NEXT: .LBB209_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB209_3 ; RV32IA-NEXT: bne a5, s1, .LBB209_3
; RV32IA-NEXT: j .LBB209_4 ; RV32IA-NEXT: j .LBB209_4
; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB209_7 ; RV32IA-NEXT: bnez a0, .LBB209_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB209_4 ; RV32IA-NEXT: beq a5, s1, .LBB209_4
; RV32IA-NEXT: .LBB209_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB209_3: # %atomicrmw.start
; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB209_5 ; RV32IA-NEXT: j .LBB209_5
; RV32IA-NEXT: .LBB209_4: ; RV32IA-NEXT: .LBB209_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB209_1 ; RV32IA-NEXT: bnez a0, .LBB209_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB209_1 ; RV32IA-NEXT: j .LBB209_1
; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_seq_cst: ; RV64I-LABEL: atomicrmw_min_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s0, a2, .LBB209_3 ; RV64I-NEXT: blt s1, a3, .LBB209_3
; RV64I-NEXT: .LBB209_1: # %atomicrmw.start ; RV64I-NEXT: .LBB209_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB209_4 ; RV64I-NEXT: bnez a0, .LBB209_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB209_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB209_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s0, a2, .LBB209_1 ; RV64I-NEXT: bge s1, a3, .LBB209_1
; RV64I-NEXT: .LBB209_3: # %atomicrmw.start ; RV64I-NEXT: .LBB209_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB209_1 ; RV64I-NEXT: j .LBB209_1
; RV64I-NEXT: .LBB209_4: # %atomicrmw.end ; RV64I-NEXT: .LBB209_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b seq_cst %1 = atomicrmw min i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_monotonic: ; RV32I-LABEL: atomicrmw_umax_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB210_3 ; RV32I-NEXT: bne a5, s1, .LBB210_3
; RV32I-NEXT: j .LBB210_4 ; RV32I-NEXT: j .LBB210_4
; RV32I-NEXT: .LBB210_1: # %atomicrmw.start ; RV32I-NEXT: .LBB210_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB210_7 ; RV32I-NEXT: bnez a0, .LBB210_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB210_4 ; RV32I-NEXT: beq a5, s1, .LBB210_4
; RV32I-NEXT: .LBB210_3: # %atomicrmw.start ; RV32I-NEXT: .LBB210_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB210_5 ; RV32I-NEXT: j .LBB210_5
; RV32I-NEXT: .LBB210_4: ; RV32I-NEXT: .LBB210_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB210_5: # %atomicrmw.start ; RV32I-NEXT: .LBB210_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB210_1 ; RV32I-NEXT: bnez a0, .LBB210_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB210_1 ; RV32I-NEXT: j .LBB210_1
; RV32I-NEXT: .LBB210_7: # %atomicrmw.end ; RV32I-NEXT: .LBB210_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB210_3 ; RV32IA-NEXT: bne a5, s1, .LBB210_3
; RV32IA-NEXT: j .LBB210_4 ; RV32IA-NEXT: j .LBB210_4
; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB210_7 ; RV32IA-NEXT: bnez a0, .LBB210_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB210_4 ; RV32IA-NEXT: beq a5, s1, .LBB210_4
; RV32IA-NEXT: .LBB210_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB210_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB210_5 ; RV32IA-NEXT: j .LBB210_5
; RV32IA-NEXT: .LBB210_4: ; RV32IA-NEXT: .LBB210_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB210_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB210_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB210_1 ; RV32IA-NEXT: bnez a0, .LBB210_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB210_1 ; RV32IA-NEXT: j .LBB210_1
; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_monotonic: ; RV64I-LABEL: atomicrmw_umax_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB210_3 ; RV64I-NEXT: bgeu s1, a3, .LBB210_3
; RV64I-NEXT: .LBB210_1: # %atomicrmw.start ; RV64I-NEXT: .LBB210_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB210_4 ; RV64I-NEXT: bnez a0, .LBB210_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB210_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB210_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB210_1 ; RV64I-NEXT: bltu s1, a3, .LBB210_1
; RV64I-NEXT: .LBB210_3: # %atomicrmw.start ; RV64I-NEXT: .LBB210_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB210_1 ; RV64I-NEXT: j .LBB210_1
; RV64I-NEXT: .LBB210_4: # %atomicrmw.end ; RV64I-NEXT: .LBB210_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b monotonic %1 = atomicrmw umax i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_acquire: ; RV32I-LABEL: atomicrmw_umax_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB211_3 ; RV32I-NEXT: bne a5, s1, .LBB211_3
; RV32I-NEXT: j .LBB211_4 ; RV32I-NEXT: j .LBB211_4
; RV32I-NEXT: .LBB211_1: # %atomicrmw.start ; RV32I-NEXT: .LBB211_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB211_7 ; RV32I-NEXT: bnez a0, .LBB211_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB211_4 ; RV32I-NEXT: beq a5, s1, .LBB211_4
; RV32I-NEXT: .LBB211_3: # %atomicrmw.start ; RV32I-NEXT: .LBB211_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB211_5 ; RV32I-NEXT: j .LBB211_5
; RV32I-NEXT: .LBB211_4: ; RV32I-NEXT: .LBB211_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB211_5: # %atomicrmw.start ; RV32I-NEXT: .LBB211_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB211_1 ; RV32I-NEXT: bnez a0, .LBB211_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB211_1 ; RV32I-NEXT: j .LBB211_1
; RV32I-NEXT: .LBB211_7: # %atomicrmw.end ; RV32I-NEXT: .LBB211_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_acquire: ; RV32IA-LABEL: atomicrmw_umax_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB211_3 ; RV32IA-NEXT: bne a5, s1, .LBB211_3
; RV32IA-NEXT: j .LBB211_4 ; RV32IA-NEXT: j .LBB211_4
; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB211_7 ; RV32IA-NEXT: bnez a0, .LBB211_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB211_4 ; RV32IA-NEXT: beq a5, s1, .LBB211_4
; RV32IA-NEXT: .LBB211_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB211_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB211_5 ; RV32IA-NEXT: j .LBB211_5
; RV32IA-NEXT: .LBB211_4: ; RV32IA-NEXT: .LBB211_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB211_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB211_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB211_1 ; RV32IA-NEXT: bnez a0, .LBB211_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB211_1 ; RV32IA-NEXT: j .LBB211_1
; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_acquire: ; RV64I-LABEL: atomicrmw_umax_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB211_3 ; RV64I-NEXT: bgeu s1, a3, .LBB211_3
; RV64I-NEXT: .LBB211_1: # %atomicrmw.start ; RV64I-NEXT: .LBB211_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB211_4 ; RV64I-NEXT: bnez a0, .LBB211_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB211_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB211_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB211_1 ; RV64I-NEXT: bltu s1, a3, .LBB211_1
; RV64I-NEXT: .LBB211_3: # %atomicrmw.start ; RV64I-NEXT: .LBB211_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB211_1 ; RV64I-NEXT: j .LBB211_1
; RV64I-NEXT: .LBB211_4: # %atomicrmw.end ; RV64I-NEXT: .LBB211_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_acquire: ; RV64IA-LABEL: atomicrmw_umax_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b acquire %1 = atomicrmw umax i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_release: ; RV32I-LABEL: atomicrmw_umax_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB212_3 ; RV32I-NEXT: bne a5, s1, .LBB212_3
; RV32I-NEXT: j .LBB212_4 ; RV32I-NEXT: j .LBB212_4
; RV32I-NEXT: .LBB212_1: # %atomicrmw.start ; RV32I-NEXT: .LBB212_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB212_7 ; RV32I-NEXT: bnez a0, .LBB212_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB212_4 ; RV32I-NEXT: beq a5, s1, .LBB212_4
; RV32I-NEXT: .LBB212_3: # %atomicrmw.start ; RV32I-NEXT: .LBB212_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB212_5 ; RV32I-NEXT: j .LBB212_5
; RV32I-NEXT: .LBB212_4: ; RV32I-NEXT: .LBB212_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB212_5: # %atomicrmw.start ; RV32I-NEXT: .LBB212_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB212_1 ; RV32I-NEXT: bnez a0, .LBB212_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB212_1 ; RV32I-NEXT: j .LBB212_1
; RV32I-NEXT: .LBB212_7: # %atomicrmw.end ; RV32I-NEXT: .LBB212_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_release: ; RV32IA-LABEL: atomicrmw_umax_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB212_3 ; RV32IA-NEXT: bne a5, s1, .LBB212_3
; RV32IA-NEXT: j .LBB212_4 ; RV32IA-NEXT: j .LBB212_4
; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB212_7 ; RV32IA-NEXT: bnez a0, .LBB212_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB212_4 ; RV32IA-NEXT: beq a5, s1, .LBB212_4
; RV32IA-NEXT: .LBB212_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB212_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB212_5 ; RV32IA-NEXT: j .LBB212_5
; RV32IA-NEXT: .LBB212_4: ; RV32IA-NEXT: .LBB212_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB212_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB212_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB212_1 ; RV32IA-NEXT: bnez a0, .LBB212_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB212_1 ; RV32IA-NEXT: j .LBB212_1
; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_release: ; RV64I-LABEL: atomicrmw_umax_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB212_3 ; RV64I-NEXT: bgeu s1, a3, .LBB212_3
; RV64I-NEXT: .LBB212_1: # %atomicrmw.start ; RV64I-NEXT: .LBB212_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB212_4 ; RV64I-NEXT: bnez a0, .LBB212_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB212_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB212_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB212_1 ; RV64I-NEXT: bltu s1, a3, .LBB212_1
; RV64I-NEXT: .LBB212_3: # %atomicrmw.start ; RV64I-NEXT: .LBB212_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB212_1 ; RV64I-NEXT: j .LBB212_1
; RV64I-NEXT: .LBB212_4: # %atomicrmw.end ; RV64I-NEXT: .LBB212_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_release: ; RV64IA-LABEL: atomicrmw_umax_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b release %1 = atomicrmw umax i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB213_3 ; RV32I-NEXT: bne a5, s1, .LBB213_3
; RV32I-NEXT: j .LBB213_4 ; RV32I-NEXT: j .LBB213_4
; RV32I-NEXT: .LBB213_1: # %atomicrmw.start ; RV32I-NEXT: .LBB213_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB213_7 ; RV32I-NEXT: bnez a0, .LBB213_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB213_4 ; RV32I-NEXT: beq a5, s1, .LBB213_4
; RV32I-NEXT: .LBB213_3: # %atomicrmw.start ; RV32I-NEXT: .LBB213_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB213_5 ; RV32I-NEXT: j .LBB213_5
; RV32I-NEXT: .LBB213_4: ; RV32I-NEXT: .LBB213_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB213_5: # %atomicrmw.start ; RV32I-NEXT: .LBB213_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB213_1 ; RV32I-NEXT: bnez a0, .LBB213_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB213_1 ; RV32I-NEXT: j .LBB213_1
; RV32I-NEXT: .LBB213_7: # %atomicrmw.end ; RV32I-NEXT: .LBB213_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB213_3 ; RV32IA-NEXT: bne a5, s1, .LBB213_3
; RV32IA-NEXT: j .LBB213_4 ; RV32IA-NEXT: j .LBB213_4
; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB213_7 ; RV32IA-NEXT: bnez a0, .LBB213_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB213_4 ; RV32IA-NEXT: beq a5, s1, .LBB213_4
; RV32IA-NEXT: .LBB213_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB213_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB213_5 ; RV32IA-NEXT: j .LBB213_5
; RV32IA-NEXT: .LBB213_4: ; RV32IA-NEXT: .LBB213_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB213_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB213_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB213_1 ; RV32IA-NEXT: bnez a0, .LBB213_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB213_1 ; RV32IA-NEXT: j .LBB213_1
; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB213_3 ; RV64I-NEXT: bgeu s1, a3, .LBB213_3
; RV64I-NEXT: .LBB213_1: # %atomicrmw.start ; RV64I-NEXT: .LBB213_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB213_4 ; RV64I-NEXT: bnez a0, .LBB213_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB213_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB213_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB213_1 ; RV64I-NEXT: bltu s1, a3, .LBB213_1
; RV64I-NEXT: .LBB213_3: # %atomicrmw.start ; RV64I-NEXT: .LBB213_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB213_1 ; RV64I-NEXT: j .LBB213_1
; RV64I-NEXT: .LBB213_4: # %atomicrmw.end ; RV64I-NEXT: .LBB213_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b acq_rel %1 = atomicrmw umax i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB214_3 ; RV32I-NEXT: bne a5, s1, .LBB214_3
; RV32I-NEXT: j .LBB214_4 ; RV32I-NEXT: j .LBB214_4
; RV32I-NEXT: .LBB214_1: # %atomicrmw.start ; RV32I-NEXT: .LBB214_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB214_7 ; RV32I-NEXT: bnez a0, .LBB214_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB214_4 ; RV32I-NEXT: beq a5, s1, .LBB214_4
; RV32I-NEXT: .LBB214_3: # %atomicrmw.start ; RV32I-NEXT: .LBB214_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB214_5 ; RV32I-NEXT: j .LBB214_5
; RV32I-NEXT: .LBB214_4: ; RV32I-NEXT: .LBB214_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB214_5: # %atomicrmw.start ; RV32I-NEXT: .LBB214_5: # %atomicrmw.start
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB214_1 ; RV32I-NEXT: bnez a0, .LBB214_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB214_1 ; RV32I-NEXT: j .LBB214_1
; RV32I-NEXT: .LBB214_7: # %atomicrmw.end ; RV32I-NEXT: .LBB214_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB214_3 ; RV32IA-NEXT: bne a5, s1, .LBB214_3
; RV32IA-NEXT: j .LBB214_4 ; RV32IA-NEXT: j .LBB214_4
; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB214_7 ; RV32IA-NEXT: bnez a0, .LBB214_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB214_4 ; RV32IA-NEXT: beq a5, s1, .LBB214_4
; RV32IA-NEXT: .LBB214_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB214_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB214_5 ; RV32IA-NEXT: j .LBB214_5
; RV32IA-NEXT: .LBB214_4: ; RV32IA-NEXT: .LBB214_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB214_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB214_5: # %atomicrmw.start
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB214_1 ; RV32IA-NEXT: bnez a0, .LBB214_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB214_1 ; RV32IA-NEXT: j .LBB214_1
; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB214_3 ; RV64I-NEXT: bgeu s1, a3, .LBB214_3
; RV64I-NEXT: .LBB214_1: # %atomicrmw.start ; RV64I-NEXT: .LBB214_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB214_4 ; RV64I-NEXT: bnez a0, .LBB214_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB214_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB214_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB214_1 ; RV64I-NEXT: bltu s1, a3, .LBB214_1
; RV64I-NEXT: .LBB214_3: # %atomicrmw.start ; RV64I-NEXT: .LBB214_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB214_1 ; RV64I-NEXT: j .LBB214_1
; RV64I-NEXT: .LBB214_4: # %atomicrmw.end ; RV64I-NEXT: .LBB214_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b seq_cst %1 = atomicrmw umax i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_monotonic: ; RV32I-LABEL: atomicrmw_umin_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB215_3 ; RV32I-NEXT: bne a5, s1, .LBB215_3
; RV32I-NEXT: j .LBB215_4 ; RV32I-NEXT: j .LBB215_4
; RV32I-NEXT: .LBB215_1: # %atomicrmw.start ; RV32I-NEXT: .LBB215_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB215_7 ; RV32I-NEXT: bnez a0, .LBB215_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB215_4 ; RV32I-NEXT: beq a5, s1, .LBB215_4
; RV32I-NEXT: .LBB215_3: # %atomicrmw.start ; RV32I-NEXT: .LBB215_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB215_5 ; RV32I-NEXT: j .LBB215_5
; RV32I-NEXT: .LBB215_4: ; RV32I-NEXT: .LBB215_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB215_5: # %atomicrmw.start ; RV32I-NEXT: .LBB215_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB215_1 ; RV32I-NEXT: bnez a0, .LBB215_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB215_1 ; RV32I-NEXT: j .LBB215_1
; RV32I-NEXT: .LBB215_7: # %atomicrmw.end ; RV32I-NEXT: .LBB215_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB215_3 ; RV32IA-NEXT: bne a5, s1, .LBB215_3
; RV32IA-NEXT: j .LBB215_4 ; RV32IA-NEXT: j .LBB215_4
; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB215_7 ; RV32IA-NEXT: bnez a0, .LBB215_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB215_4 ; RV32IA-NEXT: beq a5, s1, .LBB215_4
; RV32IA-NEXT: .LBB215_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB215_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB215_5 ; RV32IA-NEXT: j .LBB215_5
; RV32IA-NEXT: .LBB215_4: ; RV32IA-NEXT: .LBB215_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB215_1 ; RV32IA-NEXT: bnez a0, .LBB215_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB215_1 ; RV32IA-NEXT: j .LBB215_1
; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_monotonic: ; RV64I-LABEL: atomicrmw_umin_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB215_3 ; RV64I-NEXT: bltu s1, a3, .LBB215_3
; RV64I-NEXT: .LBB215_1: # %atomicrmw.start ; RV64I-NEXT: .LBB215_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB215_4 ; RV64I-NEXT: bnez a0, .LBB215_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB215_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB215_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB215_1 ; RV64I-NEXT: bgeu s1, a3, .LBB215_1
; RV64I-NEXT: .LBB215_3: # %atomicrmw.start ; RV64I-NEXT: .LBB215_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB215_1 ; RV64I-NEXT: j .LBB215_1
; RV64I-NEXT: .LBB215_4: # %atomicrmw.end ; RV64I-NEXT: .LBB215_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d a0, a1, (a0) ; RV64IA-NEXT: amominu.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b monotonic %1 = atomicrmw umin i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_acquire: ; RV32I-LABEL: atomicrmw_umin_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB216_3 ; RV32I-NEXT: bne a5, s1, .LBB216_3
; RV32I-NEXT: j .LBB216_4 ; RV32I-NEXT: j .LBB216_4
; RV32I-NEXT: .LBB216_1: # %atomicrmw.start ; RV32I-NEXT: .LBB216_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB216_7 ; RV32I-NEXT: bnez a0, .LBB216_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB216_4 ; RV32I-NEXT: beq a5, s1, .LBB216_4
; RV32I-NEXT: .LBB216_3: # %atomicrmw.start ; RV32I-NEXT: .LBB216_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB216_5 ; RV32I-NEXT: j .LBB216_5
; RV32I-NEXT: .LBB216_4: ; RV32I-NEXT: .LBB216_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB216_5: # %atomicrmw.start ; RV32I-NEXT: .LBB216_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB216_1 ; RV32I-NEXT: bnez a0, .LBB216_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB216_1 ; RV32I-NEXT: j .LBB216_1
; RV32I-NEXT: .LBB216_7: # %atomicrmw.end ; RV32I-NEXT: .LBB216_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_acquire: ; RV32IA-LABEL: atomicrmw_umin_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB216_3 ; RV32IA-NEXT: bne a5, s1, .LBB216_3
; RV32IA-NEXT: j .LBB216_4 ; RV32IA-NEXT: j .LBB216_4
; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB216_7 ; RV32IA-NEXT: bnez a0, .LBB216_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB216_4 ; RV32IA-NEXT: beq a5, s1, .LBB216_4
; RV32IA-NEXT: .LBB216_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB216_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB216_5 ; RV32IA-NEXT: j .LBB216_5
; RV32IA-NEXT: .LBB216_4: ; RV32IA-NEXT: .LBB216_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB216_1 ; RV32IA-NEXT: bnez a0, .LBB216_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB216_1 ; RV32IA-NEXT: j .LBB216_1
; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_acquire: ; RV64I-LABEL: atomicrmw_umin_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB216_3 ; RV64I-NEXT: bltu s1, a3, .LBB216_3
; RV64I-NEXT: .LBB216_1: # %atomicrmw.start ; RV64I-NEXT: .LBB216_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB216_4 ; RV64I-NEXT: bnez a0, .LBB216_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB216_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB216_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB216_1 ; RV64I-NEXT: bgeu s1, a3, .LBB216_1
; RV64I-NEXT: .LBB216_3: # %atomicrmw.start ; RV64I-NEXT: .LBB216_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB216_1 ; RV64I-NEXT: j .LBB216_1
; RV64I-NEXT: .LBB216_4: # %atomicrmw.end ; RV64I-NEXT: .LBB216_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_acquire: ; RV64IA-LABEL: atomicrmw_umin_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aq a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b acquire %1 = atomicrmw umin i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_release: ; RV32I-LABEL: atomicrmw_umin_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB217_3 ; RV32I-NEXT: bne a5, s1, .LBB217_3
; RV32I-NEXT: j .LBB217_4 ; RV32I-NEXT: j .LBB217_4
; RV32I-NEXT: .LBB217_1: # %atomicrmw.start ; RV32I-NEXT: .LBB217_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB217_7 ; RV32I-NEXT: bnez a0, .LBB217_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB217_4 ; RV32I-NEXT: beq a5, s1, .LBB217_4
; RV32I-NEXT: .LBB217_3: # %atomicrmw.start ; RV32I-NEXT: .LBB217_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB217_5 ; RV32I-NEXT: j .LBB217_5
; RV32I-NEXT: .LBB217_4: ; RV32I-NEXT: .LBB217_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB217_5: # %atomicrmw.start ; RV32I-NEXT: .LBB217_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB217_1 ; RV32I-NEXT: bnez a0, .LBB217_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB217_1 ; RV32I-NEXT: j .LBB217_1
; RV32I-NEXT: .LBB217_7: # %atomicrmw.end ; RV32I-NEXT: .LBB217_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_release: ; RV32IA-LABEL: atomicrmw_umin_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB217_3 ; RV32IA-NEXT: bne a5, s1, .LBB217_3
; RV32IA-NEXT: j .LBB217_4 ; RV32IA-NEXT: j .LBB217_4
; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB217_7 ; RV32IA-NEXT: bnez a0, .LBB217_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB217_4 ; RV32IA-NEXT: beq a5, s1, .LBB217_4
; RV32IA-NEXT: .LBB217_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB217_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB217_5 ; RV32IA-NEXT: j .LBB217_5
; RV32IA-NEXT: .LBB217_4: ; RV32IA-NEXT: .LBB217_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB217_1 ; RV32IA-NEXT: bnez a0, .LBB217_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB217_1 ; RV32IA-NEXT: j .LBB217_1
; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_release: ; RV64I-LABEL: atomicrmw_umin_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB217_3 ; RV64I-NEXT: bltu s1, a3, .LBB217_3
; RV64I-NEXT: .LBB217_1: # %atomicrmw.start ; RV64I-NEXT: .LBB217_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB217_4 ; RV64I-NEXT: bnez a0, .LBB217_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB217_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB217_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB217_1 ; RV64I-NEXT: bgeu s1, a3, .LBB217_1
; RV64I-NEXT: .LBB217_3: # %atomicrmw.start ; RV64I-NEXT: .LBB217_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB217_1 ; RV64I-NEXT: j .LBB217_1
; RV64I-NEXT: .LBB217_4: # %atomicrmw.end ; RV64I-NEXT: .LBB217_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_release: ; RV64IA-LABEL: atomicrmw_umin_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.rl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b release %1 = atomicrmw umin i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB218_3 ; RV32I-NEXT: bne a5, s1, .LBB218_3
; RV32I-NEXT: j .LBB218_4 ; RV32I-NEXT: j .LBB218_4
; RV32I-NEXT: .LBB218_1: # %atomicrmw.start ; RV32I-NEXT: .LBB218_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB218_7 ; RV32I-NEXT: bnez a0, .LBB218_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB218_4 ; RV32I-NEXT: beq a5, s1, .LBB218_4
; RV32I-NEXT: .LBB218_3: # %atomicrmw.start ; RV32I-NEXT: .LBB218_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB218_5 ; RV32I-NEXT: j .LBB218_5
; RV32I-NEXT: .LBB218_4: ; RV32I-NEXT: .LBB218_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB218_5: # %atomicrmw.start ; RV32I-NEXT: .LBB218_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB218_1 ; RV32I-NEXT: bnez a0, .LBB218_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB218_1 ; RV32I-NEXT: j .LBB218_1
; RV32I-NEXT: .LBB218_7: # %atomicrmw.end ; RV32I-NEXT: .LBB218_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB218_3 ; RV32IA-NEXT: bne a5, s1, .LBB218_3
; RV32IA-NEXT: j .LBB218_4 ; RV32IA-NEXT: j .LBB218_4
; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB218_7 ; RV32IA-NEXT: bnez a0, .LBB218_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB218_4 ; RV32IA-NEXT: beq a5, s1, .LBB218_4
; RV32IA-NEXT: .LBB218_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB218_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB218_5 ; RV32IA-NEXT: j .LBB218_5
; RV32IA-NEXT: .LBB218_4: ; RV32IA-NEXT: .LBB218_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB218_1 ; RV32IA-NEXT: bnez a0, .LBB218_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB218_1 ; RV32IA-NEXT: j .LBB218_1
; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB218_3 ; RV64I-NEXT: bltu s1, a3, .LBB218_3
; RV64I-NEXT: .LBB218_1: # %atomicrmw.start ; RV64I-NEXT: .LBB218_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB218_4 ; RV64I-NEXT: bnez a0, .LBB218_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB218_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB218_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB218_1 ; RV64I-NEXT: bgeu s1, a3, .LBB218_1
; RV64I-NEXT: .LBB218_3: # %atomicrmw.start ; RV64I-NEXT: .LBB218_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB218_1 ; RV64I-NEXT: j .LBB218_1
; RV64I-NEXT: .LBB218_4: # %atomicrmw.end ; RV64I-NEXT: .LBB218_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b acq_rel %1 = atomicrmw umin i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: mv s3, sp ; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: bne a1, s0, .LBB219_3 ; RV32I-NEXT: bne a5, s1, .LBB219_3
; RV32I-NEXT: j .LBB219_4 ; RV32I-NEXT: j .LBB219_4
; RV32I-NEXT: .LBB219_1: # %atomicrmw.start ; RV32I-NEXT: .LBB219_1: # %atomicrmw.start
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a4, 0(sp)
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw a1, 4(sp) ; RV32I-NEXT: lw a5, 4(sp)
; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: lw a4, 0(sp)
; RV32I-NEXT: bnez a0, .LBB219_7 ; RV32I-NEXT: bnez a0, .LBB219_7
; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
; RV32I-NEXT: beq a1, s0, .LBB219_4 ; RV32I-NEXT: beq a5, s1, .LBB219_4
; RV32I-NEXT: .LBB219_3: # %atomicrmw.start ; RV32I-NEXT: .LBB219_3: # %atomicrmw.start
; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB219_5 ; RV32I-NEXT: j .LBB219_5
; RV32I-NEXT: .LBB219_4: ; RV32I-NEXT: .LBB219_4:
; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB219_5: # %atomicrmw.start ; RV32I-NEXT: .LBB219_5: # %atomicrmw.start
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: sw a2, 0(sp) ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB219_1 ; RV32I-NEXT: bnez a0, .LBB219_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB219_1 ; RV32I-NEXT: j .LBB219_1
; RV32I-NEXT: .LBB219_7: # %atomicrmw.end ; RV32I-NEXT: .LBB219_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp)
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp)
; RV32IA-NEXT: sw s3, 12(sp) ; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: mv s1, a0
; RV32IA-NEXT: lw a1, 4(a0)
; RV32IA-NEXT: lw a2, 0(a0)
; RV32IA-NEXT: mv s3, sp ; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: bne a1, s0, .LBB219_3 ; RV32IA-NEXT: bne a5, s1, .LBB219_3
; RV32IA-NEXT: j .LBB219_4 ; RV32IA-NEXT: j .LBB219_4
; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start
; RV32IA-NEXT: sw a1, 4(sp) ; RV32IA-NEXT: sw a4, 0(sp)
; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: sw a5, 4(sp)
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw a1, 4(sp) ; RV32IA-NEXT: lw a5, 4(sp)
; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: lw a4, 0(sp)
; RV32IA-NEXT: bnez a0, .LBB219_7 ; RV32IA-NEXT: bnez a0, .LBB219_7
; RV32IA-NEXT: # %bb.2: # %atomicrmw.start ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
; RV32IA-NEXT: beq a1, s0, .LBB219_4 ; RV32IA-NEXT: beq a5, s1, .LBB219_4
; RV32IA-NEXT: .LBB219_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB219_3: # %atomicrmw.start
; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB219_5 ; RV32IA-NEXT: j .LBB219_5
; RV32IA-NEXT: .LBB219_4: ; RV32IA-NEXT: .LBB219_4:
; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start
; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: sw a2, 0(sp) ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB219_1 ; RV32IA-NEXT: bnez a0, .LBB219_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB219_1 ; RV32IA-NEXT: j .LBB219_1
; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp)
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp)
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: addi s2, sp, 8 ; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s0, a2, .LBB219_3 ; RV64I-NEXT: bltu s1, a3, .LBB219_3
; RV64I-NEXT: .LBB219_1: # %atomicrmw.start ; RV64I-NEXT: .LBB219_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: sd a3, 8(sp)
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: ld a3, 8(sp)
; RV64I-NEXT: bnez a0, .LBB219_4 ; RV64I-NEXT: bnez a0, .LBB219_4
; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # %bb.2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB219_1 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB219_1 Depth=1
; RV64I-NEXT: sd a2, 8(sp) ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s0, a2, .LBB219_1 ; RV64I-NEXT: bgeu s1, a3, .LBB219_1
; RV64I-NEXT: .LBB219_3: # %atomicrmw.start ; RV64I-NEXT: .LBB219_3: # %atomicrmw.start
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB219_1 ; RV64I-NEXT: j .LBB219_1
; RV64I-NEXT: .LBB219_4: # %atomicrmw.end ; RV64I-NEXT: .LBB219_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b seq_cst %1 = atomicrmw umin i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/bare-select.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select: ; RV32I-LABEL: bare_select:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a3, a0, 1
; RV32I-NEXT: bnez a0, .LBB0_2 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a3, .LBB0_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c %1 = select i1 %a, i32 %b, i32 %c
ret i32 %1 ret i32 %1
} }
define float @bare_select_float(i1 %a, float %b, float %c) nounwind { define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32I-LABEL: bare_select_float: ; RV32I-LABEL: bare_select_float:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a3, a0, 1
; RV32I-NEXT: bnez a0, .LBB1_2 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a3, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = select i1 %a, float %b, float %c %1 = select i1 %a, float %b, float %c
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/blockaddress.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
@addr = global i8* null @addr = global i8* null
define void @test_blockaddress() nounwind { define void @test_blockaddress() nounwind {
; RV32I-LABEL: test_blockaddress: ; RV32I-LABEL: test_blockaddress:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a0, %hi(.Ltmp0) ; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: addi a0, a0, %lo(.Ltmp0) ; RV32I-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-NEXT: lui a1, %hi(addr) ; RV32I-NEXT: addi a1, a1, %lo(.Ltmp0)
; RV32I-NEXT: sw a0, %lo(addr)(a1) ; RV32I-NEXT: sw a1, %lo(addr)(a0)
; RV32I-NEXT: lw a0, %lo(addr)(a1) ; RV32I-NEXT: lw a0, %lo(addr)(a0)
; RV32I-NEXT: jr a0 ; RV32I-NEXT: jr a0
; RV32I-NEXT: .Ltmp0: # Block address taken ; RV32I-NEXT: .Ltmp0: # Block address taken
; RV32I-NEXT: .LBB0_1: # %block ; RV32I-NEXT: .LBB0_1: # %block
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
%val = load volatile i8*, i8** @addr %val = load volatile i8*, i8** @addr
indirectbr i8* %val, [label %block] indirectbr i8* %val, [label %block]
block: block:
ret void ret void
} }

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

Show All 23 Lines
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a) %tmp = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %tmp ret i16 %tmp
} }
define i32 @test_bswap_i32(i32 %a) nounwind { define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32: ; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: addi a1, a1, -256 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: srli a2, a0, 8 ; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a) %tmp = call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @test_bswap_i64(i64 %a) nounwind { define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64: ; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, -256
; RV32I-NEXT: srli a2, a1, 8 ; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: lui a5, 4080 ; RV32I-NEXT: lui a5, 4080
; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a1, a1, a4
Show All 19 Lines
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_2 ; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 24 Lines
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1 ; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: beqz a1, .LBB4_2 ; RV32I-NEXT: beqz a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 21 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: beqz a0, .LBB5_2 ; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 28 Lines
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 28 Lines
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw s6, 0(sp) ; RV32I-NEXT: sw s6, 0(sp)
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi s5, a1, 1365
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s6, a1, 257
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s1, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB7_2 ; RV32I-NEXT: bnez s4, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3 ; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s2, 24
Show All 16 Lines
define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind { define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8_zero_undef: ; RV32I-LABEL: test_cttz_i8_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 15 Lines
define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind { define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16_zero_undef: ; RV32I-LABEL: test_cttz_i16_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 15 Lines
define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32_zero_undef: ; RV32I-LABEL: test_cttz_i32_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 24 Lines
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw s6, 0(sp) ; RV32I-NEXT: sw s6, 0(sp)
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi s5, a1, 1365
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s6, a1, 257
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s1, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB11_2 ; RV32I-NEXT: bnez s4, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3 ; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s2, 24
Show All 13 Lines; RV32I-NEXT: ret
ret i64 %tmp ret i64 %tmp
} }
define i32 @test_ctpop_i32(i32 %a) nounwind { define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctpop_i32: ; RV32I-LABEL: test_ctpop_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
Show All 14 Lines

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

Show All 17 Lines
; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
; something appropriate. ; something appropriate.
define void @callee() nounwind { define void @callee() nounwind {
; ILP32-LP64-LABEL: callee: ; ILP32-LP64-LABEL: callee:
; ILP32-LP64: # %bb.0: ; ILP32-LP64: # %bb.0:
; ILP32-LP64-NEXT: lui a0, %hi(var) ; ILP32-LP64-NEXT: lui a0, %hi(var)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: flw ft0, %lo(var)(a0) ; ILP32-LP64-NEXT: flw ft0, %lo(var)(a0)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: flw ft1, 4(a1) ; ILP32-LP64-NEXT: flw ft1, 4(a1)
; ILP32-LP64-NEXT: flw ft2, 8(a1) ; ILP32-LP64-NEXT: flw ft2, 8(a1)
; ILP32-LP64-NEXT: flw ft3, 12(a1) ; ILP32-LP64-NEXT: flw ft3, 12(a1)
; ILP32-LP64-NEXT: flw ft4, 16(a1) ; ILP32-LP64-NEXT: flw ft4, 16(a1)
; ILP32-LP64-NEXT: flw ft5, 20(a1) ; ILP32-LP64-NEXT: flw ft5, 20(a1)
; ILP32-LP64-NEXT: flw ft6, 24(a1) ; ILP32-LP64-NEXT: flw ft6, 24(a1)
; ILP32-LP64-NEXT: flw ft7, 28(a1) ; ILP32-LP64-NEXT: flw ft7, 28(a1)
; ILP32-LP64-NEXT: flw fa0, 32(a1) ; ILP32-LP64-NEXT: flw fa0, 32(a1)
Show All 11 Lines
; ILP32-LP64-NEXT: flw fs0, 80(a1) ; ILP32-LP64-NEXT: flw fs0, 80(a1)
; ILP32-LP64-NEXT: flw fs1, 84(a1) ; ILP32-LP64-NEXT: flw fs1, 84(a1)
; ILP32-LP64-NEXT: flw fs2, 88(a1) ; ILP32-LP64-NEXT: flw fs2, 88(a1)
; ILP32-LP64-NEXT: flw fs3, 92(a1) ; ILP32-LP64-NEXT: flw fs3, 92(a1)
; ILP32-LP64-NEXT: flw fs4, 96(a1) ; ILP32-LP64-NEXT: flw fs4, 96(a1)
; ILP32-LP64-NEXT: flw fs5, 100(a1) ; ILP32-LP64-NEXT: flw fs5, 100(a1)
; ILP32-LP64-NEXT: flw fs6, 104(a1) ; ILP32-LP64-NEXT: flw fs6, 104(a1)
; ILP32-LP64-NEXT: flw fs7, 108(a1) ; ILP32-LP64-NEXT: flw fs7, 108(a1)
; ILP32-LP64-NEXT: flw fs8, 112(a1) ; ILP32-LP64-NEXT: flw fs8, 124(a1)
; ILP32-LP64-NEXT: flw fs9, 116(a1) ; ILP32-LP64-NEXT: flw fs9, 120(a1)
; ILP32-LP64-NEXT: flw fs10, 120(a1) ; ILP32-LP64-NEXT: flw fs10, 116(a1)
; ILP32-LP64-NEXT: flw fs11, 124(a1) ; ILP32-LP64-NEXT: flw fs11, 112(a1)
; ILP32-LP64-NEXT: fsw fs11, 124(a1) ; ILP32-LP64-NEXT: fsw fs8, 124(a1)
; ILP32-LP64-NEXT: fsw fs10, 120(a1) ; ILP32-LP64-NEXT: fsw fs9, 120(a1)
; ILP32-LP64-NEXT: fsw fs9, 116(a1) ; ILP32-LP64-NEXT: fsw fs10, 116(a1)
; ILP32-LP64-NEXT: fsw fs8, 112(a1) ; ILP32-LP64-NEXT: fsw fs11, 112(a1)
; ILP32-LP64-NEXT: fsw fs7, 108(a1) ; ILP32-LP64-NEXT: fsw fs7, 108(a1)
; ILP32-LP64-NEXT: fsw fs6, 104(a1) ; ILP32-LP64-NEXT: fsw fs6, 104(a1)
; ILP32-LP64-NEXT: fsw fs5, 100(a1) ; ILP32-LP64-NEXT: fsw fs5, 100(a1)
; ILP32-LP64-NEXT: fsw fs4, 96(a1) ; ILP32-LP64-NEXT: fsw fs4, 96(a1)
; ILP32-LP64-NEXT: fsw fs3, 92(a1) ; ILP32-LP64-NEXT: fsw fs3, 92(a1)
; ILP32-LP64-NEXT: fsw fs2, 88(a1) ; ILP32-LP64-NEXT: fsw fs2, 88(a1)
; ILP32-LP64-NEXT: fsw fs1, 84(a1) ; ILP32-LP64-NEXT: fsw fs1, 84(a1)
; ILP32-LP64-NEXT: fsw fs0, 80(a1) ; ILP32-LP64-NEXT: fsw fs0, 80(a1)
Show All 30 Lines
; ILP32F-LP64F-NEXT: fsw fs5, 24(sp) ; ILP32F-LP64F-NEXT: fsw fs5, 24(sp)
; ILP32F-LP64F-NEXT: fsw fs6, 20(sp) ; ILP32F-LP64F-NEXT: fsw fs6, 20(sp)
; ILP32F-LP64F-NEXT: fsw fs7, 16(sp) ; ILP32F-LP64F-NEXT: fsw fs7, 16(sp)
; ILP32F-LP64F-NEXT: fsw fs8, 12(sp) ; ILP32F-LP64F-NEXT: fsw fs8, 12(sp)
; ILP32F-LP64F-NEXT: fsw fs9, 8(sp) ; ILP32F-LP64F-NEXT: fsw fs9, 8(sp)
; ILP32F-LP64F-NEXT: fsw fs10, 4(sp) ; ILP32F-LP64F-NEXT: fsw fs10, 4(sp)
; ILP32F-LP64F-NEXT: fsw fs11, 0(sp) ; ILP32F-LP64F-NEXT: fsw fs11, 0(sp)
; ILP32F-LP64F-NEXT: lui a0, %hi(var) ; ILP32F-LP64F-NEXT: lui a0, %hi(var)
; ILP32F-LP64F-NEXT: flw ft0, %lo(var)(a0)
lenaryUnsubmitted
Not Done
ReplyInline Actions

I don't know where this came from, but having both flw ... %lo(var)(a0) followed by addi ... %lo(var) does not seem so amenable for linker relaxation, though @jrtc27 would have a better idea about this than me.

lenary: I don't know where this came from, but having both `flw ... %lo(var)(a0)` followed by `addi ...
; ILP32F-LP64F-NEXT: addi a1, a0, %lo(var) ; ILP32F-LP64F-NEXT: addi a1, a0, %lo(var)
; ;
; ILP32D-LP64D-LABEL: callee: ; ILP32D-LP64D-LABEL: callee:
; ILP32D-LP64D: # %bb.0: ; ILP32D-LP64D: # %bb.0:
; ILP32D-LP64D-NEXT: addi sp, sp, -96 ; ILP32D-LP64D-NEXT: addi sp, sp, -96
; ILP32D-LP64D-NEXT: fsd fs0, 88(sp) ; ILP32D-LP64D-NEXT: fsd fs0, 88(sp)
; ILP32D-LP64D-NEXT: fsd fs1, 80(sp) ; ILP32D-LP64D-NEXT: fsd fs1, 80(sp)
; ILP32D-LP64D-NEXT: fsd fs2, 72(sp) ; ILP32D-LP64D-NEXT: fsd fs2, 72(sp)
; ILP32D-LP64D-NEXT: fsd fs3, 64(sp) ; ILP32D-LP64D-NEXT: fsd fs3, 64(sp)
; ILP32D-LP64D-NEXT: fsd fs4, 56(sp) ; ILP32D-LP64D-NEXT: fsd fs4, 56(sp)
; ILP32D-LP64D-NEXT: fsd fs5, 48(sp) ; ILP32D-LP64D-NEXT: fsd fs5, 48(sp)
; ILP32D-LP64D-NEXT: fsd fs6, 40(sp) ; ILP32D-LP64D-NEXT: fsd fs6, 40(sp)
; ILP32D-LP64D-NEXT: fsd fs7, 32(sp) ; ILP32D-LP64D-NEXT: fsd fs7, 32(sp)
; ILP32D-LP64D-NEXT: fsd fs8, 24(sp) ; ILP32D-LP64D-NEXT: fsd fs8, 24(sp)
; ILP32D-LP64D-NEXT: fsd fs9, 16(sp) ; ILP32D-LP64D-NEXT: fsd fs9, 16(sp)
; ILP32D-LP64D-NEXT: fsd fs10, 8(sp) ; ILP32D-LP64D-NEXT: fsd fs10, 8(sp)
; ILP32D-LP64D-NEXT: fsd fs11, 0(sp) ; ILP32D-LP64D-NEXT: fsd fs11, 0(sp)
; ILP32D-LP64D-NEXT: lui a0, %hi(var) ; ILP32D-LP64D-NEXT: lui a0, %hi(var)
; ILP32D-LP64D-NEXT: flw ft0, %lo(var)(a0)
; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var) ; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var)
%val = load [32 x float], [32 x float]* @var %val = load [32 x float], [32 x float]* @var
store volatile [32 x float] %val, [32 x float]* @var store volatile [32 x float] %val, [32 x float]* @var
ret void ret void
} }
; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
; something appropriate. ; something appropriate.
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

Show All 13 Lines
; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
; something appropriate. ; something appropriate.
define void @callee() nounwind { define void @callee() nounwind {
; ILP32-LP64-LABEL: callee: ; ILP32-LP64-LABEL: callee:
; ILP32-LP64: # %bb.0: ; ILP32-LP64: # %bb.0:
; ILP32-LP64-NEXT: lui a0, %hi(var) ; ILP32-LP64-NEXT: lui a0, %hi(var)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: fld ft0, %lo(var)(a0) ; ILP32-LP64-NEXT: fld ft0, %lo(var)(a0)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: fld ft1, 8(a1) ; ILP32-LP64-NEXT: fld ft1, 8(a1)
; ILP32-LP64-NEXT: fld ft2, 16(a1) ; ILP32-LP64-NEXT: fld ft2, 16(a1)
; ILP32-LP64-NEXT: fld ft3, 24(a1) ; ILP32-LP64-NEXT: fld ft3, 24(a1)
; ILP32-LP64-NEXT: fld ft4, 32(a1) ; ILP32-LP64-NEXT: fld ft4, 32(a1)
; ILP32-LP64-NEXT: fld ft5, 40(a1) ; ILP32-LP64-NEXT: fld ft5, 40(a1)
; ILP32-LP64-NEXT: fld ft6, 48(a1) ; ILP32-LP64-NEXT: fld ft6, 48(a1)
; ILP32-LP64-NEXT: fld ft7, 56(a1) ; ILP32-LP64-NEXT: fld ft7, 56(a1)
; ILP32-LP64-NEXT: fld fa0, 64(a1) ; ILP32-LP64-NEXT: fld fa0, 64(a1)
Show All 11 Lines
; ILP32-LP64-NEXT: fld fs0, 160(a1) ; ILP32-LP64-NEXT: fld fs0, 160(a1)
; ILP32-LP64-NEXT: fld fs1, 168(a1) ; ILP32-LP64-NEXT: fld fs1, 168(a1)
; ILP32-LP64-NEXT: fld fs2, 176(a1) ; ILP32-LP64-NEXT: fld fs2, 176(a1)
; ILP32-LP64-NEXT: fld fs3, 184(a1) ; ILP32-LP64-NEXT: fld fs3, 184(a1)
; ILP32-LP64-NEXT: fld fs4, 192(a1) ; ILP32-LP64-NEXT: fld fs4, 192(a1)
; ILP32-LP64-NEXT: fld fs5, 200(a1) ; ILP32-LP64-NEXT: fld fs5, 200(a1)
; ILP32-LP64-NEXT: fld fs6, 208(a1) ; ILP32-LP64-NEXT: fld fs6, 208(a1)
; ILP32-LP64-NEXT: fld fs7, 216(a1) ; ILP32-LP64-NEXT: fld fs7, 216(a1)
; ILP32-LP64-NEXT: fld fs8, 224(a1) ; ILP32-LP64-NEXT: fld fs8, 248(a1)
; ILP32-LP64-NEXT: fld fs9, 232(a1) ; ILP32-LP64-NEXT: fld fs9, 240(a1)
; ILP32-LP64-NEXT: fld fs10, 240(a1) ; ILP32-LP64-NEXT: fld fs10, 232(a1)
; ILP32-LP64-NEXT: fld fs11, 248(a1) ; ILP32-LP64-NEXT: fld fs11, 224(a1)
; ILP32-LP64-NEXT: fsd fs11, 248(a1) ; ILP32-LP64-NEXT: fsd fs8, 248(a1)
; ILP32-LP64-NEXT: fsd fs10, 240(a1) ; ILP32-LP64-NEXT: fsd fs9, 240(a1)
; ILP32-LP64-NEXT: fsd fs9, 232(a1) ; ILP32-LP64-NEXT: fsd fs10, 232(a1)
; ILP32-LP64-NEXT: fsd fs8, 224(a1) ; ILP32-LP64-NEXT: fsd fs11, 224(a1)
; ILP32-LP64-NEXT: fsd fs7, 216(a1) ; ILP32-LP64-NEXT: fsd fs7, 216(a1)
; ILP32-LP64-NEXT: fsd fs6, 208(a1) ; ILP32-LP64-NEXT: fsd fs6, 208(a1)
; ILP32-LP64-NEXT: fsd fs5, 200(a1) ; ILP32-LP64-NEXT: fsd fs5, 200(a1)
; ILP32-LP64-NEXT: fsd fs4, 192(a1) ; ILP32-LP64-NEXT: fsd fs4, 192(a1)
; ILP32-LP64-NEXT: fsd fs3, 184(a1) ; ILP32-LP64-NEXT: fsd fs3, 184(a1)
; ILP32-LP64-NEXT: fsd fs2, 176(a1) ; ILP32-LP64-NEXT: fsd fs2, 176(a1)
; ILP32-LP64-NEXT: fsd fs1, 168(a1) ; ILP32-LP64-NEXT: fsd fs1, 168(a1)
; ILP32-LP64-NEXT: fsd fs0, 160(a1) ; ILP32-LP64-NEXT: fsd fs0, 160(a1)
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; ILP32D-LP64D-NEXT: fsd fs5, 48(sp) ; ILP32D-LP64D-NEXT: fsd fs5, 48(sp)
; ILP32D-LP64D-NEXT: fsd fs6, 40(sp) ; ILP32D-LP64D-NEXT: fsd fs6, 40(sp)
; ILP32D-LP64D-NEXT: fsd fs7, 32(sp) ; ILP32D-LP64D-NEXT: fsd fs7, 32(sp)
; ILP32D-LP64D-NEXT: fsd fs8, 24(sp) ; ILP32D-LP64D-NEXT: fsd fs8, 24(sp)
; ILP32D-LP64D-NEXT: fsd fs9, 16(sp) ; ILP32D-LP64D-NEXT: fsd fs9, 16(sp)
; ILP32D-LP64D-NEXT: fsd fs10, 8(sp) ; ILP32D-LP64D-NEXT: fsd fs10, 8(sp)
; ILP32D-LP64D-NEXT: fsd fs11, 0(sp) ; ILP32D-LP64D-NEXT: fsd fs11, 0(sp)
; ILP32D-LP64D-NEXT: lui a0, %hi(var) ; ILP32D-LP64D-NEXT: lui a0, %hi(var)
; ILP32D-LP64D-NEXT: fld ft0, %lo(var)(a0)
; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var) ; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var)
%val = load [32 x double], [32 x double]* @var %val = load [32 x double], [32 x double]* @var
store volatile [32 x double] %val, [32 x double]* @var store volatile [32 x double] %val, [32 x double]* @var
ret void ret void
} }
; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
; something appropriate. ; something appropriate.
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llvm/test/CodeGen/RISCV/callee-saved-gprs.ll

Show All 35 Lines
; RV32I-NEXT: sw s5, 56(sp) ; RV32I-NEXT: sw s5, 56(sp)
; RV32I-NEXT: sw s6, 52(sp) ; RV32I-NEXT: sw s6, 52(sp)
; RV32I-NEXT: sw s7, 48(sp) ; RV32I-NEXT: sw s7, 48(sp)
; RV32I-NEXT: sw s8, 44(sp) ; RV32I-NEXT: sw s8, 44(sp)
; RV32I-NEXT: sw s9, 40(sp) ; RV32I-NEXT: sw s9, 40(sp)
; RV32I-NEXT: sw s10, 36(sp) ; RV32I-NEXT: sw s10, 36(sp)
; RV32I-NEXT: sw s11, 32(sp) ; RV32I-NEXT: sw s11, 32(sp)
; RV32I-NEXT: lui a0, %hi(var) ; RV32I-NEXT: lui a0, %hi(var)
; RV32I-NEXT: addi a1, a0, %lo(var) ; RV32I-NEXT: lw a1, %lo(var)(a0)
; RV32I-NEXT: sw a1, 28(sp)
; RV32I-NEXT: addi a2, a0, %lo(var)
lenaryUnsubmitted
Not Done
ReplyInline Actions

We seem to have gained a lw; sw pair here. Not entirely sure why. There are a few additions like this in this testcase.

lenary: We seem to have gained a `lw; sw` pair here. Not entirely sure why. There are a few additions…
jrtc27Unsubmitted
Not Done
ReplyInline Actions

I assume these were previously scheduled after the addi but have now been hoisted. Note that these check lines do not continue to the end of the function, these are truncated, and manually created rather than using update_llc_test_checks.py for this file.

jrtc27: I assume these were previously scheduled after the `addi` but have now been hoisted. Note that…
; ;
; RV32I-WITH-FP-LABEL: callee: ; RV32I-WITH-FP-LABEL: callee:
; RV32I-WITH-FP: # %bb.0: ; RV32I-WITH-FP: # %bb.0:
; RV32I-WITH-FP-NEXT: addi sp, sp, -80 ; RV32I-WITH-FP-NEXT: addi sp, sp, -80
; RV32I-WITH-FP-NEXT: sw ra, 76(sp) ; RV32I-WITH-FP-NEXT: sw ra, 76(sp)
; RV32I-WITH-FP-NEXT: sw s0, 72(sp) ; RV32I-WITH-FP-NEXT: sw s0, 72(sp)
; RV32I-WITH-FP-NEXT: sw s1, 68(sp) ; RV32I-WITH-FP-NEXT: sw s1, 68(sp)
; RV32I-WITH-FP-NEXT: sw s2, 64(sp) ; RV32I-WITH-FP-NEXT: sw s2, 64(sp)
; RV32I-WITH-FP-NEXT: sw s3, 60(sp) ; RV32I-WITH-FP-NEXT: sw s3, 60(sp)
; RV32I-WITH-FP-NEXT: sw s4, 56(sp) ; RV32I-WITH-FP-NEXT: sw s4, 56(sp)
; RV32I-WITH-FP-NEXT: sw s5, 52(sp) ; RV32I-WITH-FP-NEXT: sw s5, 52(sp)
; RV32I-WITH-FP-NEXT: sw s6, 48(sp) ; RV32I-WITH-FP-NEXT: sw s6, 48(sp)
; RV32I-WITH-FP-NEXT: sw s7, 44(sp) ; RV32I-WITH-FP-NEXT: sw s7, 44(sp)
; RV32I-WITH-FP-NEXT: sw s8, 40(sp) ; RV32I-WITH-FP-NEXT: sw s8, 40(sp)
; RV32I-WITH-FP-NEXT: sw s9, 36(sp) ; RV32I-WITH-FP-NEXT: sw s9, 36(sp)
; RV32I-WITH-FP-NEXT: sw s10, 32(sp) ; RV32I-WITH-FP-NEXT: sw s10, 32(sp)
; RV32I-WITH-FP-NEXT: sw s11, 28(sp) ; RV32I-WITH-FP-NEXT: sw s11, 28(sp)
; RV32I-WITH-FP-NEXT: addi s0, sp, 80 ; RV32I-WITH-FP-NEXT: addi s0, sp, 80
; RV32I-WITH-FP-NEXT: lui a0, %hi(var) ; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
; RV32I-WITH-FP-NEXT: addi a1, a0, %lo(var) ; RV32I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV32I-WITH-FP-NEXT: sw a1, -56(s0)
; RV32I-WITH-FP-NEXT: addi a2, a0, %lo(var)
; ;
; RV64I-LABEL: callee: ; RV64I-LABEL: callee:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -144 ; RV64I-NEXT: addi sp, sp, -144
; RV64I-NEXT: sd s0, 136(sp) ; RV64I-NEXT: sd s0, 136(sp)
; RV64I-NEXT: sd s1, 128(sp) ; RV64I-NEXT: sd s1, 128(sp)
; RV64I-NEXT: sd s2, 120(sp) ; RV64I-NEXT: sd s2, 120(sp)
; RV64I-NEXT: sd s3, 112(sp) ; RV64I-NEXT: sd s3, 112(sp)
; RV64I-NEXT: sd s4, 104(sp) ; RV64I-NEXT: sd s4, 104(sp)
; RV64I-NEXT: sd s5, 96(sp) ; RV64I-NEXT: sd s5, 96(sp)
; RV64I-NEXT: sd s6, 88(sp) ; RV64I-NEXT: sd s6, 88(sp)
; RV64I-NEXT: sd s7, 80(sp) ; RV64I-NEXT: sd s7, 80(sp)
; RV64I-NEXT: sd s8, 72(sp) ; RV64I-NEXT: sd s8, 72(sp)
; RV64I-NEXT: sd s9, 64(sp) ; RV64I-NEXT: sd s9, 64(sp)
; RV64I-NEXT: sd s10, 56(sp) ; RV64I-NEXT: sd s10, 56(sp)
; RV64I-NEXT: sd s11, 48(sp) ; RV64I-NEXT: sd s11, 48(sp)
; RV64I-NEXT: lui a0, %hi(var) ; RV64I-NEXT: lui a0, %hi(var)
; RV64I-NEXT: addi a1, a0, %lo(var) ; RV64I-NEXT: lw a1, %lo(var)(a0)
; RV64I-NEXT: sd a1, 40(sp)
; RV64I-NEXT: addi a2, a0, %lo(var)
; ;
; RV64I-WITH-FP-LABEL: callee: ; RV64I-WITH-FP-LABEL: callee:
; RV64I-WITH-FP: # %bb.0: ; RV64I-WITH-FP: # %bb.0:
; RV64I-WITH-FP-NEXT: addi sp, sp, -160 ; RV64I-WITH-FP-NEXT: addi sp, sp, -160
; RV64I-WITH-FP-NEXT: sd ra, 152(sp) ; RV64I-WITH-FP-NEXT: sd ra, 152(sp)
; RV64I-WITH-FP-NEXT: sd s0, 144(sp) ; RV64I-WITH-FP-NEXT: sd s0, 144(sp)
; RV64I-WITH-FP-NEXT: sd s1, 136(sp) ; RV64I-WITH-FP-NEXT: sd s1, 136(sp)
; RV64I-WITH-FP-NEXT: sd s2, 128(sp) ; RV64I-WITH-FP-NEXT: sd s2, 128(sp)
; RV64I-WITH-FP-NEXT: sd s3, 120(sp) ; RV64I-WITH-FP-NEXT: sd s3, 120(sp)
; RV64I-WITH-FP-NEXT: sd s4, 112(sp) ; RV64I-WITH-FP-NEXT: sd s4, 112(sp)
; RV64I-WITH-FP-NEXT: sd s5, 104(sp) ; RV64I-WITH-FP-NEXT: sd s5, 104(sp)
; RV64I-WITH-FP-NEXT: sd s6, 96(sp) ; RV64I-WITH-FP-NEXT: sd s6, 96(sp)
; RV64I-WITH-FP-NEXT: sd s7, 88(sp) ; RV64I-WITH-FP-NEXT: sd s7, 88(sp)
; RV64I-WITH-FP-NEXT: sd s8, 80(sp) ; RV64I-WITH-FP-NEXT: sd s8, 80(sp)
; RV64I-WITH-FP-NEXT: sd s9, 72(sp) ; RV64I-WITH-FP-NEXT: sd s9, 72(sp)
; RV64I-WITH-FP-NEXT: sd s10, 64(sp) ; RV64I-WITH-FP-NEXT: sd s10, 64(sp)
; RV64I-WITH-FP-NEXT: sd s11, 56(sp) ; RV64I-WITH-FP-NEXT: sd s11, 56(sp)
; RV64I-WITH-FP-NEXT: addi s0, sp, 160 ; RV64I-WITH-FP-NEXT: addi s0, sp, 160
; RV64I-WITH-FP-NEXT: lui a0, %hi(var) ; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
; RV64I-WITH-FP-NEXT: addi a1, a0, %lo(var) ; RV64I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV64I-WITH-FP-NEXT: sd a1, -112(s0)
; RV64I-WITH-FP-NEXT: addi a2, a0, %lo(var)
%val = load [32 x i32], [32 x i32]* @var %val = load [32 x i32], [32 x i32]* @var
store volatile [32 x i32] %val, [32 x i32]* @var store volatile [32 x i32] %val, [32 x i32]* @var
ret void ret void
} }
; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
; something appropriate. ; something appropriate.
define void @caller() nounwind { define void @caller() nounwind {
; RV32I-LABEL: caller: ; RV32I-LABEL: caller:
; RV32I: lui a0, %hi(var) ; RV32I: lui a0, %hi(var)
; RV32I-NEXT: addi s1, a0, %lo(var) ; RV32I-NEXT: lw a1, %lo(var)(a0)
; RV32I-NEXT: sw a1, 88(sp)
; RV32I-NEXT: addi s0, a0, %lo(var)
; RV32I: sw a0, 8(sp) ; RV32I: sw a0, 8(sp)
; RV32I-NEXT: lw s2, 84(s1) ; RV32I-NEXT: lw s2, 84(s0)
; RV32I-NEXT: lw s3, 88(s1) ; RV32I-NEXT: lw s3, 88(s0)
; RV32I-NEXT: lw s4, 92(s1) ; RV32I-NEXT: lw s4, 92(s0)
; RV32I-NEXT: lw s5, 96(s1) ; RV32I-NEXT: lw s5, 96(s0)
; RV32I-NEXT: lw s6, 100(s1) ; RV32I-NEXT: lw s6, 100(s0)
; RV32I-NEXT: lw s7, 104(s1) ; RV32I-NEXT: lw s7, 104(s0)
; RV32I-NEXT: lw s8, 108(s1) ; RV32I-NEXT: lw s8, 108(s0)
; RV32I-NEXT: lw s9, 112(s1) ; RV32I-NEXT: lw s9, 112(s0)
; RV32I-NEXT: lw s10, 116(s1) ; RV32I-NEXT: lw s10, 116(s0)
; RV32I-NEXT: lw s11, 120(s1) ; RV32I-NEXT: lw s11, 120(s0)
; RV32I-NEXT: lw s0, 124(s1) ; RV32I-NEXT: lw s1, 124(s0)
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee
; RV32I-NEXT: sw s0, 124(s1) ; RV32I-NEXT: sw s1, 124(s0)
; RV32I-NEXT: sw s11, 120(s1) ; RV32I-NEXT: sw s11, 120(s0)
; RV32I-NEXT: sw s10, 116(s1) ; RV32I-NEXT: sw s10, 116(s0)
; RV32I-NEXT: sw s9, 112(s1) ; RV32I-NEXT: sw s9, 112(s0)
; RV32I-NEXT: sw s8, 108(s1) ; RV32I-NEXT: sw s8, 108(s0)
; RV32I-NEXT: sw s7, 104(s1) ; RV32I-NEXT: sw s7, 104(s0)
; RV32I-NEXT: sw s6, 100(s1) ; RV32I-NEXT: sw s6, 100(s0)
; RV32I-NEXT: sw s5, 96(s1) ; RV32I-NEXT: sw s5, 96(s0)
; RV32I-NEXT: sw s4, 92(s1) ; RV32I-NEXT: sw s4, 92(s0)
; RV32I-NEXT: sw s3, 88(s1) ; RV32I-NEXT: sw s3, 88(s0)
; RV32I-NEXT: sw s2, 84(s1) ; RV32I-NEXT: sw s2, 84(s0)
; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw a0, 8(sp)
; ;
; RV32I-WITH-FP-LABEL: caller: ; RV32I-WITH-FP-LABEL: caller:
; RV32I-WITH-FP: addi s0, sp, 144 ; RV32I-WITH-FP: addi s0, sp, 144
; RV32I-WITH-FP-NEXT: lui a0, %hi(var) ; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
; RV32I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV32I-WITH-FP-NEXT: sw a1, -56(s0)
; RV32I-WITH-FP-NEXT: addi s1, a0, %lo(var) ; RV32I-WITH-FP-NEXT: addi s1, a0, %lo(var)
; RV32I-WITH-FP: sw a0, -140(s0) ; RV32I-WITH-FP: sw a0, -140(s0)
; RV32I-WITH-FP-NEXT: lw s5, 88(s1) ; RV32I-WITH-FP-NEXT: lw s5, 88(s1)
; RV32I-WITH-FP-NEXT: lw s6, 92(s1) ; RV32I-WITH-FP-NEXT: lw s6, 92(s1)
; RV32I-WITH-FP-NEXT: lw s7, 96(s1) ; RV32I-WITH-FP-NEXT: lw s7, 96(s1)
; RV32I-WITH-FP-NEXT: lw s8, 100(s1) ; RV32I-WITH-FP-NEXT: lw s8, 100(s1)
; RV32I-WITH-FP-NEXT: lw s9, 104(s1) ; RV32I-WITH-FP-NEXT: lw s9, 104(s1)
; RV32I-WITH-FP-NEXT: lw s10, 108(s1) ; RV32I-WITH-FP-NEXT: lw s10, 108(s1)
Show All 11 Lines
; RV32I-WITH-FP-NEXT: sw s8, 100(s1) ; RV32I-WITH-FP-NEXT: sw s8, 100(s1)
; RV32I-WITH-FP-NEXT: sw s7, 96(s1) ; RV32I-WITH-FP-NEXT: sw s7, 96(s1)
; RV32I-WITH-FP-NEXT: sw s6, 92(s1) ; RV32I-WITH-FP-NEXT: sw s6, 92(s1)
; RV32I-WITH-FP-NEXT: sw s5, 88(s1) ; RV32I-WITH-FP-NEXT: sw s5, 88(s1)
; RV32I-WITH-FP-NEXT: lw a0, -140(s0) ; RV32I-WITH-FP-NEXT: lw a0, -140(s0)
; ;
; RV64I-LABEL: caller: ; RV64I-LABEL: caller:
; RV64I: lui a0, %hi(var) ; RV64I: lui a0, %hi(var)
; RV64I-NEXT: addi s1, a0, %lo(var) ; RV64I-NEXT: lw a1, %lo(var)(a0)
; RV64I-NEXT: sd a1, 160(sp)
; RV64I-NEXT: addi s0, a0, %lo(var)
; RV64I: sd a0, 0(sp) ; RV64I: sd a0, 0(sp)
; RV64I-NEXT: lw s2, 84(s1) ; RV64I-NEXT: lw s2, 84(s0)
; RV64I-NEXT: lw s3, 88(s1) ; RV64I-NEXT: lw s3, 88(s0)
; RV64I-NEXT: lw s4, 92(s1) ; RV64I-NEXT: lw s4, 92(s0)
; RV64I-NEXT: lw s5, 96(s1) ; RV64I-NEXT: lw s5, 96(s0)
; RV64I-NEXT: lw s6, 100(s1) ; RV64I-NEXT: lw s6, 100(s0)
; RV64I-NEXT: lw s7, 104(s1) ; RV64I-NEXT: lw s7, 104(s0)
; RV64I-NEXT: lw s8, 108(s1) ; RV64I-NEXT: lw s8, 108(s0)
; RV64I-NEXT: lw s9, 112(s1) ; RV64I-NEXT: lw s9, 112(s0)
; RV64I-NEXT: lw s10, 116(s1) ; RV64I-NEXT: lw s10, 116(s0)
; RV64I-NEXT: lw s11, 120(s1) ; RV64I-NEXT: lw s11, 120(s0)
; RV64I-NEXT: lw s0, 124(s1) ; RV64I-NEXT: lw s1, 124(s0)
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee
; RV64I-NEXT: sw s0, 124(s1) ; RV64I-NEXT: sw s1, 124(s0)
; RV64I-NEXT: sw s11, 120(s1) ; RV64I-NEXT: sw s11, 120(s0)
; RV64I-NEXT: sw s10, 116(s1) ; RV64I-NEXT: sw s10, 116(s0)
; RV64I-NEXT: sw s9, 112(s1) ; RV64I-NEXT: sw s9, 112(s0)
; RV64I-NEXT: sw s8, 108(s1) ; RV64I-NEXT: sw s8, 108(s0)
; RV64I-NEXT: sw s7, 104(s1) ; RV64I-NEXT: sw s7, 104(s0)
; RV64I-NEXT: sw s6, 100(s1) ; RV64I-NEXT: sw s6, 100(s0)
; RV64I-NEXT: sw s5, 96(s1) ; RV64I-NEXT: sw s5, 96(s0)
; RV64I-NEXT: sw s4, 92(s1) ; RV64I-NEXT: sw s4, 92(s0)
; RV64I-NEXT: sw s3, 88(s1) ; RV64I-NEXT: sw s3, 88(s0)
; RV64I-NEXT: sw s2, 84(s1) ; RV64I-NEXT: sw s2, 84(s0)
; RV64I-NEXT: ld a0, 0(sp) ; RV64I-NEXT: ld a0, 0(sp)
; ;
; RV64I-WITH-FP-LABEL: caller: ; RV64I-WITH-FP-LABEL: caller:
; RV64I-WITH-FP: addi s0, sp, 288 ; RV64I-WITH-FP: addi s0, sp, 288
; RV64I-WITH-FP-NEXT: lui a0, %hi(var) ; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
; RV64I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV64I-WITH-FP-NEXT: sd a1, -112(s0)
; RV64I-WITH-FP-NEXT: addi s1, a0, %lo(var) ; RV64I-WITH-FP-NEXT: addi s1, a0, %lo(var)
; RV64I-WITH-FP: sd a0, -280(s0) ; RV64I-WITH-FP: sd a0, -280(s0)
; RV64I-WITH-FP-NEXT: lw s5, 88(s1) ; RV64I-WITH-FP-NEXT: lw s5, 88(s1)
; RV64I-WITH-FP-NEXT: lw s6, 92(s1) ; RV64I-WITH-FP-NEXT: lw s6, 92(s1)
; RV64I-WITH-FP-NEXT: lw s7, 96(s1) ; RV64I-WITH-FP-NEXT: lw s7, 96(s1)
; RV64I-WITH-FP-NEXT: lw s8, 100(s1) ; RV64I-WITH-FP-NEXT: lw s8, 100(s1)
; RV64I-WITH-FP-NEXT: lw s9, 104(s1) ; RV64I-WITH-FP-NEXT: lw s9, 104(s1)
; RV64I-WITH-FP-NEXT: lw s10, 108(s1) ; RV64I-WITH-FP-NEXT: lw s10, 108(s1)
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llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
} }
define i32 @caller_double_in_regs() nounwind { define i32 @caller_double_in_regs() nounwind {
; RV32I-FPELIM-LABEL: caller_double_in_regs: ; RV32I-FPELIM-LABEL: caller_double_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: lui a2, 262144 ; RV32I-FPELIM-NEXT: lui a2, 262144
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: call callee_double_in_regs ; RV32I-FPELIM-NEXT: call callee_double_in_regs
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_double_in_regs: ; RV32I-WITHFP-LABEL: caller_double_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: lui a2, 262144 ; RV32I-WITHFP-NEXT: lui a2, 262144
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: call callee_double_in_regs ; RV32I-WITHFP-NEXT: call callee_double_in_regs
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_double_in_regs(i32 1, double 2.0) %1 = call i32 @callee_double_in_regs(i32 1, double 2.0)
ret i32 %1 ret i32 %1
} }
; Check 2x*xlen values are aligned appropriately when passed on the stack ; Check 2x*xlen values are aligned appropriately when passed on the stack
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind { define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind {
; The double should be 8-byte aligned on the stack, but the two-element array ; The double should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned ; should only be 4-byte aligned
; RV32I-FPELIM-LABEL: callee_aligned_stack: ; RV32I-FPELIM-LABEL: callee_aligned_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 0(a2) ; RV32I-FPELIM-NEXT: lw a0, 0(a2)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: lw a1, 0(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 8(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 20(sp) ; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: lw a2, 0(sp)
; RV32I-FPELIM-NEXT: lw a3, 8(sp)
; RV32I-FPELIM-NEXT: lw a4, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: add a0, a0, a2
; RV32I-FPELIM-NEXT: add a0, a0, a3
; RV32I-FPELIM-NEXT: add a0, a0, a4
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_aligned_stack: ; RV32I-WITHFP-LABEL: callee_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(a2) ; RV32I-WITHFP-NEXT: lw a0, 0(a2)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: lw a1, 0(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 8(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 20(s0) ; RV32I-WITHFP-NEXT: lw a1, 20(s0)
; RV32I-WITHFP-NEXT: lw a2, 0(s0)
; RV32I-WITHFP-NEXT: lw a3, 8(s0)
; RV32I-WITHFP-NEXT: lw a4, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a3
; RV32I-WITHFP-NEXT: add a0, a0, a4
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = bitcast fp128 %c to i128 %1 = bitcast fp128 %c to i128
%2 = trunc i128 %1 to i32 %2 = trunc i128 %1 to i32
%3 = add i32 %2, %g %3 = add i32 %2, %g
Show All 33 Lines
; RV32I-FPELIM-NEXT: sw a0, 44(sp) ; RV32I-FPELIM-NEXT: sw a0, 44(sp)
; RV32I-FPELIM-NEXT: lui a0, 545260 ; RV32I-FPELIM-NEXT: lui a0, 545260
; RV32I-FPELIM-NEXT: addi a0, a0, -1967 ; RV32I-FPELIM-NEXT: addi a0, a0, -1967
; RV32I-FPELIM-NEXT: sw a0, 40(sp) ; RV32I-FPELIM-NEXT: sw a0, 40(sp)
; RV32I-FPELIM-NEXT: lui a0, 964690 ; RV32I-FPELIM-NEXT: lui a0, 964690
; RV32I-FPELIM-NEXT: addi a0, a0, -328 ; RV32I-FPELIM-NEXT: addi a0, a0, -328
; RV32I-FPELIM-NEXT: sw a0, 36(sp) ; RV32I-FPELIM-NEXT: sw a0, 36(sp)
; RV32I-FPELIM-NEXT: lui a0, 335544 ; RV32I-FPELIM-NEXT: lui a0, 335544
; RV32I-FPELIM-NEXT: addi a0, a0, 1311 ; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: lui a0, 688509 ; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048 ; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32 ; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11 ; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a3, zero, 12 ; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13 ; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14 ; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp)
; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_aligned_stack: ; RV32I-WITHFP-LABEL: caller_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64 ; RV32I-WITHFP-NEXT: addi sp, sp, -64
Show All 19 Lines
; RV32I-WITHFP-NEXT: sw a0, -20(s0) ; RV32I-WITHFP-NEXT: sw a0, -20(s0)
; RV32I-WITHFP-NEXT: lui a0, 545260 ; RV32I-WITHFP-NEXT: lui a0, 545260
; RV32I-WITHFP-NEXT: addi a0, a0, -1967 ; RV32I-WITHFP-NEXT: addi a0, a0, -1967
; RV32I-WITHFP-NEXT: sw a0, -24(s0) ; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: lui a0, 964690 ; RV32I-WITHFP-NEXT: lui a0, 964690
; RV32I-WITHFP-NEXT: addi a0, a0, -328 ; RV32I-WITHFP-NEXT: addi a0, a0, -328
; RV32I-WITHFP-NEXT: sw a0, -28(s0) ; RV32I-WITHFP-NEXT: sw a0, -28(s0)
; RV32I-WITHFP-NEXT: lui a0, 335544 ; RV32I-WITHFP-NEXT: lui a0, 335544
; RV32I-WITHFP-NEXT: addi a0, a0, 1311 ; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, 688509 ; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048 ; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32 ; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11 ; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a3, zero, 12 ; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13 ; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14 ; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0)
; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64 ; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_aligned_stack(i32 1, i32 11, %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16, i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
[2 x i32] [i32 17, i32 18]) [2 x i32] [i32 17, i32 18])
ret void ret void
} }
define double @callee_small_scalar_ret() nounwind { define double @callee_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: callee_small_scalar_ret: ; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: lui a1, 261888 ; RV32I-FPELIM-NEXT: lui a1, 261888
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_small_scalar_ret: ; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lui a1, 261888 ; RV32I-WITHFP-NEXT: lui a1, 261888
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
ret double 1.0 ret double 1.0
} }
define i64 @caller_small_scalar_ret() nounwind { define i64 @caller_small_scalar_ret() nounwind {
Show All 24 Lines

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; RV32I-WITHFP-NEXT: ret
ret i32 %1 ret i32 %1
} }
; Check that the stack is used once the GPRs are exhausted ; Check that the stack is used once the GPRs are exhausted
define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind { define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind {
; RV32I-FPELIM-LABEL: callee_many_scalars: ; RV32I-FPELIM-LABEL: callee_many_scalars:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw t0, 0(sp) ; RV32I-FPELIM-NEXT: lw t0, 4(sp)
; RV32I-FPELIM-NEXT: xor a4, a4, t0 ; RV32I-FPELIM-NEXT: lw t1, 0(sp)
; RV32I-FPELIM-NEXT: xor a3, a3, a7 ; RV32I-FPELIM-NEXT: andi t2, a0, 255
; RV32I-FPELIM-NEXT: or a3, a3, a4 ; RV32I-FPELIM-NEXT: lui a0, 16
; RV32I-FPELIM-NEXT: lui a4, 16 ; RV32I-FPELIM-NEXT: addi a0, a0, -1
; RV32I-FPELIM-NEXT: addi a4, a4, -1 ; RV32I-FPELIM-NEXT: and a0, a1, a0
; RV32I-FPELIM-NEXT: and a1, a1, a4 ; RV32I-FPELIM-NEXT: add a0, t2, a0
; RV32I-FPELIM-NEXT: andi a0, a0, 255
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: add a0, a0, a2 ; RV32I-FPELIM-NEXT: add a0, a0, a2
; RV32I-FPELIM-NEXT: seqz a1, a3 ; RV32I-FPELIM-NEXT: xor a1, a4, t1
; RV32I-FPELIM-NEXT: xor a2, a3, a7
; RV32I-FPELIM-NEXT: or a1, a2, a1
; RV32I-FPELIM-NEXT: seqz a1, a1
; RV32I-FPELIM-NEXT: add a0, a1, a0 ; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-FPELIM-NEXT: add a0, a0, a5 ; RV32I-FPELIM-NEXT: add a0, a0, a5
; RV32I-FPELIM-NEXT: add a0, a0, a6 ; RV32I-FPELIM-NEXT: add a0, a0, a6
; RV32I-FPELIM-NEXT: lw a1, 4(sp) ; RV32I-FPELIM-NEXT: add a0, a0, t0
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_many_scalars: ; RV32I-WITHFP-LABEL: callee_many_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw t0, 0(s0) ; RV32I-WITHFP-NEXT: lw t0, 4(s0)
; RV32I-WITHFP-NEXT: xor a4, a4, t0 ; RV32I-WITHFP-NEXT: lw t1, 0(s0)
; RV32I-WITHFP-NEXT: xor a3, a3, a7 ; RV32I-WITHFP-NEXT: andi t2, a0, 255
; RV32I-WITHFP-NEXT: or a3, a3, a4 ; RV32I-WITHFP-NEXT: lui a0, 16
; RV32I-WITHFP-NEXT: lui a4, 16 ; RV32I-WITHFP-NEXT: addi a0, a0, -1
; RV32I-WITHFP-NEXT: addi a4, a4, -1 ; RV32I-WITHFP-NEXT: and a0, a1, a0
; RV32I-WITHFP-NEXT: and a1, a1, a4 ; RV32I-WITHFP-NEXT: add a0, t2, a0
; RV32I-WITHFP-NEXT: andi a0, a0, 255
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: add a0, a0, a2 ; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: seqz a1, a3 ; RV32I-WITHFP-NEXT: xor a1, a4, t1
; RV32I-WITHFP-NEXT: xor a2, a3, a7
; RV32I-WITHFP-NEXT: or a1, a2, a1
; RV32I-WITHFP-NEXT: seqz a1, a1
; RV32I-WITHFP-NEXT: add a0, a1, a0 ; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: add a0, a0, a5 ; RV32I-WITHFP-NEXT: add a0, a0, a5
; RV32I-WITHFP-NEXT: add a0, a0, a6 ; RV32I-WITHFP-NEXT: add a0, a0, a6
; RV32I-WITHFP-NEXT: lw a1, 4(s0) ; RV32I-WITHFP-NEXT: add a0, a0, t0
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%a_ext = zext i8 %a to i32 %a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32 %b_ext = zext i16 %b to i32
%1 = add i32 %a_ext, %b_ext %1 = add i32 %a_ext, %b_ext
%2 = add i32 %1, %c %2 = add i32 %1, %c
%3 = icmp eq i64 %d, %g %3 = icmp eq i64 %d, %g
%4 = zext i1 %3 to i32 %4 = zext i1 %3 to i32
%5 = add i32 %4, %2 %5 = add i32 %4, %2
%6 = add i32 %5, %e %6 = add i32 %5, %e
%7 = add i32 %6, %f %7 = add i32 %6, %f
%8 = add i32 %7, %h %8 = add i32 %7, %h
ret i32 %8 ret i32 %8
} }
define i32 @caller_many_scalars() nounwind { define i32 @caller_many_scalars() nounwind {
; RV32I-FPELIM-LABEL: caller_many_scalars: ; RV32I-FPELIM-LABEL: caller_many_scalars:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8 ; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 4(sp) ; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3 ; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4 ; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: addi a5, zero, 5 ; RV32I-FPELIM-NEXT: addi a5, zero, 5
; RV32I-FPELIM-NEXT: addi a6, zero, 6 ; RV32I-FPELIM-NEXT: addi a6, zero, 6
; RV32I-FPELIM-NEXT: addi a7, zero, 7 ; RV32I-FPELIM-NEXT: addi a7, zero, 7
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: call callee_many_scalars ; RV32I-FPELIM-NEXT: call callee_many_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_many_scalars: ; RV32I-WITHFP-LABEL: caller_many_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 8 ; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, 4(sp) ; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3 ; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4 ; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: addi a5, zero, 5 ; RV32I-WITHFP-NEXT: addi a5, zero, 5
; RV32I-WITHFP-NEXT: addi a6, zero, 6 ; RV32I-WITHFP-NEXT: addi a6, zero, 6
; RV32I-WITHFP-NEXT: addi a7, zero, 7 ; RV32I-WITHFP-NEXT: addi a7, zero, 7
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: call callee_many_scalars ; RV32I-WITHFP-NEXT: call callee_many_scalars
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8) %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
ret i32 %1 ret i32 %1
} }
; Check that i128 and fp128 are passed indirectly ; Check that i128 and fp128 are passed indirectly
define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind { define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
; RV32I-FPELIM-LABEL: callee_large_scalars: ; RV32I-FPELIM-LABEL: callee_large_scalars:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a2, 12(a1) ; RV32I-FPELIM-NEXT: lw a6, 0(a1)
; RV32I-FPELIM-NEXT: lw a3, 12(a0) ; RV32I-FPELIM-NEXT: lw a7, 0(a0)
; RV32I-FPELIM-NEXT: xor a2, a3, a2 ; RV32I-FPELIM-NEXT: lw a4, 4(a1)
; RV32I-FPELIM-NEXT: lw a3, 4(a1) ; RV32I-FPELIM-NEXT: lw a5, 12(a1)
; RV32I-FPELIM-NEXT: lw a4, 4(a0) ; RV32I-FPELIM-NEXT: lw a2, 12(a0)
; RV32I-FPELIM-NEXT: xor a3, a4, a3 ; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a1, 8(a1)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: xor a2, a2, a5
; RV32I-FPELIM-NEXT: xor a3, a3, a4
; RV32I-FPELIM-NEXT: or a2, a3, a2 ; RV32I-FPELIM-NEXT: or a2, a3, a2
; RV32I-FPELIM-NEXT: lw a3, 8(a1)
; RV32I-FPELIM-NEXT: lw a4, 8(a0)
; RV32I-FPELIM-NEXT: xor a3, a4, a3
; RV32I-FPELIM-NEXT: lw a1, 0(a1)
; RV32I-FPELIM-NEXT: lw a0, 0(a0)
; RV32I-FPELIM-NEXT: xor a0, a0, a1 ; RV32I-FPELIM-NEXT: xor a0, a0, a1
; RV32I-FPELIM-NEXT: or a0, a0, a3 ; RV32I-FPELIM-NEXT: xor a1, a7, a6
; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a2 ; RV32I-FPELIM-NEXT: or a0, a0, a2
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalars: ; RV32I-WITHFP-LABEL: callee_large_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a2, 12(a1) ; RV32I-WITHFP-NEXT: lw a6, 0(a1)
; RV32I-WITHFP-NEXT: lw a3, 12(a0) ; RV32I-WITHFP-NEXT: lw a7, 0(a0)
; RV32I-WITHFP-NEXT: xor a2, a3, a2 ; RV32I-WITHFP-NEXT: lw a4, 4(a1)
; RV32I-WITHFP-NEXT: lw a3, 4(a1) ; RV32I-WITHFP-NEXT: lw a5, 12(a1)
; RV32I-WITHFP-NEXT: lw a4, 4(a0) ; RV32I-WITHFP-NEXT: lw a2, 12(a0)
; RV32I-WITHFP-NEXT: xor a3, a4, a3 ; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a1, 8(a1)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: xor a2, a2, a5
; RV32I-WITHFP-NEXT: xor a3, a3, a4
; RV32I-WITHFP-NEXT: or a2, a3, a2 ; RV32I-WITHFP-NEXT: or a2, a3, a2
; RV32I-WITHFP-NEXT: lw a3, 8(a1)
; RV32I-WITHFP-NEXT: lw a4, 8(a0)
; RV32I-WITHFP-NEXT: xor a3, a4, a3
; RV32I-WITHFP-NEXT: lw a1, 0(a1)
; RV32I-WITHFP-NEXT: lw a0, 0(a0)
; RV32I-WITHFP-NEXT: xor a0, a0, a1 ; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: or a0, a0, a3 ; RV32I-WITHFP-NEXT: xor a1, a7, a6
; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a2 ; RV32I-WITHFP-NEXT: or a0, a0, a2
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%b_bitcast = bitcast fp128 %b to i128 %b_bitcast = bitcast fp128 %b to i128
%1 = icmp eq i128 %a, %b_bitcast %1 = icmp eq i128 %a, %b_bitcast
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; RV32I-FPELIM-NEXT: lui a0, 524272 ; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 12(sp) ; RV32I-FPELIM-NEXT: sw a0, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp) ; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: sw zero, 4(sp) ; RV32I-FPELIM-NEXT: sw zero, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp) ; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: sw zero, 36(sp) ; RV32I-FPELIM-NEXT: sw zero, 36(sp)
; RV32I-FPELIM-NEXT: sw zero, 32(sp) ; RV32I-FPELIM-NEXT: sw zero, 32(sp)
; RV32I-FPELIM-NEXT: sw zero, 28(sp) ; RV32I-FPELIM-NEXT: sw zero, 28(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a2, zero, 1
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 24 ; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: mv a1, sp ; RV32I-FPELIM-NEXT: mv a1, sp
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
; RV32I-FPELIM-NEXT: call callee_large_scalars ; RV32I-FPELIM-NEXT: call callee_large_scalars
; RV32I-FPELIM-NEXT: lw ra, 44(sp) ; RV32I-FPELIM-NEXT: lw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_scalars: ; RV32I-WITHFP-LABEL: caller_large_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -48 ; RV32I-WITHFP-NEXT: addi sp, sp, -48
; RV32I-WITHFP-NEXT: sw ra, 44(sp) ; RV32I-WITHFP-NEXT: sw ra, 44(sp)
; RV32I-WITHFP-NEXT: sw s0, 40(sp) ; RV32I-WITHFP-NEXT: sw s0, 40(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 48 ; RV32I-WITHFP-NEXT: addi s0, sp, 48
; RV32I-WITHFP-NEXT: lui a0, 524272 ; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0) ; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0) ; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0) ; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0) ; RV32I-WITHFP-NEXT: sw zero, -12(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0) ; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a2, zero, 1
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: addi a1, s0, -48 ; RV32I-WITHFP-NEXT: addi a1, s0, -48
; RV32I-WITHFP-NEXT: sw a2, -24(s0)
; RV32I-WITHFP-NEXT: call callee_large_scalars ; RV32I-WITHFP-NEXT: call callee_large_scalars
; RV32I-WITHFP-NEXT: lw s0, 40(sp) ; RV32I-WITHFP-NEXT: lw s0, 40(sp)
; RV32I-WITHFP-NEXT: lw ra, 44(sp) ; RV32I-WITHFP-NEXT: lw ra, 44(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48 ; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000) %1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000)
ret i32 %1 ret i32 %1
} }
; Check that arguments larger than 2*xlen are handled correctly when their ; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory ; address is passed on the stack rather than in memory
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind { define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind {
; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs: ; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 4(sp) ; RV32I-FPELIM-NEXT: lw a0, 4(sp)
; RV32I-FPELIM-NEXT: lw a1, 12(a0) ; RV32I-FPELIM-NEXT: lw a6, 0(a0)
; RV32I-FPELIM-NEXT: lw a2, 12(a7) ; RV32I-FPELIM-NEXT: lw t0, 0(a7)
; RV32I-FPELIM-NEXT: xor a1, a2, a1 ; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a2, 4(a0) ; RV32I-FPELIM-NEXT: lw a4, 12(a0)
; RV32I-FPELIM-NEXT: lw a3, 4(a7) ; RV32I-FPELIM-NEXT: lw a5, 12(a7)
; RV32I-FPELIM-NEXT: xor a2, a3, a2 ; RV32I-FPELIM-NEXT: lw a1, 4(a7)
; RV32I-FPELIM-NEXT: or a1, a2, a1 ; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: lw a2, 8(a0) ; RV32I-FPELIM-NEXT: lw a2, 8(a7)
; RV32I-FPELIM-NEXT: lw a3, 8(a7) ; RV32I-FPELIM-NEXT: xor a4, a5, a4
; RV32I-FPELIM-NEXT: xor a2, a3, a2 ; RV32I-FPELIM-NEXT: xor a1, a1, a3
; RV32I-FPELIM-NEXT: lw a0, 0(a0) ; RV32I-FPELIM-NEXT: or a1, a1, a4
; RV32I-FPELIM-NEXT: lw a3, 0(a7) ; RV32I-FPELIM-NEXT: xor a0, a2, a0
; RV32I-FPELIM-NEXT: xor a0, a3, a0 ; RV32I-FPELIM-NEXT: xor a2, t0, a6
; RV32I-FPELIM-NEXT: or a0, a0, a2 ; RV32I-FPELIM-NEXT: or a0, a2, a0
; RV32I-FPELIM-NEXT: or a0, a0, a1 ; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs: ; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 4(s0) ; RV32I-WITHFP-NEXT: lw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw a1, 12(a0) ; RV32I-WITHFP-NEXT: lw a6, 0(a0)
; RV32I-WITHFP-NEXT: lw a2, 12(a7) ; RV32I-WITHFP-NEXT: lw t0, 0(a7)
; RV32I-WITHFP-NEXT: xor a1, a2, a1 ; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a2, 4(a0) ; RV32I-WITHFP-NEXT: lw a4, 12(a0)
; RV32I-WITHFP-NEXT: lw a3, 4(a7) ; RV32I-WITHFP-NEXT: lw a5, 12(a7)
; RV32I-WITHFP-NEXT: xor a2, a3, a2 ; RV32I-WITHFP-NEXT: lw a1, 4(a7)
; RV32I-WITHFP-NEXT: or a1, a2, a1 ; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: lw a2, 8(a0) ; RV32I-WITHFP-NEXT: lw a2, 8(a7)
; RV32I-WITHFP-NEXT: lw a3, 8(a7) ; RV32I-WITHFP-NEXT: xor a4, a5, a4
; RV32I-WITHFP-NEXT: xor a2, a3, a2 ; RV32I-WITHFP-NEXT: xor a1, a1, a3
; RV32I-WITHFP-NEXT: lw a0, 0(a0) ; RV32I-WITHFP-NEXT: or a1, a1, a4
; RV32I-WITHFP-NEXT: lw a3, 0(a7) ; RV32I-WITHFP-NEXT: xor a0, a2, a0
; RV32I-WITHFP-NEXT: xor a0, a3, a0 ; RV32I-WITHFP-NEXT: xor a2, t0, a6
; RV32I-WITHFP-NEXT: or a0, a0, a2 ; RV32I-WITHFP-NEXT: or a0, a2, a0
; RV32I-WITHFP-NEXT: or a0, a0, a1 ; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%j_bitcast = bitcast fp128 %j to i128 %j_bitcast = bitcast fp128 %j to i128
%1 = icmp eq i128 %h, %j_bitcast %1 = icmp eq i128 %h, %j_bitcast
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; RV32I-FPELIM-NEXT: lui a0, 524272 ; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 28(sp) ; RV32I-FPELIM-NEXT: sw a0, 28(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp) ; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp) ; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp) ; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 52(sp) ; RV32I-FPELIM-NEXT: sw zero, 52(sp)
; RV32I-FPELIM-NEXT: sw zero, 48(sp) ; RV32I-FPELIM-NEXT: sw zero, 48(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp) ; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8 ; RV32I-FPELIM-NEXT: addi t0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
; RV32I-FPELIM-NEXT: addi a7, sp, 40 ; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3 ; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4 ; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: addi a4, zero, 5 ; RV32I-FPELIM-NEXT: addi a4, zero, 5
; RV32I-FPELIM-NEXT: addi a5, zero, 6 ; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7 ; RV32I-FPELIM-NEXT: addi a6, zero, 7
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs: ; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64 ; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp) ; RV32I-WITHFP-NEXT: sw ra, 60(sp)
; RV32I-WITHFP-NEXT: sw s0, 56(sp) ; RV32I-WITHFP-NEXT: sw s0, 56(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 64 ; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, s0, -48 ; RV32I-WITHFP-NEXT: addi a0, s0, -48
; RV32I-WITHFP-NEXT: sw a0, 4(sp) ; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 9 ; RV32I-WITHFP-NEXT: addi a0, zero, 9
; RV32I-WITHFP-NEXT: sw a0, 0(sp) ; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: lui a0, 524272 ; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0) ; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0) ; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0) ; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0) ; RV32I-WITHFP-NEXT: sw zero, -12(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0) ; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 8 ; RV32I-WITHFP-NEXT: addi t0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: addi a7, s0, -24 ; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3 ; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4 ; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: addi a4, zero, 5 ; RV32I-WITHFP-NEXT: addi a4, zero, 5
; RV32I-WITHFP-NEXT: addi a5, zero, 6 ; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7 ; RV32I-WITHFP-NEXT: addi a6, zero, 7
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64 ; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_large_scalars_exhausted_regs( %1 = call i32 @callee_large_scalars_exhausted_regs(
i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
fp128 0xL00000000000000007FFF000000000000) fp128 0xL00000000000000007FFF000000000000)
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; Check large struct arguments, which are passed byval ; Check large struct arguments, which are passed byval
%struct.large = type { i32, i32, i32, i32 } %struct.large = type { i32, i32, i32, i32 }
define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind { define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind {
; RV32I-FPELIM-LABEL: callee_large_struct: ; RV32I-FPELIM-LABEL: callee_large_struct:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a1, 12(a0) ; RV32I-FPELIM-NEXT: lw a1, 0(a0)
; RV32I-FPELIM-NEXT: lw a0, 0(a0) ; RV32I-FPELIM-NEXT: lw a0, 12(a0)
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_struct: ; RV32I-WITHFP-LABEL: callee_large_struct:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a1, 12(a0) ; RV32I-WITHFP-NEXT: lw a1, 0(a0)
; RV32I-WITHFP-NEXT: lw a0, 0(a0) ; RV32I-WITHFP-NEXT: lw a0, 12(a0)
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0 %1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0
%2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3 %2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3
%3 = load i32, i32* %1 %3 = load i32, i32* %1
%4 = load i32, i32* %2 %4 = load i32, i32* %2
%5 = add i32 %3, %4 %5 = add i32 %3, %4
ret i32 %5 ret i32 %5
} }
define i32 @caller_large_struct() nounwind { define i32 @caller_large_struct() nounwind {
; RV32I-FPELIM-LABEL: caller_large_struct: ; RV32I-FPELIM-LABEL: caller_large_struct:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48 ; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp) ; RV32I-FPELIM-NEXT: sw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: sw a0, 24(sp) ; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 28(sp)
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: sw a2, 32(sp)
; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: sw a3, 36(sp)
; RV32I-FPELIM-NEXT: sw a0, 8(sp) ; RV32I-FPELIM-NEXT: sw a0, 8(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 2 ; RV32I-FPELIM-NEXT: sw a1, 12(sp)
; RV32I-FPELIM-NEXT: sw a0, 28(sp) ; RV32I-FPELIM-NEXT: sw a2, 16(sp)
; RV32I-FPELIM-NEXT: sw a0, 12(sp) ; RV32I-FPELIM-NEXT: sw a3, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 3
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 4
; RV32I-FPELIM-NEXT: sw a0, 36(sp)
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 8 ; RV32I-FPELIM-NEXT: addi a0, sp, 8
; RV32I-FPELIM-NEXT: call callee_large_struct ; RV32I-FPELIM-NEXT: call callee_large_struct
; RV32I-FPELIM-NEXT: lw ra, 44(sp) ; RV32I-FPELIM-NEXT: lw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_struct: ; RV32I-WITHFP-LABEL: caller_large_struct:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -48 ; RV32I-WITHFP-NEXT: addi sp, sp, -48
; RV32I-WITHFP-NEXT: sw ra, 44(sp) ; RV32I-WITHFP-NEXT: sw ra, 44(sp)
; RV32I-WITHFP-NEXT: sw s0, 40(sp) ; RV32I-WITHFP-NEXT: sw s0, 40(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 48 ; RV32I-WITHFP-NEXT: addi s0, sp, 48
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: sw a0, -24(s0) ; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, -20(s0)
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: sw a2, -16(s0)
; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: sw a3, -12(s0)
; RV32I-WITHFP-NEXT: sw a0, -40(s0) ; RV32I-WITHFP-NEXT: sw a0, -40(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 2 ; RV32I-WITHFP-NEXT: sw a1, -36(s0)
; RV32I-WITHFP-NEXT: sw a0, -20(s0) ; RV32I-WITHFP-NEXT: sw a2, -32(s0)
; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw a3, -28(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 3
; RV32I-WITHFP-NEXT: sw a0, -16(s0)
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 4
; RV32I-WITHFP-NEXT: sw a0, -12(s0)
; RV32I-WITHFP-NEXT: sw a0, -28(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -40 ; RV32I-WITHFP-NEXT: addi a0, s0, -40
; RV32I-WITHFP-NEXT: call callee_large_struct ; RV32I-WITHFP-NEXT: call callee_large_struct
; RV32I-WITHFP-NEXT: lw s0, 40(sp) ; RV32I-WITHFP-NEXT: lw s0, 40(sp)
; RV32I-WITHFP-NEXT: lw ra, 44(sp) ; RV32I-WITHFP-NEXT: lw ra, 44(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48 ; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%ls = alloca %struct.large, align 4 %ls = alloca %struct.large, align 4
%1 = bitcast %struct.large* %ls to i8* %1 = bitcast %struct.large* %ls to i8*
Show All 12 Lines
; Check 2x*xlen values are aligned appropriately when passed on the stack ; Check 2x*xlen values are aligned appropriately when passed on the stack
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, i64 %i, i32 %j, [2 x i32] %k) nounwind { define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, i64 %i, i32 %j, [2 x i32] %k) nounwind {
; The i64 should be 8-byte aligned on the stack, but the two-element array ; The i64 should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned ; should only be 4-byte aligned
; RV32I-FPELIM-LABEL: callee_aligned_stack: ; RV32I-FPELIM-LABEL: callee_aligned_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 0(a2) ; RV32I-FPELIM-NEXT: lw a0, 0(a2)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: lw a1, 0(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 8(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 20(sp) ; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: lw a2, 0(sp)
; RV32I-FPELIM-NEXT: lw a3, 8(sp)
; RV32I-FPELIM-NEXT: lw a4, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: add a0, a0, a2
; RV32I-FPELIM-NEXT: add a0, a0, a3
; RV32I-FPELIM-NEXT: add a0, a0, a4
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_aligned_stack: ; RV32I-WITHFP-LABEL: callee_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(a2) ; RV32I-WITHFP-NEXT: lw a0, 0(a2)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: lw a1, 0(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 8(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 20(s0) ; RV32I-WITHFP-NEXT: lw a1, 20(s0)
; RV32I-WITHFP-NEXT: lw a2, 0(s0)
; RV32I-WITHFP-NEXT: lw a3, 8(s0)
; RV32I-WITHFP-NEXT: lw a4, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a3
; RV32I-WITHFP-NEXT: add a0, a0, a4
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = bitcast fp128 %c to i128 %1 = bitcast fp128 %c to i128
%2 = trunc i128 %1 to i32 %2 = trunc i128 %1 to i32
%3 = add i32 %2, %g %3 = add i32 %2, %g
Show All 29 Lines
; RV32I-FPELIM-NEXT: sw a0, 44(sp) ; RV32I-FPELIM-NEXT: sw a0, 44(sp)
; RV32I-FPELIM-NEXT: lui a0, 545260 ; RV32I-FPELIM-NEXT: lui a0, 545260
; RV32I-FPELIM-NEXT: addi a0, a0, -1967 ; RV32I-FPELIM-NEXT: addi a0, a0, -1967
; RV32I-FPELIM-NEXT: sw a0, 40(sp) ; RV32I-FPELIM-NEXT: sw a0, 40(sp)
; RV32I-FPELIM-NEXT: lui a0, 964690 ; RV32I-FPELIM-NEXT: lui a0, 964690
; RV32I-FPELIM-NEXT: addi a0, a0, -328 ; RV32I-FPELIM-NEXT: addi a0, a0, -328
; RV32I-FPELIM-NEXT: sw a0, 36(sp) ; RV32I-FPELIM-NEXT: sw a0, 36(sp)
; RV32I-FPELIM-NEXT: lui a0, 335544 ; RV32I-FPELIM-NEXT: lui a0, 335544
; RV32I-FPELIM-NEXT: addi a0, a0, 1311 ; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: lui a0, 688509 ; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048 ; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32 ; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11 ; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a3, zero, 12 ; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13 ; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14 ; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp)
; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_aligned_stack: ; RV32I-WITHFP-LABEL: caller_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64 ; RV32I-WITHFP-NEXT: addi sp, sp, -64
Show All 16 Lines
; RV32I-WITHFP-NEXT: sw a0, -20(s0) ; RV32I-WITHFP-NEXT: sw a0, -20(s0)
; RV32I-WITHFP-NEXT: lui a0, 545260 ; RV32I-WITHFP-NEXT: lui a0, 545260
; RV32I-WITHFP-NEXT: addi a0, a0, -1967 ; RV32I-WITHFP-NEXT: addi a0, a0, -1967
; RV32I-WITHFP-NEXT: sw a0, -24(s0) ; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: lui a0, 964690 ; RV32I-WITHFP-NEXT: lui a0, 964690
; RV32I-WITHFP-NEXT: addi a0, a0, -328 ; RV32I-WITHFP-NEXT: addi a0, a0, -328
; RV32I-WITHFP-NEXT: sw a0, -28(s0) ; RV32I-WITHFP-NEXT: sw a0, -28(s0)
; RV32I-WITHFP-NEXT: lui a0, 335544 ; RV32I-WITHFP-NEXT: lui a0, 335544
; RV32I-WITHFP-NEXT: addi a0, a0, 1311 ; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, 688509 ; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048 ; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32 ; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11 ; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a3, zero, 12 ; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13 ; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14 ; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0)
; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64 ; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_aligned_stack(i32 1, i32 11, %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
i64 20000000000, i32 14, i32 15, i64 16, i32 17, i64 20000000000, i32 14, i32 15, i64 16, i32 17,
Show All 27 Lines; RV32I-WITHFP-NEXT: ret
ret i64 1234567898765 ret i64 1234567898765
} }
define i32 @caller_small_scalar_ret() nounwind { define i32 @caller_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_small_scalar_ret: ; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: sw s0, 8(sp)
; RV32I-FPELIM-NEXT: lui a0, 56
; RV32I-FPELIM-NEXT: addi s0, a0, 580
; RV32I-FPELIM-NEXT: call callee_small_scalar_ret ; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
; RV32I-FPELIM-NEXT: xor a1, a1, s0 ; RV32I-FPELIM-NEXT: lui a2, 56
; RV32I-FPELIM-NEXT: addi a2, a2, 580
; RV32I-FPELIM-NEXT: xor a1, a1, a2
; RV32I-FPELIM-NEXT: lui a2, 200614 ; RV32I-FPELIM-NEXT: lui a2, 200614
; RV32I-FPELIM-NEXT: addi a2, a2, 647 ; RV32I-FPELIM-NEXT: addi a2, a2, 647
; RV32I-FPELIM-NEXT: xor a0, a0, a2 ; RV32I-FPELIM-NEXT: xor a0, a0, a2
; RV32I-FPELIM-NEXT: or a0, a0, a1 ; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: lw s0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_small_scalar_ret: ; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: sw s1, 4(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a0, 56
; RV32I-WITHFP-NEXT: addi s1, a0, 580
; RV32I-WITHFP-NEXT: call callee_small_scalar_ret ; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
; RV32I-WITHFP-NEXT: xor a1, a1, s1 ; RV32I-WITHFP-NEXT: lui a2, 56
; RV32I-WITHFP-NEXT: addi a2, a2, 580
; RV32I-WITHFP-NEXT: xor a1, a1, a2
; RV32I-WITHFP-NEXT: lui a2, 200614 ; RV32I-WITHFP-NEXT: lui a2, 200614
; RV32I-WITHFP-NEXT: addi a2, a2, 647 ; RV32I-WITHFP-NEXT: addi a2, a2, 647
; RV32I-WITHFP-NEXT: xor a0, a0, a2 ; RV32I-WITHFP-NEXT: xor a0, a0, a2
; RV32I-WITHFP-NEXT: or a0, a0, a1 ; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s1, 4(sp)
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i64 @callee_small_scalar_ret() %1 = call i64 @callee_small_scalar_ret()
%2 = icmp eq i64 987654321234567, %1 %2 = icmp eq i64 987654321234567, %1
%3 = zext i1 %2 to i32 %3 = zext i1 %2 to i32
ret i32 %3 ret i32 %3
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines; RV32I-WITHFP-NEXT: ret
ret void ret void
} }
; Check return of >2x xlen structs ; Check return of >2x xlen structs
define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind { define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
; RV32I-FPELIM-LABEL: callee_large_struct_ret: ; RV32I-FPELIM-LABEL: callee_large_struct_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi a1, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 3
; RV32I-FPELIM-NEXT: sw a1, 8(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 4(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 1
; RV32I-FPELIM-NEXT: sw a1, 0(a0) ; RV32I-FPELIM-NEXT: sw a1, 0(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 4(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 3
; RV32I-FPELIM-NEXT: sw a1, 8(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_struct_ret: ; RV32I-WITHFP-LABEL: callee_large_struct_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a1, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 3
; RV32I-WITHFP-NEXT: sw a1, 8(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, 4(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 1
; RV32I-WITHFP-NEXT: sw a1, 0(a0) ; RV32I-WITHFP-NEXT: sw a1, 0(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, 4(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 3
; RV32I-WITHFP-NEXT: sw a1, 8(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0 %a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0
store i32 1, i32* %a, align 4 store i32 1, i32* %a, align 4
%b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1 %b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1
store i32 2, i32* %b, align 4 store i32 2, i32* %b, align 4
%c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 2 %c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 2
store i32 3, i32* %c, align 4 store i32 3, i32* %c, align 4
%d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 3 %d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 3
store i32 4, i32* %d, align 4 store i32 4, i32* %d, align 4
ret void ret void
} }
define i32 @caller_large_struct_ret() nounwind { define i32 @caller_large_struct_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_large_struct_ret: ; RV32I-FPELIM-LABEL: caller_large_struct_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) ; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 8 ; RV32I-FPELIM-NEXT: addi a0, sp, 8
; RV32I-FPELIM-NEXT: call callee_large_struct_ret ; RV32I-FPELIM-NEXT: call callee_large_struct_ret
; RV32I-FPELIM-NEXT: lw a0, 20(sp) ; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw a1, 8(sp) ; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: add a0, a1, a0 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_struct_ret: ; RV32I-WITHFP-LABEL: caller_large_struct_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32 ; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: call callee_large_struct_ret ; RV32I-WITHFP-NEXT: call callee_large_struct_ret
; RV32I-WITHFP-NEXT: lw a0, -12(s0) ; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw a1, -24(s0) ; RV32I-WITHFP-NEXT: lw a1, -12(s0)
; RV32I-WITHFP-NEXT: add a0, a1, a0 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 32 ; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = alloca %struct.large %1 = alloca %struct.large
call void @callee_large_struct_ret(%struct.large* sret %1) call void @callee_large_struct_ret(%struct.large* sret %1)
%2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0 %2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0
%3 = load i32, i32* %2 %3 = load i32, i32* %2
%4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3
%5 = load i32, i32* %4 %5 = load i32, i32* %4
%6 = add i32 %3, %5 %6 = add i32 %3, %5
ret i32 %6 ret i32 %6
} }

llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines; RV32I-WITHFP-NEXT: ret
ret i32 %3 ret i32 %3
} }
define i32 @caller_float_on_stack() nounwind { define i32 @caller_float_on_stack() nounwind {
; RV32I-FPELIM-LABEL: caller_float_on_stack: ; RV32I-FPELIM-LABEL: caller_float_on_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: lui a0, 264704 ; RV32I-FPELIM-NEXT: lui a1, 264704
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: addi a2, zero, 2 ; RV32I-FPELIM-NEXT: addi a2, zero, 2
; RV32I-FPELIM-NEXT: mv a3, zero
; RV32I-FPELIM-NEXT: addi a4, zero, 3 ; RV32I-FPELIM-NEXT: addi a4, zero, 3
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: mv a3, zero
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: mv a7, zero ; RV32I-FPELIM-NEXT: mv a7, zero
; RV32I-FPELIM-NEXT: call callee_float_on_stack ; RV32I-FPELIM-NEXT: call callee_float_on_stack
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_float_on_stack: ; RV32I-WITHFP-LABEL: caller_float_on_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a0, 264704 ; RV32I-WITHFP-NEXT: lui a1, 264704
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: addi a2, zero, 2 ; RV32I-WITHFP-NEXT: addi a2, zero, 2
; RV32I-WITHFP-NEXT: mv a3, zero
; RV32I-WITHFP-NEXT: addi a4, zero, 3 ; RV32I-WITHFP-NEXT: addi a4, zero, 3
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 0(sp)
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: mv a3, zero
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: mv a7, zero ; RV32I-WITHFP-NEXT: mv a7, zero
; RV32I-WITHFP-NEXT: call callee_float_on_stack ; RV32I-WITHFP-NEXT: call callee_float_on_stack
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_float_on_stack(i64 1, i64 2, i64 3, i64 4, float 5.0) %1 = call i32 @callee_float_on_stack(i64 1, i64 2, i64 3, i64 4, float 5.0)
ret i32 %1 ret i32 %1
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

Show All 32 Lines; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_fpr(i32 1, double 2.0) %1 = call i32 @callee_double_in_fpr(i32 1, double 2.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind { define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind {
; RV32-ILP32D-LABEL: callee_double_in_fpr_exhausted_gprs: ; RV32-ILP32D-LABEL: callee_double_in_fpr_exhausted_gprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: fcvt.w.d a0, fa0, rtz ; RV32-ILP32D-NEXT: lw a0, 0(sp)
; RV32-ILP32D-NEXT: lw a1, 0(sp) ; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a1, a0 ; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%f_fptosi = fptosi double %f to i32 %f_fptosi = fptosi double %f to i32
%1 = add i32 %e, %f_fptosi %1 = add i32 %e, %f_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_fpr_exhausted_gprs() nounwind { define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_fpr_exhausted_gprs: ; RV32-ILP32D-LABEL: caller_double_in_fpr_exhausted_gprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: addi a0, zero, 5 ; RV32-ILP32D-NEXT: addi a1, zero, 5
; RV32-ILP32D-NEXT: sw a0, 0(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI3_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI3_0) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI3_0)
; RV32-ILP32D-NEXT: fld fa0, 0(a0) ; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1 ; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: addi a2, zero, 2 ; RV32-ILP32D-NEXT: addi a2, zero, 2
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: addi a4, zero, 3 ; RV32-ILP32D-NEXT: addi a4, zero, 3
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: addi a6, zero, 4 ; RV32-ILP32D-NEXT: addi a6, zero, 4
; RV32-ILP32D-NEXT: sw a1, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero ; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs ; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp)
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_fpr_exhausted_gprs( %1 = call i32 @callee_double_in_fpr_exhausted_gprs(
i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0) i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind { define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind {
; RV32-ILP32D-LABEL: callee_double_in_gpr_exhausted_fprs: ; RV32-ILP32D-LABEL: callee_double_in_gpr_exhausted_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw a0, 8(sp) ; RV32-ILP32D-NEXT: sw a0, 8(sp)
; RV32-ILP32D-NEXT: sw a1, 12(sp) ; RV32-ILP32D-NEXT: sw a1, 12(sp)
; RV32-ILP32D-NEXT: fld ft0, 8(sp) ; RV32-ILP32D-NEXT: fld ft0, 8(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz
; RV32-ILP32D-NEXT: fcvt.w.d a1, fa7, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a1, ft0, rtz
; RV32-ILP32D-NEXT: add a0, a1, a0 ; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%h_fptosi = fptosi double %h to i32 %h_fptosi = fptosi double %h to i32
%i_fptosi = fptosi double %i to i32 %i_fptosi = fptosi double %i to i32
%1 = add i32 %h_fptosi, %i_fptosi %1 = add i32 %h_fptosi, %i_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_gpr_exhausted_fprs() nounwind { define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_gpr_exhausted_fprs: ; RV32-ILP32D-LABEL: caller_double_in_gpr_exhausted_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_0) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI5_1) ; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: addi a1, a1, %lo(.LCPI5_1) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI5_2) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_1)
; RV32-ILP32D-NEXT: addi a2, a2, %lo(.LCPI5_2) ; RV32-ILP32D-NEXT: fld fa1, 0(a0)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI5_3) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32D-NEXT: addi a3, a3, %lo(.LCPI5_3) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_2)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI5_4) ; RV32-ILP32D-NEXT: fld fa2, 0(a0)
; RV32-ILP32D-NEXT: addi a4, a4, %lo(.LCPI5_4) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI5_5) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_3)
; RV32-ILP32D-NEXT: addi a5, a5, %lo(.LCPI5_5) ; RV32-ILP32D-NEXT: fld fa3, 0(a0)
; RV32-ILP32D-NEXT: fld fa0, 0(a5) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32D-NEXT: fld fa1, 0(a4) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_4)
; RV32-ILP32D-NEXT: fld fa2, 0(a3) ; RV32-ILP32D-NEXT: fld fa4, 0(a0)
; RV32-ILP32D-NEXT: fld fa3, 0(a2) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa4, 0(a1) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa5, 0(a0) ; RV32-ILP32D-NEXT: fld fa5, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_6) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_6)
; RV32-ILP32D-NEXT: fld fa6, 0(a0) ; RV32-ILP32D-NEXT: fld fa6, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_7) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_7)
; RV32-ILP32D-NEXT: fld fa7, 0(a0) ; RV32-ILP32D-NEXT: fld fa7, 0(a0)
; RV32-ILP32D-NEXT: mv a0, zero
; RV32-ILP32D-NEXT: lui a1, 262688 ; RV32-ILP32D-NEXT: lui a1, 262688
; RV32-ILP32D-NEXT: mv a0, zero
; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs ; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp)
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_gpr_exhausted_fprs( %1 = call i32 @callee_double_in_gpr_exhausted_fprs(
double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,
double 7.0, double 8.0, double 9.0) double 7.0, double 8.0, double 9.0)
ret i32 %1 ret i32 %1
Show All 17 Lines; RV32-ILP32D-NEXT: ret
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind { define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs: ; RV32-ILP32D-LABEL: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: lui a0, 262816 ; RV32-ILP32D-NEXT: lui a1, 262816
; RV32-ILP32D-NEXT: sw a0, 0(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32D-NEXT: addi a6, a0, %lo(.LCPI7_0) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI7_1) ; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: addi a1, a1, %lo(.LCPI7_1) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI7_2) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_1)
; RV32-ILP32D-NEXT: addi a2, a2, %lo(.LCPI7_2) ; RV32-ILP32D-NEXT: fld fa1, 0(a0)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI7_3) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32D-NEXT: addi a3, a3, %lo(.LCPI7_3) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_2)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI7_4) ; RV32-ILP32D-NEXT: fld fa2, 0(a0)
; RV32-ILP32D-NEXT: addi a4, a4, %lo(.LCPI7_4) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_3)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI7_5) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_3)
; RV32-ILP32D-NEXT: addi a5, a5, %lo(.LCPI7_5) ; RV32-ILP32D-NEXT: fld fa3, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_4)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_4)
; RV32-ILP32D-NEXT: fld fa4, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_5)
; RV32-ILP32D-NEXT: fld fa5, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_6) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_6)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_6) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_6)
; RV32-ILP32D-NEXT: fld fa0, 0(a0) ; RV32-ILP32D-NEXT: fld fa6, 0(a0)
; RV32-ILP32D-NEXT: fld fa1, 0(a5)
; RV32-ILP32D-NEXT: fld fa2, 0(a4)
; RV32-ILP32D-NEXT: fld fa3, 0(a3)
; RV32-ILP32D-NEXT: fld fa4, 0(a2)
; RV32-ILP32D-NEXT: fld fa5, 0(a1)
; RV32-ILP32D-NEXT: fld fa6, 0(a6)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_7) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_7)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_7) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_7)
; RV32-ILP32D-NEXT: fld fa7, 0(a0) ; RV32-ILP32D-NEXT: fld fa7, 0(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1 ; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: addi a2, zero, 3 ; RV32-ILP32D-NEXT: addi a2, zero, 3
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: addi a4, zero, 5 ; RV32-ILP32D-NEXT: addi a4, zero, 5
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: addi a6, zero, 7 ; RV32-ILP32D-NEXT: addi a6, zero, 7
; RV32-ILP32D-NEXT: sw a1, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero ; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs ; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp)
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs( %1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(
i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0, i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0,
double 9.0, double 10.0, double 11.0, double 12.0, double 13.0) double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
Show All 17 Lines
define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind { define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_on_stack_exhausted_gprs_fprs: ; RV32-ILP32D-LABEL: caller_double_on_stack_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: lui a0, 262816 ; RV32-ILP32D-NEXT: lui a0, 262816
; RV32-ILP32D-NEXT: sw a0, 4(sp) ; RV32-ILP32D-NEXT: sw a0, 4(sp)
; RV32-ILP32D-NEXT: sw zero, 0(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-ILP32D-NEXT: addi a6, a0, %lo(.LCPI9_0) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI9_1) ; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: addi a1, a1, %lo(.LCPI9_1) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI9_2) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_1)
; RV32-ILP32D-NEXT: addi a2, a2, %lo(.LCPI9_2) ; RV32-ILP32D-NEXT: fld fa1, 0(a0)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI9_3) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_2)
; RV32-ILP32D-NEXT: addi a3, a3, %lo(.LCPI9_3) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_2)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI9_4) ; RV32-ILP32D-NEXT: fld fa2, 0(a0)
; RV32-ILP32D-NEXT: addi a4, a4, %lo(.LCPI9_4) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_3)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI9_5) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_3)
; RV32-ILP32D-NEXT: addi a5, a5, %lo(.LCPI9_5) ; RV32-ILP32D-NEXT: fld fa3, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_4)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_4)
; RV32-ILP32D-NEXT: fld fa4, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_5)
; RV32-ILP32D-NEXT: fld fa5, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_6) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_6)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_6) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_6)
; RV32-ILP32D-NEXT: fld fa0, 0(a0) ; RV32-ILP32D-NEXT: fld fa6, 0(a0)
; RV32-ILP32D-NEXT: fld fa1, 0(a5)
; RV32-ILP32D-NEXT: fld fa2, 0(a4)
; RV32-ILP32D-NEXT: fld fa3, 0(a3)
; RV32-ILP32D-NEXT: fld fa4, 0(a2)
; RV32-ILP32D-NEXT: fld fa5, 0(a1)
; RV32-ILP32D-NEXT: fld fa6, 0(a6)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_7) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_7)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_7) ; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_7)
; RV32-ILP32D-NEXT: fld fa7, 0(a0) ; RV32-ILP32D-NEXT: fld fa7, 0(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1 ; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: addi a2, zero, 3 ; RV32-ILP32D-NEXT: addi a2, zero, 3
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: addi a4, zero, 5 ; RV32-ILP32D-NEXT: addi a4, zero, 5
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: addi a6, zero, 7 ; RV32-ILP32D-NEXT: addi a6, zero, 7
; RV32-ILP32D-NEXT: sw zero, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero ; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs ; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp)
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs( %1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs(
i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0, i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0,
double 9.0, double 10.0, double 11.0, double 12.0, double 13.0) double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
Show All 29 Lines

llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll

Show All 35 Lines; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_in_fpr(i32 1, float 2.0) %1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind { define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs: ; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa0, rtz ; RV32-ILP32FD-NEXT: lw a0, 0(sp)
; RV32-ILP32FD-NEXT: lw a1, 0(sp) ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a1, a0 ; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%f_fptosi = fptosi float %f to i32 %f_fptosi = fptosi float %f to i32
%1 = add i32 %e, %f_fptosi %1 = add i32 %e, %f_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_in_fpr_exhausted_gprs() nounwind { define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs: ; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp)
; RV32-ILP32FD-NEXT: addi a0, zero, 5 ; RV32-ILP32FD-NEXT: addi a1, zero, 5
; RV32-ILP32FD-NEXT: sw a0, 0(sp)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI3_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI3_0) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI3_0)
; RV32-ILP32FD-NEXT: flw fa0, 0(a0) ; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1 ; RV32-ILP32FD-NEXT: addi a0, zero, 1
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: addi a2, zero, 2 ; RV32-ILP32FD-NEXT: addi a2, zero, 2
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: addi a4, zero, 3 ; RV32-ILP32FD-NEXT: addi a4, zero, 3
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: addi a6, zero, 4 ; RV32-ILP32FD-NEXT: addi a6, zero, 4
; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero ; RV32-ILP32FD-NEXT: mv a7, zero
; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs ; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp)
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_in_fpr_exhausted_gprs( %1 = call i32 @callee_float_in_fpr_exhausted_gprs(
i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0) i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind { define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs: ; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa7, rtz
; RV32-ILP32FD-NEXT: fmv.w.x ft0, a0 ; RV32-ILP32FD-NEXT: fmv.w.x ft0, a0
; RV32-ILP32FD-NEXT: fcvt.w.s a0, ft0, rtz ; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
; RV32-ILP32FD-NEXT: add a0, a1, a0 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, ft0, rtz
; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%h_fptosi = fptosi float %h to i32 %h_fptosi = fptosi float %h to i32
%i_fptosi = fptosi float %i to i32 %i_fptosi = fptosi float %i to i32
%1 = add i32 %h_fptosi, %i_fptosi %1 = add i32 %h_fptosi, %i_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_in_gpr_exhausted_fprs() nounwind { define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs: ; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_0) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV32-ILP32FD-NEXT: lui a1, %hi(.LCPI5_1) ; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: addi a1, a1, %lo(.LCPI5_1) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32FD-NEXT: lui a2, %hi(.LCPI5_2) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_1)
; RV32-ILP32FD-NEXT: addi a2, a2, %lo(.LCPI5_2) ; RV32-ILP32FD-NEXT: flw fa1, 0(a0)
; RV32-ILP32FD-NEXT: lui a3, %hi(.LCPI5_3) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32FD-NEXT: addi a3, a3, %lo(.LCPI5_3) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_2)
; RV32-ILP32FD-NEXT: lui a4, %hi(.LCPI5_4) ; RV32-ILP32FD-NEXT: flw fa2, 0(a0)
; RV32-ILP32FD-NEXT: addi a4, a4, %lo(.LCPI5_4) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32FD-NEXT: lui a5, %hi(.LCPI5_5) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_3)
; RV32-ILP32FD-NEXT: addi a5, a5, %lo(.LCPI5_5) ; RV32-ILP32FD-NEXT: flw fa3, 0(a0)
; RV32-ILP32FD-NEXT: flw fa0, 0(a5) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32FD-NEXT: flw fa1, 0(a4) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_4)
; RV32-ILP32FD-NEXT: flw fa2, 0(a3) ; RV32-ILP32FD-NEXT: flw fa4, 0(a0)
; RV32-ILP32FD-NEXT: flw fa3, 0(a2) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32FD-NEXT: flw fa4, 0(a1) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_5)
; RV32-ILP32FD-NEXT: flw fa5, 0(a0) ; RV32-ILP32FD-NEXT: flw fa5, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_6) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_6) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_6)
; RV32-ILP32FD-NEXT: flw fa6, 0(a0) ; RV32-ILP32FD-NEXT: flw fa6, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_7) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_7) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_7)
; RV32-ILP32FD-NEXT: flw fa7, 0(a0) ; RV32-ILP32FD-NEXT: flw fa7, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, 266496 ; RV32-ILP32FD-NEXT: lui a0, 266496
Show All 21 Lines; RV32-ILP32FD-NEXT: ret
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind { define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs: ; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp)
; RV32-ILP32FD-NEXT: lui a0, 267520 ; RV32-ILP32FD-NEXT: lui a1, 267520
; RV32-ILP32FD-NEXT: sw a0, 0(sp)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32FD-NEXT: addi a6, a0, %lo(.LCPI7_0) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_0)
; RV32-ILP32FD-NEXT: lui a1, %hi(.LCPI7_1) ; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: addi a1, a1, %lo(.LCPI7_1) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32FD-NEXT: lui a2, %hi(.LCPI7_2) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_1)
; RV32-ILP32FD-NEXT: addi a2, a2, %lo(.LCPI7_2) ; RV32-ILP32FD-NEXT: flw fa1, 0(a0)
; RV32-ILP32FD-NEXT: lui a3, %hi(.LCPI7_3) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32FD-NEXT: addi a3, a3, %lo(.LCPI7_3) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_2)
; RV32-ILP32FD-NEXT: lui a4, %hi(.LCPI7_4) ; RV32-ILP32FD-NEXT: flw fa2, 0(a0)
; RV32-ILP32FD-NEXT: addi a4, a4, %lo(.LCPI7_4) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_3)
; RV32-ILP32FD-NEXT: lui a5, %hi(.LCPI7_5) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_3)
; RV32-ILP32FD-NEXT: addi a5, a5, %lo(.LCPI7_5) ; RV32-ILP32FD-NEXT: flw fa3, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_4)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_4)
; RV32-ILP32FD-NEXT: flw fa4, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_5)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_5)
; RV32-ILP32FD-NEXT: flw fa5, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_6) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_6)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_6) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_6)
; RV32-ILP32FD-NEXT: flw fa0, 0(a0) ; RV32-ILP32FD-NEXT: flw fa6, 0(a0)
; RV32-ILP32FD-NEXT: flw fa1, 0(a5)
; RV32-ILP32FD-NEXT: flw fa2, 0(a4)
; RV32-ILP32FD-NEXT: flw fa3, 0(a3)
; RV32-ILP32FD-NEXT: flw fa4, 0(a2)
; RV32-ILP32FD-NEXT: flw fa5, 0(a1)
; RV32-ILP32FD-NEXT: flw fa6, 0(a6)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_7) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_7)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_7) ; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_7)
; RV32-ILP32FD-NEXT: flw fa7, 0(a0) ; RV32-ILP32FD-NEXT: flw fa7, 0(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1 ; RV32-ILP32FD-NEXT: addi a0, zero, 1
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: addi a2, zero, 3 ; RV32-ILP32FD-NEXT: addi a2, zero, 3
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: addi a4, zero, 5 ; RV32-ILP32FD-NEXT: addi a4, zero, 5
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: addi a6, zero, 7 ; RV32-ILP32FD-NEXT: addi a6, zero, 7
; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero ; RV32-ILP32FD-NEXT: mv a7, zero
; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs ; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp)
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs( %1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(
i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0, i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,
float 9.0, float 10.0, float 11.0, float 12.0, float 13.0) float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)
Show All 27 Lines

llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i64 %1 ret i64 %1
} }
; Check that the stack is used once the GPRs are exhausted ; Check that the stack is used once the GPRs are exhausted
define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f, i128 %g, i32 %h) nounwind { define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f, i128 %g, i32 %h) nounwind {
; RV64I-LABEL: callee_many_scalars: ; RV64I-LABEL: callee_many_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld t0, 0(sp) ; RV64I-NEXT: lw t0, 8(sp)
; RV64I-NEXT: xor a4, a4, t0 ; RV64I-NEXT: ld t1, 0(sp)
; RV64I-NEXT: xor a3, a3, a7 ; RV64I-NEXT: andi t2, a0, 255
; RV64I-NEXT: or a3, a3, a4 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: lui a4, 16 ; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addiw a4, a4, -1 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: and a1, a1, a4 ; RV64I-NEXT: add a0, t2, a0
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: seqz a1, a3 ; RV64I-NEXT: xor a1, a4, t1
; RV64I-NEXT: xor a2, a3, a7
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: add a0, a0, a5 ; RV64I-NEXT: add a0, a0, a5
; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: lw a1, 8(sp) ; RV64I-NEXT: addw a0, a0, t0
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ext = zext i8 %a to i32 %a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32 %b_ext = zext i16 %b to i32
%1 = add i32 %a_ext, %b_ext %1 = add i32 %a_ext, %b_ext
%2 = add i32 %1, %c %2 = add i32 %1, %c
%3 = icmp eq i128 %d, %g %3 = icmp eq i128 %d, %g
%4 = zext i1 %3 to i32 %4 = zext i1 %3 to i32
%5 = add i32 %4, %2 %5 = add i32 %4, %2
%6 = add i32 %5, %e %6 = add i32 %5, %e
%7 = add i32 %6, %f %7 = add i32 %6, %f
%8 = add i32 %7, %h %8 = add i32 %7, %h
ret i32 %8 ret i32 %8
} }
define i32 @caller_many_scalars() nounwind { define i32 @caller_many_scalars() nounwind {
; RV64I-LABEL: caller_many_scalars: ; RV64I-LABEL: caller_many_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp)
; RV64I-NEXT: addi a0, zero, 8 ; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: addi a5, zero, 5 ; RV64I-NEXT: addi a5, zero, 5
; RV64I-NEXT: addi a6, zero, 6 ; RV64I-NEXT: addi a6, zero, 6
; RV64I-NEXT: addi a7, zero, 7 ; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call callee_many_scalars ; RV64I-NEXT: call callee_many_scalars
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp)
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8) %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8)
ret i32 %1 ret i32 %1
} }
; Check that i256 is passed indirectly. ; Check that i256 is passed indirectly.
define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind { define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
; RV64I-LABEL: callee_large_scalars: ; RV64I-LABEL: callee_large_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld a2, 24(a1) ; RV64I-NEXT: ld a6, 0(a1)
; RV64I-NEXT: ld a3, 24(a0) ; RV64I-NEXT: ld a7, 0(a0)
; RV64I-NEXT: xor a2, a3, a2 ; RV64I-NEXT: ld a4, 8(a1)
; RV64I-NEXT: ld a3, 8(a1) ; RV64I-NEXT: ld a5, 24(a1)
; RV64I-NEXT: ld a4, 8(a0) ; RV64I-NEXT: ld a2, 24(a0)
; RV64I-NEXT: xor a3, a4, a3 ; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a1, 16(a1)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: xor a3, a3, a4
; RV64I-NEXT: or a2, a3, a2 ; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: ld a3, 16(a1)
; RV64I-NEXT: ld a4, 16(a0)
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a1, 0(a1)
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: xor a1, a7, a6
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = icmp eq i256 %a, %b %1 = icmp eq i256 %a, %b
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @caller_large_scalars() nounwind { define i64 @caller_large_scalars() nounwind {
; RV64I-LABEL: caller_large_scalars: ; RV64I-LABEL: caller_large_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -80 ; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 72(sp) ; RV64I-NEXT: sd ra, 72(sp)
; RV64I-NEXT: addi a0, zero, 2
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd zero, 16(sp) ; RV64I-NEXT: sd zero, 16(sp)
; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: sd zero, 8(sp)
; RV64I-NEXT: addi a0, zero, 2
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: sd zero, 48(sp) ; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: addi a0, sp, 32 ; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd a2, 32(sp)
; RV64I-NEXT: call callee_large_scalars ; RV64I-NEXT: call callee_large_scalars
; RV64I-NEXT: ld ra, 72(sp) ; RV64I-NEXT: ld ra, 72(sp)
; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_large_scalars(i256 1, i256 2) %1 = call i64 @callee_large_scalars(i256 1, i256 2)
ret i64 %1 ret i64 %1
} }
; Check that arguments larger than 2*xlen are handled correctly when their ; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory ; address is passed on the stack rather than in memory
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i256 %h, i64 %i, i256 %j) nounwind { define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i256 %h, i64 %i, i256 %j) nounwind {
; RV64I-LABEL: callee_large_scalars_exhausted_regs: ; RV64I-LABEL: callee_large_scalars_exhausted_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld a0, 8(sp) ; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 24(a0) ; RV64I-NEXT: ld a6, 0(a0)
; RV64I-NEXT: ld a2, 24(a7) ; RV64I-NEXT: ld t0, 0(a7)
; RV64I-NEXT: xor a1, a2, a1 ; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a2, 8(a0) ; RV64I-NEXT: ld a4, 24(a0)
; RV64I-NEXT: ld a3, 8(a7) ; RV64I-NEXT: ld a5, 24(a7)
; RV64I-NEXT: xor a2, a3, a2 ; RV64I-NEXT: ld a1, 8(a7)
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: ld a2, 16(a0) ; RV64I-NEXT: ld a2, 16(a7)
; RV64I-NEXT: ld a3, 16(a7) ; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a2, a3, a2 ; RV64I-NEXT: xor a1, a1, a3
; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: or a1, a1, a4
; RV64I-NEXT: ld a3, 0(a7) ; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: xor a0, a3, a0 ; RV64I-NEXT: xor a2, t0, a6
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = icmp eq i256 %h, %j %1 = icmp eq i256 %h, %j
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @caller_large_scalars_exhausted_regs() nounwind { define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-LABEL: caller_large_scalars_exhausted_regs: ; RV64I-LABEL: caller_large_scalars_exhausted_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd ra, 88(sp)
; RV64I-NEXT: addi a0, sp, 16 ; RV64I-NEXT: addi a0, sp, 16
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: addi a0, zero, 9 ; RV64I-NEXT: addi a0, zero, 9
; RV64I-NEXT: sd a0, 0(sp) ; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 32(sp) ; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: sd zero, 72(sp) ; RV64I-NEXT: sd zero, 72(sp)
; RV64I-NEXT: sd zero, 64(sp) ; RV64I-NEXT: sd zero, 64(sp)
; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: addi a0, zero, 8 ; RV64I-NEXT: addi t0, zero, 8
; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: addi a7, sp, 48 ; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6 ; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: addi a6, zero, 7 ; RV64I-NEXT: addi a6, zero, 7
; RV64I-NEXT: sd t0, 48(sp)
; RV64I-NEXT: call callee_large_scalars_exhausted_regs ; RV64I-NEXT: call callee_large_scalars_exhausted_regs
; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: ld ra, 88(sp)
; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_large_scalars_exhausted_regs( %1 = call i64 @callee_large_scalars_exhausted_regs(
i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9,
i256 10) i256 10)
ret i64 %1 ret i64 %1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; Check large struct arguments, which are passed byval ; Check large struct arguments, which are passed byval
%struct.large = type { i64, i64, i64, i64 } %struct.large = type { i64, i64, i64, i64 }
define i64 @callee_large_struct(%struct.large* byval align 8 %a) nounwind { define i64 @callee_large_struct(%struct.large* byval align 8 %a) nounwind {
; RV64I-LABEL: callee_large_struct: ; RV64I-LABEL: callee_large_struct:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld a1, 24(a0) ; RV64I-NEXT: ld a1, 0(a0)
; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: ld a0, 24(a0)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 0 %1 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 0
%2 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 3 %2 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 3
%3 = load i64, i64* %1 %3 = load i64, i64* %1
%4 = load i64, i64* %2 %4 = load i64, i64* %2
%5 = add i64 %3, %4 %5 = add i64 %3, %4
ret i64 %5 ret i64 %5
} }
define i64 @caller_large_struct() nounwind { define i64 @caller_large_struct() nounwind {
; RV64I-LABEL: caller_large_struct: ; RV64I-LABEL: caller_large_struct:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -80 ; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 72(sp) ; RV64I-NEXT: sd ra, 72(sp)
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sd a1, 48(sp)
; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: sd a2, 56(sp)
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: sd a3, 64(sp)
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: addi a0, zero, 2 ; RV64I-NEXT: sd a1, 16(sp)
; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: sd a2, 24(sp)
; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: addi a0, zero, 3
; RV64I-NEXT: sd a0, 56(sp)
; RV64I-NEXT: sd a0, 24(sp)
; RV64I-NEXT: addi a0, zero, 4
; RV64I-NEXT: sd a0, 64(sp)
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: addi a0, sp, 8 ; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct ; RV64I-NEXT: call callee_large_struct
; RV64I-NEXT: ld ra, 72(sp) ; RV64I-NEXT: ld ra, 72(sp)
; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%ls = alloca %struct.large, align 8 %ls = alloca %struct.large, align 8
%1 = bitcast %struct.large* %ls to i8* %1 = bitcast %struct.large* %ls to i8*
%a = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 0 %a = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 0
Show All 10 Lines
; Check 2x*xlen values are aligned appropriately when passed on the stack ; Check 2x*xlen values are aligned appropriately when passed on the stack
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i64 @callee_aligned_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i128 %f, i64 %g, i64 %h, i128 %i, i64 %j, [2 x i64] %k) nounwind { define i64 @callee_aligned_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i128 %f, i64 %g, i64 %h, i128 %i, i64 %j, [2 x i64] %k) nounwind {
; The i128 should be 16-byte aligned on the stack, but the two-element array ; The i128 should be 16-byte aligned on the stack, but the two-element array
; should only be 8-byte aligned ; should only be 8-byte aligned
; RV64I-LABEL: callee_aligned_stack: ; RV64I-LABEL: callee_aligned_stack:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a5, a7 ; RV64I-NEXT: ld a0, 40(sp)
; RV64I-NEXT: ld a1, 0(sp) ; RV64I-NEXT: ld a1, 0(sp)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ld a2, 16(sp)
; RV64I-NEXT: ld a1, 16(sp) ; RV64I-NEXT: ld a3, 32(sp)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a4, a5, a7
; RV64I-NEXT: ld a1, 32(sp) ; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: ld a1, 40(sp) ; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%f_trunc = trunc i128 %f to i64 %f_trunc = trunc i128 %f to i64
%1 = add i64 %f_trunc, %g %1 = add i64 %f_trunc, %g
%2 = add i64 %1, %h %2 = add i64 %1, %h
%3 = trunc i128 %i to i64 %3 = trunc i128 %i to i64
%4 = add i64 %2, %3 %4 = add i64 %2, %3
%5 = add i64 %4, %j %5 = add i64 %4, %j
%6 = extractvalue [2 x i64] %k, 0 %6 = extractvalue [2 x i64] %k, 0
Show All 9 Lines
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: addi a0, zero, 12 ; RV64I-NEXT: addi a0, zero, 12
; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: addi a0, zero, 11 ; RV64I-NEXT: addi a0, zero, 11
; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: addi a0, zero, 10 ; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 32(sp) ; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 9 ; RV64I-NEXT: addi a0, zero, 9
; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: addi a0, zero, 8 ; RV64I-NEXT: addi a6, zero, 8
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6 ; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: mv a6, zero
; RV64I-NEXT: addi a7, zero, 7 ; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd a6, 0(sp)
; RV64I-NEXT: mv a6, zero
; RV64I-NEXT: call callee_aligned_stack ; RV64I-NEXT: call callee_aligned_stack
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_aligned_stack(i64 1, i64 2, i64 3, i64 4, i64 5, %1 = call i64 @callee_aligned_stack(i64 1, i64 2, i64 3, i64 4, i64 5,
i128 6, i64 7, i64 8, i128 9, i64 10, [2 x i64] [i64 11, i64 12]) i128 6, i64 7, i64 8, i128 9, i64 10, [2 x i64] [i64 11, i64 12])
ret void ret void
} }
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret void ret void
} }
; Check return of >2x xlen structs ; Check return of >2x xlen structs
define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind { define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
; RV64I-LABEL: callee_large_struct_ret: ; RV64I-LABEL: callee_large_struct_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 4
; RV64I-NEXT: sw a1, 24(a0)
; RV64I-NEXT: addi a1, zero, 3
; RV64I-NEXT: sw a1, 16(a0)
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sw a1, 8(a0)
; RV64I-NEXT: sw zero, 28(a0)
; RV64I-NEXT: sw zero, 20(a0)
; RV64I-NEXT: sw zero, 12(a0)
; RV64I-NEXT: sw zero, 4(a0) ; RV64I-NEXT: sw zero, 4(a0)
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: sw a1, 0(a0) ; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: sw zero, 12(a0)
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sw a1, 8(a0)
; RV64I-NEXT: sw zero, 20(a0)
; RV64I-NEXT: addi a1, zero, 3
; RV64I-NEXT: sw a1, 16(a0)
; RV64I-NEXT: sw zero, 28(a0)
; RV64I-NEXT: addi a1, zero, 4
; RV64I-NEXT: sw a1, 24(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 0 %a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 0
store i64 1, i64* %a, align 4 store i64 1, i64* %a, align 4
%b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 1 %b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 1
store i64 2, i64* %b, align 4 store i64 2, i64* %b, align 4
%c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 2 %c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 2
store i64 3, i64* %c, align 4 store i64 3, i64* %c, align 4
%d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 3 %d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 3
store i64 4, i64* %d, align 4 store i64 4, i64* %d, align 4
ret void ret void
} }
define i64 @caller_large_struct_ret() nounwind { define i64 @caller_large_struct_ret() nounwind {
; RV64I-LABEL: caller_large_struct_ret: ; RV64I-LABEL: caller_large_struct_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: addi a0, sp, 8 ; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct_ret ; RV64I-NEXT: call callee_large_struct_ret
; RV64I-NEXT: ld a0, 32(sp) ; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 8(sp) ; RV64I-NEXT: ld a1, 32(sp)
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca %struct.large %1 = alloca %struct.large
call void @callee_large_struct_ret(%struct.large* sret %1) call void @callee_large_struct_ret(%struct.large* sret %1)
%2 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 0 %2 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 0
%3 = load i64, i64* %2 %3 = load i64, i64* %2
%4 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 3 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 3
%5 = load i64, i64* %4 %5 = load i64, i64* %4
%6 = add i64 %3, %5 %6 = add i64 %3, %5
ret i64 %6 ret i64 %6
} }

llvm/test/CodeGen/RISCV/calling-conv-lp64.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines; RV64I-WITHFP-NEXT: ret
ret i64 %3 ret i64 %3
} }
define i64 @caller_float_on_stack() nounwind { define i64 @caller_float_on_stack() nounwind {
; RV64I-FPELIM-LABEL: caller_float_on_stack: ; RV64I-FPELIM-LABEL: caller_float_on_stack:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16 ; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) ; RV64I-FPELIM-NEXT: sd ra, 8(sp)
; RV64I-FPELIM-NEXT: lui a0, 264704 ; RV64I-FPELIM-NEXT: lui a1, 264704
; RV64I-FPELIM-NEXT: sd a0, 0(sp)
; RV64I-FPELIM-NEXT: addi a0, zero, 1 ; RV64I-FPELIM-NEXT: addi a0, zero, 1
; RV64I-FPELIM-NEXT: mv a1, zero
; RV64I-FPELIM-NEXT: addi a2, zero, 2 ; RV64I-FPELIM-NEXT: addi a2, zero, 2
; RV64I-FPELIM-NEXT: mv a3, zero
; RV64I-FPELIM-NEXT: addi a4, zero, 3 ; RV64I-FPELIM-NEXT: addi a4, zero, 3
; RV64I-FPELIM-NEXT: mv a5, zero
; RV64I-FPELIM-NEXT: addi a6, zero, 4 ; RV64I-FPELIM-NEXT: addi a6, zero, 4
; RV64I-FPELIM-NEXT: sd a1, 0(sp)
; RV64I-FPELIM-NEXT: mv a1, zero
; RV64I-FPELIM-NEXT: mv a3, zero
; RV64I-FPELIM-NEXT: mv a5, zero
; RV64I-FPELIM-NEXT: mv a7, zero ; RV64I-FPELIM-NEXT: mv a7, zero
; RV64I-FPELIM-NEXT: call callee_float_on_stack ; RV64I-FPELIM-NEXT: call callee_float_on_stack
; RV64I-FPELIM-NEXT: ld ra, 8(sp) ; RV64I-FPELIM-NEXT: ld ra, 8(sp)
; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: caller_float_on_stack: ; RV64I-WITHFP-LABEL: caller_float_on_stack:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -32 ; RV64I-WITHFP-NEXT: addi sp, sp, -32
; RV64I-WITHFP-NEXT: sd ra, 24(sp) ; RV64I-WITHFP-NEXT: sd ra, 24(sp)
; RV64I-WITHFP-NEXT: sd s0, 16(sp) ; RV64I-WITHFP-NEXT: sd s0, 16(sp)
; RV64I-WITHFP-NEXT: addi s0, sp, 32 ; RV64I-WITHFP-NEXT: addi s0, sp, 32
; RV64I-WITHFP-NEXT: lui a0, 264704 ; RV64I-WITHFP-NEXT: lui a1, 264704
; RV64I-WITHFP-NEXT: sd a0, 0(sp)
; RV64I-WITHFP-NEXT: addi a0, zero, 1 ; RV64I-WITHFP-NEXT: addi a0, zero, 1
; RV64I-WITHFP-NEXT: mv a1, zero
; RV64I-WITHFP-NEXT: addi a2, zero, 2 ; RV64I-WITHFP-NEXT: addi a2, zero, 2
; RV64I-WITHFP-NEXT: mv a3, zero
; RV64I-WITHFP-NEXT: addi a4, zero, 3 ; RV64I-WITHFP-NEXT: addi a4, zero, 3
; RV64I-WITHFP-NEXT: mv a5, zero
; RV64I-WITHFP-NEXT: addi a6, zero, 4 ; RV64I-WITHFP-NEXT: addi a6, zero, 4
; RV64I-WITHFP-NEXT: sd a1, 0(sp)
; RV64I-WITHFP-NEXT: mv a1, zero
; RV64I-WITHFP-NEXT: mv a3, zero
; RV64I-WITHFP-NEXT: mv a5, zero
; RV64I-WITHFP-NEXT: mv a7, zero ; RV64I-WITHFP-NEXT: mv a7, zero
; RV64I-WITHFP-NEXT: call callee_float_on_stack ; RV64I-WITHFP-NEXT: call callee_float_on_stack
; RV64I-WITHFP-NEXT: ld s0, 16(sp) ; RV64I-WITHFP-NEXT: ld s0, 16(sp)
; RV64I-WITHFP-NEXT: ld ra, 24(sp) ; RV64I-WITHFP-NEXT: ld ra, 24(sp)
; RV64I-WITHFP-NEXT: addi sp, sp, 32 ; RV64I-WITHFP-NEXT: addi sp, sp, 32
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
%1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0) %1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
ret i64 %1 ret i64 %1
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

Show All 27 Lines
} }
define float @caller_onstack_f32_noop(float %a) nounwind { define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-LABEL: caller_onstack_f32_noop: ; RV32IF-LABEL: caller_onstack_f32_noop:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw a0, 4(sp) ; RV32IF-NEXT: sw a0, 4(sp)
; RV32IF-NEXT: lui a0, 264704 ; RV32IF-NEXT: lui a1, 264704
; RV32IF-NEXT: sw a0, 0(sp)
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: addi a2, zero, 2 ; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: addi a4, zero, 3 ; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: addi a6, zero, 4 ; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: sw a1, 0(sp)
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero ; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop ; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float 5.0, float %a) %1 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float 5.0, float %a)
ret float %1 ret float %1
} }
define float @caller_onstack_f32_fadd(float %a, float %b) nounwind { define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF-LABEL: caller_onstack_f32_fadd: ; RV32IF-LABEL: caller_onstack_f32_fadd:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fsub.s ft2, ft1, ft0 ; RV32IF-NEXT: fadd.s ft2, ft1, ft0
; RV32IF-NEXT: fsw ft2, 4(sp) ; RV32IF-NEXT: fsub.s ft0, ft0, ft1
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: fsw ft0, 0(sp)
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: addi a2, zero, 2 ; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: addi a4, zero, 3 ; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: addi a6, zero, 4 ; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: fsw ft2, 0(sp)
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero ; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop ; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = fsub float %b, %a %2 = fsub float %b, %a
%3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2) %3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2)
ret float %3 ret float %3
} }

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind { define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-SMALL-LABEL: lower_blockaddress_displ: ; RV32I-SMALL-LABEL: lower_blockaddress_displ:
; RV32I-SMALL: # %bb.0: # %entry ; RV32I-SMALL: # %bb.0: # %entry
; RV32I-SMALL-NEXT: addi sp, sp, -16 ; RV32I-SMALL-NEXT: addi sp, sp, -16
; RV32I-SMALL-NEXT: sw ra, 12(sp) ; RV32I-SMALL-NEXT: sw ra, 12(sp)
; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0) ; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0) ; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)
; RV32I-SMALL-NEXT: addi a2, zero, 101
; RV32I-SMALL-NEXT: sw a1, 8(sp) ; RV32I-SMALL-NEXT: sw a1, 8(sp)
; RV32I-SMALL-NEXT: addi a1, zero, 101 ; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3
; RV32I-SMALL-NEXT: blt a0, a1, .LBB2_3
; RV32I-SMALL-NEXT: # %bb.1: # %if.then ; RV32I-SMALL-NEXT: # %bb.1: # %if.then
; RV32I-SMALL-NEXT: lw a0, 8(sp) ; RV32I-SMALL-NEXT: lw a0, 8(sp)
; RV32I-SMALL-NEXT: jr a0 ; RV32I-SMALL-NEXT: jr a0
; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken ; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken
; RV32I-SMALL-NEXT: .LBB2_2: # %return ; RV32I-SMALL-NEXT: .LBB2_2: # %return
; RV32I-SMALL-NEXT: addi a0, zero, 4 ; RV32I-SMALL-NEXT: addi a0, zero, 4
; RV32I-SMALL-NEXT: j .LBB2_4 ; RV32I-SMALL-NEXT: j .LBB2_4
; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone ; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone
; RV32I-SMALL-NEXT: addi a0, zero, 3 ; RV32I-SMALL-NEXT: addi a0, zero, 3
; RV32I-SMALL-NEXT: .LBB2_4: # %.split ; RV32I-SMALL-NEXT: .LBB2_4: # %.split
; RV32I-SMALL-NEXT: lw ra, 12(sp) ; RV32I-SMALL-NEXT: lw ra, 12(sp)
; RV32I-SMALL-NEXT: addi sp, sp, 16 ; RV32I-SMALL-NEXT: addi sp, sp, 16
; RV32I-SMALL-NEXT: ret ; RV32I-SMALL-NEXT: ret
; ;
; RV32I-MEDIUM-LABEL: lower_blockaddress_displ: ; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:
; RV32I-MEDIUM: # %bb.0: # %entry ; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi sp, sp, -16 ; RV32I-MEDIUM-NEXT: addi sp, sp, -16
; RV32I-MEDIUM-NEXT: sw ra, 12(sp) ; RV32I-MEDIUM-NEXT: sw ra, 12(sp)
; RV32I-MEDIUM-NEXT: .LBB2_5: # %entry ; RV32I-MEDIUM-NEXT: .LBB2_5: # %entry
; RV32I-MEDIUM-NEXT: # Label of block must be emitted ; RV32I-MEDIUM-NEXT: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0) ; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_5) ; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_5)
; RV32I-MEDIUM-NEXT: addi a2, zero, 101
; RV32I-MEDIUM-NEXT: sw a1, 8(sp) ; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
; RV32I-MEDIUM-NEXT: addi a1, zero, 101 ; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3
; RV32I-MEDIUM-NEXT: blt a0, a1, .LBB2_3
; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then ; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then
; RV32I-MEDIUM-NEXT: lw a0, 8(sp) ; RV32I-MEDIUM-NEXT: lw a0, 8(sp)
; RV32I-MEDIUM-NEXT: jr a0 ; RV32I-MEDIUM-NEXT: jr a0
; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken ; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken
; RV32I-MEDIUM-NEXT: .LBB2_2: # %return ; RV32I-MEDIUM-NEXT: .LBB2_2: # %return
; RV32I-MEDIUM-NEXT: addi a0, zero, 4 ; RV32I-MEDIUM-NEXT: addi a0, zero, 4
; RV32I-MEDIUM-NEXT: j .LBB2_4 ; RV32I-MEDIUM-NEXT: j .LBB2_4
; RV32I-MEDIUM-NEXT: .LBB2_3: # %return.clone ; RV32I-MEDIUM-NEXT: .LBB2_3: # %return.clone
Show All 26 Linesindirectgoto:
indirectbr i8* %addr, [ label %test_block ] indirectbr i8* %addr, [ label %test_block ]
} }
; Check lowering of constantpools ; Check lowering of constantpools
define float @lower_constantpool(float %a) nounwind { define float @lower_constantpool(float %a) nounwind {
; RV32I-SMALL-LABEL: lower_constantpool: ; RV32I-SMALL-LABEL: lower_constantpool:
; RV32I-SMALL: # %bb.0: ; RV32I-SMALL: # %bb.0:
; RV32I-SMALL-NEXT: fmv.w.x ft0, a0 ; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0)
; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI3_0) ; RV32I-SMALL-NEXT: addi a1, a1, %lo(.LCPI3_0)
; RV32I-SMALL-NEXT: addi a0, a0, %lo(.LCPI3_0) ; RV32I-SMALL-NEXT: flw ft0, 0(a1)
; RV32I-SMALL-NEXT: flw ft1, 0(a0) ; RV32I-SMALL-NEXT: fmv.w.x ft1, a0
; RV32I-SMALL-NEXT: fadd.s ft0, ft0, ft1 ; RV32I-SMALL-NEXT: fadd.s ft0, ft1, ft0
; RV32I-SMALL-NEXT: fmv.x.w a0, ft0 ; RV32I-SMALL-NEXT: fmv.x.w a0, ft0
; RV32I-SMALL-NEXT: ret ; RV32I-SMALL-NEXT: ret
; ;
; RV32I-MEDIUM-LABEL: lower_constantpool: ; RV32I-MEDIUM-LABEL: lower_constantpool:
; RV32I-MEDIUM: # %bb.0: ; RV32I-MEDIUM: # %bb.0:
; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted ; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0) ; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1) ; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1)
; RV32I-MEDIUM-NEXT: flw ft0, 0(a1) ; RV32I-MEDIUM-NEXT: flw ft0, 0(a1)
; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0 ; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0
; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0 ; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0
; RV32I-MEDIUM-NEXT: fmv.x.w a0, ft0 ; RV32I-MEDIUM-NEXT: fmv.x.w a0, ft0
; RV32I-MEDIUM-NEXT: ret ; RV32I-MEDIUM-NEXT: ret
%1 = fadd float %a, 1.0 %1 = fadd float %a, 1.0
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/compress.ll

Show All 13 Lines
; Note: TODOs in this file are only appropriate if they highlight a case where ; Note: TODOs in this file are only appropriate if they highlight a case where
; a generated instruction that can be compressed by an existing pattern isn't. ; a generated instruction that can be compressed by an existing pattern isn't.
; It may be useful to have tests that indicate where better compression would be ; It may be useful to have tests that indicate where better compression would be
; possible if alternative codegen choices were made, but they belong in a ; possible if alternative codegen choices were made, but they belong in a
; different test file. ; different test file.
define i32 @simple_arith(i32 %a, i32 %b) nounwind { define i32 @simple_arith(i32 %a, i32 %b) nounwind {
; RV32IC-LABEL: simple_arith: ; RV32IC-LABEL: simple_arith:
; RV32IC: c.srai a1, 9 ; RV32IC: addi a2, a0, 1
; RV32IC-NEXT: addi a2, a0, 1
; RV32IC-NEXT: c.andi a2, 11 ; RV32IC-NEXT: c.andi a2, 11
; RV32IC-NEXT: c.slli a2, 7 ; RV32IC-NEXT: c.slli a2, 7
; RV32IC-NEXT: c.srai a1, 9
; RV32IC-NEXT: c.add a1, a2 ; RV32IC-NEXT: c.add a1, a2
; RV32IC-NEXT: sub a0, a1, a0 ; RV32IC-NEXT: sub a0, a1, a0
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
%1 = add i32 %a, 1 %1 = add i32 %a, 1
%2 = and i32 %1, 11 %2 = and i32 %1, 11
%3 = shl i32 %2, 7 %3 = shl i32 %2, 7
%4 = ashr i32 %b, 9 %4 = ashr i32 %b, 9
%5 = add i32 %3, %4 %5 = add i32 %3, %4
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/div.ll

Show First 20 Lines • Show All 451 Lines • ▼ Show 20 Lines
; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: sdiv64_sext_operands: ; RV64IM-LABEL: sdiv64_sext_operands:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: div a0, a0, a1 ; RV64IM-NEXT: div a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = sext i32 %a to i64 %1 = sext i32 %a to i64
%2 = sext i32 %b to i64 %2 = sext i32 %b to i64
%3 = sdiv i64 %1, %2 %3 = sdiv i64 %1, %2
ret i64 %3 ret i64 %3
} }

llvm/test/CodeGen/RISCV/double-arith.ll

Show First 20 Lines • Show All 467 Lines • ▼ Show 20 Lines
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmsub_d: ; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2 ; RV64IFD-NEXT: lui a3, %hi(.LCPI15_0)
; RV64IFD-NEXT: lui a2, %hi(.LCPI15_0) ; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI15_0)
; RV64IFD-NEXT: addi a2, a2, %lo(.LCPI15_0) ; RV64IFD-NEXT: fld ft0, 0(a3)
; RV64IFD-NEXT: fld ft1, 0(a2)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0 ; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmv.d.x ft3, a2
; RV64IFD-NEXT: fadd.d ft0, ft3, ft0
; RV64IFD-NEXT: fmsub.d ft0, ft2, ft1, ft0 ; RV64IFD-NEXT: fmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%c_ = fadd double 0.0, %c ; avoid negation using xor %c_ = fadd double 0.0, %c ; avoid negation using xor
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %b, double %negc) %1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
ret double %1 ret double %1
} }
define double @fnmadd_d(double %a, double %b, double %c) nounwind { define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d: ; RV32IFD-LABEL: fnmadd_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a4, 8(sp) ; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp) ; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp) ; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI16_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI16_0)
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI16_0) ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI16_0)
; RV32IFD-NEXT: fld ft3, 0(a0) ; RV32IFD-NEXT: fld ft3, 0(a0)
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fadd.d ft1, ft1, ft3 ; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
; RV32IFD-NEXT: fnmadd.d ft0, ft1, ft0, ft2 ; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d: ; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2 ; RV64IFD-NEXT: lui a3, %hi(.LCPI16_0)
; RV64IFD-NEXT: lui a2, %hi(.LCPI16_0) ; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI16_0)
; RV64IFD-NEXT: addi a2, a2, %lo(.LCPI16_0) ; RV64IFD-NEXT: fld ft0, 0(a3)
; RV64IFD-NEXT: fld ft1, 0(a2) ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fmv.d.x ft2, a2
; RV64IFD-NEXT: fmv.d.x ft2, a0 ; RV64IFD-NEXT: fmv.d.x ft3, a0
; RV64IFD-NEXT: fadd.d ft1, ft2, ft1 ; RV64IFD-NEXT: fadd.d ft3, ft3, ft0
; RV64IFD-NEXT: fmv.d.x ft2, a1 ; RV64IFD-NEXT: fadd.d ft0, ft2, ft0
; RV64IFD-NEXT: fnmadd.d ft0, ft1, ft2, ft0 ; RV64IFD-NEXT: fnmadd.d ft0, ft3, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a %a_ = fadd double 0.0, %a
%c_ = fadd double 0.0, %c %c_ = fadd double 0.0, %c
%nega = fsub double -0.0, %a_ %nega = fsub double -0.0, %a_
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %nega, double %b, double %negc) %1 = call double @llvm.fma.f64(double %nega, double %b, double %negc)
ret double %1 ret double %1
Show All 20 Lines
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d: ; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: lui a3, %hi(.LCPI17_0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI17_0) ; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI17_0)
; RV64IFD-NEXT: addi a0, a0, %lo(.LCPI17_0) ; RV64IFD-NEXT: fld ft0, 0(a3)
; RV64IFD-NEXT: fld ft1, 0(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft1, a2 ; RV64IFD-NEXT: fmv.d.x ft1, a2
; RV64IFD-NEXT: fmv.d.x ft2, a1 ; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fmv.d.x ft3, a0
; RV64IFD-NEXT: fadd.d ft0, ft3, ft0
; RV64IFD-NEXT: fnmsub.d ft0, ft0, ft2, ft1 ; RV64IFD-NEXT: fnmsub.d ft0, ft0, ft2, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a %a_ = fadd double 0.0, %a
%nega = fsub double -0.0, %a_ %nega = fsub double -0.0, %a_
%1 = call double @llvm.fma.f64(double %nega, double %b, double %c) %1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64I-LABEL: fcopysign_fneg: ; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: addi a2, zero, -1 ; RV64I-NEXT: addi a2, zero, -1
; RV64I-NEXT: slli a2, a2, 63 ; RV64I-NEXT: slli a2, a2, 63
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: addi a2, a2, -1 ; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: fcopysign_fneg: ; RV64IFD-LABEL: fcopysign_fneg:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
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llvm/test/CodeGen/RISCV/double-br-fcmp.ll

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; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB8_2: # %if.then ; RV32IFD-NEXT: .LBB8_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort
; ;
; RV64IFD-LABEL: br_fcmp_ord: ; RV64IFD-LABEL: br_fcmp_ord:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: and a0, a0, a1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB8_2 ; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB8_2: # %if.then ; RV64IFD-NEXT: .LBB8_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort
%1 = fcmp ord double %a, %b %1 = fcmp ord double %a, %b
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; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB15_2: # %if.then ; RV32IFD-NEXT: .LBB15_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort
; ;
; RV64IFD-LABEL: br_fcmp_uno: ; RV64IFD-LABEL: br_fcmp_uno:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: and a0, a0, a1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: bnez a0, .LBB15_2 ; RV64IFD-NEXT: bnez a0, .LBB15_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB15_2: # %if.then ; RV64IFD-NEXT: .LBB15_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort
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llvm/test/CodeGen/RISCV/double-calling-conv.ll

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} }
define double @caller_double_split_reg_stack() nounwind { define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-LABEL: caller_double_split_reg_stack: ; RV32IFD-LABEL: caller_double_split_reg_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: lui a0, 262510 ; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a0, a0, 327 ; RV32IFD-NEXT: addi a2, a0, 327
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: lui a0, 262446 ; RV32IFD-NEXT: lui a0, 262446
; RV32IFD-NEXT: addi a6, a0, 327 ; RV32IFD-NEXT: addi a6, a0, 327
; RV32IFD-NEXT: lui a0, 713032 ; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a5, a0, -1311 ; RV32IFD-NEXT: addi a5, a0, -1311
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a1, zero, 2 ; RV32IFD-NEXT: addi a1, zero, 2
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: addi a3, zero, 3 ; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: mv a4, zero ; RV32IFD-NEXT: mv a4, zero
; RV32IFD-NEXT: mv a7, a5 ; RV32IFD-NEXT: mv a7, a5
; RV32IFD-NEXT: call callee_double_split_reg_stack ; RV32IFD-NEXT: call callee_double_split_reg_stack
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72) %1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
ret double %1 ret double %1
Show All 18 Lines
define double @caller_double_stack() nounwind { define double @caller_double_stack() nounwind {
; RV32IFD-LABEL: caller_double_stack: ; RV32IFD-LABEL: caller_double_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: lui a0, 262510 ; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a0, a0, 327 ; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 4(sp) ; RV32IFD-NEXT: sw a0, 4(sp)
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a1, a0, -1311
; RV32IFD-NEXT: sw a1, 0(sp)
; RV32IFD-NEXT: lui a0, 262574 ; RV32IFD-NEXT: lui a0, 262574
; RV32IFD-NEXT: addi a0, a0, 327 ; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 12(sp) ; RV32IFD-NEXT: sw a0, 12(sp)
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a0, a0, -1311
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: addi a2, zero, 2 ; RV32IFD-NEXT: addi a2, zero, 2
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: addi a4, zero, 3 ; RV32IFD-NEXT: addi a4, zero, 3
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: addi a6, zero, 4 ; RV32IFD-NEXT: addi a6, zero, 4
; RV32IFD-NEXT: sw a1, 8(sp)
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: mv a7, zero ; RV32IFD-NEXT: mv a7, zero
; RV32IFD-NEXT: call callee_double_stack ; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72) %1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-convert.ll

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; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmv_d_x: ; RV64IFD-LABEL: fmv_d_x:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = bitcast i64 %a to double %1 = bitcast i64 %a to double
%2 = bitcast i64 %b to double %2 = bitcast i64 %b to double
%3 = fadd double %1, %2 %3 = fadd double %1, %2
ret double %3 ret double %3
} }

llvm/test/CodeGen/RISCV/double-fcmp.ll

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; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcmp_ord: ; RV64IFD-LABEL: fcmp_ord:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: and a0, a0, a1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ord double %a, %b %1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ueq(double %a, double %b) nounwind { define i32 @fcmp_ueq(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_ueq: ; RV32IFD-LABEL: fcmp_ueq:
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; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: seqz a0, a0
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcmp_uno: ; RV64IFD-LABEL: fcmp_uno:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: and a0, a0, a1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, %b %1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_true(double %a, double %b) nounwind { define i32 @fcmp_true(double %a, double %b) nounwind {
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llvm/test/CodeGen/RISCV/double-imm.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: double_imm_op: ; RV64IFD-LABEL: double_imm_op:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: lui a1, %hi(.LCPI1_0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IFD-NEXT: addi a1, a1, %lo(.LCPI1_0)
; RV64IFD-NEXT: addi a0, a0, %lo(.LCPI1_0) ; RV64IFD-NEXT: fld ft0, 0(a1)
; RV64IFD-NEXT: fld ft1, 0(a0) ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fadd double %a, 1.0 %1 = fadd double %a, 1.0
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-intrinsics.ll

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; The sin+cos combination results in an FSINCOS SelectionDAG node. ; The sin+cos combination results in an FSINCOS SelectionDAG node.
define double @sincos_f64(double %a) nounwind { define double @sincos_f64(double %a) nounwind {
; RV32IFD-LABEL: sincos_f64: ; RV32IFD-LABEL: sincos_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw s0, 24(sp) ; RV32IFD-NEXT: sw s0, 24(sp)
; RV32IFD-NEXT: sw s1, 20(sp) ; RV32IFD-NEXT: sw s1, 20(sp)
; RV32IFD-NEXT: sw s2, 16(sp)
; RV32IFD-NEXT: sw s3, 12(sp)
; RV32IFD-NEXT: mv s0, a1 ; RV32IFD-NEXT: mv s0, a1
; RV32IFD-NEXT: mv s1, a0 ; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: call sin ; RV32IFD-NEXT: call sin
; RV32IFD-NEXT: mv s2, a0 ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: mv s3, a1 ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: mv a0, s1 ; RV32IFD-NEXT: mv a0, s1
; RV32IFD-NEXT: mv a1, s0 ; RV32IFD-NEXT: mv a1, s0
; RV32IFD-NEXT: call cos ; RV32IFD-NEXT: call cos
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw s2, 0(sp)
; RV32IFD-NEXT: sw s3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 0(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 4(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw s3, 12(sp)
; RV32IFD-NEXT: lw s2, 16(sp)
; RV32IFD-NEXT: lw s1, 20(sp) ; RV32IFD-NEXT: lw s1, 20(sp)
; RV32IFD-NEXT: lw s0, 24(sp) ; RV32IFD-NEXT: lw s0, 24(sp)
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: sincos_f64: ; RV64IFD-LABEL: sincos_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32 ; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp) ; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd s0, 16(sp) ; RV64IFD-NEXT: sd s0, 16(sp)
; RV64IFD-NEXT: sd s1, 8(sp)
; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: call sin ; RV64IFD-NEXT: call sin
; RV64IFD-NEXT: mv s1, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp)
; RV64IFD-NEXT: mv a0, s0 ; RV64IFD-NEXT: mv a0, s0
; RV64IFD-NEXT: call cos ; RV64IFD-NEXT: call cos
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, s1 ; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s1, 8(sp)
; RV64IFD-NEXT: ld s0, 16(sp) ; RV64IFD-NEXT: ld s0, 16(sp)
; RV64IFD-NEXT: ld ra, 24(sp) ; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32 ; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.sin.f64(double %a) %1 = call double @llvm.sin.f64(double %a)
%2 = call double @llvm.cos.f64(double %a) %2 = call double @llvm.cos.f64(double %a)
%3 = fadd double %1, %2 %3 = fadd double %1, %2
ret double %3 ret double %3
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declare double @llvm.fmuladd.f64(double, double, double) declare double @llvm.fmuladd.f64(double, double, double)
define double @fmuladd_f64(double %a, double %b, double %c) nounwind { define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd ; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd
; RV32IFD-LABEL: fmuladd_f64: ; RV32IFD-LABEL: fmuladd_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fmul.d ft0, ft1, ft0 ; RV32IFD-NEXT: fmul.d ft1, ft2, ft1
; RV32IFD-NEXT: sw a4, 8(sp) ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmuladd_f64: ; RV64IFD-LABEL: fmuladd_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmul.d ft0, ft1, ft0 ; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmv.d.x ft1, a2 ; RV64IFD-NEXT: fmul.d ft1, ft2, ft1
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c) %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
ret double %1 ret double %1
} }
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
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llvm/test/CodeGen/RISCV/double-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @fld(double *%a) nounwind { define double @fld(double *%a) nounwind {
; RV32IFD-LABEL: fld: ; RV32IFD-LABEL: fld:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fld ft0, 24(a0) ; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: fld ft1, 0(a0) ; RV32IFD-NEXT: fld ft1, 24(a0)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld: ; RV64IFD-LABEL: fld:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fld ft0, 24(a0) ; RV64IFD-NEXT: fld ft0, 0(a0)
; RV64IFD-NEXT: fld ft1, 0(a0) ; RV64IFD-NEXT: fld ft1, 24(a0)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = load double, double* %a %1 = load double, double* %a
%2 = getelementptr double, double* %a, i32 3 %2 = getelementptr double, double* %a, i32 3
%3 = load double, double* %2 %3 = load double, double* %2
; Use both loaded values in an FP op to ensure an fld is used, even for the ; Use both loaded values in an FP op to ensure an fld is used, even for the
; soft float ABI ; soft float ABI
%4 = fadd double %1, %3 %4 = fadd double %1, %3
ret double %4 ret double %4
} }
define void @fsd(double *%a, double %b, double %c) nounwind { define void @fsd(double *%a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fsd: ; RV32IFD-LABEL: fsd:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a3, 8(sp) ; RV32IFD-NEXT: sw a3, 8(sp)
; RV32IFD-NEXT: sw a4, 12(sp) ; RV32IFD-NEXT: sw a4, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a1, 8(sp) ; RV32IFD-NEXT: sw a1, 8(sp)
; RV32IFD-NEXT: sw a2, 12(sp) ; RV32IFD-NEXT: sw a2, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 64(a0)
; RV32IFD-NEXT: fsd ft0, 0(a0) ; RV32IFD-NEXT: fsd ft0, 0(a0)
; RV32IFD-NEXT: fsd ft0, 64(a0)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fsd: ; RV64IFD-LABEL: fsd:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2 ; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, 64(a0)
; RV64IFD-NEXT: fsd ft0, 0(a0) ; RV64IFD-NEXT: fsd ft0, 0(a0)
; RV64IFD-NEXT: fsd ft0, 64(a0)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; Use %b and %c in an FP op to ensure floating point registers are used, even ; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
%1 = fadd double %b, %c %1 = fadd double %b, %c
store double %1, double* %a store double %1, double* %a
%2 = getelementptr double, double* %a, i32 8 %2 = getelementptr double, double* %a, i32 8
store double %1, double* %2 store double %1, double* %2
ret void ret void
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; RV64IFD-LABEL: fld_fsd_global: ; RV64IFD-LABEL: fld_fsd_global:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: lui a0, %hi(G) ; RV64IFD-NEXT: lui a0, %hi(G)
; RV64IFD-NEXT: fld ft1, %lo(G)(a0) ; RV64IFD-NEXT: fld ft1, %lo(G)(a0)
; RV64IFD-NEXT: fsd ft0, %lo(G)(a0) ; RV64IFD-NEXT: fsd ft0, %lo(G)(a0)
; RV64IFD-NEXT: addi a0, a0, %lo(G) ; RV64IFD-NEXT: addi a1, a0, %lo(G)
; RV64IFD-NEXT: fld ft1, 72(a0) ; RV64IFD-NEXT: fld ft1, 72(a1)
; RV64IFD-NEXT: fsd ft0, 72(a0)
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 72(a1)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even ; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
%1 = fadd double %a, %b %1 = fadd double %a, %b
%2 = load volatile double, double* @G %2 = load volatile double, double* @G
store double %1, double* @G store double %1, double* @G
%3 = getelementptr double, double* @G, i32 9 %3 = getelementptr double, double* @G, i32 9
%4 = load volatile double, double* %3 %4 = load volatile double, double* %3
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; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld_fsd_constant: ; RV64IFD-LABEL: fld_fsd_constant:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: lui a1, 56
; RV64IFD-NEXT: lui a0, 56 ; RV64IFD-NEXT: addiw a1, a1, -1353
; RV64IFD-NEXT: addiw a0, a0, -1353 ; RV64IFD-NEXT: slli a1, a1, 14
; RV64IFD-NEXT: slli a0, a0, 14 ; RV64IFD-NEXT: fld ft0, -273(a1)
; RV64IFD-NEXT: fld ft1, -273(a0) ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, -273(a0)
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, -273(a1)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = inttoptr i32 3735928559 to double* %1 = inttoptr i32 3735928559 to double*
%2 = load volatile double, double* %1 %2 = load volatile double, double* %1
%3 = fadd double %a, %2 %3 = fadd double %a, %2
store double %3, double* %1 store double %3, double* %1
ret double %3 ret double %3
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define double @fld_stack(double %a) nounwind { define double @fld_stack(double %a) nounwind {
; RV32IFD-LABEL: fld_stack: ; RV32IFD-LABEL: fld_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw s0, 24(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw s1, 20(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: mv s0, a1 ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: sw s1, 0(sp)
; RV32IFD-NEXT: sw s0, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a0, 0(sp) ; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: lw a1, 4(sp) ; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: lw s1, 20(sp) ; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: lw s0, 24(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld_stack: ; RV64IFD-LABEL: fld_stack:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32 ; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp) ; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd s0, 16(sp) ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: fsd ft0, 8(sp)
; RV64IFD-NEXT: addi a0, sp, 8 ; RV64IFD-NEXT: addi a0, sp, 16
; RV64IFD-NEXT: call notdead ; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: fmv.d.x ft0, s0 ; RV64IFD-NEXT: fld ft0, 16(sp)
; RV64IFD-NEXT: fld ft1, 8(sp) ; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s0, 16(sp)
; RV64IFD-NEXT: ld ra, 24(sp) ; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32 ; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = alloca double, align 8 %1 = alloca double, align 8
%2 = bitcast double* %1 to i8* %2 = bitcast double* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load double, double* %1 %3 = load double, double* %1
%4 = fadd double %3, %a ; force load in to FPR64 %4 = fadd double %3, %a ; force load in to FPR64
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llvm/test/CodeGen/RISCV/double-previous-failure.ll

Show All 11 Lines
; This previously failed complaining of multiple vreg defs due to an ABI ; This previously failed complaining of multiple vreg defs due to an ABI
; lowering issue. ; lowering issue.
define i32 @main() nounwind { define i32 @main() nounwind {
; RV32IFD-LABEL: main: ; RV32IFD-LABEL: main:
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call test ; RV32IFD-NEXT: call test
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0) ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
; RV32IFD-NEXT: fld ft1, 0(a0) ; RV32IFD-NEXT: fld ft1, 0(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1 ; RV32IFD-NEXT: flt.d a0, ft0, ft1
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llvm/test/CodeGen/RISCV/double-select-fcmp.ll

Show First 20 Lines • Show All 292 Lines • ▼ Show 20 Lines; RV64IFD-NEXT: ret
%2 = select i1 %1, double %a, double %b %2 = select i1 %1, double %a, double %b
ret double %2 ret double %2
} }
define double @select_fcmp_ueq(double %a, double %b) nounwind { define double @select_fcmp_ueq(double %a, double %b) nounwind {
; RV32IFD-LABEL: select_fcmp_ueq: ; RV32IFD-LABEL: select_fcmp_ueq:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: and a1, a2, a1
; RV32IFD-NEXT: feq.d a1, ft0, ft1 ; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: or a0, a1, a0 ; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB8_2 ; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft0, ft1 ; RV32IFD-NEXT: fmv.d ft1, ft0
; RV32IFD-NEXT: .LBB8_2: ; RV32IFD-NEXT: .LBB8_2:
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft1, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: select_fcmp_ueq: ; RV64IFD-LABEL: select_fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a0, ft0, ft1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: feq.d a1, ft1, ft1
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: feq.d a2, ft0, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft1 ; RV64IFD-NEXT: and a1, a2, a1
; RV64IFD-NEXT: or a0, a1, a0 ; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB8_2 ; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1 ; RV64IFD-NEXT: fmv.d ft0, ft1
; RV64IFD-NEXT: .LBB8_2: ; RV64IFD-NEXT: .LBB8_2:
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
%2 = select i1 %1, double %a, double %b %2 = select i1 %1, double %a, double %b
▲ Show 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a1, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB16_2 ; RV32IFD-NEXT: mv a0, a4
; RV32IFD-NEXT: bnez a1, .LBB16_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: mv a4, a5 ; RV32IFD-NEXT: mv a0, a5
; RV32IFD-NEXT: .LBB16_2: ; RV32IFD-NEXT: .LBB16_2:
; RV32IFD-NEXT: mv a0, a4
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: i32_select_fcmp_oeq: ; RV64IFD-LABEL: i32_select_fcmp_oeq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a1, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB16_2 ; RV64IFD-NEXT: mv a0, a2
; RV64IFD-NEXT: bnez a1, .LBB16_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: mv a2, a3 ; RV64IFD-NEXT: mv a0, a3
; RV64IFD-NEXT: .LBB16_2: ; RV64IFD-NEXT: .LBB16_2:
; RV64IFD-NEXT: mv a0, a2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp oeq double %a, %b %1 = fcmp oeq double %a, %b
%2 = select i1 %1, i32 %c, i32 %d %2 = select i1 %1, i32 %c, i32 %d
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll

Show All 31 Lines
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: func: ; RV64IFD-LABEL: func:
; RV64IFD: # %bb.0: # %entry ; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: slli a2, a1, 32
; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: slli a0, a1, 32 ; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: srli a0, a0, 32
; RV64IFD-NEXT: beqz a0, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1 ; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp) ; RV64IFD-NEXT: fsd ft0, 0(sp)
; RV64IFD-NEXT: call func ; RV64IFD-NEXT: call func
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fld ft1, 0(sp) ; RV64IFD-NEXT: fld ft1, 0(sp)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
Show All 18 Lines

llvm/test/CodeGen/RISCV/float-arith.ll

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c) %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1 ret float %1
} }
define float @fmsub_s(float %a, float %b, float %c) nounwind { define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s: ; RV32IF-LABEL: fmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2 ; RV32IF-NEXT: lui a3, %hi(.LCPI15_0)
; RV32IF-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IF-NEXT: addi a3, a3, %lo(.LCPI15_0)
; RV32IF-NEXT: addi a2, a2, %lo(.LCPI15_0) ; RV32IF-NEXT: flw ft0, 0(a3)
; RV32IF-NEXT: flw ft1, 0(a2)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0 ; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmv.w.x ft3, a2
; RV32IF-NEXT: fadd.s ft0, ft3, ft0
; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0 ; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmsub_s: ; RV64IF-LABEL: fmsub_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2 ; RV64IF-NEXT: lui a3, %hi(.LCPI15_0)
; RV64IF-NEXT: lui a2, %hi(.LCPI15_0) ; RV64IF-NEXT: addi a3, a3, %lo(.LCPI15_0)
; RV64IF-NEXT: addi a2, a2, %lo(.LCPI15_0) ; RV64IF-NEXT: flw ft0, 0(a3)
; RV64IF-NEXT: flw ft1, 0(a2)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0 ; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmv.w.x ft3, a2
; RV64IF-NEXT: fadd.s ft0, ft3, ft0
; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0 ; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor %c_ = fadd float 0.0, %c ; avoid negation using xor
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %b, float %negc) %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
ret float %1 ret float %1
} }
define float @fnmadd_s(float %a, float %b, float %c) nounwind { define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s: ; RV32IF-LABEL: fnmadd_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2 ; RV32IF-NEXT: lui a3, %hi(.LCPI16_0)
; RV32IF-NEXT: lui a2, %hi(.LCPI16_0) ; RV32IF-NEXT: addi a3, a3, %lo(.LCPI16_0)
; RV32IF-NEXT: addi a2, a2, %lo(.LCPI16_0) ; RV32IF-NEXT: flw ft0, 0(a3)
; RV32IF-NEXT: flw ft1, 0(a2) ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fmv.w.x ft2, a2
; RV32IF-NEXT: fmv.w.x ft2, a0 ; RV32IF-NEXT: fmv.w.x ft3, a0
; RV32IF-NEXT: fadd.s ft1, ft2, ft1 ; RV32IF-NEXT: fadd.s ft3, ft3, ft0
; RV32IF-NEXT: fmv.w.x ft2, a1 ; RV32IF-NEXT: fadd.s ft0, ft2, ft0
; RV32IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0 ; RV32IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s: ; RV64IF-LABEL: fnmadd_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2 ; RV64IF-NEXT: lui a3, %hi(.LCPI16_0)
; RV64IF-NEXT: lui a2, %hi(.LCPI16_0) ; RV64IF-NEXT: addi a3, a3, %lo(.LCPI16_0)
; RV64IF-NEXT: addi a2, a2, %lo(.LCPI16_0) ; RV64IF-NEXT: flw ft0, 0(a3)
; RV64IF-NEXT: flw ft1, 0(a2) ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft0, ft1 ; RV64IF-NEXT: fmv.w.x ft2, a2
; RV64IF-NEXT: fmv.w.x ft2, a0 ; RV64IF-NEXT: fmv.w.x ft3, a0
; RV64IF-NEXT: fadd.s ft1, ft2, ft1 ; RV64IF-NEXT: fadd.s ft3, ft3, ft0
; RV64IF-NEXT: fmv.w.x ft2, a1 ; RV64IF-NEXT: fadd.s ft0, ft2, ft0
; RV64IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0 ; RV64IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a %a_ = fadd float 0.0, %a
%c_ = fadd float 0.0, %c %c_ = fadd float 0.0, %c
%nega = fsub float -0.0, %a_ %nega = fsub float -0.0, %a_
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %negc) %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
ret float %1 ret float %1
} }
define float @fnmsub_s(float %a, float %b, float %c) nounwind { define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s: ; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: lui a3, %hi(.LCPI17_0)
; RV32IF-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IF-NEXT: addi a3, a3, %lo(.LCPI17_0)
; RV32IF-NEXT: addi a0, a0, %lo(.LCPI17_0) ; RV32IF-NEXT: flw ft0, 0(a3)
; RV32IF-NEXT: flw ft1, 0(a0)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.w.x ft1, a2 ; RV32IF-NEXT: fmv.w.x ft1, a2
; RV32IF-NEXT: fmv.w.x ft2, a1 ; RV32IF-NEXT: fmv.w.x ft2, a1
; RV32IF-NEXT: fmv.w.x ft3, a0
; RV32IF-NEXT: fadd.s ft0, ft3, ft0
; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1 ; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s: ; RV64IF-LABEL: fnmsub_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: lui a3, %hi(.LCPI17_0)
; RV64IF-NEXT: lui a0, %hi(.LCPI17_0) ; RV64IF-NEXT: addi a3, a3, %lo(.LCPI17_0)
; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0) ; RV64IF-NEXT: flw ft0, 0(a3)
; RV64IF-NEXT: flw ft1, 0(a0)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.w.x ft1, a2 ; RV64IF-NEXT: fmv.w.x ft1, a2
; RV64IF-NEXT: fmv.w.x ft2, a1 ; RV64IF-NEXT: fmv.w.x ft2, a1
; RV64IF-NEXT: fmv.w.x ft3, a0
; RV64IF-NEXT: fadd.s ft0, ft3, ft0
; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1 ; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a %a_ = fadd float 0.0, %a
%nega = fsub float -0.0, %a_ %nega = fsub float -0.0, %a_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c) %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

Show First 20 Lines • Show All 331 Lines • ▼ Show 20 Linesif.then:
unreachable unreachable
} }
define void @br_fcmp_ord(float %a, float %b) nounwind { define void @br_fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ord: ; RV32IF-LABEL: br_fcmp_ord:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: and a0, a0, a1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB8_2 ; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB8_2: # %if.then ; RV32IF-NEXT: .LBB8_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort
; ;
; RV64IF-LABEL: br_fcmp_ord: ; RV64IF-LABEL: br_fcmp_ord:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: and a0, a0, a1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB8_2 ; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB8_2: # %if.then ; RV64IF-NEXT: .LBB8_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort
%1 = fcmp ord float %a, %b %1 = fcmp ord float %a, %b
▲ Show 20 Lines • Show All 260 Lines • ▼ Show 20 Lines
} }
define void @br_fcmp_uno(float %a, float %b) nounwind { define void @br_fcmp_uno(float %a, float %b) nounwind {
; TODO: sltiu+bne -> beq ; TODO: sltiu+bne -> beq
; RV32IF-LABEL: br_fcmp_uno: ; RV32IF-LABEL: br_fcmp_uno:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: and a0, a0, a1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: bnez a0, .LBB15_2 ; RV32IF-NEXT: bnez a0, .LBB15_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB15_2: # %if.then ; RV32IF-NEXT: .LBB15_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort
; ;
; RV64IF-LABEL: br_fcmp_uno: ; RV64IF-LABEL: br_fcmp_uno:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: and a0, a0, a1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: bnez a0, .LBB15_2 ; RV64IF-NEXT: bnez a0, .LBB15_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB15_2: # %if.then ; RV64IF-NEXT: .LBB15_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort
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llvm/test/CodeGen/RISCV/float-convert.ll

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; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float %1 = uitofp i32 %a to float
ret float %1 ret float %1
} }
define float @fmv_w_x(i32 %a, i32 %b) nounwind { define float @fmv_w_x(i32 %a, i32 %b) nounwind {
; RV32IF-LABEL: fmv_w_x: ; RV32IF-LABEL: fmv_w_x:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmv_w_x: ; RV64IF-LABEL: fmv_w_x:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; Ensure fmv.w.x is generated even for a soft float calling convention ; Ensure fmv.w.x is generated even for a soft float calling convention
%1 = bitcast i32 %a to float %1 = bitcast i32 %a to float
%2 = bitcast i32 %b to float %2 = bitcast i32 %b to float
%3 = fadd float %1, %2 %3 = fadd float %1, %2
ret float %3 ret float %3
} }
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llvm/test/CodeGen/RISCV/float-fcmp.ll

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%1 = fcmp one float %a, %b %1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ord(float %a, float %b) nounwind { define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ord: ; RV32IF-LABEL: fcmp_ord:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: and a0, a0, a1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcmp_ord: ; RV64IF-LABEL: fcmp_ord:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: and a0, a0, a1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b %1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ueq(float %a, float %b) nounwind { define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ueq: ; RV32IF-LABEL: fcmp_ueq:
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%1 = fcmp une float %a, %b %1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_uno(float %a, float %b) nounwind { define i32 @fcmp_uno(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_uno: ; RV32IF-LABEL: fcmp_uno:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: and a0, a0, a1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcmp_uno: ; RV64IF-LABEL: fcmp_uno:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: and a0, a0, a1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp uno float %a, %b %1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_true(float %a, float %b) nounwind { define i32 @fcmp_true(float %a, float %b) nounwind {
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llvm/test/CodeGen/RISCV/float-imm.ll

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; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
ret float 3.14159274101257324218750 ret float 3.14159274101257324218750
} }
define float @float_imm_op(float %a) nounwind { define float @float_imm_op(float %a) nounwind {
; TODO: addi should be folded in to the flw ; TODO: addi should be folded in to the flw
; RV32IF-LABEL: float_imm_op: ; RV32IF-LABEL: float_imm_op:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: lui a1, %hi(.LCPI1_0)
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IF-NEXT: addi a1, a1, %lo(.LCPI1_0)
; RV32IF-NEXT: addi a0, a0, %lo(.LCPI1_0) ; RV32IF-NEXT: flw ft0, 0(a1)
; RV32IF-NEXT: flw ft1, 0(a0) ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: float_imm_op: ; RV64IF-LABEL: float_imm_op:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: lui a1, %hi(.LCPI1_0)
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IF-NEXT: addi a1, a1, %lo(.LCPI1_0)
; RV64IF-NEXT: addi a0, a0, %lo(.LCPI1_0) ; RV64IF-NEXT: flw ft0, 0(a1)
; RV64IF-NEXT: flw ft1, 0(a0) ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft0, ft1 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, 1.0 %1 = fadd float %a, 1.0
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/float-intrinsics.ll

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; The sin+cos combination results in an FSINCOS SelectionDAG node. ; The sin+cos combination results in an FSINCOS SelectionDAG node.
define float @sincos_f32(float %a) nounwind { define float @sincos_f32(float %a) nounwind {
; RV32IF-LABEL: sincos_f32: ; RV32IF-LABEL: sincos_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s0, 8(sp) ; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: sw s1, 4(sp)
; RV32IF-NEXT: mv s0, a0 ; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: call sinf ; RV32IF-NEXT: call sinf
; RV32IF-NEXT: mv s1, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: mv a0, s0 ; RV32IF-NEXT: mv a0, s0
; RV32IF-NEXT: call cosf ; RV32IF-NEXT: call cosf
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, s1 ; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s1, 4(sp)
; RV32IF-NEXT: lw s0, 8(sp) ; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: sincos_f32: ; RV64IF-LABEL: sincos_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -32 ; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp) ; RV64IF-NEXT: sd ra, 24(sp)
; RV64IF-NEXT: sd s0, 16(sp) ; RV64IF-NEXT: sd s0, 16(sp)
; RV64IF-NEXT: sd s1, 8(sp)
; RV64IF-NEXT: mv s0, a0 ; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: call sinf ; RV64IF-NEXT: call sinf
; RV64IF-NEXT: mv s1, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fsw ft0, 12(sp)
; RV64IF-NEXT: mv a0, s0 ; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call cosf ; RV64IF-NEXT: call cosf
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, s1 ; RV64IF-NEXT: flw ft1, 12(sp)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s1, 8(sp)
; RV64IF-NEXT: ld s0, 16(sp) ; RV64IF-NEXT: ld s0, 16(sp)
; RV64IF-NEXT: ld ra, 24(sp) ; RV64IF-NEXT: ld ra, 24(sp)
; RV64IF-NEXT: addi sp, sp, 32 ; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.sin.f32(float %a) %1 = call float @llvm.sin.f32(float %a)
%2 = call float @llvm.cos.f32(float %a) %2 = call float @llvm.cos.f32(float %a)
%3 = fadd float %1, %2 %3 = fadd float %1, %2
ret float %3 ret float %3
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} }
declare float @llvm.fmuladd.f32(float, float, float) declare float @llvm.fmuladd.f32(float, float, float)
define float @fmuladd_f32(float %a, float %b, float %c) nounwind { define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd ; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd
; RV32IF-LABEL: fmuladd_f32: ; RV32IF-LABEL: fmuladd_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmul.s ft0, ft1, ft0 ; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmv.w.x ft1, a2 ; RV32IF-NEXT: fmul.s ft1, ft2, ft1
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmuladd_f32: ; RV64IF-LABEL: fmuladd_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmul.s ft0, ft1, ft0 ; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmv.w.x ft1, a2 ; RV64IF-NEXT: fmul.s ft1, ft2, ft1
; RV64IF-NEXT: fadd.s ft0, ft0, ft1 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
ret float %1 ret float %1
} }
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
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llvm/test/CodeGen/RISCV/float-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
define float @flw(float *%a) nounwind { define float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw: ; RV32IF-LABEL: flw:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: flw ft0, 12(a0) ; RV32IF-NEXT: flw ft0, 0(a0)
; RV32IF-NEXT: flw ft1, 0(a0) ; RV32IF-NEXT: flw ft1, 12(a0)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw: ; RV64IF-LABEL: flw:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: flw ft0, 12(a0) ; RV64IF-NEXT: flw ft0, 0(a0)
; RV64IF-NEXT: flw ft1, 0(a0) ; RV64IF-NEXT: flw ft1, 12(a0)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = load float, float* %a %1 = load float, float* %a
%2 = getelementptr float, float* %a, i32 3 %2 = getelementptr float, float* %a, i32 3
%3 = load float, float* %2 %3 = load float, float* %2
; Use both loaded values in an FP op to ensure an flw is used, even for the ; Use both loaded values in an FP op to ensure an flw is used, even for the
; soft float ABI ; soft float ABI
%4 = fadd float %1, %3 %4 = fadd float %1, %3
ret float %4 ret float %4
} }
define void @fsw(float *%a, float %b, float %c) nounwind { define void @fsw(float *%a, float %b, float %c) nounwind {
; Use %b and %c in an FP op to ensure floating point registers are used, even ; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
; RV32IF-LABEL: fsw: ; RV32IF-LABEL: fsw:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2 ; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fsw ft0, 32(a0)
; RV32IF-NEXT: fsw ft0, 0(a0) ; RV32IF-NEXT: fsw ft0, 0(a0)
; RV32IF-NEXT: fsw ft0, 32(a0)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fsw: ; RV64IF-LABEL: fsw:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2 ; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fsw ft0, 32(a0)
; RV64IF-NEXT: fsw ft0, 0(a0) ; RV64IF-NEXT: fsw ft0, 0(a0)
; RV64IF-NEXT: fsw ft0, 32(a0)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %b, %c %1 = fadd float %b, %c
store float %1, float* %a store float %1, float* %a
%2 = getelementptr float, float* %a, i32 8 %2 = getelementptr float, float* %a, i32 8
store float %1, float* %2 store float %1, float* %2
ret void ret void
} }
; Check load and store to a global ; Check load and store to a global
@G = global float 0.0 @G = global float 0.0
define float @flw_fsw_global(float %a, float %b) nounwind { define float @flw_fsw_global(float %a, float %b) nounwind {
; Use %a and %b in an FP op to ensure floating point registers are used, even ; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
; RV32IF-LABEL: flw_fsw_global: ; RV32IF-LABEL: flw_fsw_global:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: lui a0, %hi(G) ; RV32IF-NEXT: lui a0, %hi(G)
; RV32IF-NEXT: flw ft1, %lo(G)(a0) ; RV32IF-NEXT: flw ft1, %lo(G)(a0)
; RV32IF-NEXT: fsw ft0, %lo(G)(a0) ; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
; RV32IF-NEXT: addi a0, a0, %lo(G) ; RV32IF-NEXT: addi a1, a0, %lo(G)
; RV32IF-NEXT: flw ft1, 36(a0) ; RV32IF-NEXT: flw ft1, 36(a1)
; RV32IF-NEXT: fsw ft0, 36(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: fsw ft0, 36(a1)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_fsw_global: ; RV64IF-LABEL: flw_fsw_global:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: lui a0, %hi(G) ; RV64IF-NEXT: lui a0, %hi(G)
; RV64IF-NEXT: flw ft1, %lo(G)(a0) ; RV64IF-NEXT: flw ft1, %lo(G)(a0)
; RV64IF-NEXT: fsw ft0, %lo(G)(a0) ; RV64IF-NEXT: fsw ft0, %lo(G)(a0)
; RV64IF-NEXT: addi a0, a0, %lo(G) ; RV64IF-NEXT: addi a1, a0, %lo(G)
; RV64IF-NEXT: flw ft1, 36(a0) ; RV64IF-NEXT: flw ft1, 36(a1)
; RV64IF-NEXT: fsw ft0, 36(a0)
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: fsw ft0, 36(a1)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = load volatile float, float* @G %2 = load volatile float, float* @G
store float %1, float* @G store float %1, float* @G
%3 = getelementptr float, float* @G, i32 9 %3 = getelementptr float, float* @G, i32 9
%4 = load volatile float, float* %3 %4 = load volatile float, float* %3
store float %1, float* %3 store float %1, float* %3
ret float %1 ret float %1
} }
; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
define float @flw_fsw_constant(float %a) nounwind { define float @flw_fsw_constant(float %a) nounwind {
; RV32IF-LABEL: flw_fsw_constant: ; RV32IF-LABEL: flw_fsw_constant:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: lui a1, 912092
; RV32IF-NEXT: lui a0, 912092 ; RV32IF-NEXT: flw ft0, -273(a1)
; RV32IF-NEXT: flw ft1, -273(a0) ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fsw ft0, -273(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: fsw ft0, -273(a1)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_fsw_constant: ; RV64IF-LABEL: flw_fsw_constant:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: lui a1, 56
; RV64IF-NEXT: lui a0, 56 ; RV64IF-NEXT: addiw a1, a1, -1353
; RV64IF-NEXT: addiw a0, a0, -1353 ; RV64IF-NEXT: slli a1, a1, 14
; RV64IF-NEXT: slli a0, a0, 14 ; RV64IF-NEXT: flw ft0, -273(a1)
; RV64IF-NEXT: flw ft1, -273(a0) ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft0, ft1 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fsw ft0, -273(a0)
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: fsw ft0, -273(a1)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = inttoptr i32 3735928559 to float* %1 = inttoptr i32 3735928559 to float*
%2 = load volatile float, float* %1 %2 = load volatile float, float* %1
%3 = fadd float %a, %2 %3 = fadd float %a, %2
store float %3, float* %1 store float %3, float* %1
ret float %3 ret float %3
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define float @flw_stack(float %a) nounwind { define float @flw_stack(float %a) nounwind {
; RV32IF-LABEL: flw_stack: ; RV32IF-LABEL: flw_stack:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s0, 8(sp) ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: mv s0, a0 ; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: addi a0, sp, 4 ; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead ; RV32IF-NEXT: call notdead
; RV32IF-NEXT: fmv.w.x ft0, s0 ; RV32IF-NEXT: flw ft0, 8(sp)
; RV32IF-NEXT: flw ft1, 4(sp) ; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_stack: ; RV64IF-LABEL: flw_stack:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -32 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 24(sp) ; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd s0, 16(sp) ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: mv s0, a0 ; RV64IF-NEXT: fsw ft0, 0(sp)
; RV64IF-NEXT: addi a0, sp, 12 ; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead ; RV64IF-NEXT: call notdead
; RV64IF-NEXT: fmv.w.x ft0, s0 ; RV64IF-NEXT: flw ft0, 4(sp)
; RV64IF-NEXT: flw ft1, 12(sp) ; RV64IF-NEXT: flw ft1, 0(sp)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s0, 16(sp) ; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: ld ra, 24(sp) ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = alloca float, align 4 %1 = alloca float, align 4
%2 = bitcast float* %1 to i8* %2 = bitcast float* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load float, float* %1 %3 = load float, float* %1
%4 = fadd float %3, %a ; force load in to FPR32 %4 = fadd float %3, %a ; force load in to FPR32
ret float %4 ret float %4
} }
Show All 36 Lines

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

Show First 20 Lines • Show All 234 Lines • ▼ Show 20 Lines; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b %1 = fcmp ord float %a, %b
%2 = select i1 %1, float %a, float %b %2 = select i1 %1, float %a, float %b
ret float %2 ret float %2
} }
define float @select_fcmp_ueq(float %a, float %b) nounwind { define float @select_fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: select_fcmp_ueq: ; RV32IF-LABEL: select_fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: feq.s a1, ft1, ft1
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: feq.s a2, ft0, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft1 ; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: or a0, a1, a0 ; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB8_2 ; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1 ; RV32IF-NEXT: fmv.s ft0, ft1
; RV32IF-NEXT: .LBB8_2: ; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: select_fcmp_ueq: ; RV64IF-LABEL: select_fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: feq.s a1, ft1, ft1
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: feq.s a2, ft0, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft1 ; RV64IF-NEXT: and a1, a2, a1
; RV64IF-NEXT: or a0, a1, a0 ; RV64IF-NEXT: seqz a1, a1
; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB8_2 ; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1 ; RV64IF-NEXT: fmv.s ft0, ft1
; RV64IF-NEXT: .LBB8_2: ; RV64IF-NEXT: .LBB8_2:
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
%2 = select i1 %1, float %a, float %b %2 = select i1 %1, float %a, float %b
▲ Show 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
} }
; Ensure that ISel succeeds for a select+fcmp that has an i32 result type. ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind { define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
; RV32IF-LABEL: i32_select_fcmp_oeq: ; RV32IF-LABEL: i32_select_fcmp_oeq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a1, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB16_2 ; RV32IF-NEXT: mv a0, a2
; RV32IF-NEXT: bnez a1, .LBB16_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: mv a2, a3 ; RV32IF-NEXT: mv a0, a3
; RV32IF-NEXT: .LBB16_2: ; RV32IF-NEXT: .LBB16_2:
; RV32IF-NEXT: mv a0, a2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: i32_select_fcmp_oeq: ; RV64IF-LABEL: i32_select_fcmp_oeq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a1, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB16_2 ; RV64IF-NEXT: mv a0, a2
; RV64IF-NEXT: bnez a1, .LBB16_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: mv a2, a3 ; RV64IF-NEXT: mv a0, a3
; RV64IF-NEXT: .LBB16_2: ; RV64IF-NEXT: .LBB16_2:
; RV64IF-NEXT: mv a0, a2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b %1 = fcmp oeq float %a, %b
%2 = select i1 %1, i32 %c, i32 %d %2 = select i1 %1, i32 %c, i32 %d
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/RISCV/fp128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 @x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 @y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
; Besides anything else, these tests help verify that libcall ABI lowering ; Besides anything else, these tests help verify that libcall ABI lowering
; works correctly ; works correctly
define i32 @test_load_and_cmp() nounwind { define i32 @test_load_and_cmp() nounwind {
; RV32I-LABEL: test_load_and_cmp: ; RV32I-LABEL: test_load_and_cmp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: lui a0, %hi(y) ; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a1, %lo(y)(a0) ; RV32I-NEXT: addi a1, a0, %lo(x)
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: lw a6, 4(a1)
; RV32I-NEXT: lui a1, %hi(x) ; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a2, %lo(x)(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sw a2, 24(sp) ; RV32I-NEXT: lw a0, %lo(x)(a0)
; RV32I-NEXT: addi a0, a0, %lo(y) ; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a2, 12(a0) ; RV32I-NEXT: addi a5, a4, %lo(y)
; RV32I-NEXT: sw a2, 20(sp) ; RV32I-NEXT: lw a2, 4(a5)
; RV32I-NEXT: lw a2, 8(a0) ; RV32I-NEXT: lw a3, 8(a5)
; RV32I-NEXT: sw a2, 16(sp) ; RV32I-NEXT: lw a5, 12(a5)
; RV32I-NEXT: lw a0, 4(a0) ; RV32I-NEXT: lw a4, %lo(y)(a4)
; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: addi a0, a1, %lo(x) ; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lw a1, 12(a0) ; RV32I-NEXT: sw a5, 20(sp)
; RV32I-NEXT: sw a3, 16(sp)
; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: sw a1, 36(sp) ; RV32I-NEXT: sw a1, 36(sp)
; RV32I-NEXT: lw a1, 8(a0) ; RV32I-NEXT: sw a7, 32(sp)
; RV32I-NEXT: sw a1, 32(sp)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a6, 28(sp)
; RV32I-NEXT: call __netf2 ; RV32I-NEXT: call __netf2
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16 %1 = load fp128, fp128* @x, align 16
%2 = load fp128, fp128* @y, align 16 %2 = load fp128, fp128* @y, align 16
%cmp = fcmp une fp128 %1, %2 %cmp = fcmp une fp128 %1, %2
%3 = zext i1 %cmp to i32 %3 = zext i1 %cmp to i32
ret i32 %3 ret i32 %3
} }
define i32 @test_add_and_fptosi() nounwind { define i32 @test_add_and_fptosi() nounwind {
; RV32I-LABEL: test_add_and_fptosi: ; RV32I-LABEL: test_add_and_fptosi:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80 ; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp) ; RV32I-NEXT: sw ra, 76(sp)
; RV32I-NEXT: lui a0, %hi(y) ; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a1, %lo(y)(a0) ; RV32I-NEXT: addi a1, a0, %lo(x)
; RV32I-NEXT: sw a1, 24(sp) ; RV32I-NEXT: lw a6, 4(a1)
; RV32I-NEXT: lui a1, %hi(x) ; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a2, %lo(x)(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sw a2, 40(sp) ; RV32I-NEXT: lw a0, %lo(x)(a0)
; RV32I-NEXT: addi a0, a0, %lo(y) ; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a2, 12(a0) ; RV32I-NEXT: addi a5, a4, %lo(y)
; RV32I-NEXT: sw a2, 36(sp) ; RV32I-NEXT: lw a3, 4(a5)
; RV32I-NEXT: lw a2, 8(a0) ; RV32I-NEXT: lw a2, 8(a5)
; RV32I-NEXT: lw a5, 12(a5)
; RV32I-NEXT: lw a4, %lo(y)(a4)
; RV32I-NEXT: sw a4, 24(sp)
; RV32I-NEXT: sw a0, 40(sp)
; RV32I-NEXT: sw a5, 36(sp)
; RV32I-NEXT: sw a2, 32(sp) ; RV32I-NEXT: sw a2, 32(sp)
; RV32I-NEXT: lw a0, 4(a0) ; RV32I-NEXT: sw a3, 28(sp)
; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: addi a0, a1, %lo(x)
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: sw a1, 52(sp) ; RV32I-NEXT: sw a1, 52(sp)
; RV32I-NEXT: lw a1, 8(a0) ; RV32I-NEXT: sw a7, 48(sp)
; RV32I-NEXT: sw a1, 48(sp)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 44(sp)
; RV32I-NEXT: addi a0, sp, 56 ; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40 ; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24 ; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: sw a6, 44(sp)
; RV32I-NEXT: call __addtf3 ; RV32I-NEXT: call __addtf3
; RV32I-NEXT: lw a0, 68(sp) ; RV32I-NEXT: lw a1, 56(sp)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 64(sp)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 60(sp) ; RV32I-NEXT: lw a0, 60(sp)
; RV32I-NEXT: lw a2, 64(sp)
; RV32I-NEXT: lw a3, 68(sp)
; RV32I-NEXT: sw a3, 20(sp)
; RV32I-NEXT: sw a2, 16(sp)
; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 56(sp)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: addi a0, sp, 8 ; RV32I-NEXT: addi a0, sp, 8
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: call __fixtfsi ; RV32I-NEXT: call __fixtfsi
; RV32I-NEXT: lw ra, 76(sp) ; RV32I-NEXT: lw ra, 76(sp)
; RV32I-NEXT: addi sp, sp, 80 ; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16 %1 = load fp128, fp128* @x, align 16
%2 = load fp128, fp128* @y, align 16 %2 = load fp128, fp128* @y, align 16
%3 = fadd fp128 %1, %2 %3 = fadd fp128 %1, %2
%4 = fptosi fp128 %3 to i32 %4 = fptosi fp128 %3 to i32
ret i32 %4 ret i32 %4
} }

llvm/test/CodeGen/RISCV/frame-info.ll

Show All 32 Lines
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) ; RV64-NEXT: sd ra, 8(sp)
; RV64-NEXT: sd s0, 0(sp) ; RV64-NEXT: sd s0, 0(sp)
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_offset s0, -16 ; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: addi s0, sp, 16 ; RV64-NEXT: addi s0, sp, 16
; RV64-NEXT: .cfi_def_cfa s0, 0 ; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: addi a1, a1, -16
; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: addi a0, a0, 15 ; RV64-NEXT: addi a0, a0, 15
; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: addi a1, a1, -16
; RV64-NEXT: and a0, a0, a1 ; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: sub a0, sp, a0 ; RV64-NEXT: sub a0, sp, a0
; RV64-NEXT: mv sp, a0 ; RV64-NEXT: mv sp, a0
; RV64-NEXT: call bar ; RV64-NEXT: call bar
; RV64-NEXT: addi sp, s0, -16 ; RV64-NEXT: addi sp, s0, -16
; RV64-NEXT: ld s0, 0(sp) ; RV64-NEXT: ld s0, 0(sp)
; RV64-NEXT: .cfi_def_cfa sp, 16 ; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: ld ra, 8(sp) ; RV64-NEXT: ld ra, 8(sp)
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llvm/test/CodeGen/RISCV/get-setcc-result-type.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) nounwind { define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) nounwind {
; RV32I-LABEL: getSetCCResultType: ; RV32I-LABEL: getSetCCResultType:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lw a1, 12(a0) ; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lw a2, 8(a0)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: neg a4, a4
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: neg a1, a1 ; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: lw a1, 8(a0) ; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: neg a1, a1 ; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%0 = load <4 x i32>, <4 x i32>* %p, align 16 %0 = load <4 x i32>, <4 x i32>* %p, align 16
%cmp = icmp eq <4 x i32> %0, zeroinitializer %cmp = icmp eq <4 x i32> %0, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32> %sext = sext <4 x i1> %cmp to <4 x i32>
store <4 x i32> %sext, <4 x i32>* %p, align 16 store <4 x i32> %sext, <4 x i32>* %p, align 16
ret void ret void
} }

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
%struct.S = type { [40 x i32], i32, i32, i32, [4100 x i32], i32, i32, i32 } %struct.S = type { [40 x i32], i32, i32, i32, [4100 x i32], i32, i32, i32 }
@s = common dso_local global %struct.S zeroinitializer, align 4 @s = common dso_local global %struct.S zeroinitializer, align 4
@foo = global [6 x i16] [i16 1, i16 2, i16 3, i16 4, i16 5, i16 0], align 2 @foo = global [6 x i16] [i16 1, i16 2, i16 3, i16 4, i16 5, i16 0], align 2
@g = global [1048576 x i8] zeroinitializer, align 1 @g = global [1048576 x i8] zeroinitializer, align 1
define dso_local void @multiple_stores() local_unnamed_addr nounwind { define dso_local void @multiple_stores() local_unnamed_addr nounwind {
; CHECK-LABEL: multiple_stores: ; CHECK-LABEL: multiple_stores:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s) ; CHECK-NEXT: lui a0, %hi(s)
; CHECK-NEXT: addi a0, a0, %lo(s) ; CHECK-NEXT: addi a0, a0, %lo(s)
; CHECK-NEXT: addi a1, zero, 20
; CHECK-NEXT: sw a1, 164(a0)
; CHECK-NEXT: addi a1, zero, 10 ; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: sw a1, 160(a0) ; CHECK-NEXT: sw a1, 160(a0)
; CHECK-NEXT: addi a1, zero, 20
; CHECK-NEXT: sw a1, 164(a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4 store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
store i32 20, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 2), align 4 store i32 20, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 2), align 4
ret void ret void
} }
define dso_local void @control_flow_with_mem_access() local_unnamed_addr nounwind { define dso_local void @control_flow_with_mem_access() local_unnamed_addr nounwind {
▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/imm-cse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
@src = global i32 0 @src = global i32 0
@dst = global i32 0 @dst = global i32 0
; Tests that the common hi20 value (1) for the constants is used rather than ; Tests that the common hi20 value (1) for the constants is used rather than
; redundantly re-materialised. ; redundantly re-materialised.
define void @imm32_cse() nounwind { define void @imm32_cse() nounwind {
; RV32I-LABEL: imm32_cse: ; RV32I-LABEL: imm32_cse:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, %hi(src)
; RV32I-NEXT: addi a0, a0, 1 ; RV32I-NEXT: lw a1, %lo(src)(a0)
; RV32I-NEXT: lui a1, %hi(src) ; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: lw a2, %lo(src)(a1)
; RV32I-NEXT: add a2, a2, a0
; RV32I-NEXT: lui a3, %hi(dst)
; RV32I-NEXT: sw a2, %lo(dst)(a3)
; RV32I-NEXT: lw a2, %lo(src)(a1)
; RV32I-NEXT: add a2, a2, a0
; RV32I-NEXT: addi a2, a2, 1 ; RV32I-NEXT: addi a2, a2, 1
; RV32I-NEXT: sw a2, %lo(dst)(a3) ; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: lw a1, %lo(src)(a1) ; RV32I-NEXT: lui a3, %hi(dst)
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: sw a1, %lo(dst)(a3)
; RV32I-NEXT: lw a1, %lo(src)(a0)
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: addi a1, a1, 1
; RV32I-NEXT: sw a1, %lo(dst)(a3)
; RV32I-NEXT: lw a0, %lo(src)(a0)
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: addi a0, a0, 2 ; RV32I-NEXT: addi a0, a0, 2
; RV32I-NEXT: sw a0, %lo(dst)(a3) ; RV32I-NEXT: sw a0, %lo(dst)(a3)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = load volatile i32, i32* @src %1 = load volatile i32, i32* @src
%2 = add i32 %1, 4097 %2 = add i32 %1, 4097
store volatile i32 %2, i32* @dst store volatile i32 %2, i32* @dst
%3 = load volatile i32, i32* @src %3 = load volatile i32, i32* @src
%4 = add i32 %3, 4098 %4 = add i32 %3, 4098
store volatile i32 %4, i32* @dst store volatile i32 %4, i32* @dst
%5 = load volatile i32, i32* @src %5 = load volatile i32, i32* @src
%6 = add i32 %5, 4099 %6 = add i32 %5, 4099
store volatile i32 %6, i32* @dst store volatile i32 %6, i32* @dst
ret void ret void
} }

llvm/test/CodeGen/RISCV/imm.ll

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i64 4294967295 ret i64 4294967295
} }
define i64 @imm64_3() nounwind { define i64 @imm64_3() nounwind {
; RV32I-LABEL: imm64_3: ; RV32I-LABEL: imm64_3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: addi a1, zero, 1 ; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: imm64_3: ; RV64I-LABEL: imm64_3:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i64 4294967296 ret i64 4294967296
} }
define i64 @imm64_4() nounwind { define i64 @imm64_4() nounwind {
; RV32I-LABEL: imm64_4: ; RV32I-LABEL: imm64_4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: imm64_4: ; RV64I-LABEL: imm64_4:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i64 9223372036854775808 ret i64 9223372036854775808
} }
define i64 @imm64_5() nounwind { define i64 @imm64_5() nounwind {
; RV32I-LABEL: imm64_5: ; RV32I-LABEL: imm64_5:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: imm64_5: ; RV64I-LABEL: imm64_5:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i64 -9223372036854775808 ret i64 -9223372036854775808
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; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i64 1311768467463790320 ret i64 1311768467463790320
} }
define i64 @imm64_9() nounwind { define i64 @imm64_9() nounwind {
; RV32I-LABEL: imm64_9: ; RV32I-LABEL: imm64_9:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, -1 ; RV32I-NEXT: addi a0, zero, -1
; RV32I-NEXT: addi a1, zero, -1 ; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: imm64_9: ; RV64I-LABEL: imm64_9:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i64 -1 ret i64 -1
} }

llvm/test/CodeGen/RISCV/indirectbr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
define i32 @indirectbr(i8* %target) nounwind { define i32 @indirectbr(i8* %target) nounwind {
; RV32I-LABEL: indirectbr: ; RV32I-LABEL: indirectbr:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: jr a0 ; RV32I-NEXT: jr a0
; RV32I-NEXT: .LBB0_1: ; RV32I-NEXT: .LBB0_1: # %test_label
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
indirectbr i8* %target, [label %test_label] indirectbr i8* %target, [label %test_label]
test_label: test_label:
br label %ret br label %ret
ret: ret:
ret i32 0 ret i32 0
} }
define i32 @indirectbr_with_offset(i8* %a) nounwind { define i32 @indirectbr_with_offset(i8* %a) nounwind {
; RV32I-LABEL: indirectbr_with_offset: ; RV32I-LABEL: indirectbr_with_offset:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: jr 1380(a0) ; RV32I-NEXT: jr 1380(a0)
; RV32I-NEXT: .LBB1_1: ; RV32I-NEXT: .LBB1_1: # %test_label
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%target = getelementptr inbounds i8, i8* %a, i32 1380 %target = getelementptr inbounds i8, i8* %a, i32 1380
indirectbr i8* %target, [label %test_label] indirectbr i8* %target, [label %test_label]
test_label: test_label:
br label %ret br label %ret
ret: ret:
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll

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; RV32F-NEXT: fsd ft0, 8(sp) ; RV32F-NEXT: fsd ft0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp) ; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp) ; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_f_double: ; RV64F-LABEL: constraint_f_double:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: fmv.d.x ft0, a0 ; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: lui a0, %hi(gd) ; RV64F-NEXT: fld ft0, %lo(gd)(a1)
; RV64F-NEXT: fld ft1, %lo(gd)(a0) ; RV64F-NEXT: fmv.d.x ft1, a0
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.d ft0, ft0, ft1 ; RV64F-NEXT: fadd.d ft0, ft1, ft0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.d a0, ft0 ; RV64F-NEXT: fmv.x.d a0, ft0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = load double, double* @gd %1 = load double, double* @gd
%2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1) %2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
ret double %2 ret double %2
} }
Show All 12 Lines
; RV32F-NEXT: fsd ft0, 8(sp) ; RV32F-NEXT: fsd ft0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp) ; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp) ; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_f_double_abi_name: ; RV64F-LABEL: constraint_f_double_abi_name:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: fld fs0, %lo(gd)(a1)
; RV64F-NEXT: fmv.d.x fa1, a0 ; RV64F-NEXT: fmv.d.x fa1, a0
; RV64F-NEXT: lui a0, %hi(gd)
; RV64F-NEXT: fld fs0, %lo(gd)(a0)
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.d ft0, fa1, fs0 ; RV64F-NEXT: fadd.d ft0, fa1, fs0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.d a0, ft0 ; RV64F-NEXT: fmv.x.d a0, ft0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = load double, double* @gd %1 = load double, double* @gd
%2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1) %2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1)
ret double %2 ret double %2
} }

llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s ; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s ; RUN: | FileCheck -check-prefix=RV64F %s
@gf = external global float @gf = external global float
define float @constraint_f_float(float %a) nounwind { define float @constraint_f_float(float %a) nounwind {
; RV32F-LABEL: constraint_f_float: ; RV32F-LABEL: constraint_f_float:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a0 ; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: lui a0, %hi(gf) ; RV32F-NEXT: flw ft0, %lo(gf)(a1)
; RV32F-NEXT: flw ft1, %lo(gf)(a0) ; RV32F-NEXT: fmv.w.x ft1, a0
; RV32F-NEXT: #APP ; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.s ft0, ft0, ft1 ; RV32F-NEXT: fadd.s ft0, ft1, ft0
; RV32F-NEXT: #NO_APP ; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, ft0 ; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_f_float: ; RV64F-LABEL: constraint_f_float:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a0 ; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: lui a0, %hi(gf) ; RV64F-NEXT: flw ft0, %lo(gf)(a1)
; RV64F-NEXT: flw ft1, %lo(gf)(a0) ; RV64F-NEXT: fmv.w.x ft1, a0
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.s ft0, ft0, ft1 ; RV64F-NEXT: fadd.s ft0, ft1, ft0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, ft0 ; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = load float, float* @gf %1 = load float, float* @gf
%2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1) %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)
ret float %2 ret float %2
} }
define float @constraint_f_float_abi_name(float %a) nounwind { define float @constraint_f_float_abi_name(float %a) nounwind {
; RV32F-LABEL: constraint_f_float_abi_name: ; RV32F-LABEL: constraint_f_float_abi_name:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw fs0, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x fa0, a0 ; RV32F-NEXT: fmv.w.x fa0, a0
; RV32F-NEXT: lui a0, %hi(gf)
; RV32F-NEXT: flw fs0, %lo(gf)(a0)
; RV32F-NEXT: #APP ; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.s ft0, fa0, fs0 ; RV32F-NEXT: fadd.s ft0, fa0, fs0
; RV32F-NEXT: #NO_APP ; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, ft0 ; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_f_float_abi_name: ; RV64F-LABEL: constraint_f_float_abi_name:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw fs0, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x fa0, a0 ; RV64F-NEXT: fmv.w.x fa0, a0
; RV64F-NEXT: lui a0, %hi(gf)
; RV64F-NEXT: flw fs0, %lo(gf)(a0)
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.s ft0, fa0, fs0 ; RV64F-NEXT: fadd.s ft0, fa0, fs0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, ft0 ; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = load float, float* @gf %1 = load float, float* @gf
%2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1) %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1)
ret float %2 ret float %2
} }

llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_float: ; CHECK-RV32IF-LABEL: foo_float:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -16 ; CHECK-RV32IF-NEXT: addi sp, sp, -16
; CHECK-RV32IF-NEXT: sw a0, 12(sp) ; CHECK-RV32IF-NEXT: sw a0, 12(sp)
; CHECK-RV32IF-NEXT: fsw ft0, 8(sp) ; CHECK-RV32IF-NEXT: fsw ft0, 8(sp)
; CHECK-RV32IF-NEXT: fsw ft1, 4(sp) ; CHECK-RV32IF-NEXT: fsw ft1, 4(sp)
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(e) ; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft1, %lo(e)(a0) ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IF-NEXT: lui a0, %hi(d) ; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: flw ft1, 4(sp) ; CHECK-RV32IF-NEXT: flw ft1, 4(sp)
; CHECK-RV32IF-NEXT: flw ft0, 8(sp) ; CHECK-RV32IF-NEXT: flw ft0, 8(sp)
; CHECK-RV32IF-NEXT: lw a0, 12(sp) ; CHECK-RV32IF-NEXT: lw a0, 12(sp)
; CHECK-RV32IF-NEXT: addi sp, sp, 16 ; CHECK-RV32IF-NEXT: addi sp, sp, 16
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_float: ; CHECK-RV32IFD-LABEL: foo_float:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) ; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(e) ; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(e)(a0) ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft1, ft0 ; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d) ; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 16(sp)
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) ; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e %1 = load float, float* @e
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; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -32 ; CHECK-RV32IF-NEXT: addi sp, sp, -32
; CHECK-RV32IF-NEXT: sw ra, 28(sp) ; CHECK-RV32IF-NEXT: sw ra, 28(sp)
; CHECK-RV32IF-NEXT: sw s0, 24(sp) ; CHECK-RV32IF-NEXT: sw s0, 24(sp)
; CHECK-RV32IF-NEXT: sw a0, 20(sp) ; CHECK-RV32IF-NEXT: sw a0, 20(sp)
; CHECK-RV32IF-NEXT: fsw ft0, 16(sp) ; CHECK-RV32IF-NEXT: fsw ft0, 16(sp)
; CHECK-RV32IF-NEXT: fsw ft1, 12(sp) ; CHECK-RV32IF-NEXT: fsw ft1, 12(sp)
; CHECK-RV32IF-NEXT: addi s0, sp, 32 ; CHECK-RV32IF-NEXT: addi s0, sp, 32
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(e) ; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft1, %lo(e)(a0) ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IF-NEXT: lui a0, %hi(d) ; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: flw ft1, 12(sp) ; CHECK-RV32IF-NEXT: flw ft1, 12(sp)
; CHECK-RV32IF-NEXT: flw ft0, 16(sp) ; CHECK-RV32IF-NEXT: flw ft0, 16(sp)
; CHECK-RV32IF-NEXT: lw a0, 20(sp) ; CHECK-RV32IF-NEXT: lw a0, 20(sp)
; CHECK-RV32IF-NEXT: lw s0, 24(sp) ; CHECK-RV32IF-NEXT: lw s0, 24(sp)
; CHECK-RV32IF-NEXT: lw ra, 28(sp) ; CHECK-RV32IF-NEXT: lw ra, 28(sp)
; CHECK-RV32IF-NEXT: addi sp, sp, 32 ; CHECK-RV32IF-NEXT: addi sp, sp, 32
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_fp_float: ; CHECK-RV32IFD-LABEL: foo_fp_float:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) ; CHECK-RV32IFD-NEXT: sw ra, 28(sp)
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) ; CHECK-RV32IFD-NEXT: sw s0, 24(sp)
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) ; CHECK-RV32IFD-NEXT: sw a0, 20(sp)
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
; CHECK-RV32IFD-NEXT: addi s0, sp, 32 ; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(e) ; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(e)(a0) ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft1, ft0 ; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d) ; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 8(sp)
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) ; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) ; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) ; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
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; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_double: ; CHECK-RV32IFD-LABEL: foo_double:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) ; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(h) ; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(h)(a0) ; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g) ; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0) ; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 16(sp)
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) ; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h %1 = load double, double* @h
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; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) ; CHECK-RV32IFD-NEXT: sw ra, 28(sp)
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) ; CHECK-RV32IFD-NEXT: sw s0, 24(sp)
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) ; CHECK-RV32IFD-NEXT: sw a0, 20(sp)
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
; CHECK-RV32IFD-NEXT: addi s0, sp, 32 ; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(h) ; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(h)(a0) ; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g) ; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0) ; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 8(sp)
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) ; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) ; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) ; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
Show All 10 Lines

llvm/test/CodeGen/RISCV/legalize-fneg.ll

Show All 9 Lines
; RV32-NEXT: lw a1, 0(a1) ; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a2, 524288 ; RV32-NEXT: lui a2, 524288
; RV32-NEXT: xor a1, a1, a2 ; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: sw a1, 0(a0) ; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: test1: ; RV64-LABEL: test1:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: addi a2, zero, 1 ; RV64-NEXT: addi a2, zero, 1
; RV64-NEXT: slli a2, a2, 31 ; RV64-NEXT: slli a2, a2, 31
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: xor a1, a1, a2 ; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sw a1, 0(a0) ; RV64-NEXT: sw a1, 0(a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = load float, float* %b %0 = load float, float* %b
%neg = fneg float %0 %neg = fneg float %0
store float %neg, float* %a store float %neg, float* %a
ret void ret void
} }
define void @test2(double* %a, double* %b) nounwind { define void @test2(double* %a, double* %b) nounwind {
; RV32-LABEL: test2: ; RV32-LABEL: test2:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a1) ; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a1, 0(a1) ; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a3, 524288
; RV32-NEXT: xor a2, a2, a3
; RV32-NEXT: sw a1, 0(a0) ; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: sw a2, 4(a0)
; RV32-NEXT: xor a1, a2, a1
; RV32-NEXT: sw a1, 4(a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: test2: ; RV64-LABEL: test2:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: addi a2, zero, -1 ; RV64-NEXT: addi a2, zero, -1
; RV64-NEXT: slli a2, a2, 63 ; RV64-NEXT: slli a2, a2, 63
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: xor a1, a1, a2 ; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: sd a1, 0(a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = load double, double* %b %0 = load double, double* %b
%neg = fneg double %0 %neg = fneg double %0
store double %neg, double* %a store double %neg, double* %a
ret void ret void
} }
define void @test3(fp128* %a, fp128* %b) nounwind { define void @test3(fp128* %a, fp128* %b) nounwind {
; RV32-LABEL: test3: ; RV32-LABEL: test3:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 12(a1) ; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a3, 4(a1) ; RV32-NEXT: lw a3, 12(a1)
; RV32-NEXT: lw a4, 0(a1) ; RV32-NEXT: lw a4, 8(a1)
; RV32-NEXT: lw a1, 8(a1) ; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: sw a1, 8(a0) ; RV32-NEXT: lui a5, 524288
; RV32-NEXT: sw a4, 0(a0) ; RV32-NEXT: xor a3, a3, a5
; RV32-NEXT: sw a3, 4(a0) ; RV32-NEXT: sw a4, 8(a0)
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: xor a1, a2, a1 ; RV32-NEXT: sw a2, 4(a0)
; RV32-NEXT: sw a1, 12(a0) ; RV32-NEXT: sw a3, 12(a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: test3: ; RV64-LABEL: test3:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a2, 8(a1) ; RV64-NEXT: ld a2, 8(a1)
; RV64-NEXT: ld a1, 0(a1) ; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: addi a3, zero, -1
; RV64-NEXT: slli a3, a3, 63
; RV64-NEXT: xor a2, a2, a3
; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: sd a1, 0(a0)
; RV64-NEXT: addi a1, zero, -1 ; RV64-NEXT: sd a2, 8(a0)
; RV64-NEXT: slli a1, a1, 63
; RV64-NEXT: xor a1, a2, a1
; RV64-NEXT: sd a1, 8(a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = load fp128, fp128* %b %0 = load fp128, fp128* %b
%neg = fneg fp128 %0 %neg = fneg fp128 %0
store fp128 %neg, fp128* %a store fp128 %neg, fp128* %a
ret void ret void
} }

llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
@a = global [4096 x i32] zeroinitializer, align 4 @a = global [4096 x i32] zeroinitializer, align 4
@b = global [4096 x i32] zeroinitializer, align 4 @b = global [4096 x i32] zeroinitializer, align 4
; This test demonstrates very slightly improved codegen in the case that ; This test demonstrates very slightly improved codegen in the case that
; a correct isLegalAddImmediate is implemented, thanks to LoopStrengthReduce. ; a correct isLegalAddImmediate is implemented, thanks to LoopStrengthReduce.
define i32 @main() nounwind { define i32 @main() nounwind {
; RV32I-LABEL: main: ; RV32I-LABEL: main:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(b) ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: addi a0, a0, %lo(b) ; RV32I-NEXT: lui a1, %hi(b)
; RV32I-NEXT: lui a1, %hi(a) ; RV32I-NEXT: addi a1, a1, %lo(b)
; RV32I-NEXT: addi a1, a1, %lo(a) ; RV32I-NEXT: lui a2, %hi(a)
; RV32I-NEXT: lui a2, 1 ; RV32I-NEXT: addi a2, a2, %lo(a)
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: lui a3, 1
; RV32I-NEXT: .LBB0_1: # %for.body ; RV32I-NEXT: .LBB0_1: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: addi a4, a3, -2048 ; RV32I-NEXT: addi a4, a0, -2048
; RV32I-NEXT: sw a4, 0(a1) ; RV32I-NEXT: sw a4, 0(a2)
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: addi a1, a1, 4 ; RV32I-NEXT: addi a1, a1, 4
; RV32I-NEXT: sw a3, 0(a0) ; RV32I-NEXT: addi a2, a2, 4
; RV32I-NEXT: addi a0, a0, 4 ; RV32I-NEXT: bne a0, a3, .LBB0_1
; RV32I-NEXT: addi a3, a3, 1
; RV32I-NEXT: bne a3, a2, .LBB0_1
; RV32I-NEXT: # %bb.2: # %for.end ; RV32I-NEXT: # %bb.2: # %for.end
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
br label %for.body br label %for.body
for.body: for.body:
%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
Show All 12 Lines

llvm/test/CodeGen/RISCV/mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; Check indexed and unindexed, sext, zext and anyext loads ; Check indexed and unindexed, sext, zext and anyext loads
define i32 @lb(i8 *%a) nounwind { define i32 @lb(i8 *%a) nounwind {
; RV32I-LABEL: lb: ; RV32I-LABEL: lb:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0) ; RV32I-NEXT: lb a1, 1(a0)
; RV32I-NEXT: lb a0, 1(a0) ; RV32I-NEXT: lb a0, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 1 %1 = getelementptr i8, i8* %a, i32 1
%2 = load i8, i8* %1 %2 = load i8, i8* %1
%3 = sext i8 %2 to i32 %3 = sext i8 %2 to i32
; the unused load will produce an anyext for selection ; the unused load will produce an anyext for selection
%4 = load volatile i8, i8* %a %4 = load volatile i8, i8* %a
ret i32 %3 ret i32 %3
} }
define i32 @lh(i16 *%a) nounwind { define i32 @lh(i16 *%a) nounwind {
; RV32I-LABEL: lh: ; RV32I-LABEL: lh:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lh a1, 0(a0) ; RV32I-NEXT: lh a1, 4(a0)
; RV32I-NEXT: lh a0, 4(a0) ; RV32I-NEXT: lh a0, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 2 %1 = getelementptr i16, i16* %a, i32 2
%2 = load i16, i16* %1 %2 = load i16, i16* %1
%3 = sext i16 %2 to i32 %3 = sext i16 %2 to i32
; the unused load will produce an anyext for selection ; the unused load will produce an anyext for selection
%4 = load volatile i16, i16* %a %4 = load volatile i16, i16* %a
ret i32 %3 ret i32 %3
} }
define i32 @lw(i32 *%a) nounwind { define i32 @lw(i32 *%a) nounwind {
; RV32I-LABEL: lw: ; RV32I-LABEL: lw:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0) ; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lw a0, 12(a0) ; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 3 %1 = getelementptr i32, i32* %a, i32 3
%2 = load i32, i32* %1 %2 = load i32, i32* %1
%3 = load volatile i32, i32* %a %3 = load volatile i32, i32* %a
ret i32 %2 ret i32 %2
} }
define i32 @lbu(i8 *%a) nounwind { define i32 @lbu(i8 *%a) nounwind {
; RV32I-LABEL: lbu: ; RV32I-LABEL: lbu:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lbu a1, 0(a0) ; RV32I-NEXT: lbu a1, 4(a0)
; RV32I-NEXT: lbu a0, 4(a0) ; RV32I-NEXT: lbu a0, 0(a0)
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 4 %1 = getelementptr i8, i8* %a, i32 4
%2 = load i8, i8* %1 %2 = load i8, i8* %1
%3 = zext i8 %2 to i32 %3 = zext i8 %2 to i32
%4 = load volatile i8, i8* %a %4 = load volatile i8, i8* %a
%5 = zext i8 %4 to i32 %5 = zext i8 %4 to i32
%6 = add i32 %3, %5 %6 = add i32 %3, %5
ret i32 %6 ret i32 %6
} }
define i32 @lhu(i16 *%a) nounwind { define i32 @lhu(i16 *%a) nounwind {
; RV32I-LABEL: lhu: ; RV32I-LABEL: lhu:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 10(a0)
; RV32I-NEXT: lhu a0, 10(a0) ; RV32I-NEXT: lhu a0, 0(a0)
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 5 %1 = getelementptr i16, i16* %a, i32 5
%2 = load i16, i16* %1 %2 = load i16, i16* %1
%3 = zext i16 %2 to i32 %3 = zext i16 %2 to i32
%4 = load volatile i16, i16* %a %4 = load volatile i16, i16* %a
%5 = zext i16 %4 to i32 %5 = zext i16 %4 to i32
%6 = add i32 %3, %5 %6 = add i32 %3, %5
ret i32 %6 ret i32 %6
} }
; Check indexed and unindexed stores ; Check indexed and unindexed stores
define void @sb(i8 *%a, i8 %b) nounwind { define void @sb(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: sb: ; RV32I-LABEL: sb:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: sb a1, 0(a0) ; RV32I-NEXT: sb a1, 0(a0)
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
store i8 %b, i8* %a store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 6 %1 = getelementptr i8, i8* %a, i32 6
store i8 %b, i8* %1 store i8 %b, i8* %1
ret void ret void
} }
define void @sh(i16 *%a, i16 %b) nounwind { define void @sh(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: sh: ; RV32I-LABEL: sh:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: sh a1, 0(a0) ; RV32I-NEXT: sh a1, 0(a0)
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
store i16 %b, i16* %a store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 7 %1 = getelementptr i16, i16* %a, i32 7
store i16 %b, i16* %1 store i16 %b, i16* %1
ret void ret void
} }
define void @sw(i32 *%a, i32 %b) nounwind { define void @sw(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: sw: ; RV32I-LABEL: sw:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: sw a1, 0(a0) ; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
store i32 %b, i32* %a store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 8 %1 = getelementptr i32, i32* %a, i32 8
store i32 %b, i32* %1 store i32 %b, i32* %1
ret void ret void
} }
; Check load and store to an i1 location ; Check load and store to an i1 location
define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind { define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1: ; RV32I-LABEL: load_sext_zext_anyext_i1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0) ; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0) ; RV32I-NEXT: lbu a2, 2(a0)
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lb a0, 0(a0)
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; sextload i1 ; sextload i1
%1 = getelementptr i1, i1* %a, i32 1 %1 = getelementptr i1, i1* %a, i32 1
%2 = load i1, i1* %1 %2 = load i1, i1* %1
%3 = sext i1 %2 to i32 %3 = sext i1 %2 to i32
; zextload i1 ; zextload i1
%4 = getelementptr i1, i1* %a, i32 2 %4 = getelementptr i1, i1* %a, i32 2
%5 = load i1, i1* %4 %5 = load i1, i1* %4
%6 = zext i1 %5 to i32 %6 = zext i1 %5 to i32
%7 = add i32 %3, %6 %7 = add i32 %3, %6
; extload i1 (anyext). Produced as the load is unused. ; extload i1 (anyext). Produced as the load is unused.
%8 = load volatile i1, i1* %a %8 = load volatile i1, i1* %a
ret i32 %7 ret i32 %7
} }
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind { define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1_i16: ; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0) ; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0) ; RV32I-NEXT: lbu a2, 2(a0)
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lb a0, 0(a0)
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; sextload i1 ; sextload i1
%1 = getelementptr i1, i1* %a, i32 1 %1 = getelementptr i1, i1* %a, i32 1
%2 = load i1, i1* %1 %2 = load i1, i1* %1
%3 = sext i1 %2 to i16 %3 = sext i1 %2 to i16
; zextload i1 ; zextload i1
%4 = getelementptr i1, i1* %a, i32 2 %4 = getelementptr i1, i1* %a, i32 2
%5 = load i1, i1* %4 %5 = load i1, i1* %4
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/mem64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; Check indexed and unindexed, sext, zext and anyext loads ; Check indexed and unindexed, sext, zext and anyext loads
define i64 @lb(i8 *%a) nounwind { define i64 @lb(i8 *%a) nounwind {
; RV64I-LABEL: lb: ; RV64I-LABEL: lb:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 0(a0) ; RV64I-NEXT: lb a1, 1(a0)
; RV64I-NEXT: lb a0, 1(a0) ; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 1 %1 = getelementptr i8, i8* %a, i32 1
%2 = load i8, i8* %1 %2 = load i8, i8* %1
%3 = sext i8 %2 to i64 %3 = sext i8 %2 to i64
; the unused load will produce an anyext for selection ; the unused load will produce an anyext for selection
%4 = load volatile i8, i8* %a %4 = load volatile i8, i8* %a
ret i64 %3 ret i64 %3
} }
define i64 @lh(i16 *%a) nounwind { define i64 @lh(i16 *%a) nounwind {
; RV64I-LABEL: lh: ; RV64I-LABEL: lh:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lh a1, 0(a0) ; RV64I-NEXT: lh a1, 4(a0)
; RV64I-NEXT: lh a0, 4(a0) ; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 2 %1 = getelementptr i16, i16* %a, i32 2
%2 = load i16, i16* %1 %2 = load i16, i16* %1
%3 = sext i16 %2 to i64 %3 = sext i16 %2 to i64
; the unused load will produce an anyext for selection ; the unused load will produce an anyext for selection
%4 = load volatile i16, i16* %a %4 = load volatile i16, i16* %a
ret i64 %3 ret i64 %3
} }
define i64 @lw(i32 *%a) nounwind { define i64 @lw(i32 *%a) nounwind {
; RV64I-LABEL: lw: ; RV64I-LABEL: lw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lw a1, 0(a0) ; RV64I-NEXT: lw a1, 12(a0)
; RV64I-NEXT: lw a0, 12(a0) ; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 3 %1 = getelementptr i32, i32* %a, i32 3
%2 = load i32, i32* %1 %2 = load i32, i32* %1
%3 = sext i32 %2 to i64 %3 = sext i32 %2 to i64
; the unused load will produce an anyext for selection ; the unused load will produce an anyext for selection
%4 = load volatile i32, i32* %a %4 = load volatile i32, i32* %a
ret i64 %3 ret i64 %3
} }
define i64 @lbu(i8 *%a) nounwind { define i64 @lbu(i8 *%a) nounwind {
; RV64I-LABEL: lbu: ; RV64I-LABEL: lbu:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lbu a1, 0(a0) ; RV64I-NEXT: lbu a1, 4(a0)
; RV64I-NEXT: lbu a0, 4(a0) ; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 4 %1 = getelementptr i8, i8* %a, i32 4
%2 = load i8, i8* %1 %2 = load i8, i8* %1
%3 = zext i8 %2 to i64 %3 = zext i8 %2 to i64
%4 = load volatile i8, i8* %a %4 = load volatile i8, i8* %a
%5 = zext i8 %4 to i64 %5 = zext i8 %4 to i64
%6 = add i64 %3, %5 %6 = add i64 %3, %5
ret i64 %6 ret i64 %6
} }
define i64 @lhu(i16 *%a) nounwind { define i64 @lhu(i16 *%a) nounwind {
; RV64I-LABEL: lhu: ; RV64I-LABEL: lhu:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 10(a0)
; RV64I-NEXT: lhu a0, 10(a0) ; RV64I-NEXT: lhu a0, 0(a0)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 5 %1 = getelementptr i16, i16* %a, i32 5
%2 = load i16, i16* %1 %2 = load i16, i16* %1
%3 = zext i16 %2 to i64 %3 = zext i16 %2 to i64
%4 = load volatile i16, i16* %a %4 = load volatile i16, i16* %a
%5 = zext i16 %4 to i64 %5 = zext i16 %4 to i64
%6 = add i64 %3, %5 %6 = add i64 %3, %5
ret i64 %6 ret i64 %6
} }
define i64 @lwu(i32 *%a) nounwind { define i64 @lwu(i32 *%a) nounwind {
; RV64I-LABEL: lwu: ; RV64I-LABEL: lwu:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lwu a1, 0(a0) ; RV64I-NEXT: lwu a1, 24(a0)
; RV64I-NEXT: lwu a0, 24(a0) ; RV64I-NEXT: lwu a0, 0(a0)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 6 %1 = getelementptr i32, i32* %a, i32 6
%2 = load i32, i32* %1 %2 = load i32, i32* %1
%3 = zext i32 %2 to i64 %3 = zext i32 %2 to i64
%4 = load volatile i32, i32* %a %4 = load volatile i32, i32* %a
%5 = zext i32 %4 to i64 %5 = zext i32 %4 to i64
%6 = add i64 %3, %5 %6 = add i64 %3, %5
ret i64 %6 ret i64 %6
} }
; Check indexed and unindexed stores ; Check indexed and unindexed stores
define void @sb(i8 *%a, i8 %b) nounwind { define void @sb(i8 *%a, i8 %b) nounwind {
; RV64I-LABEL: sb: ; RV64I-LABEL: sb:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sb a1, 7(a0)
; RV64I-NEXT: sb a1, 0(a0) ; RV64I-NEXT: sb a1, 0(a0)
; RV64I-NEXT: sb a1, 7(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
store i8 %b, i8* %a store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 7 %1 = getelementptr i8, i8* %a, i32 7
store i8 %b, i8* %1 store i8 %b, i8* %1
ret void ret void
} }
define void @sh(i16 *%a, i16 %b) nounwind { define void @sh(i16 *%a, i16 %b) nounwind {
; RV64I-LABEL: sh: ; RV64I-LABEL: sh:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sh a1, 16(a0)
; RV64I-NEXT: sh a1, 0(a0) ; RV64I-NEXT: sh a1, 0(a0)
; RV64I-NEXT: sh a1, 16(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
store i16 %b, i16* %a store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 8 %1 = getelementptr i16, i16* %a, i32 8
store i16 %b, i16* %1 store i16 %b, i16* %1
ret void ret void
} }
define void @sw(i32 *%a, i32 %b) nounwind { define void @sw(i32 *%a, i32 %b) nounwind {
; RV64I-LABEL: sw: ; RV64I-LABEL: sw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sw a1, 36(a0)
; RV64I-NEXT: sw a1, 0(a0) ; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: sw a1, 36(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
store i32 %b, i32* %a store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 9 %1 = getelementptr i32, i32* %a, i32 9
store i32 %b, i32* %1 store i32 %b, i32* %1
ret void ret void
} }
; 64-bit loads and stores ; 64-bit loads and stores
define i64 @ld(i64 *%a) nounwind { define i64 @ld(i64 *%a) nounwind {
; RV64I-LABEL: ld: ; RV64I-LABEL: ld:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld a1, 0(a0) ; RV64I-NEXT: ld a1, 80(a0)
; RV64I-NEXT: ld a0, 80(a0) ; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = getelementptr i64, i64* %a, i32 10 %1 = getelementptr i64, i64* %a, i32 10
%2 = load i64, i64* %1 %2 = load i64, i64* %1
%3 = load volatile i64, i64* %a %3 = load volatile i64, i64* %a
ret i64 %2 ret i64 %2
} }
define void @sd(i64 *%a, i64 %b) nounwind { define void @sd(i64 *%a, i64 %b) nounwind {
; RV64I-LABEL: sd: ; RV64I-LABEL: sd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sd a1, 88(a0)
; RV64I-NEXT: sd a1, 0(a0) ; RV64I-NEXT: sd a1, 0(a0)
; RV64I-NEXT: sd a1, 88(a0)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
store i64 %b, i64* %a store i64 %b, i64* %a
%1 = getelementptr i64, i64* %a, i32 11 %1 = getelementptr i64, i64* %a, i32 11
store i64 %b, i64* %1 store i64 %b, i64* %1
ret void ret void
} }
; Check load and store to an i1 location ; Check load and store to an i1 location
define i64 @load_sext_zext_anyext_i1(i1 *%a) nounwind { define i64 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV64I-LABEL: load_sext_zext_anyext_i1: ; RV64I-LABEL: load_sext_zext_anyext_i1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 0(a0)
; RV64I-NEXT: lbu a1, 1(a0) ; RV64I-NEXT: lbu a1, 1(a0)
; RV64I-NEXT: lbu a0, 2(a0) ; RV64I-NEXT: lbu a2, 2(a0)
; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; sextload i1 ; sextload i1
%1 = getelementptr i1, i1* %a, i32 1 %1 = getelementptr i1, i1* %a, i32 1
%2 = load i1, i1* %1 %2 = load i1, i1* %1
%3 = sext i1 %2 to i64 %3 = sext i1 %2 to i64
; zextload i1 ; zextload i1
%4 = getelementptr i1, i1* %a, i32 2 %4 = getelementptr i1, i1* %a, i32 2
%5 = load i1, i1* %4 %5 = load i1, i1* %4
%6 = zext i1 %5 to i64 %6 = zext i1 %5 to i64
%7 = add i64 %3, %6 %7 = add i64 %3, %6
; extload i1 (anyext). Produced as the load is unused. ; extload i1 (anyext). Produced as the load is unused.
%8 = load volatile i1, i1* %a %8 = load volatile i1, i1* %a
ret i64 %7 ret i64 %7
} }
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind { define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV64I-LABEL: load_sext_zext_anyext_i1_i16: ; RV64I-LABEL: load_sext_zext_anyext_i1_i16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 0(a0)
; RV64I-NEXT: lbu a1, 1(a0) ; RV64I-NEXT: lbu a1, 1(a0)
; RV64I-NEXT: lbu a0, 2(a0) ; RV64I-NEXT: lbu a2, 2(a0)
; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; sextload i1 ; sextload i1
%1 = getelementptr i1, i1* %a, i32 1 %1 = getelementptr i1, i1* %a, i32 1
%2 = load i1, i1* %1 %2 = load i1, i1* %1
%3 = sext i1 %2 to i16 %3 = sext i1 %2 to i16
; zextload i1 ; zextload i1
%4 = getelementptr i1, i1* %a, i32 2 %4 = getelementptr i1, i1* %a, i32 2
%5 = load i1, i1* %4 %5 = load i1, i1* %4
Show All 28 Lines

llvm/test/CodeGen/RISCV/mul.ll

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: mulhs: ; RV64IM-LABEL: mulhs:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = sext i32 %a to i64 %1 = sext i32 %a to i64
%2 = sext i32 %b to i64 %2 = sext i32 %b to i64
%3 = mul i64 %1, %2 %3 = mul i64 %1, %2
%4 = lshr i64 %3, 32 %4 = lshr i64 %3, 32
%5 = trunc i64 %4 to i32 %5 = trunc i64 %4 to i32
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/remat.ll

Show All 31 Lines
; RV32I-NEXT: sw s4, 40(sp) ; RV32I-NEXT: sw s4, 40(sp)
; RV32I-NEXT: sw s5, 36(sp) ; RV32I-NEXT: sw s5, 36(sp)
; RV32I-NEXT: sw s6, 32(sp) ; RV32I-NEXT: sw s6, 32(sp)
; RV32I-NEXT: sw s7, 28(sp) ; RV32I-NEXT: sw s7, 28(sp)
; RV32I-NEXT: sw s8, 24(sp) ; RV32I-NEXT: sw s8, 24(sp)
; RV32I-NEXT: sw s9, 20(sp) ; RV32I-NEXT: sw s9, 20(sp)
; RV32I-NEXT: sw s10, 16(sp) ; RV32I-NEXT: sw s10, 16(sp)
; RV32I-NEXT: sw s11, 12(sp) ; RV32I-NEXT: sw s11, 12(sp)
; RV32I-NEXT: lui s9, %hi(a) ; RV32I-NEXT: lui s6, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s9) ; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: beqz a0, .LBB0_11 ; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader ; RV32I-NEXT: # %bb.1: # %for.body.preheader
; RV32I-NEXT: lui s2, %hi(l) ; RV32I-NEXT: lui s2, %hi(l)
; RV32I-NEXT: lui s3, %hi(k) ; RV32I-NEXT: lui s3, %hi(k)
; RV32I-NEXT: lui s4, %hi(j) ; RV32I-NEXT: lui s4, %hi(j)
; RV32I-NEXT: lui s6, %hi(i) ; RV32I-NEXT: lui s5, %hi(i)
; RV32I-NEXT: lui s5, %hi(h) ; RV32I-NEXT: lui s1, %hi(d)
; RV32I-NEXT: lui s7, %hi(g) ; RV32I-NEXT: lui s0, %hi(e)
; RV32I-NEXT: lui s8, %hi(f) ; RV32I-NEXT: lui s7, %hi(f)
; RV32I-NEXT: lui s1, %hi(e) ; RV32I-NEXT: lui s8, %hi(g)
; RV32I-NEXT: lui s0, %hi(d) ; RV32I-NEXT: lui s9, %hi(h)
; RV32I-NEXT: lui s10, %hi(c) ; RV32I-NEXT: lui s10, %hi(c)
; RV32I-NEXT: lui s11, %hi(b) ; RV32I-NEXT: lui s11, %hi(b)
; RV32I-NEXT: lw a1, %lo(l)(s2) ; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: bnez a1, .LBB0_4 ; RV32I-NEXT: bnez a1, .LBB0_4
; RV32I-NEXT: j .LBB0_5 ; RV32I-NEXT: j .LBB0_5
; RV32I-NEXT: .LBB0_2: # %for.inc ; RV32I-NEXT: .LBB0_2: # %for.inc
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a0, %lo(a)(s9) ; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: sw a0, %lo(a)(s9) ; RV32I-NEXT: sw a0, %lo(a)(s6)
; RV32I-NEXT: beqz a0, .LBB0_11 ; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.3: # %for.body ; RV32I-NEXT: # %bb.3: # %for.body
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a1, %lo(l)(s2) ; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: beqz a1, .LBB0_5 ; RV32I-NEXT: beqz a1, .LBB0_5
; RV32I-NEXT: .LBB0_4: # %if.then ; RV32I-NEXT: .LBB0_4: # %if.then
; RV32I-NEXT: lw a4, %lo(e)(s1)
; RV32I-NEXT: lw a3, %lo(d)(s0)
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(b)(s11) ; RV32I-NEXT: lw a1, %lo(b)(s11)
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a4, %lo(e)(s0)
; RV32I-NEXT: addi a5, zero, 32 ; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_5: # %if.end ; RV32I-NEXT: .LBB0_5: # %if.end
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: lw a0, %lo(k)(s3) ; RV32I-NEXT: lw a0, %lo(k)(s3)
; RV32I-NEXT: beqz a0, .LBB0_7 ; RV32I-NEXT: beqz a0, .LBB0_7
; RV32I-NEXT: # %bb.6: # %if.then3 ; RV32I-NEXT: # %bb.6: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a4, %lo(f)(s8)
; RV32I-NEXT: lw a3, %lo(e)(s1)
; RV32I-NEXT: lw a2, %lo(d)(s0)
; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a0, %lo(b)(s11) ; RV32I-NEXT: lw a0, %lo(b)(s11)
; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a3, %lo(e)(s0)
; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: addi a5, zero, 64 ; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_7: # %if.end5 ; RV32I-NEXT: .LBB0_7: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a0, %lo(j)(s4) ; RV32I-NEXT: lw a0, %lo(j)(s4)
; RV32I-NEXT: beqz a0, .LBB0_9 ; RV32I-NEXT: beqz a0, .LBB0_9
; RV32I-NEXT: # %bb.8: # %if.then7 ; RV32I-NEXT: # %bb.8: # %if.then7
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a4, %lo(g)(s7)
; RV32I-NEXT: lw a3, %lo(f)(s8)
; RV32I-NEXT: lw a2, %lo(e)(s1)
; RV32I-NEXT: lw a1, %lo(d)(s0)
; RV32I-NEXT: lw a0, %lo(c)(s10) ; RV32I-NEXT: lw a0, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1)
; RV32I-NEXT: lw a2, %lo(e)(s0)
; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: addi a5, zero, 32 ; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_9: # %if.end9 ; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s6) ; RV32I-NEXT: lw a0, %lo(i)(s5)
; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.10: # %if.then11 ; RV32I-NEXT: # %bb.10: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a4, %lo(h)(s5) ; RV32I-NEXT: lw a0, %lo(d)(s1)
; RV32I-NEXT: lw a3, %lo(g)(s7) ; RV32I-NEXT: lw a1, %lo(e)(s0)
; RV32I-NEXT: lw a2, %lo(f)(s8) ; RV32I-NEXT: lw a2, %lo(f)(s7)
; RV32I-NEXT: lw a1, %lo(e)(s1) ; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a0, %lo(d)(s0) ; RV32I-NEXT: lw a4, %lo(h)(s9)
; RV32I-NEXT: addi a5, zero, 32 ; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo
; RV32I-NEXT: j .LBB0_2 ; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end ; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1 ; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: lw s11, 12(sp) ; RV32I-NEXT: lw s11, 12(sp)
; RV32I-NEXT: lw s10, 16(sp) ; RV32I-NEXT: lw s10, 16(sp)
; RV32I-NEXT: lw s9, 20(sp) ; RV32I-NEXT: lw s9, 20(sp)
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64f-float-convert.ll

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
ret i32 %2 ret i32 %2
} }
define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind { define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
; RV64IF-LABEL: bcvt_i64_to_f32_via_i32: ; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = trunc i64 %a to i32 %1 = trunc i64 %a to i32
%2 = trunc i64 %b to i32 %2 = trunc i64 %b to i32
%3 = bitcast i32 %1 to float %3 = bitcast i32 %1 to float
%4 = bitcast i32 %2 to float %4 = bitcast i32 %2 to float
%5 = fadd float %3, %4 %5 = fadd float %3, %4
ret float %5 ret float %5
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64i-complex-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
; The complex floating value will be returned by a single register for LP64 ABI. ; The complex floating value will be returned by a single register for LP64 ABI.
; The test case check that the real part returned by __addsf3 will be ; The test case check that the real part returned by __addsf3 will be
; cleared upper bits by shifts to avoid corrupting the imaginary part. ; cleared upper bits by shifts to avoid corrupting the imaginary part.
define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind { define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind {
; CHECK-LABEL: complex_float_add: ; CHECK-LABEL: complex_float_add:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) ; CHECK-NEXT: sd ra, 24(sp)
; CHECK-NEXT: sd s0, 16(sp) ; CHECK-NEXT: sd s0, 16(sp)
; CHECK-NEXT: sd s1, 8(sp) ; CHECK-NEXT: sd s1, 8(sp)
; CHECK-NEXT: sd s2, 0(sp) ; CHECK-NEXT: sd s2, 0(sp)
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: srli s2, a0, 32
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: srli s1, a1, 32
; CHECK-NEXT: call __addsf3 ; CHECK-NEXT: call __addsf3
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: srli a0, s1, 32 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: srli a1, s0, 32 ; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __addsf3 ; CHECK-NEXT: call __addsf3
; CHECK-NEXT: slli a1, s2, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: slli a0, a0, 32 ; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: slli a1, s0, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: or a0, a0, a1 ; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ld s2, 0(sp) ; CHECK-NEXT: ld s2, 0(sp)
; CHECK-NEXT: ld s1, 8(sp) ; CHECK-NEXT: ld s1, 8(sp)
; CHECK-NEXT: ld s0, 16(sp) ; CHECK-NEXT: ld s0, 16(sp)
; CHECK-NEXT: ld ra, 24(sp) ; CHECK-NEXT: ld ra, 24(sp)
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 20 Lines

llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind { define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
; CHECK-LABEL: addw: ; CHECK-LABEL: addw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bge a0, a1, .LBB0_2 ; CHECK-NEXT: bge a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0 ; CHECK-NEXT: not a2, a0
; CHECK-NEXT: add a2, a2, a1 ; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: mul a3, a2, a3
; CHECK-NEXT: slli a2, a2, 32
; CHECK-NEXT: srli a2, a2, 32
; CHECK-NEXT: sub a1, a1, a0 ; CHECK-NEXT: sub a1, a1, a0
; CHECK-NEXT: addi a1, a1, -2 ; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32 ; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: slli a3, a2, 32 ; CHECK-NEXT: mul a1, a2, a1
; CHECK-NEXT: srli a3, a3, 32
; CHECK-NEXT: mul a1, a3, a1
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: srli a1, a1, 1 ; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: add a0, a3, a0
; CHECK-NEXT: addw a0, a0, a1 ; CHECK-NEXT: addw a0, a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: mv a0, zero ; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp6 = icmp slt i32 %s, %n %cmp6 = icmp slt i32 %s, %n
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
Show All 19 Linesfor.cond.cleanup: ; preds = %for.body.preheader, %entry
ret i32 %sum.0.lcssa ret i32 %sum.0.lcssa
} }
define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind { define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
; CHECK-LABEL: subw: ; CHECK-LABEL: subw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bge a0, a1, .LBB1_2 ; CHECK-NEXT: bge a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: sub a2, a1, a0 ; CHECK-NEXT: not a2, a0
; CHECK-NEXT: addi a2, a2, -2 ; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: slli a2, a2, 32 ; CHECK-NEXT: mul a2, a3, a2
; CHECK-NEXT: srli a2, a2, 32 ; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: not a3, a0 ; CHECK-NEXT: srli a3, a3, 32
; CHECK-NEXT: add a1, a3, a1 ; CHECK-NEXT: sub a1, a1, a0
; CHECK-NEXT: slli a4, a1, 32 ; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: srli a4, a4, 32 ; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: mul a2, a4, a2 ; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a3, a1
; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: srli a1, a2, 1 ; CHECK-NEXT: sub a0, a2, a0
; CHECK-NEXT: subw a0, a0, a1 ; CHECK-NEXT: subw a0, a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: mv a0, zero ; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp6 = icmp slt i32 %s, %n %cmp6 = icmp slt i32 %s, %n
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
Show All 21 Lines

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

Show All 34 Linesentry:
%cond = select i1 %cmp, i64 %b, i64 %c %cond = select i1 %cmp, i64 %b, i64 %c
ret i64 %cond ret i64 %cond
} }
define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind { define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV32I-LABEL: cmovcc128: ; RV32I-LABEL: cmovcc128:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: xori a1, a1, 123 ; RV32I-NEXT: xori a1, a1, 123
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a2, a1, a2
; RV32I-NEXT: beqz a1, .LBB1_2 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: beqz a2, .LBB1_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a4
; RV32I-NEXT: .LBB1_2: # %entry
; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: beqz a2, .LBB1_6
; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a1, a4, 4 ; RV32I-NEXT: addi a1, a4, 4
; RV32I-NEXT: addi a2, a4, 8 ; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: addi a5, a4, 12 ; RV32I-NEXT: bnez a2, .LBB1_7
; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: j .LBB1_3 ; RV32I-NEXT: addi a1, a3, 8
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: bnez a2, .LBB1_8
; RV32I-NEXT: .LBB1_5:
; RV32I-NEXT: addi a2, a3, 12
; RV32I-NEXT: j .LBB1_9
; RV32I-NEXT: .LBB1_6:
; RV32I-NEXT: addi a1, a3, 4 ; RV32I-NEXT: addi a1, a3, 4
; RV32I-NEXT: addi a2, a3, 8 ; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: addi a5, a3, 12 ; RV32I-NEXT: beqz a2, .LBB1_4
; RV32I-NEXT: .LBB1_3: # %entry ; RV32I-NEXT: .LBB1_7: # %entry
; RV32I-NEXT: lw a4, 0(a5) ; RV32I-NEXT: addi a1, a4, 8
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 4(a0) ; RV32I-NEXT: beqz a2, .LBB1_5
; RV32I-NEXT: lw a1, 0(a3) ; RV32I-NEXT: .LBB1_8: # %entry
; RV32I-NEXT: sw a1, 0(a0) ; RV32I-NEXT: addi a2, a4, 12
; RV32I-NEXT: .LBB1_9: # %entry
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: cmovcc128: ; RV64I-LABEL: cmovcc128:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi a5, zero, 123 ; RV64I-NEXT: addi a5, zero, 123
; RV64I-NEXT: beq a0, a5, .LBB1_2 ; RV64I-NEXT: beq a0, a5, .LBB1_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a3 ; RV64I-NEXT: mv a1, a3
; RV64I-NEXT: mv a2, a4 ; RV64I-NEXT: mv a2, a4
; RV64I-NEXT: .LBB1_2: # %entry ; RV64I-NEXT: .LBB1_2: # %entry
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%cmp = icmp eq i64 %a, 123 %cmp = icmp eq i64 %a, 123
%cond = select i1 %cmp, i128 %b, i128 %c %cond = select i1 %cmp, i128 %b, i128 %c
ret i128 %cond ret i128 %cond
} }
define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind { define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov64: ; RV32I-LABEL: cmov64:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a5, a0, 1
; RV32I-NEXT: bnez a0, .LBB2_2 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a5, .LBB2_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: .LBB2_2: # %entry ; RV32I-NEXT: .LBB2_2: # %entry
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: cmov64: ; RV64I-LABEL: cmov64:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a3, a0, 1
; RV64I-NEXT: bnez a0, .LBB2_2 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: bnez a3, .LBB2_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB2_2: # %entry ; RV64I-NEXT: .LBB2_2: # %entry
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%cond = select i1 %a, i64 %b, i64 %c %cond = select i1 %a, i64 %b, i64 %c
ret i64 %cond ret i64 %cond
} }
define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind { define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV32I-LABEL: cmov128: ; RV32I-LABEL: cmov128:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a1, a1, 1 ; RV32I-NEXT: andi a4, a1, 1
; RV32I-NEXT: bnez a1, .LBB3_2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: bnez a4, .LBB3_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB3_2: # %entry
; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: bnez a4, .LBB3_6
; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a1, a3, 4 ; RV32I-NEXT: addi a1, a3, 4
; RV32I-NEXT: addi a4, a3, 8 ; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: addi a5, a3, 12 ; RV32I-NEXT: beqz a4, .LBB3_7
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: .LBB3_4:
; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: addi a1, a2, 8
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: beqz a4, .LBB3_8
; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: addi a2, a2, 12
; RV32I-NEXT: j .LBB3_9
; RV32I-NEXT: .LBB3_6:
; RV32I-NEXT: addi a1, a2, 4 ; RV32I-NEXT: addi a1, a2, 4
; RV32I-NEXT: addi a4, a2, 8 ; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: addi a5, a2, 12 ; RV32I-NEXT: bnez a4, .LBB3_4
; RV32I-NEXT: .LBB3_3: # %entry ; RV32I-NEXT: .LBB3_7: # %entry
; RV32I-NEXT: lw a3, 0(a5) ; RV32I-NEXT: addi a1, a3, 8
; RV32I-NEXT: sw a3, 12(a0)
; RV32I-NEXT: lw a3, 0(a4)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 4(a0) ; RV32I-NEXT: bnez a4, .LBB3_5
; RV32I-NEXT: lw a1, 0(a2) ; RV32I-NEXT: .LBB3_8: # %entry
; RV32I-NEXT: sw a1, 0(a0) ; RV32I-NEXT: addi a2, a3, 12
; RV32I-NEXT: .LBB3_9: # %entry
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: cmov128: ; RV64I-LABEL: cmov128:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a5, a0, 1
; RV64I-NEXT: bnez a0, .LBB3_2 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: bnez a5, .LBB3_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: mv a2, a4 ; RV64I-NEXT: mv a2, a4
; RV64I-NEXT: .LBB3_2: # %entry ; RV64I-NEXT: .LBB3_2: # %entry
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%cond = select i1 %a, i128 %b, i128 %c %cond = select i1 %a, i128 %b, i128 %c
ret i128 %cond ret i128 %cond
} }
define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind { define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Linesentry:
ret i32 %ret ret i32 %ret
} }
; Check that selects with different conditions aren't incorrectly optimized. ; Check that selects with different conditions aren't incorrectly optimized.
define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind { define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
; RV32I-LABEL: cmovdiffcc: ; RV32I-LABEL: cmovdiffcc:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: andi a1, a1, 1 ; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: beqz a1, .LBB7_3 ; RV32I-NEXT: beqz a0, .LBB7_3
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: beqz a1, .LBB7_4
; RV32I-NEXT: beqz a0, .LBB7_4
; RV32I-NEXT: .LBB7_2: # %entry ; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: add a0, a2, a4 ; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_3: # %entry ; RV32I-NEXT: .LBB7_3: # %entry
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bnez a1, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: add a0, a2, a4 ; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: cmovdiffcc: ; RV64I-LABEL: cmovdiffcc:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: andi a1, a1, 1 ; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: beqz a1, .LBB7_3 ; RV64I-NEXT: beqz a0, .LBB7_3
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: beqz a1, .LBB7_4
; RV64I-NEXT: beqz a0, .LBB7_4
; RV64I-NEXT: .LBB7_2: # %entry ; RV64I-NEXT: .LBB7_2: # %entry
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_3: # %entry ; RV64I-NEXT: .LBB7_3: # %entry
; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bnez a1, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%cond1 = select i1 %a, i32 %c, i32 %d %cond1 = select i1 %a, i32 %c, i32 %d
%cond2 = select i1 %b, i32 %e, i32 %f %cond2 = select i1 %b, i32 %e, i32 %f
%ret = add i32 %cond1, %cond2 %ret = add i32 %cond1, %cond2
ret i32 %ret ret i32 %ret
} }

llvm/test/CodeGen/RISCV/setcc-logic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: and_icmp_eq: ; RV32I-LABEL: and_icmp_eq:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: xor a1, a2, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: and_icmp_eq: ; RV64I-LABEL: and_icmp_eq:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: xor a1, a2, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%cmp1 = icmp eq i32 %a, %b %cmp1 = icmp eq i32 %a, %b
%cmp2 = icmp eq i32 %c, %d %cmp2 = icmp eq i32 %c, %d
%and = and i1 %cmp1, %cmp2 %and = and i1 %cmp1, %cmp2
ret i1 %and ret i1 %and
} }
define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: or_icmp_ne: ; RV32I-LABEL: or_icmp_ne:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: xor a1, a2, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: or_icmp_ne: ; RV64I-LABEL: or_icmp_ne:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: xor a1, a2, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%cmp1 = icmp ne i32 %a, %b %cmp1 = icmp ne i32 %a, %b
%cmp2 = icmp ne i32 %c, %d %cmp2 = icmp ne i32 %c, %d
%or = or i1 %cmp1, %cmp2 %or = or i1 %cmp1, %cmp2
ret i1 %or ret i1 %or
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%b = icmp ne i32 %x, 60 %b = icmp ne i32 %x, 60
%r = and i1 %a, %b %r = and i1 %a, %b
ret i1 %r ret i1 %r
} }
define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind { define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
; RV32I-LABEL: and_icmps_const_not1bit_diff: ; RV32I-LABEL: and_icmps_const_not1bit_diff:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xori a1, a0, 92 ; RV32I-NEXT: xori a1, a0, 44
; RV32I-NEXT: snez a1, a1 ; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: xori a0, a0, 44 ; RV32I-NEXT: xori a0, a0, 92
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: and_icmps_const_not1bit_diff: ; RV64I-LABEL: and_icmps_const_not1bit_diff:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: xori a1, a0, 92 ; RV64I-NEXT: xori a1, a0, 44
; RV64I-NEXT: snez a1, a1 ; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: xori a0, a0, 44 ; RV64I-NEXT: xori a0, a0, 92
; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a = icmp ne i32 %x, 44 %a = icmp ne i32 %x, 44
%b = icmp ne i32 %x, 92 %b = icmp ne i32 %x, 92
%r = and i1 %a, %b %r = and i1 %a, %b
ret i1 %r ret i1 %r
} }

llvm/test/CodeGen/RISCV/shifts.ll

Show All 11 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB0_2 ; RV32I-NEXT: bltz a3, .LBB0_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a0, a1, a3 ; RV32I-NEXT: srl a0, a1, a3
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31 ; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2 ; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1 ; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3 ; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: srl a1, a1, a2 ; RV32I-NEXT: srl a2, a1, a2
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: lshr64: ; RV64I-LABEL: lshr64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = lshr i64 %a, %b %1 = lshr i64 %a, %b
ret i64 %1 ret i64 %1
Show All 22 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB2_2 ; RV32I-NEXT: bltz a3, .LBB2_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sra a0, a1, a3 ; RV32I-NEXT: sra a0, a1, a3
; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31 ; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2 ; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1 ; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3 ; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2 ; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: ashr64: ; RV64I-LABEL: ashr64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1 ; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
Show All 24 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB4_2 ; RV32I-NEXT: bltz a3, .LBB4_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a1, a0, a3 ; RV32I-NEXT: sll a1, a0, a3
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: addi a3, zero, 31 ; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2 ; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: srli a4, a0, 1 ; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3 ; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sll a0, a0, a2 ; RV32I-NEXT: sll a2, a0, a2
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: shl64: ; RV64I-LABEL: shl64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = shl i64 %a, %b %1 = shl i64 %a, %b
ret i64 %1 ret i64 %1
Show All 18 Lines
} }
define i128 @lshr128(i128 %a, i128 %b) nounwind { define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128: ; RV32I-LABEL: lshr128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a0, 12(a1)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 8(a1)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __lshrti3 ; RV32I-NEXT: call __lshrti3
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0) ; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 32(sp) ; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a0, 8(s0) ; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: lw a0, 28(sp) ; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: lshr128: ; RV64I-LABEL: lshr128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB6_2 ; RV64I-NEXT: bltz a3, .LBB6_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srl a0, a1, a3 ; RV64I-NEXT: srl a0, a1, a3
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: addi a3, zero, 63 ; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2 ; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1 ; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3 ; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srl a1, a1, a2 ; RV64I-NEXT: srl a2, a1, a2
; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = lshr i128 %a, %b %1 = lshr i128 %a, %b
ret i128 %1 ret i128 %1
} }
define i128 @ashr128(i128 %a, i128 %b) nounwind { define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128: ; RV32I-LABEL: ashr128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a0, 12(a1)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 8(a1)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashrti3 ; RV32I-NEXT: call __ashrti3
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0) ; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 32(sp) ; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a0, 8(s0) ; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: lw a0, 28(sp) ; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: ashr128: ; RV64I-LABEL: ashr128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB7_2 ; RV64I-NEXT: bltz a3, .LBB7_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sra a0, a1, a3 ; RV64I-NEXT: sra a0, a1, a3
; RV64I-NEXT: srai a1, a1, 63 ; RV64I-NEXT: srai a1, a1, 63
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2: ; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: addi a3, zero, 63 ; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2 ; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1 ; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3 ; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: sra a1, a1, a2 ; RV64I-NEXT: sra a1, a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = ashr i128 %a, %b %1 = ashr i128 %a, %b
ret i128 %1 ret i128 %1
} }
define i128 @shl128(i128 %a, i128 %b) nounwind { define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: shl128: ; RV32I-LABEL: shl128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a0, 12(a1)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 8(a1)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashlti3 ; RV32I-NEXT: call __ashlti3
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0) ; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 32(sp) ; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a0, 8(s0) ; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: lw a0, 28(sp) ; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: shl128: ; RV64I-LABEL: shl128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB8_2 ; RV64I-NEXT: bltz a3, .LBB8_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sll a1, a0, a3 ; RV64I-NEXT: sll a1, a0, a3
; RV64I-NEXT: mv a0, zero ; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: addi a3, zero, 63 ; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2 ; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: srli a4, a0, 1 ; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: srl a3, a4, a3 ; RV64I-NEXT: srl a3, a4, a3
; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: or a1, a1, a3 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: sll a0, a0, a2 ; RV64I-NEXT: sll a2, a0, a2
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = shl i128 %a, %b %1 = shl i128 %a, %b
ret i128 %1 ret i128 %1
} }

llvm/test/CodeGen/RISCV/split-offsets.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; Check that memory accesses to array elements with large offsets have those ; Check that memory accesses to array elements with large offsets have those
; offsets split into a base offset, plus a smaller offset that is folded into ; offsets split into a base offset, plus a smaller offset that is folded into
; the memory operation. We should also only compute that base offset once, ; the memory operation. We should also only compute that base offset once,
; since it can be shared for all memory operations in this test. ; since it can be shared for all memory operations in this test.
define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) { define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV32I-LABEL: test1: ; RV32I-LABEL: test1:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: lui a2, 20 ; RV32I-NEXT: lui a2, 20
; RV32I-NEXT: addi a2, a2, -1920 ; RV32I-NEXT: addi a2, a2, -1920
; RV32I-NEXT: lw a0, 0(a0) ; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: addi a3, zero, 1 ; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: sw a3, 4(a0) ; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: sw a3, 0(a1)
; RV32I-NEXT: sw a4, 0(a0) ; RV32I-NEXT: sw a2, 4(a1)
; RV32I-NEXT: add a0, a1, a2
; RV32I-NEXT: sw a4, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test1: ; RV64I-LABEL: test1:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: lui a2, 20 ; RV64I-NEXT: lui a2, 20
; RV64I-NEXT: addiw a2, a2, -1920 ; RV64I-NEXT: addiw a2, a2, -1920
; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: sw a2, 0(a0)
; RV64I-NEXT: addi a3, zero, 1 ; RV64I-NEXT: addi a3, zero, 1
; RV64I-NEXT: sw a3, 4(a0) ; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: sw a3, 0(a1)
; RV64I-NEXT: sw a4, 0(a0) ; RV64I-NEXT: sw a2, 4(a1)
; RV64I-NEXT: add a0, a1, a2
; RV64I-NEXT: sw a4, 4(a0)
; RV64I-NEXT: sw a3, 0(a0)
; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%s = load [65536 x i32]*, [65536 x i32]** %sp %s = load [65536 x i32]*, [65536 x i32]** %sp
%gep0 = getelementptr [65536 x i32], [65536 x i32]* %s, i64 0, i32 20000 %gep0 = getelementptr [65536 x i32], [65536 x i32]* %s, i64 0, i32 20000
%gep1 = getelementptr [65536 x i32], [65536 x i32]* %s, i64 0, i32 20001 %gep1 = getelementptr [65536 x i32], [65536 x i32]* %s, i64 0, i32 20001
%gep2 = getelementptr [65536 x i32], [65536 x i32]* %t, i64 0, i32 20000 %gep2 = getelementptr [65536 x i32], [65536 x i32]* %t, i64 0, i32 20000
%gep3 = getelementptr [65536 x i32], [65536 x i32]* %t, i64 0, i32 20001 %gep3 = getelementptr [65536 x i32], [65536 x i32]* %t, i64 0, i32 20001
store i32 2, i32* %gep0 store i32 2, i32* %gep0
store i32 1, i32* %gep1 store i32 1, i32* %gep1
store i32 1, i32* %gep2 store i32 1, i32* %gep2
store i32 2, i32* %gep3 store i32 2, i32* %gep3
ret void ret void
} }
; Ditto. Check it when the GEPs are not in the entry block. ; Ditto. Check it when the GEPs are not in the entry block.
define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) { define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV32I-LABEL: test2: ; RV32I-LABEL: test2:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a3, 20
; RV32I-NEXT: addi a3, a3, -1920
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: add a0, a0, a3
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: lui a0, 20
; RV32I-NEXT: addi a5, a0, -1920
; RV32I-NEXT: add a0, a1, a5
; RV32I-NEXT: add a1, a4, a5
; RV32I-NEXT: bge a3, a2, .LBB1_2 ; RV32I-NEXT: bge a3, a2, .LBB1_2
; RV32I-NEXT: .LBB1_1: # %while_body ; RV32I-NEXT: .LBB1_1: # %while_body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: addi a4, a3, 1 ; RV32I-NEXT: addi a4, a3, 1
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a1)
; RV32I-NEXT: sw a4, 0(a1) ; RV32I-NEXT: sw a4, 0(a1)
; RV32I-NEXT: sw a3, 4(a1)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: blt a3, a2, .LBB1_1 ; RV32I-NEXT: blt a3, a2, .LBB1_1
; RV32I-NEXT: .LBB1_2: # %while_end ; RV32I-NEXT: .LBB1_2: # %while_end
; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test2: ; RV64I-LABEL: test2:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: lui a3, 20
; RV64I-NEXT: addiw a3, a3, -1920
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: add a0, a0, a3
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: sext.w a2, a2
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: ld a4, 0(a0)
; RV64I-NEXT: lui a0, 20
; RV64I-NEXT: addiw a5, a0, -1920
; RV64I-NEXT: add a0, a1, a5
; RV64I-NEXT: add a1, a4, a5
; RV64I-NEXT: sext.w a2, a2
; RV64I-NEXT: sext.w a4, a3 ; RV64I-NEXT: sext.w a4, a3
; RV64I-NEXT: bge a4, a2, .LBB1_2 ; RV64I-NEXT: bge a4, a2, .LBB1_2
; RV64I-NEXT: .LBB1_1: # %while_body ; RV64I-NEXT: .LBB1_1: # %while_body
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: addi a4, a3, 1 ; RV64I-NEXT: addi a4, a3, 1
; RV64I-NEXT: sw a4, 0(a0)
; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: sw a4, 0(a1) ; RV64I-NEXT: sw a4, 0(a1)
; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: sw a4, 0(a0)
; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: mv a3, a4 ; RV64I-NEXT: mv a3, a4
; RV64I-NEXT: sext.w a4, a3 ; RV64I-NEXT: sext.w a4, a3
; RV64I-NEXT: blt a4, a2, .LBB1_1 ; RV64I-NEXT: blt a4, a2, .LBB1_1
; RV64I-NEXT: .LBB1_2: # %while_end ; RV64I-NEXT: .LBB1_2: # %while_end
; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%s = load [65536 x i32]*, [65536 x i32]** %sp %s = load [65536 x i32]*, [65536 x i32]** %sp
Show All 21 Lines

llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 { define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-LABEL: muloti_test: ; RISCV32-LABEL: muloti_test:
; RISCV32: # %bb.0: # %start ; RISCV32: # %bb.0: # %start
; RISCV32-NEXT: addi sp, sp, -80 ; RISCV32-NEXT: addi sp, sp, -96
; RISCV32-NEXT: sw ra, 76(sp) ; RISCV32-NEXT: sw ra, 92(sp)
; RISCV32-NEXT: sw s0, 72(sp) ; RISCV32-NEXT: sw s0, 88(sp)
; RISCV32-NEXT: sw s1, 68(sp) ; RISCV32-NEXT: sw s1, 84(sp)
; RISCV32-NEXT: sw s2, 64(sp) ; RISCV32-NEXT: sw s2, 80(sp)
; RISCV32-NEXT: sw s3, 60(sp) ; RISCV32-NEXT: sw s3, 76(sp)
; RISCV32-NEXT: sw s4, 56(sp) ; RISCV32-NEXT: sw s4, 72(sp)
; RISCV32-NEXT: sw s5, 52(sp) ; RISCV32-NEXT: sw s5, 68(sp)
; RISCV32-NEXT: sw s6, 48(sp) ; RISCV32-NEXT: sw s6, 64(sp)
; RISCV32-NEXT: mv s1, a2 ; RISCV32-NEXT: sw s7, 60(sp)
; RISCV32-NEXT: mv s0, a1 ; RISCV32-NEXT: sw s8, 56(sp)
; RISCV32-NEXT: mv s2, a0 ; RISCV32-NEXT: lw s2, 12(a1)
; RISCV32-NEXT: sw zero, 12(sp) ; RISCV32-NEXT: lw s6, 8(a1)
; RISCV32-NEXT: sw zero, 8(sp) ; RISCV32-NEXT: lw s3, 12(a2)
; RISCV32-NEXT: sw zero, 28(sp) ; RISCV32-NEXT: lw s7, 8(a2)
; RISCV32-NEXT: sw zero, 24(sp) ; RISCV32-NEXT: lw s0, 0(a1)
; RISCV32-NEXT: lw s3, 4(a2) ; RISCV32-NEXT: lw s8, 4(a1)
; RISCV32-NEXT: sw s3, 4(sp) ; RISCV32-NEXT: lw s1, 0(a2)
; RISCV32-NEXT: lw s5, 0(a2) ; RISCV32-NEXT: lw s5, 4(a2)
; RISCV32-NEXT: sw s5, 0(sp) ; RISCV32-NEXT: mv s4, a0
; RISCV32-NEXT: lw s4, 4(a1) ; RISCV32-NEXT: sw zero, 20(sp)
; RISCV32-NEXT: sw s4, 20(sp) ; RISCV32-NEXT: sw zero, 16(sp)
; RISCV32-NEXT: lw s6, 0(a1) ; RISCV32-NEXT: sw zero, 36(sp)
; RISCV32-NEXT: sw s6, 16(sp) ; RISCV32-NEXT: sw zero, 32(sp)
; RISCV32-NEXT: addi a0, sp, 32 ; RISCV32-NEXT: sw s5, 12(sp)
; RISCV32-NEXT: addi a1, sp, 16 ; RISCV32-NEXT: sw s1, 8(sp)
; RISCV32-NEXT: mv a2, sp ; RISCV32-NEXT: sw s8, 28(sp)
; RISCV32-NEXT: addi a0, sp, 40
; RISCV32-NEXT: addi a1, sp, 24
; RISCV32-NEXT: addi a2, sp, 8
; RISCV32-NEXT: sw s0, 24(sp)
; RISCV32-NEXT: call __multi3 ; RISCV32-NEXT: call __multi3
; RISCV32-NEXT: lw a0, 12(s0) ; RISCV32-NEXT: mul a0, s8, s7
; RISCV32-NEXT: lw a1, 8(s0) ; RISCV32-NEXT: mul a1, s3, s0
; RISCV32-NEXT: mul a2, s3, a1 ; RISCV32-NEXT: add a0, a1, a0
; RISCV32-NEXT: mul a3, a0, s5 ; RISCV32-NEXT: mulhu a5, s7, s0
; RISCV32-NEXT: add a4, a3, a2 ; RISCV32-NEXT: add a0, a5, a0
; RISCV32-NEXT: lw a2, 12(s1) ; RISCV32-NEXT: mul a1, s5, s6
; RISCV32-NEXT: lw a3, 8(s1) ; RISCV32-NEXT: mul a2, s2, s1
; RISCV32-NEXT: mul a5, s4, a3 ; RISCV32-NEXT: add a1, a2, a1
; RISCV32-NEXT: mul s1, a2, s6 ; RISCV32-NEXT: mulhu t0, s6, s1
; RISCV32-NEXT: add a5, s1, a5 ; RISCV32-NEXT: add t1, t0, a1
; RISCV32-NEXT: mul s1, a3, s6 ; RISCV32-NEXT: add a6, t1, a0
; RISCV32-NEXT: mul s0, a1, s5 ; RISCV32-NEXT: mul a1, s7, s0
; RISCV32-NEXT: add s1, s0, s1 ; RISCV32-NEXT: mul a3, s6, s1
; RISCV32-NEXT: sltu s0, s1, s0 ; RISCV32-NEXT: add a4, a3, a1
; RISCV32-NEXT: mulhu a6, a3, s6 ; RISCV32-NEXT: lw a1, 52(sp)
; RISCV32-NEXT: add t1, a6, a5 ; RISCV32-NEXT: lw a2, 48(sp)
; RISCV32-NEXT: mulhu t2, a1, s5 ; RISCV32-NEXT: sltu a3, a4, a3
; RISCV32-NEXT: add t3, t2, a4 ; RISCV32-NEXT: add a3, a6, a3
; RISCV32-NEXT: add a5, t3, t1 ; RISCV32-NEXT: add a3, a1, a3
; RISCV32-NEXT: add a5, a5, s0 ; RISCV32-NEXT: add a6, a2, a4
; RISCV32-NEXT: lw s0, 44(sp) ; RISCV32-NEXT: sltu a2, a6, a2
; RISCV32-NEXT: add a5, s0, a5 ; RISCV32-NEXT: add a7, a3, a2
; RISCV32-NEXT: lw a4, 40(sp) ; RISCV32-NEXT: beq a7, a1, .LBB0_2
; RISCV32-NEXT: add a7, a4, s1
; RISCV32-NEXT: sltu t0, a7, a4
; RISCV32-NEXT: add a5, a5, t0
; RISCV32-NEXT: beq a5, s0, .LBB0_2
; RISCV32-NEXT: # %bb.1: # %start ; RISCV32-NEXT: # %bb.1: # %start
; RISCV32-NEXT: sltu t0, a5, s0 ; RISCV32-NEXT: sltu a2, a7, a1
; RISCV32-NEXT: .LBB0_2: # %start ; RISCV32-NEXT: .LBB0_2: # %start
; RISCV32-NEXT: snez a4, s3 ; RISCV32-NEXT: sltu a0, a0, a5
; RISCV32-NEXT: snez s1, a0 ; RISCV32-NEXT: snez a1, s8
; RISCV32-NEXT: and a4, s1, a4 ; RISCV32-NEXT: snez a3, s3
; RISCV32-NEXT: snez s1, s4 ; RISCV32-NEXT: and a1, a3, a1
; RISCV32-NEXT: snez s0, a2 ; RISCV32-NEXT: mulhu a3, s3, s0
; RISCV32-NEXT: and s1, s0, s1 ; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: mulhu s0, a2, s6 ; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: snez s0, s0 ; RISCV32-NEXT: mulhu a3, s8, s7
; RISCV32-NEXT: or s1, s1, s0 ; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: mulhu s0, a0, s5 ; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: snez s0, s0 ; RISCV32-NEXT: or a0, a1, a0
; RISCV32-NEXT: or a4, a4, s0 ; RISCV32-NEXT: sltu a1, t1, t0
; RISCV32-NEXT: sltu t2, t3, t2 ; RISCV32-NEXT: snez a3, s5
; RISCV32-NEXT: mulhu s0, s3, a1 ; RISCV32-NEXT: snez a4, s2
; RISCV32-NEXT: snez s0, s0 ; RISCV32-NEXT: and a3, a4, a3
; RISCV32-NEXT: or t3, a4, s0 ; RISCV32-NEXT: mulhu a4, s2, s1
; RISCV32-NEXT: sltu s0, t1, a6 ; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: mulhu a4, s4, a3 ; RISCV32-NEXT: or a3, a3, a4
; RISCV32-NEXT: mulhu a4, s5, s6
; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: or a3, a3, a4
; RISCV32-NEXT: or a1, a3, a1
; RISCV32-NEXT: or a3, s7, s3
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or a4, s6, s2
; RISCV32-NEXT: snez a4, a4 ; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: or a4, s1, a4 ; RISCV32-NEXT: and a3, a4, a3
; RISCV32-NEXT: lw s1, 36(sp) ; RISCV32-NEXT: or a1, a3, a1
; RISCV32-NEXT: sw s1, 4(s2)
; RISCV32-NEXT: lw s1, 32(sp)
; RISCV32-NEXT: sw s1, 0(s2)
; RISCV32-NEXT: sw a7, 8(s2)
; RISCV32-NEXT: sw a5, 12(s2)
; RISCV32-NEXT: or a4, a4, s0
; RISCV32-NEXT: or a5, t3, t2
; RISCV32-NEXT: or a0, a1, a0 ; RISCV32-NEXT: or a0, a1, a0
; RISCV32-NEXT: or a1, a3, a2 ; RISCV32-NEXT: lw a1, 44(sp)
; RISCV32-NEXT: snez a1, a1 ; RISCV32-NEXT: lw a3, 40(sp)
; RISCV32-NEXT: snez a0, a0 ; RISCV32-NEXT: or a0, a0, a2
; RISCV32-NEXT: and a0, a0, a1
; RISCV32-NEXT: or a0, a0, a5
; RISCV32-NEXT: or a0, a0, a4
; RISCV32-NEXT: or a0, a0, t0
; RISCV32-NEXT: andi a0, a0, 1 ; RISCV32-NEXT: andi a0, a0, 1
; RISCV32-NEXT: sb a0, 16(s2) ; RISCV32-NEXT: sw a1, 4(s4)
; RISCV32-NEXT: lw s6, 48(sp) ; RISCV32-NEXT: sw a3, 0(s4)
; RISCV32-NEXT: lw s5, 52(sp) ; RISCV32-NEXT: sw a6, 8(s4)
; RISCV32-NEXT: lw s4, 56(sp) ; RISCV32-NEXT: sw a7, 12(s4)
; RISCV32-NEXT: lw s3, 60(sp) ; RISCV32-NEXT: sb a0, 16(s4)
; RISCV32-NEXT: lw s2, 64(sp) ; RISCV32-NEXT: lw s8, 56(sp)
; RISCV32-NEXT: lw s1, 68(sp) ; RISCV32-NEXT: lw s7, 60(sp)
; RISCV32-NEXT: lw s0, 72(sp) ; RISCV32-NEXT: lw s6, 64(sp)
; RISCV32-NEXT: lw ra, 76(sp) ; RISCV32-NEXT: lw s5, 68(sp)
; RISCV32-NEXT: addi sp, sp, 80 ; RISCV32-NEXT: lw s4, 72(sp)
; RISCV32-NEXT: lw s3, 76(sp)
; RISCV32-NEXT: lw s2, 80(sp)
; RISCV32-NEXT: lw s1, 84(sp)
; RISCV32-NEXT: lw s0, 88(sp)
; RISCV32-NEXT: lw ra, 92(sp)
; RISCV32-NEXT: addi sp, sp, 96
; RISCV32-NEXT: ret ; RISCV32-NEXT: ret
start: start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
%1 = extractvalue { i128, i1 } %0, 0 %1 = extractvalue { i128, i1 } %0, 0
%2 = extractvalue { i128, i1 } %0, 1 %2 = extractvalue { i128, i1 } %0, 1
%3 = zext i1 %2 to i8 %3 = zext i1 %2 to i8
%4 = insertvalue { i128, i8 } undef, i128 %1, 0 %4 = insertvalue { i128, i8 } undef, i128 %1, 0
%5 = insertvalue { i128, i8 } %4, i8 %3, 1 %5 = insertvalue { i128, i8 } %4, i8 %3, 1
Show All 9 Lines

llvm/test/CodeGen/RISCV/vararg.ll

Show All 40 Lines
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: mv a0, a1 ; ILP32-ILP32F-FPELIM-NEXT: mv a0, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1: ; ILP32-ILP32F-WITHFP-LABEL: va1:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1: ; LP64-LP64F-LP64D-FPELIM-LABEL: va1:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
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; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: mv a0, a1 ; ILP32-ILP32F-FPELIM-NEXT: mv a0, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg: ; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg: ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg: ; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, i32 %2 = va_arg i8** %va, i32
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; ILP32-ILP32F-FPELIM-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi s0, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: mv s1, a1 ; ILP32-ILP32F-FPELIM-NEXT: mv s1, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, s0, 8 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, s0, 8
; ILP32-ILP32F-FPELIM-NEXT: sw a0, -16(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, -16(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a1, 15 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a1, 15
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -16 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -16
; ILP32-ILP32F-FPELIM-NEXT: sub a0, sp, a0 ; ILP32-ILP32F-FPELIM-NEXT: sub a0, sp, a0
; ILP32-ILP32F-FPELIM-NEXT: mv sp, a0 ; ILP32-ILP32F-FPELIM-NEXT: mv sp, a0
; ILP32-ILP32F-FPELIM-NEXT: call notdead ; ILP32-ILP32F-FPELIM-NEXT: call notdead
; ILP32-ILP32F-FPELIM-NEXT: mv a0, s1 ; ILP32-ILP32F-FPELIM-NEXT: mv a0, s1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, s0, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, s0, -16
; ILP32-ILP32F-FPELIM-NEXT: lw s1, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw s1, 4(sp)
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; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a1, 15 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a1, 15
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -16 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -16
; ILP32-ILP32F-WITHFP-NEXT: sub a0, sp, a0 ; ILP32-ILP32F-WITHFP-NEXT: sub a0, sp, a0
; ILP32-ILP32F-WITHFP-NEXT: mv sp, a0 ; ILP32-ILP32F-WITHFP-NEXT: mv sp, a0
; ILP32-ILP32F-WITHFP-NEXT: call notdead ; ILP32-ILP32F-WITHFP-NEXT: call notdead
; ILP32-ILP32F-WITHFP-NEXT: mv a0, s1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, s1
; ILP32-ILP32F-WITHFP-NEXT: addi sp, s0, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, s0, -16
; ILP32-ILP32F-WITHFP-NEXT: lw s1, 4(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s1, 4(sp)
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; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi s0, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi s0, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s1, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s1, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 8(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 8(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, s0, 8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, s0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, -16(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, -16(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a1, 15 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a1, 15
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub a0, sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub a0, sp, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv sp, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, s1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, s1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, s0, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, s0, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s1, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s1, 4(sp)
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; LP64-LP64F-LP64D-FPELIM-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: mv s1, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv s1, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, -32(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 33 ; LP64-LP64F-LP64D-FPELIM-NEXT: srli a0, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 33
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 15 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -16
; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a1, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd s1, 8(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sub a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: sub a0, sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: mv sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead ; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead
; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, s1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, s1
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, s0, -32 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, s0, -32
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld s1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp)
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; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 33 ; LP64-LP64F-LP64D-WITHFP-NEXT: srli a0, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, -16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 33
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 15 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -16
; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a1, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sub a0, sp, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: sub a0, sp, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: mv sp, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv sp, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead ; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s1
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, s0, -32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, s0, -32
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 8(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
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} }
define void @va1_caller() nounwind { define void @va1_caller() nounwind {
; Pass a double, as a float would be promoted by a C/C++ frontend ; Pass a double, as a float would be promoted by a C/C++ frontend
; ILP32-ILP32F-FPELIM-LABEL: va1_caller: ; ILP32-ILP32F-FPELIM-LABEL: va1_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 ; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 2 ; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 2
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: call va1 ; ILP32-ILP32F-FPELIM-NEXT: call va1
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1_caller: ; ILP32-ILP32F-WITHFP-LABEL: va1_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 ; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 2 ; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 2
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: call va1 ; ILP32-ILP32F-WITHFP-NEXT: call va1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16
Show All 33 Lines
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 35
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: andi a1, a0, -8 ; ILP32-ILP32F-FPELIM-NEXT: andi a1, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 35
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a1) ; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a1)
; ILP32-ILP32F-FPELIM-NEXT: ori a1, a1, 4 ; ILP32-ILP32F-FPELIM-NEXT: ori a1, a1, 4
; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1) ; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va2: ; ILP32-ILP32F-WITHFP-LABEL: va2:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1) ; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1)
; ILP32-ILP32F-WITHFP-NEXT: ori a1, a1, 4 ; ILP32-ILP32F-WITHFP-NEXT: ori a1, a1, 4
; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1) ; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a1, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a1, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a1) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a1)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a1, a1, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a1, a1, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a1) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a1)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va2: ; LP64-LP64F-LP64D-FPELIM-LABEL: va2:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -8
; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va2: ; LP64-LP64F-LP64D-WITHFP-LABEL: va2:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32
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; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va2_va_arg: ; LP64-LP64F-LP64D-WITHFP-LABEL: va2_va_arg:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, double %2 = va_arg i8** %va, double
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
%3 = bitcast double %2 to i64 %3 = bitcast double %2 to i64
ret i64 %3 ret i64 %3
} }
define void @va2_caller() nounwind { define void @va2_caller() nounwind {
; ILP32-ILP32F-FPELIM-LABEL: va2_caller: ; ILP32-ILP32F-FPELIM-LABEL: va2_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 ; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: call va2 ; ILP32-ILP32F-FPELIM-NEXT: call va2
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va2_caller: ; ILP32-ILP32F-WITHFP-LABEL: va2_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 ; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: call va2 ; ILP32-ILP32F-WITHFP-NEXT: call va2
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va2_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va2_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16
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; ILP32-ILP32F-FPELIM-LABEL: va3: ; ILP32-ILP32F-FPELIM-LABEL: va3:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -32 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -32
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: ori a3, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a3, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a3) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3 ; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) ; ILP32-ILP32F-FPELIM-NEXT: ori a0, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 ; ILP32-ILP32F-FPELIM-NEXT: lw a4, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a3
; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1 ; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1
; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a4
; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va3: ; ILP32-ILP32F-WITHFP-LABEL: va3:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3 ; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: ori a0, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 ; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a3
; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1
; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a4
; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -32 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 19 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 19
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a3, a0, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 0(a3) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a0, a0, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a4, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a3
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 32 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va3: ; LP64-LP64F-LP64D-FPELIM-LABEL: va3:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -64 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -64
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a2, a2, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, -8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, -8
; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a2 ; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va3: ; LP64-LP64F-LP64D-WITHFP-LABEL: va3:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, -8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, -8
Show All 34 Lines
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: ori a3, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: ori a3, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) ; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: addi a4, a3, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a4, a3, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a3) ; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a3)
; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3
; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 ; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0
; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1 ; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1
; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3
; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va3_va_arg: ; ILP32-ILP32F-WITHFP-LABEL: va3_va_arg:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: addi a4, a3, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a4, a3, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a4, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3) ; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3)
; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 ; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0
; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1
; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3
; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_va_arg: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_va_arg:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a3
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va3_va_arg: ; LP64-LP64F-LP64D-FPELIM-LABEL: va3_va_arg:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -64 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -64
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ori a3, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va3_va_arg: ; LP64-LP64F-LP64D-WITHFP-LABEL: va3_va_arg:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a3, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, double %2 = va_arg i8** %va, double
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
%3 = bitcast double %2 to i64 %3 = bitcast double %2 to i64
%4 = add i64 %b, %3 %4 = add i64 %b, %3
ret i64 %4 ret i64 %4
} }
define void @va3_caller() nounwind { define void @va3_caller() nounwind {
; ILP32-ILP32F-FPELIM-LABEL: va3_caller: ; ILP32-ILP32F-FPELIM-LABEL: va3_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 2 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 2
; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 1111 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 1111
; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero ; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: mv a4, zero ; ILP32-ILP32F-FPELIM-NEXT: mv a4, zero
; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144
; ILP32-ILP32F-FPELIM-NEXT: call va3 ; ILP32-ILP32F-FPELIM-NEXT: call va3
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va3_caller: ; ILP32-ILP32F-WITHFP-LABEL: va3_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 2 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 2
; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 1111 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 1111
; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero ; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: mv a4, zero ; ILP32-ILP32F-WITHFP-NEXT: mv a4, zero
; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144
; ILP32-ILP32F-WITHFP-NEXT: call va3 ; ILP32-ILP32F-WITHFP-NEXT: call va3
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 1111 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 1111
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a4, zero ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a4, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va3_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va3_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16
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; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4
; ILP32-ILP32F-FPELIM-NEXT: addi a2, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a2, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a2, 0(a0) ; ILP32-ILP32F-FPELIM-NEXT: lw a2, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4
; ILP32-ILP32F-FPELIM-NEXT: addi a3, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a3, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, s0 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, s0
; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, a2 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, a2
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 ; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0
; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va4_va_copy: ; ILP32-ILP32F-WITHFP-LABEL: va4_va_copy:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
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; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4
; ILP32-ILP32F-WITHFP-NEXT: addi a2, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a2, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a2, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a2, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a2, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4
; ILP32-ILP32F-WITHFP-NEXT: addi a3, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, s1 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, s1
; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, a2 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, a2
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 ; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0
; ILP32-ILP32F-WITHFP-NEXT: lw s1, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s1, 20(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 24(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 24(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 28(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 28(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va4_va_copy: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va4_va_copy:
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; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, a0, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, a0, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a2, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a2, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, s0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, s0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, a2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, a2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy: ; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
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; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a2, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a2, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11
; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, s0 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, s0
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, a2 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addw a0, a1, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: addw a0, a1, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va4_va_copy: ; LP64-LP64F-LP64D-WITHFP-LABEL: va4_va_copy:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
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; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a2, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a2, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11
; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, s1 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, s1
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, a2 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addw a0, a1, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: addw a0, a1, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 112 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 112
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%vargs = alloca i8*, align 4 %vargs = alloca i8*, align 4
%wargs = alloca i8*, align 4 %wargs = alloca i8*, align 4
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; ILP32-ILP32F-FPELIM-NEXT: sw a0, 44(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 44(sp)
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 545260 ; ILP32-ILP32F-FPELIM-NEXT: lui a0, 545260
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, -1967 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, -1967
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 964690 ; ILP32-ILP32F-FPELIM-NEXT: lui a0, 964690
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, -328 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, -328
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 335544 ; ILP32-ILP32F-FPELIM-NEXT: lui a0, 335544
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 1311 ; ILP32-ILP32F-FPELIM-NEXT: addi a5, a0, 1311
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 688509 ; ILP32-ILP32F-FPELIM-NEXT: lui a0, 688509
; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048 ; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048
; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32 ; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1
; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11
; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12 ; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13 ; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13
; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee ; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 60(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 60(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 64
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va5_aligned_stack_caller: ; ILP32-ILP32F-WITHFP-LABEL: va5_aligned_stack_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64
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; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0)
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 545260 ; ILP32-ILP32F-WITHFP-NEXT: lui a0, 545260
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -1967 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -1967
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -24(s0)
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 964690 ; ILP32-ILP32F-WITHFP-NEXT: lui a0, 964690
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -328 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -328
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -28(s0)
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 335544 ; ILP32-ILP32F-WITHFP-NEXT: lui a0, 335544
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 1311 ; ILP32-ILP32F-WITHFP-NEXT: addi a5, a0, 1311
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -32(s0)
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 688509 ; ILP32-ILP32F-WITHFP-NEXT: lui a0, 688509
; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048 ; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048
; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32 ; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1
; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11
; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13 ; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13
; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a5, -32(s0)
; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee ; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 56(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 56(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 60(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 60(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va5_aligned_stack_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va5_aligned_stack_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
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; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 545260 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 545260
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, -1967 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, -1967
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 964690 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 964690
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, -328 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, -328
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 335544 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 335544
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 1311 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a5, a0, 1311
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 688509 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 688509
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 60(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 60(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 64 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 64
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -48 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -48
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 17 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 17
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 15 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 2049 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 2049
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, -1147 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, -1147
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 13 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 13
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 983 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 983
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 14 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 14
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 655 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 655
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 1475 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi t0, a0, 1475
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 1192
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 381
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a6, a0, -2048
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 1048248 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 1048248
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 1311 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 1311
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, -1147 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, -1147
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 13 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 13
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 512
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 73
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -1311
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 1147
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 14
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 983 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 983
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 15 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a2, 1192
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a2, a2, 381
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a6, a2, -2048
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 1311 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 1311
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a1, -1967 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 512
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 73
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, -1311
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 1147
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 14
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, -1967
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 11
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a4, zero, 12 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a4, zero, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a5, zero, 13 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a5, zero, 13
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a7, zero, 14 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a7, zero, 14
; LP64-LP64F-LP64D-FPELIM-NEXT: sd t0, 0(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee ; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 48 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 48
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va5_aligned_stack_caller: ; LP64-LP64F-LP64D-WITHFP-LABEL: va5_aligned_stack_caller:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -48
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 17 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 17
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 15 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 2049 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 2049
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, -1147 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, -1147
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 13 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 13
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 983 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 983
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 14 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 14
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 655 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 655
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 1475 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi t0, a0, 1475
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 1192
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 381
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a6, a0, -2048
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 1048248 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 1048248
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 1311 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 1311
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, -1147 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, -1147
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 13 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 13
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 512
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, 73
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -1311
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 1147
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 14
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 983 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 983
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 15 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a2, 1192
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a2, a2, 381
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a6, a2, -2048
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 1311 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 1311
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a1, -1967 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 512
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 73
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, -1311
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 1147
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 14
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, -1967
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 11
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a4, zero, 12 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a4, zero, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a5, zero, 13 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a5, zero, 13
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a7, zero, 14 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a7, zero, 14
; LP64-LP64F-LP64D-WITHFP-NEXT: sd t0, 0(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee ; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 48
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11, %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17]) i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
Show All 10 Lines
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 16(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 20 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 20
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 16(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va6_no_fixed_args: ; ILP32-ILP32F-WITHFP-LABEL: va6_no_fixed_args:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 0(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 0(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va6_no_fixed_args: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va6_no_fixed_args:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 16(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 20 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 20
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 16(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va6_no_fixed_args: ; LP64-LP64F-LP64D-FPELIM-LABEL: va6_no_fixed_args:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ori a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: ori a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va6_no_fixed_args: ; LP64-LP64F-LP64D-WITHFP-LABEL: va6_no_fixed_args:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a1, s0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a1, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: ori a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, i32 %2 = va_arg i8** %va, i32
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

Show All 39 Lines
} }
@shorts = global [5 x i16] zeroinitializer, align 2 @shorts = global [5 x i16] zeroinitializer, align 2
define i32 @test_zext_i16() nounwind { define i32 @test_zext_i16() nounwind {
; RV32I-LABEL: test_zext_i16: ; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(shorts) ; RV32I-NEXT: lui a0, %hi(shorts)
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lhu a1, %lo(shorts)(a0)
; RV32I-NEXT: addi a1, a1, -120 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: lhu a2, %lo(shorts)(a0) ; RV32I-NEXT: addi a2, a2, -120
; RV32I-NEXT: bne a2, a1, .LBB1_3 ; RV32I-NEXT: bne a1, a2, .LBB1_3
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: addi a0, a0, %lo(shorts) ; RV32I-NEXT: addi a0, a0, %lo(shorts)
; RV32I-NEXT: lhu a0, 2(a0) ; RV32I-NEXT: lhu a0, 2(a0)
; RV32I-NEXT: addi a1, zero, 7 ; RV32I-NEXT: addi a1, zero, 7
; RV32I-NEXT: bne a0, a1, .LBB1_3 ; RV32I-NEXT: bne a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.2: # %if.end ; RV32I-NEXT: # %bb.2: # %if.end
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 17 Lines
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll