[LLVM][Alignment] Make functions using log of alignment explicit

[gchatelet]

Summary

This patch renames functions that takes or returns alignment as log2, this patch will help with the transition to llvm::Align.
The renaming makes it explicit that we deal with log(alignment) instead of a power of two alignment.
A few renames uncovered dubious assignments

• MirParser/MirPrinter was expecting powers of two but MachineFunction and MachineBasicBlock were using deal with log2(align). This patch fixes it.
• MachineBlockPlacement exposes two flags (align-all-blocks and align-all-nofallthru-blocks) supposedly interpreted as power of two alignments, internally these values are interpreted as log2(align). This patch updates the documentation,
• MachineFunctionexposes exposes align-all-functions also interpreted as power of two alignment, internally this value is interpreted as log2(align). This patch updates the documentation,

[gchatelet]

• Also removes JumpBufSize

[gchatelet]

• Also removes JumpBufSize
• Rebasing fix

[courbet]

llvm/include/llvm/CodeGen/TargetLowering.h

2706 ↗

(On Diff #216443)

Maybe split this change to a different commit ? Also, this is part of the public API. There might be external code that depends on this. Not sure what the policy here is. Did you reach out to the original author for this ?

llvm/lib/CodeGen/MachineBlockPlacement.cpp

3105 ↗

(On Diff #216443)

These are fine, maybe just update the doc of the flags ?

llvm/lib/CodeGen/MachineFunction.cpp

184 ↗

(On Diff #216443)

ditto.

[gchatelet]

• Rebasing
• Update documentation flags.

llvm/include/llvm/CodeGen/TargetLowering.h

2706 ↗

(On Diff #216443)

This has been submitted as https://reviews.llvm.org/D66683

[gchatelet]

@arphaman do you mind having a look at the MIR parser / writer parts?
How is alignment supposed to be serialized for MIR? As power of two or a log of alignment?

[gchatelet]

• Rebasing

[gchatelet]

• Add missing renames

[gchatelet]

In D65945#1643692, @gchatelet wrote:

@arphaman do you mind having a look at the MIR parser / writer parts?
How is alignment supposed to be serialized for MIR? As power of two or a log of alignment?

Upon closer inspection, it seems like the PowerOfTwo requirement comes from https://github.com/llvm/llvm-project/commit/547a83b4ebd1
@arsenm do you mind having a look ?

[gchatelet]

• Rebasing
• Update documentation flags.
• Add missing renames
• Use powers of 2 for alignment in YAMLized mir files
• Make sure YAML MIR has align as Powers of 2. Fix tests.

[gchatelet]

@lattner I've added you to this review because I get no feedback from the authors (and you seem to be the OWNER).
The rename exposed a bug in the way alignment of basic blocks and function arguments are serialized for YAML mir.
From this patch and the parseAlignment code it is clear that the serialized form expects powers of two, but the internal structures receiving the alignment deal with log2 of alignments (MachineFunction and MachineBasicBlock).

[lattner]

Renaming this to LogAlignment is much more clear throughout the core infra, thank you! Please get someone who knows the Yaml stuff to approve as well.

[gchatelet]

In D65945#1657901, @lattner wrote:

Renaming this to LogAlignment is much more clear throughout the core infra, thank you! Please get someone who knows the Yaml stuff to approve as well.

@arsenm seems to be the one, or maybe @thegameg?

[thegameg]

Thanks for fixing the MIR issues and tests. It would be great to document this somewhere in https://llvm.org/docs/MIRLangRef.html if you can. Other than that, this LGTM!

[gchatelet]

• Rebasing
• Update documentation flags.
• Add missing renames
• Use powers of 2 for alignment in YAMLized mir files
• Make sure YAML MIR has align as Powers of 2. Fix tests.
• Added documentation in MIRLangRef.rst

[gchatelet]

Thx @thegameg and @lattner , I'll commit shortly!

llvm/trunk/docs/MIRLangRef.rst

.. code-block:: text
     bb.2.else (align 4):
       <instructions>
     bb.3(landing-pad, align 4):
       <instructions>
 
 .. TODO: Describe the way the reference to an unnamed LLVM IR block can be
    preserved.
 
+``Alignment`` is specified in bytes, and must be a power of two.
+
 Machine Instructions
 --------------------
 
 A machine instruction is composed of a name,
 :ref:`machine operands <machine-operands>`,
 :ref:`instruction flags <instruction-flags>`, and machine memory operands.
 
 The instruction's name is usually specified before the operands. The example

 .. code-block:: text
 
     constants:
       - id:               <index>
         value:            <value>
         alignment:        <alignment>
         isTargetSpecific: <target-specific>
 
-where ``<index>`` is a 32-bit unsigned integer, ``<value>`` is a `LLVM IR Constant
-<https://www.llvm.org/docs/LangRef.html#constants>`_, alignment is a 32-bit
-unsigned integer, and ``<target-specific>`` is either true or false.
+where:
+  - ``<index>`` is a 32-bit unsigned integer;
+  - ``<value>`` is a `LLVM IR Constant
+    <https://www.llvm.org/docs/LangRef.html#constants>`_;
+  - ``<alignment>`` is a 32-bit unsigned integer specified in bytes, and must be
+    power of two;
+  - ``<target-specific>`` is either true or false.
 
 Example:
 
 .. code-block:: text
 
     constants:
       - id:               0
         value:            'double 3.250000e+00'

llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h

private:
   Optional<uint64_t> IrrLoopHeaderWeight;
 
   /// Keep track of the physical registers that are livein of the basicblock.
   using LiveInVector = std::vector<RegisterMaskPair>;
   LiveInVector LiveIns;
 
   /// Alignment of the basic block. Zero if the basic block does not need to be
   /// aligned. The alignment is specified as log2(bytes).
-  unsigned Alignment = 0;
+  unsigned LogAlignment = 0;
 
   /// Indicate that this basic block is entered via an exception handler.
   bool IsEHPad = false;
 
   /// Indicate that this basic block is potentially the target of an indirect
   /// branch.
   bool AddressTaken = false;
 
#endif
   const uint32_t *getBeginClobberMask(const TargetRegisterInfo *TRI) const;
 
   /// Get the clobber mask for the end of the basic block.
   /// \see getBeginClobberMask()
   const uint32_t *getEndClobberMask(const TargetRegisterInfo *TRI) const;
 
   /// Return alignment of the basic block. The alignment is specified as
   /// log2(bytes).
-  unsigned getAlignment() const { return Alignment; }
+  unsigned getLogAlignment() const { return LogAlignment; }
 
   /// Set alignment of the basic block. The alignment is specified as
   /// log2(bytes).
-  void setAlignment(unsigned Align) { Alignment = Align; }
+  void setLogAlignment(unsigned A) { LogAlignment = A; }
 
   /// Returns true if the block is a landing pad. That is this basic block is
   /// entered via an exception handler.
   bool isEHPad() const { return IsEHPad; }
 
   /// Indicates the block is a landing pad.  That is this basic block is entered
   /// via an exception handler.
   void setIsEHPad(bool V = true) { IsEHPad = V; }

llvm/trunk/include/llvm/CodeGen/MachineFunction.h

class MachineFunction {
   BasicBlockListType BasicBlocks;
 
   /// FunctionNumber - This provides a unique ID for each function emitted in
   /// this translation unit.
   ///
   unsigned FunctionNumber;
 
   /// Alignment - The alignment of the function.
-  unsigned Alignment;
+  unsigned LogAlignment;
 
   /// ExposesReturnsTwice - True if the function calls setjmp or related
   /// functions with attribute "returns twice", but doesn't have
   /// the attribute itself.
   /// This is used to limit optimizations which cannot reason
   /// about the control flow of such functions.
   bool ExposesReturnsTwice = false;
 
public:
   WasmEHFuncInfo *getWasmEHFuncInfo() { return WasmEHInfo; }
 
   /// getWinEHFuncInfo - Return information about how the current function uses
   /// Windows exception handling. Returns null for functions that don't use
   /// funclets for exception handling.
   const WinEHFuncInfo *getWinEHFuncInfo() const { return WinEHInfo; }
   WinEHFuncInfo *getWinEHFuncInfo() { return WinEHInfo; }
 
-  /// getAlignment - Return the alignment (log2, not bytes) of the function.
-  unsigned getAlignment() const { return Alignment; }
+  /// getLogAlignment - Return the alignment of the function.
+  unsigned getLogAlignment() const { return LogAlignment; }
 
-  /// setAlignment - Set the alignment (log2, not bytes) of the function.
-  void setAlignment(unsigned A) { Alignment = A; }
+  /// setLogAlignment - Set the alignment of the function.
+  void setLogAlignment(unsigned A) { LogAlignment = A; }
 
   /// ensureAlignment - Make sure the function is at least 1 << A bytes aligned.
-  void ensureAlignment(unsigned A) {
-    if (Alignment < A) Alignment = A;
+  void ensureLogAlignment(unsigned A) {
+    if (LogAlignment < A)
+      LogAlignment = A;
   }
 
   /// exposesReturnsTwice - Returns true if the function calls setjmp or
   /// any other similar functions with attribute "returns twice" without
   /// having the attribute itself.
   bool exposesReturnsTwice() const {
     return ExposesReturnsTwice;
   }

llvm/trunk/include/llvm/CodeGen/TargetLowering.h

   }
 
   /// Return the minimum stack alignment of an argument.
   unsigned getMinStackArgumentAlignment() const {
     return MinStackArgumentAlignment;
   }
 
   /// Return the minimum function alignment.
-  unsigned getMinFunctionAlignment() const {
-    return MinFunctionAlignment;
+  unsigned getMinFunctionLogAlignment() const {
+    return MinFunctionLogAlignment;
   }
 
   /// Return the preferred function alignment.
-  unsigned getPrefFunctionAlignment() const {
-    return PrefFunctionAlignment;
+  unsigned getPrefFunctionLogAlignment() const {
+    return PrefFunctionLogAlignment;
   }
 
   /// Return the preferred loop alignment.
-  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
-    return PrefLoopAlignment;
+  virtual unsigned getPrefLoopLogAlignment(MachineLoop *ML = nullptr) const {
+    return PrefLoopLogAlignment;
   }
 
   /// Should loops be aligned even when the function is marked OptSize (but not
   /// MinSize).
   virtual bool alignLoopsWithOptSize() const {
     return false;
   }
 
protected:
   /// they want to provide a custom DAG combiner for by implementing the
   /// PerformDAGCombine virtual method.
   void setTargetDAGCombine(ISD::NodeType NT) {
     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
   }
 
   /// Set the target's minimum function alignment (in log2(bytes))
-  void setMinFunctionAlignment(unsigned Align) {
-    MinFunctionAlignment = Align;
+  void setMinFunctionLogAlignment(unsigned LogAlign) {
+    MinFunctionLogAlignment = LogAlign;
   }
 
   /// Set the target's preferred function alignment.  This should be set if
   /// there is a performance benefit to higher-than-minimum alignment (in
   /// log2(bytes))
-  void setPrefFunctionAlignment(unsigned Align) {
-    PrefFunctionAlignment = Align;
+  void setPrefFunctionLogAlignment(unsigned LogAlign) {
+    PrefFunctionLogAlignment = LogAlign;
   }
 
   /// Set the target's preferred loop alignment. Default alignment is zero, it
   /// means the target does not care about loop alignment.  The alignment is
   /// specified in log2(bytes). The target may also override
   /// getPrefLoopAlignment to provide per-loop values.
-  void setPrefLoopAlignment(unsigned Align) {
-    PrefLoopAlignment = Align;
+  void setPrefLoopLogAlignment(unsigned LogAlign) {
+    PrefLoopLogAlignment = LogAlign;
   }
 
   /// Set the minimum stack alignment of an argument (in log2(bytes)).
   void setMinStackArgumentAlignment(unsigned Align) {
     MinStackArgumentAlignment = Align;
   }
 
   /// Set the maximum atomic operation size supported by the
private:
   /// register usage.
   Sched::Preference SchedPreferenceInfo;
 
   /// The minimum alignment that any argument on the stack needs to have.
   unsigned MinStackArgumentAlignment;
 
   /// The minimum function alignment (used when optimizing for size, and to
   /// prevent explicitly provided alignment from leading to incorrect code).
-  unsigned MinFunctionAlignment;
+  unsigned MinFunctionLogAlignment;
 
   /// The preferred function alignment (used when alignment unspecified and
   /// optimizing for speed).
-  unsigned PrefFunctionAlignment;
+  unsigned PrefFunctionLogAlignment;
 
-  /// The preferred loop alignment.
-  unsigned PrefLoopAlignment;
+  /// The preferred loop alignment (in log2 bot in bytes).
+  unsigned PrefLoopLogAlignment;
 
   /// Size in bits of the maximum atomics size the backend supports.
   /// Accesses larger than this will be expanded by AtomicExpandPass.
   unsigned MaxAtomicSizeInBitsSupported;
 
   /// Size in bits of the minimum cmpxchg or ll/sc operation the
   /// backend supports.
   unsigned MinCmpXchgSizeInBits;

llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

void AsmPrinter::EmitFunctionHeader() {
   EmitConstantPool();
 
   // Print the 'header' of function.
   OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(&F, TM));
   EmitVisibility(CurrentFnSym, F.getVisibility());
 
   EmitLinkage(&F, CurrentFnSym);
   if (MAI->hasFunctionAlignment())
-    EmitAlignment(MF->getAlignment(), &F);
+    EmitAlignment(MF->getLogAlignment(), &F);
 
   if (MAI->hasDotTypeDotSizeDirective())
     OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction);
 
   if (F.hasFnAttribute(Attribute::Cold))
     OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_Cold);
 
   if (isVerbose()) {
void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) {
   if (MBB.isEHFuncletEntry()) {
     for (const HandlerInfo &HI : Handlers) {
       HI.Handler->endFunclet();
       HI.Handler->beginFunclet(MBB);
     }
   }
 
   // Emit an alignment directive for this block, if needed.
-  if (unsigned Align = MBB.getAlignment())
-    EmitAlignment(Align);
+  if (unsigned LogAlign = MBB.getLogAlignment())
+    EmitAlignment(LogAlign);
   MCCodePaddingContext Context;
   setupCodePaddingContext(MBB, Context);
   OutStreamer->EmitCodePaddingBasicBlockStart(Context);
 
   // If the block has its address taken, emit any labels that were used to
   // reference the block.  It is possible that there is more than one label
   // here, because multiple LLVM BB's may have been RAUW'd to this block after
   // the references were generated.

llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp

if (!Sym) {
     Asm->OutStreamer->BeginCOFFSymbolDef(Sym);
     Asm->OutStreamer->EmitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_STATIC);
     Asm->OutStreamer->EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION
                                          << COFF::SCT_COMPLEX_TYPE_SHIFT);
     Asm->OutStreamer->EndCOFFSymbolDef();
 
     // We want our funclet's entry point to be aligned such that no nops will be
     // present after the label.
-    Asm->EmitAlignment(std::max(Asm->MF->getAlignment(), MBB.getAlignment()),
-                       &F);
+    Asm->EmitAlignment(
+        std::max(Asm->MF->getLogAlignment(), MBB.getLogAlignment()), &F);
 
     // Now that we've emitted the alignment directive, point at our funclet.
     Asm->OutStreamer->EmitLabel(Sym);
   }
 
   // Mark 'Sym' as starting our funclet.
   if (shouldEmitMoves || shouldEmitPersonality) {
     CurrentFuncletTextSection = Asm->OutStreamer->getCurrentSectionOnly();

llvm/trunk/lib/CodeGen/BranchRelaxation.cpp

struct BasicBlockInfo {
     unsigned Size = 0;
 
     BasicBlockInfo() = default;
 
     /// Compute the offset immediately following this block. \p MBB is the next
     /// block.
     unsigned postOffset(const MachineBasicBlock &MBB) const {
       unsigned PO = Offset + Size;
-      unsigned Align = MBB.getAlignment();
-      if (Align == 0)
+      unsigned LogAlign = MBB.getLogAlignment();
+      if (LogAlign == 0)
         return PO;
 
-      unsigned AlignAmt = 1 << Align;
-      unsigned ParentAlign = MBB.getParent()->getAlignment();
-      if (Align <= ParentAlign)
+      unsigned AlignAmt = 1 << LogAlign;
+      unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
+      if (LogAlign <= ParentLogAlign)
         return PO + OffsetToAlignment(PO, AlignAmt);
 
       // The alignment of this MBB is larger than the function's alignment, so we
       // can't tell whether or not it will insert nops. Assume that it will.
       return PO + AlignAmt + OffsetToAlignment(PO, AlignAmt);
     }
   };
 

 
 INITIALIZE_PASS(BranchRelaxation, DEBUG_TYPE, BRANCH_RELAX_NAME, false, false)
 
 /// verify - check BBOffsets, BBSizes, alignment of islands
 void BranchRelaxation::verify() {
 #ifndef NDEBUG
   unsigned PrevNum = MF->begin()->getNumber();
   for (MachineBasicBlock &MBB : *MF) {
-    unsigned Align = MBB.getAlignment();
+    unsigned LogAlign = MBB.getLogAlignment();
     unsigned Num = MBB.getNumber();
-    assert(BlockInfo[Num].Offset % (1u << Align) == 0);
+    assert(BlockInfo[Num].Offset % (1u << LogAlign) == 0);
     assert(!Num || BlockInfo[PrevNum].postOffset(MBB) <= BlockInfo[Num].Offset);
     assert(BlockInfo[Num].Size == computeBlockSize(MBB));
     PrevNum = Num;
   }
 #endif
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseBasicBlockDefinition(
   }
   auto *MBB = MF.CreateMachineBasicBlock(BB);
   MF.insert(MF.end(), MBB);
   bool WasInserted = MBBSlots.insert(std::make_pair(ID, MBB)).second;
   if (!WasInserted)
     return error(Loc, Twine("redefinition of machine basic block with id #") +
                           Twine(ID));
   if (Alignment)
-    MBB->setAlignment(Alignment);
+    MBB->setLogAlignment(Log2_32(Alignment));
   if (HasAddressTaken)
     MBB->setHasAddressTaken();
   MBB->setIsEHPad(IsLandingPad);
   return false;
 }
 
 bool MIParser::parseBasicBlockDefinitions(
     DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {

llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp

MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
   if (Target) {
     // Avoid clearing state if we're using the same subtarget again.
     Target->setTarget(MF.getSubtarget());
   } else {
     Target.reset(new PerTargetMIParsingState(MF.getSubtarget()));
   }
 
   if (YamlMF.Alignment)
-    MF.setAlignment(YamlMF.Alignment);
+    MF.setLogAlignment(Log2_32(YamlMF.Alignment));
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasWinCFI(YamlMF.HasWinCFI);
 
   if (YamlMF.Legalized)
     MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
   if (YamlMF.RegBankSelected)
     MF.getProperties().set(
         MachineFunctionProperties::Property::RegBankSelected);

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
   OS << printReg(Reg, TRI);
 }
 
 void MIRPrinter::print(const MachineFunction &MF) {
   initRegisterMaskIds(MF);
 
   yaml::MachineFunction YamlMF;
   YamlMF.Name = MF.getName();
-  YamlMF.Alignment = MF.getAlignment();
+  YamlMF.Alignment = 1UL << MF.getLogAlignment();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasWinCFI = MF.hasWinCFI();
 
   YamlMF.Legalized = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Legalized);
   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
   YamlMF.Selected = MF.getProperties().hasProperty(
if (MBB.hasAddressTaken()) {
     OS << "address-taken";
     HasAttributes = true;
   }
   if (MBB.isEHPad()) {
     OS << (HasAttributes ? ", " : " (");
     OS << "landing-pad";
     HasAttributes = true;
   }
-  if (MBB.getAlignment()) {
+  if (MBB.getLogAlignment()) {
     OS << (HasAttributes ? ", " : " (");
-    OS << "align " << MBB.getAlignment();
+    OS << "align "
+       << (1UL << MBB.getLogAlignment());
     HasAttributes = true;
   }
   if (HasAttributes)
     OS << ")";
   OS << ":\n";
 
   bool HasLineAttributes = false;
   // Print the successors

llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp

if (hasAddressTaken()) {
     OS << "address-taken";
     HasAttributes = true;
   }
   if (isEHPad()) {
     OS << (HasAttributes ? ", " : " (");
     OS << "landing-pad";
     HasAttributes = true;
   }
-  if (getAlignment()) {
+  if (getLogAlignment()) {
     OS << (HasAttributes ? ", " : " (");
-    OS << "align " << getAlignment();
+    OS << "align " << getLogAlignment();
     HasAttributes = true;
   }
   if (HasAttributes)
     OS << ")";
   OS << ":\n";
 
   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
   const MachineRegisterInfo &MRI = MF->getRegInfo();

llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

 
 STATISTIC(NumCondBranches, "Number of conditional branches");
 STATISTIC(NumUncondBranches, "Number of unconditional branches");
 STATISTIC(CondBranchTakenFreq,
           "Potential frequency of taking conditional branches");
 STATISTIC(UncondBranchTakenFreq,
           "Potential frequency of taking unconditional branches");
 
-static cl::opt<unsigned> AlignAllBlock("align-all-blocks",
-                                       cl::desc("Force the alignment of all "
-                                                "blocks in the function."),
-                                       cl::init(0), cl::Hidden);
+static cl::opt<unsigned> AlignAllBlock(
+    "align-all-blocks",
+    cl::desc("Force the alignment of all blocks in the function in log2 format "
+             "(e.g 4 means align on 16B boundaries)."),
 
 static cl::opt<unsigned> AlignAllNonFallThruBlocks(
     "align-all-nofallthru-blocks",
-    cl::desc("Force the alignment of all "
-             "blocks that have no fall-through predecessors (i.e. don't add "
-             "nops that are executed)."),
+    cl::desc("Force the alignment of all blocks that have no fall-through "
+             "predecessors (i.e. don't add nops that are executed). In log2 "
+             "format (e.g 4 means align on 16B boundaries)."),
     cl::init(0), cl::Hidden);
 
 // FIXME: Find a good default for this flag and remove the flag.
 static cl::opt<unsigned> ExitBlockBias(
     "block-placement-exit-block-bias",
     cl::desc("Block frequency percentage a loop exit block needs "
              "over the original exit to be considered the new exit."),
     cl::init(0), cl::Hidden);
for (MachineBasicBlock *ChainBB : FunctionChain) {
     // Don't align non-looping basic blocks. These are unlikely to execute
     // enough times to matter in practice. Note that we'll still handle
     // unnatural CFGs inside of a natural outer loop (the common case) and
     // rotated loops.
     MachineLoop *L = MLI->getLoopFor(ChainBB);
     if (!L)
       continue;
 
-    unsigned Align = TLI->getPrefLoopAlignment(L);
-    if (!Align)
+    unsigned LogAlign = TLI->getPrefLoopLogAlignment(L);
+    if (!LogAlign)
       continue; // Don't care about loop alignment.
 
     // If the block is cold relative to the function entry don't waste space
     // aligning it.
     BlockFrequency Freq = MBFI->getBlockFreq(ChainBB);
     if (Freq < WeightedEntryFreq)
       continue;
 
     // If the block is cold relative to its loop header, don't align it
     // regardless of what edges into the block exist.
     MachineBasicBlock *LoopHeader = L->getHeader();
     BlockFrequency LoopHeaderFreq = MBFI->getBlockFreq(LoopHeader);
     if (Freq < (LoopHeaderFreq * ColdProb))
       continue;
 
     // Check for the existence of a non-layout predecessor which would benefit
     // from aligning this block.
     MachineBasicBlock *LayoutPred =
         &*std::prev(MachineFunction::iterator(ChainBB));
 
     // Force alignment if all the predecessors are jumps. We already checked
     // that the block isn't cold above.
     if (!LayoutPred->isSuccessor(ChainBB)) {
-      ChainBB->setAlignment(Align);
+      ChainBB->setLogAlignment(LogAlign);
       continue;
     }
 
     // Align this block if the layout predecessor's edge into this block is
     // cold relative to the block. When this is true, other predecessors make up
     // all of the hot entries into the block and thus alignment is likely to be
     // important.
     BranchProbability LayoutProb =
         MBPI->getEdgeProbability(LayoutPred, ChainBB);
     BlockFrequency LayoutEdgeFreq = MBFI->getBlockFreq(LayoutPred) * LayoutProb;
     if (LayoutEdgeFreq <= (Freq * ColdProb))
-      ChainBB->setAlignment(Align);
+      ChainBB->setLogAlignment(LogAlign);
   }
 }
 
 /// Tail duplicate \p BB into (some) predecessors if profitable, repeating if
 /// it was duplicated into its chain predecessor and removed.
 /// \p BB    - Basic block that may be duplicated.
 ///
 /// \p LPred - Chosen layout predecessor of \p BB.
bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
 
   BlockToChain.clear();
   ComputedEdges.clear();
   ChainAllocator.DestroyAll();
 
   if (AlignAllBlock)
     // Align all of the blocks in the function to a specific alignment.
     for (MachineBasicBlock &MBB : MF)
-      MBB.setAlignment(AlignAllBlock);
+      MBB.setLogAlignment(AlignAllBlock);
   else if (AlignAllNonFallThruBlocks) {
     // Align all of the blocks that have no fall-through predecessors to a
     // specific alignment.
     for (auto MBI = std::next(MF.begin()), MBE = MF.end(); MBI != MBE; ++MBI) {
       auto LayoutPred = std::prev(MBI);
       if (!LayoutPred->isSuccessor(&*MBI))
-        MBI->setAlignment(AlignAllNonFallThruBlocks);
+        MBI->setLogAlignment(AlignAllNonFallThruBlocks);
     }
   }
   if (ViewBlockLayoutWithBFI != GVDT_None &&
       (ViewBlockFreqFuncName.empty() ||
        F->getFunction().getName().equals(ViewBlockFreqFuncName))) {
     MBFI->view("MBP." + MF.getName(), false);
   }
 

llvm/trunk/lib/CodeGen/MachineFunction.cpp

 #include <string>
 #include <utility>
 #include <vector>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "codegen"
 
-static cl::opt<unsigned>
-AlignAllFunctions("align-all-functions",
-                  cl::desc("Force the alignment of all functions."),
-                  cl::init(0), cl::Hidden);
+static cl::opt<unsigned> AlignAllFunctions(
+    "align-all-functions",
+    cl::desc("Force the alignment of all functions in log2 format (e.g. 4 "
+             "means align on 16B boundaries)."),
 
 static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
   using P = MachineFunctionProperties::Property;
 
   switch(Prop) {
   case P::FailedISel: return "FailedISel";
   case P::IsSSA: return "IsSSA";
   case P::Legalized: return "Legalized";
FrameInfo = new (Allocator) MachineFrameInfo(
       getFnStackAlignment(STI, F), /*StackRealignable=*/CanRealignSP,
       /*ForcedRealign=*/CanRealignSP &&
           F.hasFnAttribute(Attribute::StackAlignment));
 
   if (F.hasFnAttribute(Attribute::StackAlignment))
     FrameInfo->ensureMaxAlignment(F.getFnStackAlignment());
 
   ConstantPool = new (Allocator) MachineConstantPool(getDataLayout());
-  Alignment = STI->getTargetLowering()->getMinFunctionAlignment();
+  LogAlignment = STI->getTargetLowering()->getMinFunctionLogAlignment();
 
   // FIXME: Shouldn't use pref alignment if explicit alignment is set on F.
   // FIXME: Use Function::hasOptSize().
   if (!F.hasFnAttribute(Attribute::OptimizeForSize))
-    Alignment = std::max(Alignment,
-                         STI->getTargetLowering()->getPrefFunctionAlignment());
+    LogAlignment = std::max(
+        LogAlignment, STI->getTargetLowering()->getPrefFunctionLogAlignment());
 
   if (AlignAllFunctions)
-    Alignment = AlignAllFunctions;
+    LogAlignment = AlignAllFunctions;
 
   JumpTableInfo = nullptr;
 
   if (isFuncletEHPersonality(classifyEHPersonality(
           F.hasPersonalityFn() ? F.getPersonalityFn() : nullptr))) {
     WinEHInfo = new (Allocator) WinEHFuncInfo();
   }
 

llvm/trunk/lib/CodeGen/PatchableFunction.cpp

auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(),
                      TII->get(TargetOpcode::PATCHABLE_OP))
                  .addImm(2)
                  .addImm(FirstActualI->getOpcode());
 
   for (auto &MO : FirstActualI->operands())
     MIB.add(MO);
 
   FirstActualI->eraseFromParent();
-  MF.ensureAlignment(4);
+  MF.ensureLogAlignment(4);
   return true;
 }
 
 char PatchableFunction::ID = 0;
 char &llvm::PatchableFunctionID = PatchableFunction::ID;
 INITIALIZE_PASS(PatchableFunction, "patchable-function",
                 "Implement the 'patchable-function' attribute", false, false)

llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp

TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
   JumpIsExpensive = JumpIsExpensiveOverride;
   PredictableSelectIsExpensive = false;
   EnableExtLdPromotion = false;
   StackPointerRegisterToSaveRestore = 0;
   BooleanContents = UndefinedBooleanContent;
   BooleanFloatContents = UndefinedBooleanContent;
   BooleanVectorContents = UndefinedBooleanContent;
   SchedPreferenceInfo = Sched::ILP;
-  MinFunctionAlignment = 0;
-  PrefFunctionAlignment = 0;
-  PrefLoopAlignment = 0;
+  MinFunctionLogAlignment = 0;
+  PrefFunctionLogAlignment = 0;
+  PrefLoopLogAlignment = 0;
   GatherAllAliasesMaxDepth = 18;
   MinStackArgumentAlignment = 1;
   // TODO: the default will be switched to 0 in the next commit, along
   // with the Target-specific changes necessary.
   MaxAtomicSizeInBitsSupported = 1024;
 
   MinCmpXchgSizeInBits = 0;
   SupportsUnalignedAtomics = false;

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
 
   setStackPointerRegisterToSaveRestore(AArch64::SP);
 
   setSchedulingPreference(Sched::Hybrid);
 
   EnableExtLdPromotion = true;
 
   // Set required alignment.
-  setMinFunctionAlignment(2);
+  setMinFunctionLogAlignment(2);
   // Set preferred alignments.
-  setPrefFunctionAlignment(STI.getPrefFunctionAlignment());
-  setPrefLoopAlignment(STI.getPrefLoopAlignment());
+  setPrefFunctionLogAlignment(STI.getPrefFunctionLogAlignment());
+  setPrefLoopLogAlignment(STI.getPrefLoopLogAlignment());
 
   // Only change the limit for entries in a jump table if specified by
   // the sub target, but not at the command line.
   unsigned MaxJT = STI.getMaximumJumpTableSize();
   if (MaxJT && getMaximumJumpTableSize() == UINT_MAX)
     setMaximumJumpTableSize(MaxJT);
 
   setHasExtractBitsInsn(true);

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool UseEL3ForTP = false;
   bool AllowTaggedGlobals = false;
   uint8_t MaxInterleaveFactor = 2;
   uint8_t VectorInsertExtractBaseCost = 3;
   uint16_t CacheLineSize = 0;
   uint16_t PrefetchDistance = 0;
   uint16_t MinPrefetchStride = 1;
   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
-  unsigned PrefFunctionAlignment = 0;
-  unsigned PrefLoopAlignment = 0;
+  unsigned PrefFunctionLogAlignment = 0;
+  unsigned PrefLoopLogAlignment = 0;
   unsigned MaxJumpTableSize = 0;
   unsigned WideningBaseCost = 0;
 
   // ReserveXRegister[i] - X#i is not available as a general purpose register.
   BitVector ReserveXRegister;
 
   // CustomCallUsedXRegister[i] - X#i call saved.
   BitVector CustomCallSavedXRegs;
unsigned getVectorInsertExtractBaseCost() const {
     return VectorInsertExtractBaseCost;
   }
   unsigned getCacheLineSize() const { return CacheLineSize; }
   unsigned getPrefetchDistance() const { return PrefetchDistance; }
   unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
   unsigned getMaxPrefetchIterationsAhead() const {
     return MaxPrefetchIterationsAhead;
   }
-  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
-  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
+  unsigned getPrefFunctionLogAlignment() const {
+    return PrefFunctionLogAlignment;
+  }
+  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
 
   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
 
   unsigned getWideningBaseCost() const { return WideningBaseCost; }
 
   /// CPU has TBI (top byte of addresses is ignored during HW address
   /// translation) and OS enables it.
   bool supportsAddressTopByteIgnored() const;

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

void AArch64Subtarget::initializeProperties() {
   // this in the future so we can specify it together with the subtarget
   // features.
   switch (ARMProcFamily) {
   case Others:
     break;
   case CortexA35:
     break;
   case CortexA53:
-    PrefFunctionAlignment = 3;
+    PrefFunctionLogAlignment = 3;
     break;
   case CortexA55:
     break;
   case CortexA57:
     MaxInterleaveFactor = 4;
-    PrefFunctionAlignment = 4;
+    PrefFunctionLogAlignment = 4;
     break;
   case CortexA65:
-    PrefFunctionAlignment = 3;
+    PrefFunctionLogAlignment = 3;
     break;
   case CortexA72:
   case CortexA73:
   case CortexA75:
   case CortexA76:
-    PrefFunctionAlignment = 4;
+    PrefFunctionLogAlignment = 4;
     break;
   case Cyclone:
     CacheLineSize = 64;
     PrefetchDistance = 280;
     MinPrefetchStride = 2048;
     MaxPrefetchIterationsAhead = 3;
     break;
   case ExynosM1:
     MaxInterleaveFactor = 4;
     MaxJumpTableSize = 8;
-    PrefFunctionAlignment = 4;
-    PrefLoopAlignment = 3;
+    PrefFunctionLogAlignment = 4;
+    PrefLoopLogAlignment = 3;
     break;
   case ExynosM3:
     MaxInterleaveFactor = 4;
     MaxJumpTableSize = 20;
-    PrefFunctionAlignment = 5;
-    PrefLoopAlignment = 4;
+    PrefFunctionLogAlignment = 5;
+    PrefLoopLogAlignment = 4;
     break;
   case Falkor:
     MaxInterleaveFactor = 4;
     // FIXME: remove this to enable 64-bit SLP if performance looks good.
     MinVectorRegisterBitWidth = 128;
     CacheLineSize = 128;
     PrefetchDistance = 820;
     MinPrefetchStride = 2048;
     MaxPrefetchIterationsAhead = 8;
     break;
   case Kryo:
     MaxInterleaveFactor = 4;
     VectorInsertExtractBaseCost = 2;
     CacheLineSize = 128;
     PrefetchDistance = 740;
     MinPrefetchStride = 1024;
     MaxPrefetchIterationsAhead = 11;
     // FIXME: remove this to enable 64-bit SLP if performance looks good.
     MinVectorRegisterBitWidth = 128;
     break;
   case NeoverseE1:
-    PrefFunctionAlignment = 3;
+    PrefFunctionLogAlignment = 3;
     break;
   case NeoverseN1:
-    PrefFunctionAlignment = 4;
+    PrefFunctionLogAlignment = 4;
     break;
   case Saphira:
     MaxInterleaveFactor = 4;
     // FIXME: remove this to enable 64-bit SLP if performance looks good.
     MinVectorRegisterBitWidth = 128;
     break;
   case ThunderX2T99:
     CacheLineSize = 64;
-    PrefFunctionAlignment = 3;
-    PrefLoopAlignment = 2;
+    PrefFunctionLogAlignment = 3;
+    PrefLoopLogAlignment = 2;
     MaxInterleaveFactor = 4;
     PrefetchDistance = 128;
     MinPrefetchStride = 1024;
     MaxPrefetchIterationsAhead = 4;
     // FIXME: remove this to enable 64-bit SLP if performance looks good.
     MinVectorRegisterBitWidth = 128;
     break;
   case ThunderX:
   case ThunderXT88:
   case ThunderXT81:
   case ThunderXT83:
     CacheLineSize = 128;
-    PrefFunctionAlignment = 3;
-    PrefLoopAlignment = 2;
+    PrefFunctionLogAlignment = 3;
+    PrefLoopLogAlignment = 2;
     // FIXME: remove this to enable 64-bit SLP if performance looks good.
     MinVectorRegisterBitWidth = 128;
     break;
   case TSV110:
     CacheLineSize = 64;
-    PrefFunctionAlignment = 4;
-    PrefLoopAlignment = 2;
+    PrefFunctionLogAlignment = 4;
+    PrefLoopLogAlignment = 2;
     break;
   }
 }
 
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM, bool LittleEndian)
     : AArch64GenSubtargetInfo(TT, CPU, FS),

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 
 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   CurrentProgramInfo = SIProgramInfo();
 
   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
 
   // The starting address of all shader programs must be 256 bytes aligned.
   // Regular functions just need the basic required instruction alignment.
-  MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
+  MF.setLogAlignment(MFI->isEntryFunction() ? 8 : 2);
 
   SetupMachineFunction(MF);
 
   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
   MCContext &Context = getObjFileLowering().getContext();
   // FIXME: This should be an explicit check for Mesa.
   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
     MCSectionELF *ConfigSection =

llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp

if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
   }
 }
 
 bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
 
   // Functions needs to be cacheline (256B) aligned.
-  MF.ensureAlignment(8);
+  MF.ensureLogAlignment(8);
 
   SetupMachineFunction(MF);
 
   MCContext &Context = getObjFileLowering().getContext();
   MCSectionELF *ConfigSection =
       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
   OutStreamer->SwitchSection(ConfigSection);
 

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h

public:
   bool denormalsEnabledForType(EVT VT) const;
 
   bool isKnownNeverNaNForTargetNode(SDValue Op,
                                     const SelectionDAG &DAG,
                                     bool SNaN = false,
                                     unsigned Depth = 0) const override;
   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
 
-  unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
-
+  unsigned getPrefLoopLogAlignment(MachineLoop *ML) const override;
 
   void allocateHSAUserSGPRs(CCState &CCInfo,
                             MachineFunction &MF,
                             const SIRegisterInfo &TRI,
                             SIMachineFunctionInfo &Info) const;
 
   void allocateSystemSGPRs(CCState &CCInfo,
                            MachineFunction &MF,

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

TargetLowering::computeKnownBitsForFrameIndex(Op, Known, DemandedElts,
                                                 DAG, Depth);
 
   // Set the high bits to zero based on the maximum allowed scratch size per
   // wave. We can't use vaddr in MUBUF instructions if we don't know the address
   // calculation won't overflow, so assume the sign bit is never set.
   Known.Zero.setHighBits(getSubtarget()->getKnownHighZeroBitsForFrameIndex());
 }
 
-unsigned SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
-  const unsigned PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
-  const unsigned CacheLineAlign = 6; // log2(64)
+unsigned SITargetLowering::getPrefLoopLogAlignment(MachineLoop *ML) const {
+  const unsigned PrefLogAlign = TargetLowering::getPrefLoopLogAlignment(ML);
+  const unsigned CacheLineLogAlign = 6; // log2(64)
 
   // Pre-GFX10 target did not benefit from loop alignment
   if (!ML || DisableLoopAlignment ||
       (getSubtarget()->getGeneration() < AMDGPUSubtarget::GFX10) ||
       getSubtarget()->hasInstFwdPrefetchBug())
-    return PrefAlign;
+    return PrefLogAlign;
 
   // On GFX10 I$ is 4 x 64 bytes cache lines.
   // By default prefetcher keeps one cache line behind and reads two ahead.
   // We can modify it with S_INST_PREFETCH for larger loops to have two lines
   // behind and one ahead.
   // Therefor we can benefit from aligning loop headers if loop fits 192 bytes.
   // If loop fits 64 bytes it always spans no more than two cache lines and
   // does not need an alignment.
   // Else if loop is less or equal 128 bytes we do not need to modify prefetch,
   // Else if loop is less or equal 192 bytes we need two lines behind.
 
   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
   const MachineBasicBlock *Header = ML->getHeader();
-  if (Header->getAlignment() != PrefAlign)
-    return Header->getAlignment(); // Already processed.
+  if (Header->getLogAlignment() != PrefLogAlign)
+    return Header->getLogAlignment(); // Already processed.
 
   unsigned LoopSize = 0;
   for (const MachineBasicBlock *MBB : ML->blocks()) {
     // If inner loop block is aligned assume in average half of the alignment
     // size to be added as nops.
     if (MBB != Header)
-      LoopSize += (1 << MBB->getAlignment()) / 2;
+      LoopSize += (1 << MBB->getLogAlignment()) / 2;
 
     for (const MachineInstr &MI : *MBB) {
       LoopSize += TII->getInstSizeInBytes(MI);
       if (LoopSize > 192)
-        return PrefAlign;
+        return PrefLogAlign;
     }
   }
 
   if (LoopSize <= 64)
-    return PrefAlign;
+    return PrefLogAlign;
 
   if (LoopSize <= 128)
-    return CacheLineAlign;
+    return CacheLineLogAlign;
 
   // If any of parent loops is surrounded by prefetch instructions do not
   // insert new for inner loop, which would reset parent's settings.
   for (MachineLoop *P = ML->getParentLoop(); P; P = P->getParentLoop()) {
     if (MachineBasicBlock *Exit = P->getExitBlock()) {
       auto I = Exit->getFirstNonDebugInstr();
       if (I != Exit->end() && I->getOpcode() == AMDGPU::S_INST_PREFETCH)
-        return CacheLineAlign;
+        return CacheLineLogAlign;
     }
   }
 
   MachineBasicBlock *Pre = ML->getLoopPreheader();
   MachineBasicBlock *Exit = ML->getExitBlock();
 
   if (Pre && Exit) {
     BuildMI(*Pre, Pre->getFirstTerminator(), DebugLoc(),
             TII->get(AMDGPU::S_INST_PREFETCH))
       .addImm(1); // prefetch 2 lines behind PC
 
     BuildMI(*Exit, Exit->getFirstNonDebugInstr(), DebugLoc(),
             TII->get(AMDGPU::S_INST_PREFETCH))
       .addImm(2); // prefetch 1 line behind PC
   }
 
-  return CacheLineAlign;
+  return CacheLineLogAlign;
 }
 
 LLVM_ATTRIBUTE_UNUSED
 static bool isCopyFromRegOfInlineAsm(const SDNode *N) {
   assert(N->getOpcode() == ISD::CopyFromReg);
   do {
     // Follow the chain until we find an INLINEASM node.
     N = N->getOperand(0).getNode();

llvm/trunk/lib/Target/ARC/ARCMachineFunctionInfo.h

public:
   ARCFunctionInfo()
       : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
         ReturnStackOffset(-1U), MaxCallStackReq(0) {}
 
   explicit ARCFunctionInfo(MachineFunction &MF)
       : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
         ReturnStackOffset(-1U), MaxCallStackReq(0) {
     // Functions are 4-byte (2**2) aligned.
-    MF.setAlignment(2);
+    MF.setLogAlignment(2);
   }
 
   ~ARCFunctionInfo() {}
 
   void setVarArgsFrameIndex(int off) { VarArgsFrameIndex = off; }
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
 
   void setReturnStackOffset(unsigned value) {

llvm/trunk/lib/Target/ARM/ARM.td

 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
                                              "HasVMLxForwarding", "true",
                                              "Has multiplier accumulator forwarding">;
 
 // Disable 32-bit to 16-bit narrowing for experimentation.
 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
                                              "Prefer 32-bit Thumb instrs">;
 
-def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2",
+def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
                                               "Prefer 32-bit alignment for loops">;
 
 def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1",
                         "Model MVE instructions as a 1 beat per tick architecture">;
 
 def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2",
                         "Model MVE instructions as a 2 beats per tick architecture">;
 

llvm/trunk/lib/Target/ARM/ARMBasicBlockInfo.cpp

for (MachineInstr &I : *MBB) {
     // Also consider instructions that may be shrunk later.
     else if (isThumb && mayOptimizeThumb2Instruction(&I))
       BBI.Unalign = 1;
   }
 
   // tBR_JTr contains a .align 2 directive.
   if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
     BBI.PostAlign = 2;
-    MBB->getParent()->ensureAlignment(2);
+    MBB->getParent()->ensureLogAlignment(2);
   }
 }
 
 /// getOffsetOf - Return the current offset of the specified machine instruction
 /// from the start of the function.  This offset changes as stuff is moved
 /// around inside the function.
 unsigned ARMBasicBlockUtils::getOffsetOf(MachineInstr *MI) const {
   const MachineBasicBlock *MBB = MI->getParent();
LLVM_DEBUG(dbgs() << "Adjust block:\n"
              << " - name: " << BB->getName() << "\n"
              << " - number: " << BB->getNumber() << "\n"
              << " - function: " << MF.getName() << "\n"
              << "   - blocks: " << MF.getNumBlockIDs() << "\n");
 
   for(unsigned i = BBNum + 1, e = MF.getNumBlockIDs(); i < e; ++i) {
     // Get the offset and known bits at the end of the layout predecessor.
     // Include the alignment of the current block.
-    unsigned LogAlign = MF.getBlockNumbered(i)->getAlignment();
+    unsigned LogAlign = MF.getBlockNumbered(i)->getLogAlignment();
     unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
     unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
 
     // This is where block i begins.  Stop if the offset is already correct,
     // and we have updated 2 blocks.  This is the maximum number of blocks
     // changed before calling this function.
     if (i > BBNum + 2 &&
         BBInfo[i].Offset == Offset &&

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   // constant pool users.
   initializeFunctionInfo(CPEMIs);
   CPEMIs.clear();
   LLVM_DEBUG(dumpBBs());
 
   // Functions with jump tables need an alignment of 4 because they use the ADR
   // instruction, which aligns the PC to 4 bytes before adding an offset.
   if (!T2JumpTables.empty())
-    MF->ensureAlignment(2);
+    MF->ensureLogAlignment(2);
 
   /// Remove dead constant pool entries.
   MadeChange |= removeUnusedCPEntries();
 
   // Iteratively place constant pool entries and fix up branches until there
   // is no change.
   unsigned NoCPIters = 0, NoBRIters = 0;
   while (true) {

 /// To start with, we put them all at the end of the function.
 void
 ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
   // Create the basic block to hold the CPE's.
   MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
   MF->push_back(BB);
 
   // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
-  unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
+  unsigned MaxLogAlign = Log2_32(MCP->getConstantPoolAlignment());
 
   // Mark the basic block as required by the const-pool.
-  BB->setAlignment(MaxAlign);
+  BB->setLogAlignment(MaxLogAlign);
 
   // The function needs to be as aligned as the basic blocks. The linker may
   // move functions around based on their alignment.
-  MF->ensureAlignment(BB->getAlignment());
+  MF->ensureLogAlignment(BB->getLogAlignment());
 
   // Order the entries in BB by descending alignment.  That ensures correct
   // alignment of all entries as long as BB is sufficiently aligned.  Keep
   // track of the insertion point for each alignment.  We are going to bucket
   // sort the entries as they are created.
-  SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
+  SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxLogAlign + 1,
+                                                       BB->end());
 
   // Add all of the constants from the constant pool to the end block, use an
   // identity mapping of CPI's to CPE's.
   const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
 
   const DataLayout &TD = MF->getDataLayout();
   for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
     unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
     unsigned Align = CPs[i].getAlignment();
     assert(isPowerOf2_32(Align) && "Invalid alignment");
     // Verify that all constant pool entries are a multiple of their alignment.
     // If not, we would have to pad them out so that instructions stay aligned.
     assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!");
 
     // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
     unsigned LogAlign = Log2_32(Align);
     MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
     MachineInstr *CPEMI =
       BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
         .addImm(i).addConstantPoolIndex(i).addImm(Size);
     CPEMIs.push_back(CPEMI);
 
     // Ensure that future entries with higher alignment get inserted before
     // CPEMI. This is bucket sort with iterators.
-    for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
+    for (unsigned a = LogAlign + 1; a <= MaxLogAlign; ++a)
       if (InsPoint[a] == InsAt)
         InsPoint[a] = CPEMI;
 
     // Add a new CPEntry, but no corresponding CPUser yet.
     CPEntries.emplace_back(1, CPEntry(CPEMI, i));
     ++NumCPEs;
     LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
                       << Size << ", align = " << Align << '\n');

 /// and finding all of the constant pool users.
 void ARMConstantIslands::
 initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
 
   BBUtils->computeAllBlockSizes();
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
   // The known bits of the entry block offset are determined by the function
   // alignment.
-  BBInfo.front().KnownBits = MF->getAlignment();
+  BBInfo.front().KnownBits = MF->getLogAlignment();
 
   // Compute block offsets and known bits.
   BBUtils->adjustBBOffsetsAfter(&MF->front());
 
   // Now go back through the instructions and build up our data structures.
   for (MachineBasicBlock &MBB : *MF) {
     // If this block doesn't fall through into the next MBB, then this is
     // 'water' that a constant pool island could be placed.

 ///
 /// Compute how much the function will grow by inserting a CPE after Water.
 bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
                                         MachineBasicBlock* Water, CPUser &U,
                                         unsigned &Growth) {
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
   unsigned CPELogAlign = getCPELogAlign(U.CPEMI);
   unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
-  unsigned NextBlockOffset, NextBlockAlignment;
+  unsigned NextBlockOffset, NextBlockLogAlignment;
   MachineFunction::const_iterator NextBlock = Water->getIterator();
   if (++NextBlock == MF->end()) {
     NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
-    NextBlockAlignment = 0;
+    NextBlockLogAlignment = 0;
   } else {
     NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
-    NextBlockAlignment = NextBlock->getAlignment();
+    NextBlockLogAlignment = NextBlock->getLogAlignment();
   }
   unsigned Size = U.CPEMI->getOperand(2).getImm();
   unsigned CPEEnd = CPEOffset + Size;
 
   // The CPE may be able to hide in the alignment padding before the next
   // block. It may also cause more padding to be required if it is more aligned
   // that the next block.
   if (CPEEnd > NextBlockOffset) {
     Growth = CPEEnd - NextBlockOffset;
     // Compute the padding that would go at the end of the CPE to align the next
     // block.
-    Growth += OffsetToAlignment(CPEEnd, 1ULL << NextBlockAlignment);
+    Growth += OffsetToAlignment(CPEEnd, 1ULL << NextBlockLogAlignment);
 
     // If the CPE is to be inserted before the instruction, that will raise
     // the offset of the instruction. Also account for unknown alignment padding
     // in blocks between CPE and the user.
     if (CPEOffset < UserOffset)
-      UserOffset += Growth + UnknownPadding(MF->getAlignment(), CPELogAlign);
+      UserOffset += Growth + UnknownPadding(MF->getLogAlignment(), CPELogAlign);
   } else
     // CPE fits in existing padding.
     Growth = 0;
 
   return isOffsetInRange(UserOffset, CPEOffset, U);
 }
 
 /// isCPEntryInRange - Returns true if the distance between specific MI and
void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
   // the instructions between the one currently being looked at and the
   // possible insertion point, and make sure any other instructions that
   // reference CPEs will be able to use the same island area; if not, we back
   // up the insertion point.
 
   // Try to split the block so it's fully aligned.  Compute the latest split
   // point where we can add a 4-byte branch instruction, and then align to
   // LogAlign which is the largest possible alignment in the function.
-  unsigned LogAlign = MF->getAlignment();
+  unsigned LogAlign = MF->getLogAlignment();
   assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
   unsigned KnownBits = UserBBI.internalKnownBits();
   unsigned UPad = UnknownPadding(LogAlign, KnownBits);
   unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
   LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
                               BaseInsertOffset));
 
   // The 4 in the following is for the unconditional branch we'll be inserting
if (IP != WaterList.end())
       NewWaterList.erase(WaterBB);
 
     // We are adding new water.  Update NewWaterList.
     NewWaterList.insert(NewIsland);
   }
   // Always align the new block because CP entries can be smaller than 4
   // bytes. Be careful not to decrease the existing alignment, e.g. NewMBB may
   // be an already aligned constant pool block.
-  const unsigned Align = isThumb ? 1 : 2;
-  if (NewMBB->getAlignment() < Align)
-    NewMBB->setAlignment(Align);
+  const unsigned LogAlign = isThumb ? 1 : 2;
+  if (NewMBB->getLogAlignment() < LogAlign)
+    NewMBB->setLogAlignment(LogAlign);
 
   // Remove the original WaterList entry; we want subsequent insertions in
   // this vicinity to go after the one we're about to insert.  This
   // considerably reduces the number of times we have to move the same CPE
   // more than once and is also important to ensure the algorithm terminates.
   if (IP != WaterList.end())
     WaterList.erase(IP);
 
U.CPEMI = BuildMI(NewIsland, DebugLoc(), CPEMI->getDesc())
                 .addImm(Size);
   CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
   ++NumCPEs;
 
   // Decrement the old entry, and remove it if refcount becomes 0.
   decrementCPEReferenceCount(CPI, CPEMI);
 
   // Mark the basic block as aligned as required by the const-pool entry.
-  NewIsland->setAlignment(getCPELogAlign(U.CPEMI));
+  NewIsland->setLogAlignment(getCPELogAlign(U.CPEMI));
 
   // Increase the size of the island block to account for the new entry.
   BBUtils->adjustBBSize(NewIsland, Size);
   BBUtils->adjustBBOffsetsAfter(&*--NewIsland->getIterator());
 
   // Finally, change the CPI in the instruction operand to be ID.
   for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
     if (UserMI->getOperand(i).isCPI()) {
void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
   CPEMI->eraseFromParent();
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
   BBUtils->adjustBBSize(CPEBB, -Size);
   // All succeeding offsets have the current size value added in, fix this.
   if (CPEBB->empty()) {
     BBInfo[CPEBB->getNumber()].Size = 0;
 
     // This block no longer needs to be aligned.
-    CPEBB->setAlignment(0);
+    CPEBB->setLogAlignment(0);
   } else
     // Entries are sorted by descending alignment, so realign from the front.
-    CPEBB->setAlignment(getCPELogAlign(&*CPEBB->begin()));
+    CPEBB->setLogAlignment(getCPELogAlign(&*CPEBB->begin()));
 
   BBUtils->adjustBBOffsetsAfter(CPEBB);
   // An island has only one predecessor BB and one successor BB. Check if
   // this BB's predecessor jumps directly to this BB's successor. This
   // shouldn't happen currently.
   assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
   // FIXME: remove the empty blocks after all the work is done?
 }

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

 
   // On ARM arguments smaller than 4 bytes are extended, so all arguments
   // are at least 4 bytes aligned.
   setMinStackArgumentAlignment(4);
 
   // Prefer likely predicted branches to selects on out-of-order cores.
   PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
 
-  setPrefLoopAlignment(Subtarget->getPrefLoopAlignment());
+  setPrefLoopLogAlignment(Subtarget->getPrefLoopLogAlignment());
 
-  setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
+  setMinFunctionLogAlignment(Subtarget->isThumb() ? 1 : 2);
 
   if (Subtarget->isThumb() || Subtarget->isThumb2())
     setTargetDAGCombine(ISD::ABS);
 }
 
 bool ARMTargetLowering::useSoftFloat() const {
   return Subtarget->useSoftFloat();
 }

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

protected:
   /// single issue etc).
   ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
 
   /// The adjustment that we need to apply to get the operand latency from the
   /// operand cycle returned by the itinerary data for pre-ISel operands.
   int PreISelOperandLatencyAdjustment = 2;
 
   /// What alignment is preferred for loop bodies, in log2(bytes).
-  unsigned PrefLoopAlignment = 0;
+  unsigned PrefLoopLogAlignment = 0;
 
   /// The cost factor for MVE instructions, representing the multiple beats an
   // instruction can take. The default is 2, (set in initSubtargetFeatures so
   // that we can use subtarget features less than 2).
   unsigned MVEVectorCostFactor = 0;
 
   /// OptMinSize - True if we're optimising for minimum code size, equal to
   /// the function attribute.
public:
 
   /// Allow movt+movw for PIC global address calculation.
   /// ELF does not have GOT relocations for movt+movw.
   /// ROPI does not use GOT.
   bool allowPositionIndependentMovt() const {
     return isROPI() || !isTargetELF();
   }
 
-  unsigned getPrefLoopAlignment() const {
-    return PrefLoopAlignment;
-  }
+  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
 
   unsigned getMVEVectorCostFactor() const { return MVEVectorCostFactor; }
 
   bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
                                    unsigned PhysReg) const override;
   unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
 };
 
 } // end namespace llvm
 
 #endif  // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   case CortexR7:
   case CortexM3:
   case CortexR52:
     break;
   case Exynos:
     LdStMultipleTiming = SingleIssuePlusExtras;
     MaxInterleaveFactor = 4;
     if (!isThumb())
-      PrefLoopAlignment = 3;
+      PrefLoopLogAlignment = 3;
     break;
   case Kryo:
     break;
   case Krait:
     PreISelOperandLatencyAdjustment = 1;
     break;
   case NeoverseN1:
     break;

llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp

AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
   setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
   setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN);
   setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
 
   // Trigonometric rtlib functions
   setLibcallName(RTLIB::SIN_F32, "sin");
   setLibcallName(RTLIB::COS_F32, "cos");
 
-  setMinFunctionAlignment(1);
+  setMinFunctionLogAlignment(1);
   setMinimumJumpTableEntries(UINT_MAX);
 }
 
 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
 #define NODE(name)       \
   case AVRISD::name:     \
     return #name
 

llvm/trunk/lib/Target/BPF/BPFISelLowering.cpp

for (MVT VT : MVT::integer_valuetypes()) {
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
   }
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
   // Function alignments (log2)
-  setMinFunctionAlignment(3);
-  setPrefFunctionAlignment(3);
+  setMinFunctionLogAlignment(3);
+  setPrefFunctionLogAlignment(3);
 
   if (BPFExpandMemcpyInOrder) {
     // LLVM generic code will try to expand memcpy into load/store pairs at this
     // stage which is before quite a few IR optimization passes, therefore the
     // loads and stores could potentially be moved apart from each other which
     // will cause trouble to memcpy pattern matcher inside kernel eBPF JIT
     // compilers.
     //

llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp

bool HexagonBranchRelaxation::runOnMachineFunction(MachineFunction &MF) {
   return Changed;
 }
 
 void HexagonBranchRelaxation::computeOffset(MachineFunction &MF,
       DenseMap<MachineBasicBlock*, unsigned> &OffsetMap) {
   // offset of the current instruction from the start.
   unsigned InstOffset = 0;
   for (auto &B : MF) {
-    if (B.getAlignment()) {
+    if (B.getLogAlignment()) {
       // Although we don't know the exact layout of the final code, we need
       // to account for alignment padding somehow. This heuristic pads each
       // aligned basic block according to the alignment value.
-      int ByteAlign = (1u << B.getAlignment()) - 1;
+      int ByteAlign = (1u << B.getLogAlignment()) - 1;
       InstOffset = (InstOffset + ByteAlign) & ~(ByteAlign);
     }
     OffsetMap[&B] = InstOffset;
     for (auto &MI : B.instrs()) {
       InstOffset += HII->getSize(MI);
       // Assume that all extendable branches will be extended.
       if (MI.isBranch() && HII->isExtendable(MI))
         InstOffset += HEXAGON_INSTR_SIZE;

llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp

bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
   // Map for each basic block to it's first instruction.
   DenseMap<const MachineBasicBlock *, unsigned> BlockToInstOffset;
 
   const HexagonInstrInfo *HII =
       static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
 
   // First pass - compute the offset of each basic block.
   for (const MachineBasicBlock &MBB : MF) {
-    if (MBB.getAlignment()) {
+    if (MBB.getLogAlignment()) {
       // Although we don't know the exact layout of the final code, we need
       // to account for alignment padding somehow. This heuristic pads each
       // aligned basic block according to the alignment value.
-      int ByteAlign = (1u << MBB.getAlignment()) - 1;
+      int ByteAlign = (1u << MBB.getLogAlignment()) - 1;
       InstOffset = (InstOffset + ByteAlign) & ~(ByteAlign);
     }
 
     BlockToInstOffset[&MBB] = InstOffset;
     for (const MachineInstr &MI : MBB)
       InstOffset += HII->getSize(MI);
   }
 

llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

 //===----------------------------------------------------------------------===//
 
 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
                                              const HexagonSubtarget &ST)
     : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
       Subtarget(ST) {
   auto &HRI = *Subtarget.getRegisterInfo();
 
-  setPrefLoopAlignment(4);
-  setPrefFunctionAlignment(4);
-  setMinFunctionAlignment(2);
+  setPrefLoopLogAlignment(4);
+  setPrefFunctionLogAlignment(4);
+  setMinFunctionLogAlignment(2);
   setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
   setBooleanContents(TargetLoweringBase::UndefinedBooleanContent);
   setBooleanVectorContents(TargetLoweringBase::UndefinedBooleanContent);
 
   setMaxAtomicSizeInBitsSupported(64);
   setMinCmpXchgSizeInBits(32);
 
   if (EnableHexSDNodeSched)

llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp

LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
 
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::AND);
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::XOR);
 
   // Function alignments (log2)
-  setMinFunctionAlignment(2);
-  setPrefFunctionAlignment(2);
+  setMinFunctionLogAlignment(2);
+  setPrefFunctionLogAlignment(2);
 
   setJumpIsExpensive(true);
 
   // TODO: Setting the minimum jump table entries needed before a
   // switch is transformed to a jump table to 100 to avoid creating jump tables
   // as this was causing bad performance compared to a large group of if
   // statements. Re-evaluate this on new benchmarks.
   setMinimumJumpTableEntries(100);

llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp

MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
   setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN);
   setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN);
   setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN);
   setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN);
   setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN);
   setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN);
   // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
 
-  setMinFunctionAlignment(1);
-  setPrefFunctionAlignment(1);
+  setMinFunctionLogAlignment(1);
+  setPrefFunctionLogAlignment(1);
 }
 
 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
                                              SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   case ISD::SHL: // FALLTHROUGH
   case ISD::SRL:
   case ISD::SRA:              return LowerShifts(Op, DAG);

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h

 //===-- MipsMCNaCl.h - NaCl-related declarations --------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
 
 #include "llvm/MC/MCELFStreamer.h"
 
 namespace llvm {
 
 // Log2 of the NaCl MIPS sandbox's instruction bundle size.
-static const unsigned MIPS_NACL_BUNDLE_ALIGN = 4u;
+static const unsigned MIPS_NACL_BUNDLE_LOG_ALIGN = 4u;
 
 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
                                   bool *IsStore = nullptr);
 bool baseRegNeedsLoadStoreMask(unsigned Reg);
 
 // This function creates an MCELFStreamer for Mips NaCl.
 MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
                                          std::unique_ptr<MCAsmBackend> TAB,
                                          std::unique_ptr<MCObjectWriter> OW,
                                          std::unique_ptr<MCCodeEmitter> Emitter,
                                          bool RelaxAll);
 }
 
 #endif

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp

MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
                                          std::unique_ptr<MCCodeEmitter> Emitter,
                                          bool RelaxAll) {
   MipsNaClELFStreamer *S = new MipsNaClELFStreamer(
       Context, std::move(TAB), std::move(OW), std::move(Emitter));
   if (RelaxAll)
     S->getAssembler().setRelaxAll(true);
 
   // Set bundle-alignment as required by the NaCl ABI for the target.
-  S->EmitBundleAlignMode(MIPS_NACL_BUNDLE_ALIGN);
+  S->EmitBundleAlignMode(MIPS_NACL_BUNDLE_LOG_ALIGN);
 
   return S;
 }
 
 } // end namespace llvm

llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp

 }
 
 void MipsAsmPrinter::EmitFunctionEntryLabel() {
   MipsTargetStreamer &TS = getTargetStreamer();
 
   // NaCl sandboxing requires that indirect call instructions are masked.
   // This means that function entry points should be bundle-aligned.
   if (Subtarget->isTargetNaCl())
-    EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
+    EmitAlignment(std::max(MF->getLogAlignment(), MIPS_NACL_BUNDLE_LOG_ALIGN));
 
   if (Subtarget->inMicroMipsMode()) {
     TS.emitDirectiveSetMicroMips();
     TS.setUsesMicroMips();
     TS.updateABIInfo(*Subtarget);
   } else
     TS.emitDirectiveSetNoMicroMips();
 

 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
   // Align all blocks that are jumped to through jump table.
   if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
     const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
     for (unsigned I = 0; I < JT.size(); ++I) {
       const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
 
       for (unsigned J = 0; J < MBBs.size(); ++J)
-        MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
+        MBBs[J]->setLogAlignment(MIPS_NACL_BUNDLE_LOG_ALIGN);
     }
   }
 
   // If basic block address is taken, block can be target of indirect branch.
   for (auto &MBB : MF) {
     if (MBB.hasAddressTaken())
-      MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
+      MBB.setLogAlignment(MIPS_NACL_BUNDLE_LOG_ALIGN);
   }
 }
 
 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
   return (Opcode == Mips::LONG_BRANCH_LUi
           || Opcode == Mips::LONG_BRANCH_LUi2Op
           || Opcode == Mips::LONG_BRANCH_LUi2Op_64
           || Opcode == Mips::LONG_BRANCH_ADDiu

llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp

if (!ABI.IsN64()) {
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
           .addReg(Mips::RA)
           .addReg(Mips::AT);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
           .addReg(Mips::SP)
           .addImm(0);
       if (STI->isTargetNaCl())
         // Bundle-align the target of indirect branch JR.
-        TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
+        TgtMBB->setLogAlignment(MIPS_NACL_BUNDLE_LOG_ALIGN);
 
       // In NaCl, modifying the sp is not allowed in branch delay slot.
       // For MIPS32R6, we can skip using a delay slot branch.
       bool hasDelaySlot = buildProperJumpMI(BalTgtMBB, Pos, DL);
 
       if (STI->isTargetNaCl() || !hasDelaySlot) {
         BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
             .addReg(Mips::SP)

llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp

 /// entries.  To start with, we put them all at the end of the function.
 void
 MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) {
   // Create the basic block to hold the CPE's.
   MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
   MF->push_back(BB);
 
   // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
-  unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
+  unsigned MaxLogAlign = Log2_32(MCP->getConstantPoolAlignment());
 
   // Mark the basic block as required by the const-pool.
   // If AlignConstantIslands isn't set, use 4-byte alignment for everything.
-  BB->setAlignment(AlignConstantIslands ? MaxAlign : 2);
+  BB->setLogAlignment(AlignConstantIslands ? MaxLogAlign : 2);
 
   // The function needs to be as aligned as the basic blocks. The linker may
   // move functions around based on their alignment.
-  MF->ensureAlignment(BB->getAlignment());
+  MF->ensureLogAlignment(BB->getLogAlignment());
 
   // Order the entries in BB by descending alignment.  That ensures correct
   // alignment of all entries as long as BB is sufficiently aligned.  Keep
   // track of the insertion point for each alignment.  We are going to bucket
   // sort the entries as they are created.
-  SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
+  SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxLogAlign + 1,
+                                                       BB->end());
 
   // Add all of the constants from the constant pool to the end block, use an
   // identity mapping of CPI's to CPE's.
   const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
 
   const DataLayout &TD = MF->getDataLayout();
   for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
     unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
     MachineInstr *CPEMI =
       BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
         .addImm(i).addConstantPoolIndex(i).addImm(Size);
 
     CPEMIs.push_back(CPEMI);
 
     // Ensure that future entries with higher alignment get inserted before
     // CPEMI. This is bucket sort with iterators.
-    for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
+    for (unsigned a = LogAlign + 1; a <= MaxLogAlign; ++a)
       if (InsPoint[a] == InsAt)
         InsPoint[a] = CPEMI;
     // Add a new CPEntry, but no corresponding CPUser yet.
     CPEntries.emplace_back(1, CPEntry(CPEMI, i));
     ++NumCPEs;
     LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
                       << Size << ", align = " << Align << '\n');
   }

 /// Water (a basic block) will be in range for the specific MI.
 ///
 /// Compute how much the function will grow by inserting a CPE after Water.
 bool MipsConstantIslands::isWaterInRange(unsigned UserOffset,
                                         MachineBasicBlock* Water, CPUser &U,
                                         unsigned &Growth) {
   unsigned CPELogAlign = getCPELogAlign(*U.CPEMI);
   unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
-  unsigned NextBlockOffset, NextBlockAlignment;
+  unsigned NextBlockOffset, NextBlockLogAlignment;
   MachineFunction::const_iterator NextBlock = ++Water->getIterator();
   if (NextBlock == MF->end()) {
     NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
-    NextBlockAlignment = 0;
+    NextBlockLogAlignment = 0;
   } else {
     NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
-    NextBlockAlignment = NextBlock->getAlignment();
+    NextBlockLogAlignment = NextBlock->getLogAlignment();
   }
   unsigned Size = U.CPEMI->getOperand(2).getImm();
   unsigned CPEEnd = CPEOffset + Size;
 
   // The CPE may be able to hide in the alignment padding before the next
   // block. It may also cause more padding to be required if it is more aligned
   // that the next block.
   if (CPEEnd > NextBlockOffset) {
     Growth = CPEEnd - NextBlockOffset;
     // Compute the padding that would go at the end of the CPE to align the next
     // block.
-    Growth += OffsetToAlignment(CPEEnd, 1ULL << NextBlockAlignment);
+    Growth += OffsetToAlignment(CPEEnd, 1ULL << NextBlockLogAlignment);
 
     // If the CPE is to be inserted before the instruction, that will raise
     // the offset of the instruction. Also account for unknown alignment padding
     // in blocks between CPE and the user.
     if (CPEOffset < UserOffset)
       UserOffset += Growth;
   } else
     // CPE fits in existing padding.
if (BBHasFallthrough(UserMBB)) {
     }
   }
 
   // What a big block.  Find a place within the block to split it.
 
   // Try to split the block so it's fully aligned.  Compute the latest split
   // point where we can add a 4-byte branch instruction, and then align to
   // LogAlign which is the largest possible alignment in the function.
-  unsigned LogAlign = MF->getAlignment();
+  unsigned LogAlign = MF->getLogAlignment();
   assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
   unsigned BaseInsertOffset = UserOffset + U.getMaxDisp();
   LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
                               BaseInsertOffset));
 
   // The 4 in the following is for the unconditional branch we'll be inserting
   // Alignment of the island is handled
   // inside isOffsetInRange.
bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
   // add it to the island.
   U.HighWaterMark = NewIsland;
   U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
                 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
   CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
   ++NumCPEs;
 
   // Mark the basic block as aligned as required by the const-pool entry.
-  NewIsland->setAlignment(getCPELogAlign(*U.CPEMI));
+  NewIsland->setLogAlignment(getCPELogAlign(*U.CPEMI));
 
   // Increase the size of the island block to account for the new entry.
   BBInfo[NewIsland->getNumber()].Size += Size;
   adjustBBOffsetsAfter(&*--NewIsland->getIterator());
 
   // Finally, change the CPI in the instruction operand to be ID.
   for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
     if (UserMI->getOperand(i).isCPI()) {
void MipsConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
   unsigned Size = CPEMI->getOperand(2).getImm();
   CPEMI->eraseFromParent();
   BBInfo[CPEBB->getNumber()].Size -= Size;
   // All succeeding offsets have the current size value added in, fix this.
   if (CPEBB->empty()) {
     BBInfo[CPEBB->getNumber()].Size = 0;
 
     // This block no longer needs to be aligned.
-    CPEBB->setAlignment(0);
+    CPEBB->setLogAlignment(0);
   } else
     // Entries are sorted by descending alignment, so realign from the front.
-    CPEBB->setAlignment(getCPELogAlign(*CPEBB->begin()));
+    CPEBB->setLogAlignment(getCPELogAlign(*CPEBB->begin()));
 
   adjustBBOffsetsAfter(CPEBB);
   // An island has only one predecessor BB and one successor BB. Check if
   // this BB's predecessor jumps directly to this BB's successor. This
   // shouldn't happen currently.
   assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
   // FIXME: remove the empty blocks after all the work is done?
 }
else {
     // just reducing the bits by 1 as I've done is correct.
     // The basic block we are branching too much be longword aligned.
     // we know that RA is saved because we always save it right now.
     // this requirement will be relaxed later but we also have an alternate
     // way to implement this that I will implement that does not need jal.
     // We should have a way to back out this alignment restriction if we "can" later.
     // but it is not harmful.
     //
-    DestBB->setAlignment(2);
+    DestBB->setLogAlignment(2);
     Br.MaxDisp = ((1<<24)-1) * 2;
     MI->setDesc(TII->get(Mips::JalB16));
   }
   BBInfo[MBB->getNumber()].Size += 2;
   adjustBBOffsetsAfter(MBB);
   HasFarJump = true;
   ++NumUBrFixed;
 

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
 
   if (ABI.IsO32()) {
     // These libcalls are not available in 32-bit.
     setLibcallName(RTLIB::SHL_I128, nullptr);
     setLibcallName(RTLIB::SRL_I128, nullptr);
     setLibcallName(RTLIB::SRA_I128, nullptr);
   }
 
-  setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
+  setMinFunctionLogAlignment(Subtarget.isGP64bit() ? 3 : 2);
 
   // The arguments on the stack are defined in terms of 4-byte slots on O32
   // and 8-byte slots on N32/N64.
   setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
 
   setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
 
   MaxStoresPerMemcpy = 16;

llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp

 FunctionPass *llvm::createPPCBranchSelectionPass() {
   return new PPCBSel();
 }
 
 /// In order to make MBB aligned, we need to add an adjustment value to the
 /// original Offset.
 unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB,
                                          unsigned Offset) {
-  unsigned Align = MBB.getAlignment();
-  if (!Align)
+  unsigned LogAlign = MBB.getLogAlignment();
+  if (!LogAlign)
     return 0;
 
-  unsigned AlignAmt = 1 << Align;
-  unsigned ParentAlign = MBB.getParent()->getAlignment();
+  unsigned AlignAmt = 1 << LogAlign;
+  unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
 
-  if (Align <= ParentAlign)
+  if (LogAlign <= ParentLogAlign)
     return OffsetToAlignment(Offset, AlignAmt);
 
   // The alignment of this MBB is larger than the function's alignment, so we
   // can't tell whether or not it will insert nops. Assume that it will.
   if (FirstImpreciseBlock < 0)
     FirstImpreciseBlock = MBB.getNumber();
   return AlignAmt + OffsetToAlignment(Offset, AlignAmt);
 }

 
 /// Determine the offset from the branch in Src block to the Dest block.
 /// BrOffset is the offset of the branch instruction inside Src block.
 int PPCBSel::computeBranchSize(MachineFunction &Fn,
                                const MachineBasicBlock *Src,
                                const MachineBasicBlock *Dest,
                                unsigned BrOffset) {
   int BranchSize;
-  unsigned MaxAlign = 2;
+  unsigned MaxLogAlign = 2;
   bool NeedExtraAdjustment = false;
   if (Dest->getNumber() <= Src->getNumber()) {
     // If this is a backwards branch, the delta is the offset from the
     // start of this block to this branch, plus the sizes of all blocks
     // from this block to the dest.
     BranchSize = BrOffset;
-    MaxAlign = std::max(MaxAlign, Src->getAlignment());
+    MaxLogAlign = std::max(MaxLogAlign, Src->getLogAlignment());
 
     int DestBlock = Dest->getNumber();
     BranchSize += BlockSizes[DestBlock].first;
     for (unsigned i = DestBlock+1, e = Src->getNumber(); i < e; ++i) {
       BranchSize += BlockSizes[i].first;
-      MaxAlign = std::max(MaxAlign,
-                          Fn.getBlockNumbered(i)->getAlignment());
+      MaxLogAlign =
+          std::max(MaxLogAlign, Fn.getBlockNumbered(i)->getLogAlignment());
     }
 
     NeedExtraAdjustment = (FirstImpreciseBlock >= 0) &&
                           (DestBlock >= FirstImpreciseBlock);
   } else {
     // Otherwise, add the size of the blocks between this block and the
     // dest to the number of bytes left in this block.
     unsigned StartBlock = Src->getNumber();
     BranchSize = BlockSizes[StartBlock].first - BrOffset;
 
-    MaxAlign = std::max(MaxAlign, Dest->getAlignment());
+    MaxLogAlign = std::max(MaxLogAlign, Dest->getLogAlignment());
     for (unsigned i = StartBlock+1, e = Dest->getNumber(); i != e; ++i) {
       BranchSize += BlockSizes[i].first;
-      MaxAlign = std::max(MaxAlign,
-                          Fn.getBlockNumbered(i)->getAlignment());
+      MaxLogAlign =
+          std::max(MaxLogAlign, Fn.getBlockNumbered(i)->getLogAlignment());
     }
 
     NeedExtraAdjustment = (FirstImpreciseBlock >= 0) &&
                           (Src->getNumber() >= FirstImpreciseBlock);
   }
 
   // We tend to over estimate code size due to large alignment and
   // inline assembly. Usually it causes larger computed branch offset.
int PPCBSel::computeBranchSize(MachineFunction &Fn,
   // is at most <delta> more than estimated padding bytes. So the actual
   // aligned block address is less than or equal to the estimated aligned
   // block address. So the actual branch offset is less than or equal to
   // computed branch offset.
   //
   // The computed offset is at most ((1 << alignment) - 4) bytes smaller
   // than actual offset. So we add this number to the offset for safety.
   if (NeedExtraAdjustment)
-    BranchSize += (1 << MaxAlign) - 4;
+    BranchSize += (1 << MaxLogAlign) - 4;
 
   return BranchSize;
 }
 
 bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
   const PPCInstrInfo *TII =
       static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
   // Give the blocks of the function a dense, in-order, numbering.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

unsigned getRegisterByName(const char* RegName, EVT VT,
                                SelectionDAG &DAG) const override;
 
     void computeKnownBitsForTargetNode(const SDValue Op,
                                        KnownBits &Known,
                                        const APInt &DemandedElts,
                                        const SelectionDAG &DAG,
                                        unsigned Depth = 0) const override;
 
-    unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
+    unsigned getPrefLoopLogAlignment(MachineLoop *ML) const override;
 
     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
       return true;
     }
 
     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
                                   AtomicOrdering Ord) const override;
     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

 
   // With 32 condition bits, we don't need to sink (and duplicate) compares
   // aggressively in CodeGenPrep.
   if (Subtarget.useCRBits()) {
     setHasMultipleConditionRegisters();
     setJumpIsExpensive();
   }
 
-  setMinFunctionAlignment(2);
+  setMinFunctionLogAlignment(2);
   if (Subtarget.isDarwin())
-    setPrefFunctionAlignment(4);
+    setPrefFunctionLogAlignment(4);
 
   switch (Subtarget.getDarwinDirective()) {
   default: break;
   case PPC::DIR_970:
   case PPC::DIR_A2:
   case PPC::DIR_E500:
   case PPC::DIR_E500mc:
   case PPC::DIR_E5500:
   case PPC::DIR_PWR4:
   case PPC::DIR_PWR5:
   case PPC::DIR_PWR5X:
   case PPC::DIR_PWR6:
   case PPC::DIR_PWR6X:
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
-    setPrefFunctionAlignment(4);
-    setPrefLoopAlignment(4);
+    setPrefFunctionLogAlignment(4);
+    setPrefLoopLogAlignment(4);
     break;
   }
 
   if (Subtarget.enableMachineScheduler())
     setSchedulingPreference(Sched::Source);
   else
     setSchedulingPreference(Sched::Hybrid);
 
case ISD::INTRINSIC_WO_CHAIN: {
     case Intrinsic::ppc_altivec_vcmpgtud_p:
       Known.Zero = ~1U;  // All bits but the low one are known to be zero.
       break;
     }
   }
   }
 }
 
-unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
+unsigned PPCTargetLowering::getPrefLoopLogAlignment(MachineLoop *ML) const {
   switch (Subtarget.getDarwinDirective()) {
   default: break;
   case PPC::DIR_970:
   case PPC::DIR_PWR4:
   case PPC::DIR_PWR5:
   case PPC::DIR_PWR5X:
   case PPC::DIR_PWR6:
   case PPC::DIR_PWR6X:
case PPC::DIR_PWR9: {
 
     if (LoopSize > 16 && LoopSize <= 32)
       return 5;
 
     break;
   }
   }
 
-  return TargetLowering::getPrefLoopAlignment(ML);
+  return TargetLowering::getPrefLoopLogAlignment(ML);
 }
 
 /// getConstraintType - Given a constraint, return the type of
 /// constraint it is for this target.
 PPCTargetLowering::ConstraintType
 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {

llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
   // Function alignments (log2).
   unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
-  setMinFunctionAlignment(FunctionAlignment);
-  setPrefFunctionAlignment(FunctionAlignment);
+  setMinFunctionLogAlignment(FunctionAlignment);
+  setPrefFunctionLogAlignment(FunctionAlignment);
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                             EVT VT) const {
   if (!VT.isVector())

llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   if (!Subtarget->is64Bit())
     setTargetDAGCombine(ISD::BITCAST);
 
   if (Subtarget->hasLeonCycleCounter())
     setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
-  setMinFunctionAlignment(2);
+  setMinFunctionLogAlignment(2);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 }
 
 bool SparcTargetLowering::useSoftFloat() const {
   return Subtarget->useSoftFloat();
 }
 

llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp

SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
   // such as SystemZ has with CC, so set this to the register-pressure
   // scheduler, because it can.
   setSchedulingPreference(Sched::RegPressure);
 
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   // Instructions are strings of 2-byte aligned 2-byte values.
-  setMinFunctionAlignment(2);
+  setMinFunctionLogAlignment(2);
   // For performance reasons we prefer 16-byte alignment.
-  setPrefFunctionAlignment(4);
+  setPrefFunctionLogAlignment(4);
 
   // Handle operations that are handled in a similar way for all types.
   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
        I <= MVT::LAST_FP_VALUETYPE;
        ++I) {
     MVT VT = MVT::SimpleValueType(I);
     if (isTypeLegal(VT)) {
       // Lower SET_CC into an IPM-based sequence.

llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp

struct MBBInfo {
   uint64_t Address = 0;
 
   // The size of the block in bytes, excluding terminators.
   // This value never changes.
   uint64_t Size = 0;
 
   // The minimum alignment of the block, as a log2 value.
   // This value never changes.
-  unsigned Alignment = 0;
+  unsigned LogAlignment = 0;
 
   // The number of terminators in this block.  This value never changes.
   unsigned NumTerminators = 0;
 
   MBBInfo() = default;
 };
 
 // Represents the state of a block terminator.

 struct BlockPosition {
   // The address that we assume this position has.
   uint64_t Address = 0;
 
   // The number of low bits in Address that are known to be the same
   // as the runtime address.
   unsigned KnownBits;
 
-  BlockPosition(unsigned InitialAlignment) : KnownBits(InitialAlignment) {}
+  BlockPosition(unsigned InitialLogAlignment)
+      : KnownBits(InitialLogAlignment) {}
 };
 
 class SystemZLongBranch : public MachineFunctionPass {
 public:
   static char ID;
 
   SystemZLongBranch(const SystemZTargetMachine &tm)
     : MachineFunctionPass(ID) {}

 
 } // end anonymous namespace
 
 // Position describes the state immediately before Block.  Update Block
 // accordingly and move Position to the end of the block's non-terminator
 // instructions.
 void SystemZLongBranch::skipNonTerminators(BlockPosition &Position,
                                            MBBInfo &Block) {
-  if (Block.Alignment > Position.KnownBits) {
+  if (Block.LogAlignment > Position.KnownBits) {
     // When calculating the address of Block, we need to conservatively
     // assume that Block had the worst possible misalignment.
-    Position.Address += ((uint64_t(1) << Block.Alignment) -
+    Position.Address += ((uint64_t(1) << Block.LogAlignment) -
                          (uint64_t(1) << Position.KnownBits));
-    Position.KnownBits = Block.Alignment;
+    Position.KnownBits = Block.LogAlignment;
   }
 
   // Align the addresses.
-  uint64_t AlignMask = (uint64_t(1) << Block.Alignment) - 1;
+  uint64_t AlignMask = (uint64_t(1) << Block.LogAlignment) - 1;
   Position.Address = (Position.Address + AlignMask) & ~AlignMask;
 
   // Record the block's position.
   Block.Address = Position.Address;
 
   // Move past the non-terminators in the block.
   Position.Address += Block.Size;
 }
uint64_t SystemZLongBranch::initMBBInfo() {
   unsigned NumBlocks = MF->size();
 
   MBBs.clear();
   MBBs.resize(NumBlocks);
 
   Terminators.clear();
   Terminators.reserve(NumBlocks);
 
-  BlockPosition Position(MF->getAlignment());
+  BlockPosition Position(MF->getLogAlignment());
   for (unsigned I = 0; I < NumBlocks; ++I) {
     MachineBasicBlock *MBB = MF->getBlockNumbered(I);
     MBBInfo &Block = MBBs[I];
 
     // Record the alignment, for quick access.
-    Block.Alignment = MBB->getAlignment();
+    Block.LogAlignment = MBB->getLogAlignment();
 
     // Calculate the size of the fixed part of the block.
     MachineBasicBlock::iterator MI = MBB->begin();
     MachineBasicBlock::iterator End = MBB->end();
     while (MI != End && !MI->isTerminator()) {
       Block.Size += TII->getInstSizeInBytes(*MI);
       ++MI;
     }
if (mustRelaxBranch(Terminator, Terminator.Address))
       return true;
   return false;
 }
 
 // Set the address of each block on the assumption that all branches
 // must be long.
 void SystemZLongBranch::setWorstCaseAddresses() {
   SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
-  BlockPosition Position(MF->getAlignment());
+  BlockPosition Position(MF->getLogAlignment());
   for (auto &Block : MBBs) {
     skipNonTerminators(Position, Block);
     for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
       skipTerminator(Position, *TI, true);
       ++TI;
     }
   }
 }
void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
   Terminator.Branch = nullptr;
 
   ++LongBranches;
 }
 
 // Run a shortening pass and relax any branches that need to be relaxed.
 void SystemZLongBranch::relaxBranches() {
   SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
-  BlockPosition Position(MF->getAlignment());
+  BlockPosition Position(MF->getLogAlignment());
   for (auto &Block : MBBs) {
     skipNonTerminators(Position, Block);
     for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
       assert(Position.Address <= TI->Address &&
              "Addresses shouldn't go forwards");
       if (mustRelaxBranch(*TI, Position.Address))
         relaxBranch(*TI);
       skipTerminator(Position, *TI, false);

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

 
   // TODO: These control memcmp expansion in CGP and could be raised higher, but
   // that needs to benchmarked and balanced with the potential use of vector
   // load/store types (PR33329, PR33914).
   MaxLoadsPerMemcmp = 2;
   MaxLoadsPerMemcmpOptSize = 2;
 
   // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
-  setPrefLoopAlignment(ExperimentalPrefLoopAlignment);
+  setPrefLoopLogAlignment(ExperimentalPrefLoopAlignment);
 
   // An out-of-order CPU can speculatively execute past a predictable branch,
   // but a conditional move could be stalled by an expensive earlier operation.
   PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
   EnableExtLdPromotion = true;
-  setPrefFunctionAlignment(4); // 2^4 bytes.
+  setPrefFunctionLogAlignment(4); // 2^4 bytes.
 
   verifyIntrinsicTables();
 }
 
 // This has so far only been implemented for 64-bit MachO.
 bool X86TargetLowering::useLoadStackGuardNode() const {
   return Subtarget.isTargetMachO() && Subtarget.is64Bit();
 }

llvm/trunk/lib/Target/X86/X86RetpolineThunks.cpp

void X86RetpolineThunks::populateThunk(MachineFunction &MF,
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
   CaptureSpec->setHasAddressTaken();
   CaptureSpec->addSuccessor(CaptureSpec);
 
   CallTarget->addLiveIn(Reg);
   CallTarget->setHasAddressTaken();
-  CallTarget->setAlignment(4);
+  CallTarget->setLogAlignment(4);
   insertRegReturnAddrClobber(*CallTarget, Reg);
   CallTarget->back().setPreInstrSymbol(MF, TargetSym);
   BuildMI(CallTarget, DebugLoc(), TII->get(RetOpc));
 }

llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize
     = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2;
 
   // We have target-specific dag combine patterns for the following nodes:
   setTargetDAGCombine(ISD::STORE);
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::INTRINSIC_VOID);
   setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
 
-  setMinFunctionAlignment(1);
-  setPrefFunctionAlignment(2);
+  setMinFunctionLogAlignment(1);
+  setPrefFunctionLogAlignment(2);
 }
 
 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
   if (Val.getOpcode() != ISD::LOAD)
     return false;
 
   EVT VT1 = Val.getValueType();
   if (!VT1.isSimple() || !VT1.isInteger() ||

llvm/trunk/test/CodeGen/ARM/constant-island-movwt.mir

 # pair. On windows, the IMAGE_REL_ARM_MOV32T relocation on the movw instruction
 # covers both movw and movt, so we can't allow anything to be inserted between
 # them.
 #
 # CHECK:          $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14, $noreg
 # CHECK-NEXT:     renamable $q12 = VDUP32q killed renamable $r5, 14, $noreg
 # CHECK-NEXT:     t2B %bb.2, 14, $noreg
 # CHECK-NEXT: {{^  $}}
-# CHECK-NEXT:   bb.1 (align 2):
+# CHECK-NEXT:   bb.1 (align 4):
 # CHECK-NEXT:     successors:{{ }}
 # CHECK-NEXT: {{^  $}}
 # CHECK-NEXT:    CONSTPOOL_ENTRY 1, %const.0, 4
 # CHECK-NEXT: {{^  $}}
-# CHECK-NEXT:   bb.2.entry (align 1):
+# CHECK-NEXT:   bb.2.entry (align 2):
 # CHECK-NEXT:   liveins: $d13, $s27, $r10, $r9, $r8, $s26, $d12, $s25, $s24,
 # CHECK-SAME:            $d15, $s30, $s31, $d14, $s28, $s29, $lr, $r0, $d21,
 # CHECK-SAME:            $r3, $q10, $d20, $d17, $r2, $d25, $q11, $d22, $d23,
 # CHECK-SAME:            $r1, $q8, $d16, $s3, $q14, $d28, $d29, $d19, $s17,
 # CHECK-SAME:            $d8, $s16, $r6, $r7, $r4, $q12, $q9, $d18, $s0, $q15,
 # CHECK-SAME:            $d30, $d31, $r12, $s1, $d0, $d24, $s2, $d1, $q0, $s6,
 # CHECK-SAME:            $d3, $d2, $s4, $q1, $s7, $s5, $d9, $s18, $s19, $q4
 # CHECK-NEXT: {{^  $}}
 # CHECK-NEXT:     $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14, $noreg
 # CHECK-NEXT:     $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14, $noreg

llvm/trunk/test/CodeGen/ARM/fp16-litpool-arm.mir

constants:
   - id:              1
     value:           i32 987766
     alignment:       4
   - id:              2
     value:           half 0xH2E66
     alignment:       2
 
 #CHECK:  B %[[BB4:bb.[0-9]]]
-#CHECK:  bb.{{.}} (align 2):
+#CHECK:  bb.{{.}} (align 4):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY {{.}}, %const.{{.}}, 4
-#CHECK:  bb.{{.}} (align 2):
+#CHECK:  bb.{{.}} (align 4):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY {{.}}, %const.{{.}}, 4
-#CHECK:  bb.{{.}} (align 1):
+#CHECK:  bb.{{.}} (align 2):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY {{.}}, %const.{{.}}, 2
-#CHECK:  [[BB4]].entry (align 2):
+#CHECK:  [[BB4]].entry (align 4):
 
 body:             |
   bb.0.entry:
     liveins: $r0
 
     $sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg
     frame-setup CFI_INSTRUCTION def_cfa_offset 4
     renamable $s0 = FCONSTH 112, 14, $noreg

llvm/trunk/test/CodeGen/ARM/fp16-litpool-thumb.mir

constants:
   - id:              0
     value:           i32 1109917696
     alignment:       4
   - id:              1
     value:           half 0xH2E66
     alignment:       2
 
 #CHECK:  t2B %[[BB3:bb.[0-9]]]
-#CHECK:  bb.{{.}} (align 2):
+#CHECK:  bb.{{.}} (align 4):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY 2, %const.{{.}}, 4
-#CHECK:  bb.{{.}} (align 1):
+#CHECK:  bb.{{.}} (align 2):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY 3, %const.{{.}}, 2
-#CHECK:  [[BB3]].entry (align 1):
+#CHECK:  [[BB3]].entry (align 2):
 
 body:             |
   bb.0.entry:
     $sp = frame-setup tSUBspi $sp, 2, 14, $noreg
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     renamable $r0 = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
     renamable $s0 = FCONSTH 112, 14, $noreg
     tSTRspi killed renamable $r0, $sp, 1, 14, $noreg :: (volatile store 4 into %ir.F)

llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir

- { id: 0, name: res, type: default, offset: -2, size: 2, alignment: 2,
       debug-info-location: '' }
 constants:
   - id:              0
     value:           half 0xH706B
     alignment:       2
     isTargetSpecific: false
 
 
-#CHECK:  bb.{{.*}} (align 1):
+#CHECK:  bb.{{.*}} (align 2):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY 1, %const{{.*}}, 2
 # We want this block to be 4 byte aligned:
-#CHECK:  bb.{{.*}}.LA (align 2):
+#CHECK:  bb.{{.*}}.LA (align 4):
 
 body:             |
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
 
     $sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg
     frame-setup CFI_INSTRUCTION def_cfa_offset 4
     renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load 2 from constant-pool)

llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir

- { id: 0, name: res, type: default, offset: -2, size: 2, alignment: 2,
       debug-info-location: '' }
 constants:
   - id:              0
     value:           half 0xH706B
     alignment:       2
     isTargetSpecific: false
 
 
-#CHECK:  bb.{{.*}} (align 1):
+#CHECK:  bb.{{.*}} (align 2):
 #CHECK:    successors:
 #CHECK:    CONSTPOOL_ENTRY 1, %const{{.*}}, 2
 #
 # We don't want to decrease alignment if the block already has been
 # aligned; this can e.g. be an existing CPE that has been carefully
 # aligned. Here BB.1.LA has already an 8-byte alignment, and we are
 # checking we don't set it to 4:
 #

llvm/trunk/test/CodeGen/Mips/unaligned-memops-mapping.mir

 
 # CHECK-LABEL: g:
 # CHECK:  0: 60 24 00 00   lwl $1, 0($4)
 # CHECK:  4: 60 24 10 03   lwr $1, 3($4)
 # CHECK:  8: 60 25 80 00   swl $1, 0($5)
 # CHECK:  c: 60 25 90 03   swr $1, 3($5)
 
 # CHECK-LABEL: g2:
-# CHECK: 14: 60 24 64 00   lwle  $1, 0($4)
-# CHECK: 18: 60 24 66 03   lwre  $1, 3($4)
-# CHECK: 1c: 60 25 a0 00   swle  $1, 0($5)
-# CHECK: 20: 60 25 a2 03   swre  $1, 3($5)
+# CHECK: 12: 60 24 64 00   lwle  $1, 0($4)
+# CHECK: 16: 60 24 66 03   lwre  $1, 3($4)
+# CHECK: 1a: 60 25 a0 00   swle  $1, 0($5)
+# CHECK: 1e: 60 25 a2 03   swre  $1, 3($5)

llvm/trunk/test/CodeGen/PowerPC/block-placement.mir

bb.11._ZN11xercesc_2_79XMLString6equalsEPKtS2_.exit:
     liveins: $x3
   
     BLR8 implicit $lr8, implicit $rm, implicit killed $x3
 
   ; CHECK:      bb.5.if.else.i:
   ; CHECK:        successors: %bb.11(0x80000000)
   ; CHECK:        B %bb.11
 
-  ; CHECK:      bb.8.while.body.i (align 4):
+  ; CHECK:      bb.8.while.body.i (align 16):
   ; CHECK:        successors: %bb.11(0x04000000), %bb.9(0x7c000000)
   ; CHECK:        BCC 76, killed renamable $cr0, %bb.11
 
   ; CHECK:      bb.11:
   ; CHECK:        renamable $x3 = LI8 1
   ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
 ...

llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir

body:             |
   ; CHECK:   successors: %bb.4(0x30000000), %bb.8(0x50000000)
   ; CHECK:   CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8)
   ; CHECK:   JCC_1 %bb.8, 5, implicit $eflags
   ; CHECK: bb.4:
   ; CHECK:   successors: %bb.1(0x30000000), %bb.5(0x50000000)
   ; CHECK:   $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
   ; CHECK:   TEST64rr $rax, $rax, implicit-def $eflags
   ; CHECK:   JCC_1 %bb.1, 4, implicit $eflags
-  ; CHECK: bb.5 (align 4):
+  ; CHECK: bb.5 (align 16):
   ; CHECK:   successors: %bb.6(0x71555555), %bb.8(0x0eaaaaab)
   ; CHECK:   CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8), (load 8)
   ; CHECK:   JCC_1 %bb.8, 5, implicit $eflags
   ; CHECK: bb.6:
   ; CHECK:   successors: %bb.1(0x04000000), %bb.5(0x7c000000)
   ; CHECK:   $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
   ; CHECK:   TEST64rr $rax, $rax, implicit-def $eflags
   ; CHECK:   JCC_1 %bb.5, 5, implicit $eflags

llvm/trunk/test/DebugInfo/X86/debug-loc-offset.mir

 # debug_loc entries are relative to the low_pc of the CU. The loc entry for
 # the byval argument in foo.cpp is in the second CU and so should have
 # an offset relative to that CU rather than from the beginning of the text
 # section.
 #
 # Checking that we have two compile units with two sets of high/lo_pc.
 # CHECK: .debug_info contents
 # CHECK: DW_TAG_compile_unit
-# CHECK: DW_AT_low_pc {{.*}} (0x0000000000000020 ".text")
+# CHECK: DW_AT_low_pc {{.*}} (0x0000000000000018 ".text")
 # CHECK: DW_AT_high_pc
 #
 # CHECK: DW_TAG_subprogram
 # CHECK-NOT: DW_TAG
 # CHECK: DW_AT_linkage_name [DW_FORM_strp]{{.*}}"_Z3baz1A"
 # CHECK-NOT: {{DW_TAG|NULL}}
 # CHECK: DW_TAG_formal_parameter
 # CHECK-NOT: DW_TAG
 # CHECK:       DW_AT_location [DW_FORM_sec_offset]   ({{.*}}
-# CHECK-NEXT:    [0x00000029, 0x00000037): DW_OP_breg0 EAX+0, DW_OP_deref
-# CHECK-NEXT:    [0x00000037, 0x00000063): DW_OP_breg5 EBP-8, DW_OP_deref, DW_OP_deref
+# CHECK-NEXT:    [0x00000021, 0x0000002f): DW_OP_breg0 EAX+0, DW_OP_deref
+# CHECK-NEXT:    [0x0000002f, 0x0000005b): DW_OP_breg5 EBP-8, DW_OP_deref, DW_OP_deref
 # CHECK-NEXT:  DW_AT_name [DW_FORM_strp]{{.*}}"a"
 #
 # CHECK: DW_TAG_variable
 # CHECK: DW_AT_location [DW_FORM_exprloc]
 # CHECK-NOT: DW_AT_location
 #
 # CHECK: DW_TAG_compile_unit
 # CHECK: DW_AT_low_pc {{.*}} (0x0000000000000000 ".text")