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nadav (Nadav Rotem)
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User Since
Nov 19 2012, 1:00 PM (316 w, 2 d)

Recent Activity

Oct 19 2018

nadav committed rL344819: Update the speaker list for the Glow talk. .
Update the speaker list for the Glow talk.
Oct 19 2018, 4:43 PM

Apr 29 2017

nadav accepted D32620: [DAGCombiner] shrink/widen a vselect to match its condition operand size (PR14657).

LGTM!

Apr 29 2017, 1:08 AM

Apr 27 2017

nadav added inline comments to D32620: [DAGCombiner] shrink/widen a vselect to match its condition operand size (PR14657).
Apr 27 2017, 4:05 PM

Aug 16 2016

nadav added inline comments to D23559: [ADCE] Add control dependence computation.
Aug 16 2016, 9:36 AM

Aug 5 2016

nadav added inline comments to D23225: [ADCE] Modify data structures to support removing control flow.
Aug 5 2016, 1:51 PM

Aug 3 2016

nadav added inline comments to D23102: [ADCE] Refactoring for new functionality (NFC).
Aug 3 2016, 10:10 AM

Aug 2 2016

nadav added a comment to D23065: [ADCE] Refactor anticipating new functionality (NFC).

LGTM.

Aug 2 2016, 12:19 PM

Aug 1 2016

nadav accepted D23049: [LV, X86] Be more optimistic about vectorizing shifts..

LGTM!

Aug 1 2016, 9:32 PM
nadav accepted D22952: [LoopVectorize] Detect loops in the innermost loop before creating InnerLoopVectorizer.
Aug 1 2016, 4:13 PM

Jul 29 2016

nadav added inline comments to D22952: [LoopVectorize] Detect loops in the innermost loop before creating InnerLoopVectorizer.
Jul 29 2016, 12:12 PM

Jul 4 2016

nadav added a comment to D18630: [SLPVectorizer] Account for dependence cycles to fix PR25108.

Ayal, I commented on the bug report that I don't understand why this heuristic is useful in the general case (for loops that are not this specific loop). Are you seeing any speedups on SPEC or the LLVM test suite (or other test suites?).

Jul 4 2016, 8:15 PM

Jun 20 2016

nadav added a comment to D20363: [X86] Extract HiPE prologue constants into metadata.

Magnus, I don't have any problem with this change because it is specific to Erlang. I suggest CC-ing the original author of adjustForHiPEPrologue, and if that person has no objections commit the change. Relying on metadata is not idea, but I understand the constraint.

Jun 20 2016, 1:34 PM

Jun 13 2016

nadav added a comment to D21048: [LV] Enable vectorization of loops where the IV has an external use.

LGTM.

Jun 13 2016, 11:42 PM

May 10 2016

nadav committed rL269073: Update my email address. .
Update my email address.
May 10 2016, 9:30 AM

Mar 30 2016

nadav added a comment to D18537: Don't vectorize loops when everything will be scalarized.

Hal, the code looks much better. I was thinking about this patch on the way to work this morning and I was wondering if you could mark the type <4 x i32> as legal, because you _can_ load it and store it to memory. Right?

Mar 30 2016, 11:14 AM

Mar 29 2016

nadav added a comment to D18537: Don't vectorize loops when everything will be scalarized.

I don't like the approach of passing in address-of-bool as parameter argument, especially since you did not document the parameter (is it IN, is it OUT, etc).

Mar 29 2016, 2:20 PM
nadav added a comment to D18537: Don't vectorize loops when everything will be scalarized.

Hal, I am not sure I understand the problem. Is the problem register pressure or the fact that store <8 x i32> is more expensive than 8 times store i32?

Mar 29 2016, 2:03 PM

Mar 2 2016

nadav added a comment to D17801: Fixed X86 Interrupt handler calling convention for MCU target.

LGTM.

Mar 2 2016, 9:18 AM

Feb 23 2016

nadav added a comment to D17542: Disallow generating vzeroupper before return instruction (iret) in interrupt handler function.

The patch LGTM.

Feb 23 2016, 7:07 AM

Feb 9 2016

nadav added a comment to D15646: [X86] Fix stack alignment for MCU target.

Sorry for the delay in review. This patch LGTM.

Feb 9 2016, 1:08 PM

Jan 28 2016

nadav added inline comments to D15690: Gather and Scatter intrinsics in the Loop Vectorizer.
Jan 28 2016, 9:11 AM

Jan 21 2016

nadav added a comment to D15815: [SLP] Truncate expressions to minimum required bit width.

Sounds good. Thanks Matthew.

Jan 21 2016, 10:08 AM
nadav added a comment to D15815: [SLP] Truncate expressions to minimum required bit width.

Did you see any performance improvements due to this commit? Did you measure compile times?

Jan 21 2016, 9:22 AM

Jan 12 2016

nadav added a comment to D14829: [SLP] Vectorize gather-like idioms ending at non-consecutive loads..

LGTM.

Jan 12 2016, 9:15 AM

Dec 29 2015

nadav added a comment to D15536: [JumpThreading] Fix opcode bonus in getJumpThreadDuplicationCost().

LGTM.

Dec 29 2015, 11:39 AM

Dec 21 2015

nadav added a comment to D15604: Changes in conversion cost model for X86 target.

Elena, please fix the cost table and don't change anything else.

Dec 21 2015, 10:39 AM
nadav added a comment to D15604: Changes in conversion cost model for X86 target.

We don't let the instruction Sitofp <4 x i32 > %a to <4 x f64> go through the type legalizer.

Dec 21 2015, 9:00 AM

Dec 20 2015

nadav added a comment to D15604: Changes in conversion cost model for X86 target.

Elena, I don't understand your comment. getTypeLegalizationCost imitates the type legalizer by splitting and promoting. It actually uses the type legalizer. What do you mean it does not support zero-extend and sign-extend?

Dec 20 2015, 10:37 PM

Dec 18 2015

nadav added a comment to D15604: Changes in conversion cost model for X86 target.

Thanks for explaining this Elena. Have you considered handling all of the special cases by adding them to the 'TypeConversionCostTblEntry' table? Also, have you considered improving getTypeLegalizationCost?

Dec 18 2015, 9:05 AM

Dec 17 2015

nadav added inline comments to D15604: Changes in conversion cost model for X86 target.
Dec 17 2015, 4:22 PM

Dec 16 2015

nadav added a comment to D15567: Support of x86 interrupt and exception handlers in LLVM.

LGTM Amjad!

Dec 16 2015, 10:17 AM
nadav added a comment to D15580: [SLPVectorizer] Ensure dominated reduction values..

Thanks for fixing this Charlie!

Dec 16 2015, 10:10 AM

Dec 14 2015

nadav added a comment to D6818: [SLPVectorization] Vectorize flat addition in a single tree (+(+(+ v1 v2) v3) v4).

It looks like this patch is not ready for review.

Dec 14 2015, 9:05 AM

Dec 11 2015

nadav added a comment to D14829: [SLP] Vectorize gather-like idioms ending at non-consecutive loads..

@anemet In SelectionDAG we can use the memory order chains, and don't have to scan the whole basic block for loads/stores. This is very efficient, and is already used by the load-store merger in SelectionDAG.

Dec 11 2015, 11:15 AM
nadav added a comment to D14829: [SLP] Vectorize gather-like idioms ending at non-consecutive loads..

Hal,

Thanks very much for the follow-up. Yes, I'm working on compile-time along with the type shrinking work I previously mentioned. I will post an updated revision soon.

Dec 11 2015, 10:34 AM

Dec 6 2015

nadav added a comment to D15151: Do not try to use i8 and i16 versions of FP_TO_INT soft float library calls .

LGTM.

Dec 6 2015, 7:52 AM

Nov 19 2015

nadav added a comment to D14829: [SLP] Vectorize gather-like idioms ending at non-consecutive loads..

Matthew, thanks for working on this.

Nov 19 2015, 10:21 AM
nadav added a comment to rL247435: [X86] Make sure startproc/endproc are paired.

Yes, we should merge this. LGTM!

Nov 19 2015, 9:51 AM · Restricted Project

Nov 12 2015

nadav added a comment to D13161: [PATCH, PR24373] Combine shifts for x86.

I did not get a chance to review this patch carefully. Andrea, Simon, David, Elena, Sanjay, did you get a chance to review the patch? Does it look okay? I did not see a LGTM in the thread.

Nov 12 2015, 9:20 AM

Nov 9 2015

nadav added a comment to D14495: [X86] Do not try to custom-lower sitofp/fptosi in soft-float mode.

LGTM.

Nov 9 2015, 7:01 AM

Nov 5 2015

nadav added a comment to D13161: [PATCH, PR24373] Combine shifts for x86.

Did you measure the performance impact of this patch on the llvm test suite (or SPEC or other test suite?). Is this a win?

Nov 5 2015, 9:04 AM

Nov 2 2015

nadav added a comment to D14214: [X86] DAGCombine should not introduce FILD in soft-float mode.

LGTM.

Nov 2 2015, 10:56 AM
nadav added a comment to D13295: LEA code size optimization pass (Part 2): Remove redundant LEA instructions.

LGTM.

Nov 2 2015, 7:28 AM
nadav added a comment to D13979: Introduction of FeatureX87.

LGTM.

Nov 2 2015, 7:28 AM

Oct 30 2015

nadav added a comment to D14178: Alternative to long nops for X86 CPUs.

LGTM!

Oct 30 2015, 9:47 PM

Oct 27 2015

nadav added a comment to D14063: [SLP] Try a bit harder to find reduction PHIs.

LGTM. Please commit.

Oct 27 2015, 10:16 AM

Oct 26 2015

nadav added a comment to D13949: [SLP] Treat SelectInsts as reduction values..

LGTM!

Oct 26 2015, 11:39 AM
nadav added a comment to D14059: [X86] Replace LEAs with INC/DEC.

I don’t see a problem with this commit but please email llvm-commit and allow other developers to review this patch.

Oct 26 2015, 9:20 AM
nadav added a comment to D13949: [SLP] Treat SelectInsts as reduction values..

Okay. Please go ahead and commit this patch. I do have one minor comment:

Oct 26 2015, 9:18 AM
nadav added a comment to D14063: [SLP] Try a bit harder to find reduction PHIs.

I am okay with this change, but I have a few comments on the patch:

Oct 26 2015, 9:15 AM

Oct 1 2015

nadav added a comment to D13277: [SLP] Don't vectorize loads of non-packed types (like i1, i2)..

What about SLP-vectorization of stores? I suspect that we have the same bug for stores.

Oct 1 2015, 10:05 AM

Sep 25 2015

nadav added a comment to D9804: Optimize scattered vector insert/extract pattern.

At a high level, this transformation seems overly restrictive, and will need cost-modeling work. A couple of thoughts:

  1. I don't see why you're restricting this to extracts used by stores (or inserts fed by loads); if the goal is to save on [zs]ext instructions, then this seems profitable regardless of how these are used. Moreover, I don't understand why there's a hasOneUse() check on the [zs]ext instructions.
  2. The [zs]ext instructions that you're trying to eliminate might be free, at least in combination with the extract or insert, rendering this a bad idea. Consider the (unfortunately common) case where the target does not actually support a vector extract at all, and so it is lowered by storing the vector on the stack and then doing a scalar load of the requested element. In this case, if the target supports the corresponding scalar extending load, the extension is free. Likewise, for those [zs]ext fed by loads, these might be free if the target supports the corresponding extending load. Worse, the vector [zs]ext you're forming might not be legal at all (this is the most-serious potential problem).
Sep 25 2015, 11:30 AM

Aug 31 2015

nadav added a comment to D12285: [LV] Switch to using canonical induction variables..

I think that this is a good change. In many other places in the vectorizer the design was that we let other passes (such as CSE, InstCombine and LSR) clean up after us. I am totally okay with letting LSR do the cleanup. If I remember correctly we have always relied on LSR to do the cleanup and I don't remember why we have the logic for searching other induction variables.

Aug 31 2015, 5:08 PM

Aug 20 2015

nadav added a comment to D12214: [LoopVectorize] Propagate 'nontemporal' attribute into vectorized instructions..

Maybe in a future patch we should refactor this logic in the SLP vectorizer and LoopVectorizer into a single function that verifies the metadata kind? I assume that the list should be identical.

Aug 20 2015, 1:51 PM

Jul 29 2015

nadav added a comment to D10445: Choose the best consecutive candidate for a store instruction in SLP vectorizer.

The code LGTM. Did you measure the compile time impact of this change?

Jul 29 2015, 2:25 PM

Jul 6 2015

nadav added a comment to D10950: [SLPVectorizer] Try different vectorization factors and set max vector register size based on target .

Sanjay, this patch looks okay. I think that the compile time hit should be minimal but I think that we need to measure just to be sure.

Jul 6 2015, 10:18 AM

Jul 2 2015

nadav committed rL241312: Fix an overly aggressive assertion in getCopyFromPartsVector..
Fix an overly aggressive assertion in getCopyFromPartsVector.
Jul 2 2015, 4:24 PM

Jun 19 2015

nadav added a comment to D10558: [SLP] Vectorize all-constant entries..

LGTM!

Jun 19 2015, 8:43 AM

Jun 15 2015

nadav added a comment to D10445: Choose the best consecutive candidate for a store instruction in SLP vectorizer.

Thanks for working on this. Did you run the llvm test suite? Are there any performance wins or compile time regressions?

Jun 15 2015, 9:10 AM

Jun 10 2015

nadav added a comment to D10352: Make SLP vectorizer consider the cost that vectorized instruction cannot use memory operand as destination on X86.

Hi Wei,

Jun 10 2015, 9:42 AM

Jun 2 2015

nadav added a comment to D9804: Optimize scattered vector insert/extract pattern.

Hi Lawrence,

Jun 2 2015, 12:57 PM

May 21 2015

nadav added a comment to D9923: Adjust the cost of vectorized SHL/SRL/SRA.

Looks good to me assuming that you write the cost model tests, and that you write tests for the ISel changes.

May 21 2015, 4:18 PM

May 6 2015

nadav added a comment to D9543: Populate list of vectorizable functions for Accelerate library..

Looks good to me.

May 6 2015, 5:33 PM

May 2 2015

nadav added a comment to D9463: Don't try to emit loopVectorize warning if DebugLoc isn't available.

Looks good to me.

May 2 2015, 6:44 PM

Mar 25 2015

nadav added a comment to D8609: [X86, AVX] improve insertion into zero element of 256-bit vector.

This looks good to me.

Mar 25 2015, 10:12 AM
nadav added a comment to D8600: [ValueTracking] Fix PR23011..

I am sorry for the bug. Thanks for catching and fixing it. One easy way to write a testcase is to rely on the 'overflow' optimizations in instcombine. See the function overflow_mod_mul in Transforms/InstCombine/intrinsics.ll.

Mar 25 2015, 9:08 AM

Mar 15 2015

nadav added a comment to D8350: DAGCombiner: fold (xor (shl 1, x), -1) -> (rotl -2, x).

David, the code and test case look great. The transformation is not trivial. Do you mind adding a line of comment that explains why -2 is used? Maybe an example input like 00000001 -> 11111101. Also a comment about how rotate can only pull in 1s and how large x values are undefined.

Mar 15 2015, 10:56 PM

Mar 5 2015

nadav committed rL231433: Teach ComputeNumSignBits about signed reminder..
Teach ComputeNumSignBits about signed reminder.
Mar 5 2015, 4:26 PM

Mar 3 2015

nadav accepted D8028: Teach ComputeNumSignBits about signed divisions.

r231140

Mar 3 2015, 1:41 PM
nadav committed rL231140: Teach ComputeNumSignBits about signed divisions..
Teach ComputeNumSignBits about signed divisions.
Mar 3 2015, 1:41 PM
nadav added a comment to D8040: [DAGCombine] Fix a bug in a BUILD_VECTOR combine.

LGTM.

Mar 3 2015, 1:08 PM
nadav updated the diff for D8028: Teach ComputeNumSignBits about signed divisions.
Mar 3 2015, 10:26 AM
nadav updated subscribers of D8028: Teach ComputeNumSignBits about signed divisions.
Mar 3 2015, 12:05 AM
nadav retitled D8028: Teach ComputeNumSignBits about signed divisions from to Teach ComputeNumSignBits about signed divisions.
Mar 3 2015, 12:03 AM

Feb 19 2015

nadav added a comment to D7514: Break dependencies in large loops containing reductions (LoopVectorize).

Olivier, I don’t really understand this heuristics. It looks like you are adding lots of code to handle a very specific case and I am not convinced that this heuristics is useful for the general case.

Feb 19 2015, 10:23 AM

Jan 28 2015

nadav added a comment to D7193: [LoopVectorize] Induction variables: support arbitrary constant step.

Hao, this patch LGTM. This is a major change to the vectorizer so please run the llvm test suite and try to identify miscompiles or regressions.

Jan 28 2015, 1:59 PM

Jan 27 2015

nadav added a comment to D7196: [X86] Reduce some 32-bit imuls into lea + shift.

LGTM.

Jan 27 2015, 7:42 AM

Jan 22 2015

nadav added a comment to D7126: [x86] Combine x86mmx/i64 to v2i64 conversion to use scalar_to_vector.

LGTM.

Jan 22 2015, 10:20 AM

Jan 5 2015

nadav added a comment to D6321: Fix use of DemandedMask to NewMask for SIGN_EXTEND_INREG.

Okay, so if the code is executed then we should try to come up with a testcase that exposes the bug that you found. Can you modify the test cases that broke and try to expose the bug?

Jan 5 2015, 9:19 AM

Dec 11 2014

nadav added a comment to D6527: Using Masked Load / Store intrinsics in Loop Vectorizer.

Some changes in the patch should go in separately. For example:

Dec 11 2014, 9:06 AM

Dec 8 2014

nadav added a comment to D6527: Using Masked Load / Store intrinsics in Loop Vectorizer.

+ / Returns true if vector representation of the instruction \p I
+
/ requires mask.
+ bool toBuildMaskedVectorInst(const Instruction* I) {
+ return (MaskedOp.count(I) != 0);
+ }
+ void SI();

Dec 8 2014, 8:50 AM

Dec 5 2014

nadav added a comment to D6477: Strength reduce intrinsics with overflow into regular arithmetic operations if possible..

Everything except for the function WillNotOverflowSignedMul looks great. I also agree with Philip that the refactoring should go in as a separate patch. The first part of WillNotOverflowSignedMul looks correct. The second part (SignBits == BitWidth + 1) is more complex and I prefer that someone else would take a look. I believe that Michael Gottesman is a good candidate for reviewing this part of the code.

Dec 5 2014, 8:40 AM

Dec 4 2014

nadav added a comment to D6527: Using Masked Load / Store intrinsics in Loop Vectorizer.

Hi Elena,

Dec 4 2014, 8:39 AM
nadav added a comment to D6531: [x86] @llvm.ctpop.v8i32 custom lowering.

LGTM! Thank you for the detailed measurements!

Dec 4 2014, 8:37 AM

Dec 3 2014

nadav added a comment to D6321: Fix use of DemandedMask to NewMask for SIGN_EXTEND_INREG.

This looks like an obvious bug that should be fixed, unless the code is never executed. Can you try to delete this optimization altogether and see if any tests break? You can also try to use llvm-stress to generate lots of code and see if it ever reaches this optimization.

Dec 3 2014, 8:57 AM
nadav added a comment to D6501: [X86] Improve a dag-combine that handles a vector extract -> zext sequence..

I did not review the code carefully but overall it looks good.

Dec 3 2014, 8:26 AM
nadav added a comment to D6503: [X86] Convert esp-relative movs of function arguments to pushes, step 1.

Hi Michael,

Dec 3 2014, 8:23 AM

Nov 6 2014

nadav added a comment to D6128: [X86] Fix pattern match for 32-to-64-bit zext in the presence of AssertSext.

Can you please add a check line for ‘ret’ ? I want to make sure that the check line does not mix with code from the following test. With that the code LGTM.

Nov 6 2014, 12:23 PM

Nov 5 2014

nadav added a comment to D6128: [X86] Fix pattern match for 32-to-64-bit zext in the presence of AssertSext.

Is there a way to reduce the size of the testcase? Do you need two basic blocks? Can you add additional check lines to make sure that the ‘mov’ that you are matching is the one you are expecting?

Nov 5 2014, 11:39 AM

Oct 31 2014

nadav added a comment to D6051: Induction variables: support arbitrary constant step.

Hi Alexey,

Oct 31 2014, 10:19 AM

Sep 27 2014

nadav added a comment to D5444: Allow BB duplication threshold to be adjusted through JumpThreading's ctor.

I think that he is trying to disable code duplication because GPU languages may contain barriers that must not be duplicated.

Sep 27 2014, 7:42 PM

Sep 23 2014

nadav added a comment to D5444: Allow BB duplication threshold to be adjusted through JumpThreading's ctor.

The functionality of the patch looks okay. Please add a comment that says that non-negative values override the internal default.

Sep 23 2014, 5:37 PM

Sep 18 2014

nadav added a comment to D5245: [x32] Fix segmented stacks support.

Pavel, I am sorry for the delay in review. I am not that familiar with this code. Can you check with svn-blame and see who are the last few people who touched the code?

Sep 18 2014, 8:57 AM

Sep 15 2014

nadav added a comment to D5324: Remove dead code in SimplifyCFG.

LGTM!

Sep 15 2014, 9:50 AM
nadav added a comment to D5355: [x32] Fix function indirect calls.

LGTM. :)

Sep 15 2014, 9:14 AM

Sep 3 2014

nadav added a comment to D5172: Preserve IR flags (nsw, nuw, exact, fast-math) in SLP vectorizer (PR20802).

LGTM! Thanks Sanjay!

Sep 3 2014, 9:29 AM

Aug 28 2014

nadav added a comment to D4909: fix a logic bug in x86 vector codegen: sext (zext (x) ) != sext (x) (PR20472).

Sanjay, you can commit changes like this without waiting for pre-commit code review (See item #3 in http://llvm.org/docs/DeveloperPolicy.html#code-reviews).

Aug 28 2014, 11:06 AM

Jul 30 2014

nadav added a comment to D4680: PR20234 - [SLP Vectorizer] Canonicalize tree operands of commutitive binary operands..

LGTM.

Jul 30 2014, 1:23 PM

Jul 25 2014

nadav added a comment to D4680: PR20234 - [SLP Vectorizer] Canonicalize tree operands of commutitive binary operands..

In this patch you are changing the instruction V regardless if vectorization succeeds or not. Would it be possible to only change the VL vector without modifying the binary operator V?

Jul 25 2014, 4:15 PM

Jul 20 2014

nadav added a comment to D4599: Use AA in LoopVectorize.

Hi Hal,

Jul 20 2014, 7:51 PM