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[Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions.
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Authored by andreisfr on Jul 16 2019, 3:30 PM.

Details

Summary

Add branch/jump/call/l32r instructions and fixups support. Add R_XTENSA_32/R_XTENSA_SLOT0_OP
relocations in object files generation. Modify tests to support new instructions.
Add tests for relocations and fixups.

Diff Detail

Event Timeline

andreisfr created this revision.Jul 16 2019, 3:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2019, 3:30 PM
andreisfr updated this revision to Diff 212697.Jul 31 2019, 4:07 PM

Register names are capitalized.

andreisfr updated this revision to Diff 242220.Feb 3 2020, 3:20 PM

Patch is updated according to latest upstream version. Updated licenses.

andreisfr updated this revision to Diff 328702.Mar 5 2021, 4:47 PM

Patch is updated according to latest upstream version

andreisfr updated this revision to Diff 329500.Mar 9 2021, 4:52 PM

Patch is updated according to LLVM upstream version and latest Xtensa backend version.

andreisfr updated this revision to Diff 335960.Apr 7 2021, 4:57 PM

Correct instruction descriptions, format descriptions and instruction operands according to common style for *.td files. The llvm_unreachable is substituted to report_fatal_error.

jrtc27 added a subscriber: jrtc27.Jun 8 2021, 5:44 AM
jrtc27 added inline comments.
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
502

Whatever patch includes this whitespace should be fixed.

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
97

Whitespace, and unnecessary parens.

llvm/test/MC/Xtensa/relocations.s
14 ↗(On Diff #335960)

Some assembly files have 1 leading space, some have 0, some have multiple. Please be consistent.

andreisfr updated this revision to Diff 351608.Jun 11 2021, 5:44 PM

Remove whitespaces and parentheses.

andreisfr marked an inline comment as done.Jun 11 2021, 5:51 PM

@jrtc27 ,thank you very much for comments.

llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
502

Whitespace is removed

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
97

Whitespace and parentheses are removed

llvm/test/MC/Xtensa/relocations.s
14 ↗(On Diff #335960)

I removed leading spaces from tests.

andreisfr marked an inline comment as done.

Patch is updated according to LLVM upstream version.

bero added a subscriber: bero.Apr 14 2022, 2:00 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 14 2022, 2:00 PM
andreisfr updated this revision to Diff 425080.Apr 25 2022, 5:20 PM

Patch is updated according to LLVM upstream version

andreisfr updated this revision to Diff 455450.Aug 24 2022, 6:10 PM

Update according to latest changes in upstream version

saugustine accepted this revision.Aug 29 2022, 6:06 PM
saugustine added a subscriber: saugustine.

This is also largely mechanical, and the tests are thorough.

This revision is now accepted and ready to land.Aug 29 2022, 6:06 PM
phosek added a subscriber: phosek.Sep 1 2022, 11:44 AM
andreisfr updated this revision to Diff 461122.Sep 18 2022, 6:49 PM

Test file "xtensa-valid.s" is splitted to several files according to instructions groups.

andreisfr updated this revision to Diff 485255.Dec 25 2022, 4:38 PM

Added fixes according to comments

The patch is too big, I wasn't able to review it thoroughly.

llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
107

(minor) I believe Address should be uint64_t (here and in other methods below).

121

(minor) All these method can accept const MCDisassebler *Decoder instead of const void *.

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
50

(note for the future?) This should take into account IsPCRel flag.

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
101–104

Either all of 'if's should have braces or none.

This revision was landed with ongoing or failed builds.Dec 26 2022, 4:39 AM
This revision was automatically updated to reflect the committed changes.