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[Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions.
Needs ReviewPublic

Authored by andreisfr on Jul 16 2019, 3:30 PM.

Details

Reviewers
jyknight
ivanbaev
Summary

Add branch/jump/call/l32r instructions and fixups support. Add R_XTENSA_32/R_XTENSA_SLOT0_OP
relocations in object files generation. Modify tests to support new instructions.
Add tests for relocations and fixups.

Diff Detail

Event Timeline

andreisfr created this revision.Jul 16 2019, 3:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2019, 3:30 PM
andreisfr updated this revision to Diff 212697.Jul 31 2019, 4:07 PM

Register names are capitalized.

andreisfr updated this revision to Diff 242220.Feb 3 2020, 3:20 PM

Patch is updated according to latest upstream version. Updated licenses.

andreisfr updated this revision to Diff 328702.Mar 5 2021, 4:47 PM

Patch is updated according to latest upstream version

andreisfr updated this revision to Diff 329500.Mar 9 2021, 4:52 PM

Patch is updated according to LLVM upstream version and latest Xtensa backend version.

andreisfr updated this revision to Diff 335960.Wed, Apr 7, 4:57 PM

Correct instruction descriptions, format descriptions and instruction operands according to common style for *.td files. The llvm_unreachable is substituted to report_fatal_error.