[RISCV] Support z and i operand modifiers

[asb]

Is there documentation on the operand modifiers supported by RISC-V binutils anywhere? I'm struggling to find anything...

[jrtc27]

In D57792#1549669, @asb wrote:

Is there documentation on the operand modifiers supported by RISC-V binutils anywhere? I'm struggling to find anything...

This is GCC not binutils, and I can't find them documented anywhere other than the source itself: https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/riscv/riscv.c?view=markup&revision=271293#l3181

[asb]

In D57792#1549676, @jrtc27 wrote:

In D57792#1549669, @asb wrote:

Is there documentation on the operand modifiers supported by RISC-V binutils anywhere? I'm struggling to find anything...

This is GCC not binutils, and I can't find them documented anywhere other than the source itself: https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/riscv/riscv.c?view=markup&revision=271293#l3181

Sorry, I meant GCC.

Thanks, this patch looks good to me. Tiny nit: LLVM coding guidelines prefer full sentences for comments, so the comments added to RISCVAsmPrinter.cpp should end in a full stop.

EDIT: You'll want to add nounwind attributes to the functions in your test too.

[jrtc27]

In D57792#1549678, @asb wrote:

In D57792#1549676, @jrtc27 wrote:

In D57792#1549669, @asb wrote:

Is there documentation on the operand modifiers supported by RISC-V binutils anywhere? I'm struggling to find anything...

This is GCC not binutils, and I can't find them documented anywhere other than the source itself: https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/riscv/riscv.c?view=markup&revision=271293#l3181

Sorry, I meant GCC.

Thanks, this patch looks good to me. Tiny nit: LLVM coding guidelines prefer full sentences for comments, so the comments added to RISCVAsmPrinter.cpp should end in a full stop.

Blame the Mips backend for leading me astray for this function...

EDIT: You'll want to add nounwind attributes to the functions in your test too.

Yes, just went to check that between your initial commenting and edit.

[jrtc27]

Added nounwind to tests. Added full stops to comments.

[jrtc27]

Rebased

lib/Target/RISCV/RISCVAsmPrinter.cpp

bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                       const char *ExtraCode, raw_ostream &OS) {
   if (AsmVariant != 0)
     report_fatal_error("There are no defined alternate asm variants");
 
   // First try the generic code, which knows about modifiers like 'c' and 'n'.
   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, OS))
     return false;
 
-  if (!ExtraCode) {
-    const MachineOperand &MO = MI->getOperand(OpNo);
-    switch (MO.getType()) {
-    case MachineOperand::MO_Immediate:
-      OS << MO.getImm();
-      return false;
-    case MachineOperand::MO_Register:
-      OS << RISCVInstPrinter::getRegisterName(MO.getReg());
-      return false;
-    default:
-      break;
-    }
-  }
+  if (ExtraCode && ExtraCode[0]) {
+    if (ExtraCode[1] != 0) return true; // Unknown modifier.
+
+    switch (ExtraCode[0]) {
+    default:
+      return true; // Unknown modifier
+    case 'z': // Print zero register if zero, regular printing otherwise
+      if (MO.isImm() && MO.getImm() == 0) {
+        OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
+        return false;
+      }
+      break;
+    case 'i': // Literal 'i' if operand is not a register
+      if (!MO.isReg())
+        OS << 'i';
+      return false;
+    }
+  }
+
 
   return true;
 }
 
 bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                             unsigned OpNo, unsigned AsmVariant,
                                             const char *ExtraCode,
                                             raw_ostream &OS) {

test/CodeGen/RISCV/inline-asm.ll

 ; RV32I-NEXT:    lb s1, (a0)
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
   tail call void asm sideeffect "sb s0, $0", "*A"(i8* %a)
   tail call void asm sideeffect "lb s1, $0", "*A"(i8* %a)
   ret void
 }
 
+define i32 @modifier_z_zero(i32 %a) {
+; RV32I-LABEL: modifier_z_zero:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    add a0, a0, zero
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+  %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 0)
+  ret i32 %1
+}
+
+define i32 @modifier_z_nonzero(i32 %a) {
+; RV32I-LABEL: modifier_z_nonzero:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 1
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+  %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 1)
+  ret i32 %1
+}
+
+define i32 @modifier_i_imm(i32 %a) {
+; RV32I-LABEL: modifier_i_imm:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    addi a0, a0, 1
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+  %1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
+  ret i32 %1
+}
+
+define i32 @modifier_i_reg(i32 %a, i32 %b) {
+; RV32I-LABEL: modifier_i_reg:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+  %1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 %b)
+  ret i32 %1
+}
+
 ; TODO: expend tests for more complex constraints, out of range immediates etc