[AArch64][v8.5A] Add MTE as an optional AArch64 extension

[olista01]

Summary

This adds the memory tagging extension, which is an optional extension
introduced in v8.5A. The new instructions and registers will be added by
subsequent patches.

Patch by Pablo Barrio!

[eugenis]

include/llvm/Support/AArch64TargetParser.def

74 ↗

(On Diff #166903)

Just wondering, is there a reason this is called "memtag" and not "mte"?

[olista01]

include/llvm/Support/AArch64TargetParser.def

74 ↗

(On Diff #166903)

I think we picked "memtag" over "mte" as it is more likely to be meaningful to users who don't remember all of the acronyms.

[SjoerdMeijer]

include/llvm/Support/AArch64TargetParser.def

74 ↗

(On Diff #166903)

For exactly that reason, I was thinking about commenting on "rng" on the other patch, because I initially found that a bit cryptic. Why not just "rand", which I think is a lot more meaninfull than rng. But anyway, this is probably bikeshedding, and rng has probably been synchronised with the GCC community...

[olista01]

Ping. This is the last patch for Armv8.5A (dis)assembler support which needs review, all of the ones adding the memory tagging instructions and registers are approved but depend on this one, and all of the other features are now committed.

[SjoerdMeijer]

Looks okay to me.

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

 AARCH64_ARCH_EXT_NAME("simd",     AArch64::AEK_SIMD,     "+neon",  "-neon")
 AARCH64_ARCH_EXT_NAME("fp16",     AArch64::AEK_FP16,     "+fullfp16",  "-fullfp16")
 AARCH64_ARCH_EXT_NAME("fp16fml",  AArch64::AEK_FP16FML,  "+fp16fml", "-fp16fml")
 AARCH64_ARCH_EXT_NAME("profile",  AArch64::AEK_PROFILE,  "+spe",  "-spe")
 AARCH64_ARCH_EXT_NAME("ras",      AArch64::AEK_RAS,      "+ras",  "-ras")
 AARCH64_ARCH_EXT_NAME("sve",      AArch64::AEK_SVE,      "+sve",  "-sve")
 AARCH64_ARCH_EXT_NAME("rcpc",     AArch64::AEK_RCPC,     "+rcpc", "-rcpc")
 AARCH64_ARCH_EXT_NAME("rng",      AArch64::AEK_RAND,     "+rand",  "-rand")
+AARCH64_ARCH_EXT_NAME("memtag",   AArch64::AEK_MTE,      "+mte",   "-mte")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
 #endif
 AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                 (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,

llvm/trunk/include/llvm/Support/TargetParser.h

enum ArchExtKind : unsigned {
   AEK_RCPC =        1 << 11,
   AEK_RDM =         1 << 12,
   AEK_SM4 =         1 << 13,
   AEK_SHA3 =        1 << 14,
   AEK_SHA2 =        1 << 15,
   AEK_AES =         1 << 16,
   AEK_FP16FML =     1 << 17,
   AEK_RAND =        1 << 18,
+  AEK_MTE =         1 << 19,
 };
 
 StringRef getCanonicalArchName(StringRef Arch);
 
 // Information by ID
 StringRef getFPUName(unsigned FPUKind);
 ARM::FPUVersion getFPUVersion(unsigned FPUKind);
 ARM::NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);

llvm/trunk/lib/Target/AArch64/AArch64.td

def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
     "true", "Enable Cache Clean to Point of Deep Persistence" >;
 
 def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
     "true", "Enable Branch Target Identification" >;
 
 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
     "true", "Enable Random Number generation instructions" >;
 
+def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
+    "true", "Enable Memory Tagging Extension" >;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasAlternativeNZCV = false;
   bool HasFRInt3264 = false;
   bool HasSpecRestrict = false;
   bool HasSpecCtrl = false;
   bool HasPredCtrl = false;
   bool HasCCDP = false;
   bool HasBTI = false;
   bool HasRandGen = false;
+  bool HasMTE = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
   bool HasZeroCycleZeroing = false;
   bool HasZeroCycleZeroingGP = false;
   bool HasZeroCycleZeroingFP = false;
public:
   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
   bool hasFRInt3264() const { return HasFRInt3264; }
   bool hasSpecRestrict() { return HasSpecRestrict; }
   bool hasSpecCtrl() { return HasSpecCtrl; }
   bool hasPredCtrl() { return HasPredCtrl; }
   bool hasCCDP() { return HasCCDP; }
   bool hasBTI() { return HasBTI; }
   bool hasRandGen() { return HasRandGen; }
+  bool hasMTE() { return HasMTE; }
 
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }

llvm/trunk/unittests/Support/TargetParserTest.cpp

const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
                               {"fp16fml", "nofp16fml", "+fp16fml", "-fp16fml"},
                               {"profile", "noprofile", "+spe", "-spe"},
                               {"ras", "noras", "+ras", "-ras"},
                               {"lse", "nolse", "+lse", "-lse"},
                               {"rdm", "nordm", "+rdm", "-rdm"},
                               {"sve", "nosve", "+sve", "-sve"},
                               {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
                               {"rcpc", "norcpc", "+rcpc", "-rcpc" },
-                              {"rng", "norng", "+rand", "-rand"}};
+                              {"rng", "norng", "+rand", "-rand"},
+                              {"memtag", "nomemtag", "+mte", "-mte"}};
 
   for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]),
               AArch64::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]),
               AArch64::getArchExtFeature(ArchExt[i][1]));
   }
 }
 }