This is an archive of the discontinued LLVM Phabricator instance.

Differential D45956

[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector (packed 32bit elts, unscaled)) load instructions.
AbandonedPublic

Authored by sdesmalen on Apr 23 2018, 6:50 AM.

Details

Reviewers
fhahn
rengolin
samparker
SjoerdMeijer
t.p.northover
echristo
evandro
javed.absar
Summary

Patch [6/8] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:

Diff Detail

Revision Contents

PathSize
lib/
Target/
AArch64/
17 lines
38 lines
test/
MC/
AArch64/
SVE/
12 lines
12 lines
12 lines
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Diff 143542

lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE] in {
defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>; defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>;
defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>; defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>;
defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>; defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>; defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>;
defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>; defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>;
defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>; defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>;
defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>; defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>;
// Gathers using unscaled 32-bit offsets packed in 64-bits elements, e.g.
// ld1h z32.d, p0/z, [x0, z0.d, uxtw]
defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLD1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
// continuous store with immediates // continuous store with immediates
defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>; defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>; defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>; defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>; defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>; defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>; defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>; defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;
Show All 24 Lines

lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 805 Lines • ▼ Show 20 Lines def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
(!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Memory - 64-bit Gather Group // SVE Memory - 64-bit Gather Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_mem_64b_gld_vs<bits<4> opc, bit xs, string asm,
RegisterOperand zprext>
: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Rn;
bits<5> Zm;
bits<5> Zt;
let Inst{31-25} = 0b1100010;
let Inst{24-23} = opc{3-2};
let Inst{22} = xs;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15} = 0b0;
let Inst{14-13} = opc{1-0};
let Inst{12-10} = Pg;
let Inst{9-5} = Rn;
let Inst{4-0} = Zt;
let mayLoad = 1;
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
}
multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
RegisterOperand sxtw_opnd,
RegisterOperand uxtw_opnd> {
def _UXTW_REAL : sve_mem_64b_gld_vs<opc, 0, asm, uxtw_opnd>;
def _SXTW_REAL : sve_mem_64b_gld_vs<opc, 1, asm, sxtw_opnd>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
(!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
(!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
}
class sve_mem_64b_gld_sv2<bits<4> opc, string asm, RegisterOperand zprext> class sve_mem_64b_gld_sv2<bits<4> opc, string asm, RegisterOperand zprext>
: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<3> Pg; bits<3> Pg;
bits<5> Rn; bits<5> Rn;
bits<5> Zm; bits<5> Zm;
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

test/MC/AArch64/SVE/ld1b.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 40 40 84 <unknown> // CHECK-UNKNOWN: 00 40 40 84 <unknown>
ld1b { z31.d }, p7/z, [sp, z31.d] ld1b { z31.d }, p7/z, [sp, z31.d]
// CHECK-INST: ld1b { z31.d }, p7/z, [sp, z31.d] // CHECK-INST: ld1b { z31.d }, p7/z, [sp, z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4] // CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df 5f c4 <unknown> // CHECK-UNKNOWN: ff df 5f c4 <unknown>
ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x55,0x15,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 15 c4 <unknown>
ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 55 c4 <unknown>

test/MC/AArch64/SVE/ld1d.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df df c5 <unknown> // CHECK-UNKNOWN: ff df df c5 <unknown>
ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3] ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
// CHECK-INST: ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3] // CHECK-INST: ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5] // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 cd e8 c5 <unknown> // CHECK-UNKNOWN: b7 cd e8 c5 <unknown>
ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x55,0x95,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 95 c5 <unknown>
ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x55,0xd5,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 d5 c5 <unknown>

test/MC/AArch64/SVE/ld1h.s

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df df c4 <unknown> // CHECK-UNKNOWN: ff df df c4 <unknown>
ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1] ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-INST: ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1] // CHECK-INST: ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4] // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 cd e8 c4 <unknown> // CHECK-UNKNOWN: b7 cd e8 c4 <unknown>
ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x55,0x95,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 95 c4 <unknown>
ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x55,0xd5,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 d5 c4 <unknown>

test/MC/AArch64/SVE/ld1sb.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 40 84 <unknown> // CHECK-UNKNOWN: 00 00 40 84 <unknown>
ld1sb { z31.d }, p7/z, [sp, z31.d] ld1sb { z31.d }, p7/z, [sp, z31.d]
// CHECK-INST: ld1sb { z31.d }, p7/z, [sp, z31.d] // CHECK-INST: ld1sb { z31.d }, p7/z, [sp, z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4] // CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 5f c4 <unknown> // CHECK-UNKNOWN: ff 9f 5f c4 <unknown>
ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x15,0x15,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 15 c4 <unknown>
ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 55 c4 <unknown>

test/MC/AArch64/SVE/ld1sh.s

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f df c4 <unknown> // CHECK-UNKNOWN: ff 9f df c4 <unknown>
ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-INST: ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] // CHECK-INST: ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4] // CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 8d e8 c4 <unknown> // CHECK-UNKNOWN: b7 8d e8 c4 <unknown>
ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x15,0x95,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 95 c4 <unknown>
ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x15,0xd5,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 d5 c4 <unknown>

test/MC/AArch64/SVE/ld1sw.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 5f c5 <unknown> // CHECK-UNKNOWN: ff 9f 5f c5 <unknown>
ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-INST: ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] // CHECK-INST: ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5] // CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 8d 68 c5 <unknown> // CHECK-UNKNOWN: b7 8d 68 c5 <unknown>
ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x15,0x15,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 15 c5 <unknown>
ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x15,0x55,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 15 55 c5 <unknown>

test/MC/AArch64/SVE/ld1w.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df 5f c5 <unknown> // CHECK-UNKNOWN: ff df 5f c5 <unknown>
ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2] ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-INST: ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2] // CHECK-INST: ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5] // CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 cd 68 c5 <unknown> // CHECK-UNKNOWN: b7 cd 68 c5 <unknown>
ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x55,0x15,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 15 c5 <unknown>
ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x55,0x55,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 55 55 c5 <unknown>

test/MC/AArch64/SVE/ldff1b.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 40 84 <unknown> // CHECK-UNKNOWN: 00 60 40 84 <unknown>
ldff1b { z31.d }, p7/z, [sp, z31.d] ldff1b { z31.d }, p7/z, [sp, z31.d]
// CHECK-INST: ldff1b { z31.d }, p7/z, [sp, z31.d] // CHECK-INST: ldff1b { z31.d }, p7/z, [sp, z31.d]
// CHECK-ENCODING: [0xff,0xff,0x5f,0xc4] // CHECK-ENCODING: [0xff,0xff,0x5f,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 5f c4 <unknown> // CHECK-UNKNOWN: ff ff 5f c4 <unknown>
ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x75,0x15,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 15 c4 <unknown>
ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 55 c4 <unknown>

test/MC/AArch64/SVE/ldff1d.s

Show All 30 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff df c5 <unknown> // CHECK-UNKNOWN: ff ff df c5 <unknown>
ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3] ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
// CHECK-INST: ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3] // CHECK-INST: ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5] // CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed e8 c5 <unknown> // CHECK-UNKNOWN: b7 ed e8 c5 <unknown>
ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x75,0x95,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 95 c5 <unknown>
ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x75,0xd5,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 d5 c5 <unknown>

test/MC/AArch64/SVE/ldff1h.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff df c4 <unknown> // CHECK-UNKNOWN: ff ff df c4 <unknown>
ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1] ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-INST: ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1] // CHECK-INST: ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4] // CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed e8 c4 <unknown> // CHECK-UNKNOWN: b7 ed e8 c4 <unknown>
ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x75,0x95,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 95 c4 <unknown>
ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x75,0xd5,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 d5 c4 <unknown>

test/MC/AArch64/SVE/ldff1sb.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 20 40 84 <unknown> // CHECK-UNKNOWN: 00 20 40 84 <unknown>
ldff1sb { z31.d }, p7/z, [sp, z31.d] ldff1sb { z31.d }, p7/z, [sp, z31.d]
// CHECK-INST: ldff1sb { z31.d }, p7/z, [sp, z31.d] // CHECK-INST: ldff1sb { z31.d }, p7/z, [sp, z31.d]
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4] // CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 5f c4 <unknown> // CHECK-UNKNOWN: ff bf 5f c4 <unknown>
ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x35,0x15,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 15 c4 <unknown>
ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 55 c4 <unknown>

test/MC/AArch64/SVE/ldff1sh.s

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf df c4 <unknown> // CHECK-UNKNOWN: ff bf df c4 <unknown>
ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-INST: ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] // CHECK-INST: ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
// CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4] // CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ad e8 c4 <unknown> // CHECK-UNKNOWN: b7 ad e8 c4 <unknown>
ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x35,0x95,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 95 c4 <unknown>
ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x35,0xd5,0xc4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 d5 c4 <unknown>

test/MC/AArch64/SVE/ldff1sw.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 5f c5 <unknown> // CHECK-UNKNOWN: ff bf 5f c5 <unknown>
ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-INST: ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] // CHECK-INST: ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-ENCODING: [0xb7,0xad,0x68,0xc5] // CHECK-ENCODING: [0xb7,0xad,0x68,0xc5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ad 68 c5 <unknown> // CHECK-UNKNOWN: b7 ad 68 c5 <unknown>
ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x35,0x15,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 15 c5 <unknown>
ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x35,0x55,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 35 55 c5 <unknown>

test/MC/AArch64/SVE/ldff1w.s

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// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 5f c5 <unknown> // CHECK-UNKNOWN: ff ff 5f c5 <unknown>
ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2] ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-INST: ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2] // CHECK-INST: ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
// CHECK-ENCODING: [0xb7,0xed,0x68,0xc5] // CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed 68 c5 <unknown> // CHECK-UNKNOWN: b7 ed 68 c5 <unknown>
ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x75,0x15,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 15 c5 <unknown>
ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x75,0x55,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 55 c5 <unknown>