[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector (32bit elts, unscaled)) load instructions.

[sdesmalen]

Summary

Patch [2/8] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:

• Patch [1/8]: https://reviews.llvm.org/D45951
• Patch [2/8]: https://reviews.llvm.org/D45952
• Patch [3/8]: https://reviews.llvm.org/D45953
• Patch [4/8]: https://reviews.llvm.org/D45954
• Patch [5/8]: https://reviews.llvm.org/D45955
• Patch [6/8]: https://reviews.llvm.org/D45956
• Patch [7/8]: https://reviews.llvm.org/D45957
• Patch [8/8]: https://reviews.llvm.org/D45958

[rengolin]

These patches all look very similar, I think they could be all in the same commit? Even being large, may be easier to see how they are similar and do a quick review.

[sdesmalen]

In D45952#1076019, @rengolin wrote:

These patches all look very similar, I think they could be all in the same commit? Even being large, may be easier to see how they are similar and do a quick review.

Hi Renato, they could indeed be in a single commit but I thought it would be easier to review by distinguish them as separate patches based on their addressing modes, e.g.

scalar + vector (32bit elts, unscaled)
  vs e.g.
scalar + vector (64bit elts, scaled)

I'd be happy to squash them into a single commit and upload a new patch, but would it for this series be sufficient to use the one-liner below and do a 'svn diff' to see how they compare?

for patch in $(seq 45952 45957); do
  arc patch D${patch};
done

[sdesmalen]

Replaced by D46023

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4Scale4MulVl>;
   defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s,   "ld2w", simm4Scale2MulVl>;
   defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s,  "ld3w", simm4Scale3MulVl>;
   defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4Scale4MulVl>;
   defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d,   "ld2d", simm4Scale2MulVl>;
   defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d,  "ld3d", simm4Scale3MulVl>;
   defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4Scale4MulVl>;
 
+  // Gathers using unscaled 32-bit offsets, e.g.
+  //    ld1h z32.s, p0/z, [z0.s, uxtw]
+  defm GLD1SB_S   : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb",   ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1B_S    : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1B_S  : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1SH_S   : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh",   ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1H_S    : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1H_S  : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLD1W      : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w",    ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+  defm GLDFF1W    : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w",  ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+
   // continuous store with immediates
   defm ST1B_IMM   : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
   defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
   defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
   defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
   defm ST1H_IMM   : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
   defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
   defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;

lib/Target/AArch64/SVEInstrFormats.td

 
 multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                           string asm, Operand immtype> {
   def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
                   (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
 }
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - 32-bit Gather and Unsized Contiguous Group
+//===----------------------------------------------------------------------===//
+
+class sve_mem_32b_gld_vs<bits<4> opc, bit xs, string asm,
+                         RegisterOperand zprext>
+: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+  asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zm;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1000010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22}    = xs;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Zm;
+  let Inst{15}    = 0b0;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
+                                          RegisterOperand sxtw_opnd,
+                                          RegisterOperand uxtw_opnd> {
+  def _UXTW_REAL : sve_mem_32b_gld_vs<opc, 0, asm, uxtw_opnd>;
+  def _SXTW_REAL : sve_mem_32b_gld_vs<opc, 1, asm, sxtw_opnd>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}

test/MC/AArch64/SVE/ld1b.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 55 55 a4 <unknown>
 
 ld1b    { z23.d }, p3/z, [x13, x8]
 // CHECK-INST: ld1b    { z23.d }, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 68 a4 <unknown>
+
+ld1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 84 <unknown>
+
+ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 84 <unknown>

test/MC/AArch64/SVE/ld1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 55 d5 a4 <unknown>
 
 ld1h    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1h    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d e8 a4 <unknown>
+
+ld1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 84 <unknown>
+
+ld1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 84 <unknown>

test/MC/AArch64/SVE/ld1sb.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 55 b5 a5 <unknown>
 
 ld1sb    { z23.d }, p3/z, [x13, x8]
 // CHECK-INST: ld1sb    { z23.d }, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 88 a5 <unknown>
+
+ld1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x00,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 00 84 <unknown>
+
+ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x00,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 40 84 <unknown>

test/MC/AArch64/SVE/ld1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 55 35 a5 <unknown>
 
 ld1sh    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1sh    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 08 a5 <unknown>
+
+ld1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x00,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 80 84 <unknown>
+
+ld1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 c0 84 <unknown>

test/MC/AArch64/SVE/ld1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 55 55 a5 <unknown>
 
 ld1w    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1w    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 68 a5 <unknown>
+
+ld1w    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1w    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x00,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 85 <unknown>
+
+ld1w    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1w    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 85 <unknown>

test/MC/AArch64/SVE/ldff1b.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 40 a4 <unknown>
 
 ldff1b  { z0.d }, p0/z, [x0, x0]
 // CHECK-INST: ldff1b  { z0.d }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 60 a4 <unknown>
+
+ldff1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 84 <unknown>
+
+ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 84 <unknown>

test/MC/AArch64/SVE/ldff1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 c0 a4 <unknown>
 
 ldff1h  { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1h  { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 a4 <unknown>
+
+ldff1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 80 84 <unknown>
+
+ldff1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 c0 84 <unknown>

test/MC/AArch64/SVE/ldff1sb.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 a0 a5 <unknown>
 
 ldff1sb { z0.d }, p0/z, [x0, x0]
 // CHECK-INST: ldff1sb { z0.d }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 80 a5 <unknown>
+
+ldff1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x20,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 00 84 <unknown>
+
+ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x20,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 40 84 <unknown>

test/MC/AArch64/SVE/ldff1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 20 a5 <unknown>
 
 ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 00 a5 <unknown>
+
+ldff1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x20,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 80 84 <unknown>
+
+ldff1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x20,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 c0 84 <unknown>

test/MC/AArch64/SVE/ldff1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 40 a5 <unknown>
 
 ldff1w  { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ldff1w  { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 60 a5 <unknown>
+
+ldff1w  { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x00,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 85 <unknown>
+
+ldff1w  { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 85 <unknown>