[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector (64bit elts, unscaled)) load instructions.

[sdesmalen]

Summary

Patch [4/8] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:

• Patch [1/8]: https://reviews.llvm.org/D45951
• Patch [2/8]: https://reviews.llvm.org/D45952
• Patch [3/8]: https://reviews.llvm.org/D45953
• Patch [4/8]: https://reviews.llvm.org/D45954
• Patch [5/8]: https://reviews.llvm.org/D45955
• Patch [6/8]: https://reviews.llvm.org/D45956
• Patch [7/8]: https://reviews.llvm.org/D45957
• Patch [8/8]: https://reviews.llvm.org/D45958

[sdesmalen]

Replaced by D46023

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   //    ld1h z32.s, p0/z, [z0.s, uxtw #1]
   defm GLD1SH_S   : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh",   ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
   defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
   defm GLD1H_S    : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h",    ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
   defm GLDFF1H_S  : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h",  ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
   defm GLD1W      : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w",    ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
   defm GLDFF1W    : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w",  ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
 
+  // Gathers using unscaled 64-bit offsets, e.g.
+  //    ld1h z32.d, p0/z, [x0, z0.d]
+  defm GLD1SB_D   : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
+  defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">;
+  defm GLD1B_D    : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">;
+  defm GLDFF1B_D  : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">;
+  defm GLD1SH_D   : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh">;
+  defm GLDFF1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0101, "ldff1sh">;
+  defm GLD1H_D    : sve_mem_64b_gld_vs2_64_unscaled<0b0110, "ld1h">;
+  defm GLDFF1H_D  : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
+  defm GLD1SW_D   : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
+  defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
+  defm GLD1W_D    : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">;
+  defm GLDFF1W_D  : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
+  defm GLD1D      : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">;
+  defm GLDFF1D    : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
+
   // continuous store with immediates
   defm ST1B_IMM   : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
   defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
   defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
   defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
   defm ST1H_IMM   : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
   defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
   defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;

lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
   def _UXTW_REAL : sve_mem_32b_gld_vs<opc, 0, asm, uxtw_opnd>;
   def _SXTW_REAL : sve_mem_32b_gld_vs<opc, 1, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
                   (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
                   (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 }
+
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - 64-bit Gather Group
+//===----------------------------------------------------------------------===//
+
+class sve_mem_64b_gld_vs2<bits<4> opc, string asm>
+: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm),
+  asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zm;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1100010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22-21} = 0b10;
+  let Inst{20-16} = Zm;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> {
+  def _REAL : sve_mem_64b_gld_vs2<opc, asm>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
+}

test/MC/AArch64/SVE/ld1b.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 00 84 <unknown>
 
 ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x40,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 40 84 <unknown>
+
+ld1b    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1b    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 5f c4 <unknown>

test/MC/AArch64/SVE/ld1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: f7 4f e8 a5 <unknown>
 
 ld1d    { z23.d }, p3/z, [x13, x8, lsl #3]
 // CHECK-INST: ld1d    { z23.d }, p3/z, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d e8 a5 <unknown>
+
+ld1d    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1d    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0xdf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df df c5 <unknown>

test/MC/AArch64/SVE/ld1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 5f bf 84 <unknown>
 
 ld1h    { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ld1h    { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x5f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 5f ff 84 <unknown>
+
+ld1h    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1h    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df df c4 <unknown>

test/MC/AArch64/SVE/ld1sb.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 00 84 <unknown>
 
 ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x00,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 40 84 <unknown>
+
+ld1sb   { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1sb   { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 5f c4 <unknown>

test/MC/AArch64/SVE/ld1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f bf 84 <unknown>
 
 ld1sh   { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ld1sh   { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x1f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f ff 84 <unknown>
+
+ld1sh   { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1sh   { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0x9f,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f df c4 <unknown>

test/MC/AArch64/SVE/ld1sw.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: f7 4f 88 a4 <unknown>
 
 ld1sw    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1sw    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 88 a4 <unknown>
+
+ld1sw   { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1sw   { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 5f c5 <unknown>

test/MC/AArch64/SVE/ld1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 5f 3f 85 <unknown>
 
 ld1w    { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-INST: ld1w    { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-ENCODING: [0xff,0x5f,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 5f 7f 85 <unknown>
+
+ld1w    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1w    { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 5f c5 <unknown>

test/MC/AArch64/SVE/ldff1b.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 00 84 <unknown>
 
 ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x60,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 40 84 <unknown>
+
+ldff1b  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1b  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 5f c4 <unknown>

test/MC/AArch64/SVE/ldff1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f ff a5 <unknown>
 
 ldff1d  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ldff1d  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 a5 <unknown>
+
+ldff1d  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1d  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0xdf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff df c5 <unknown>

test/MC/AArch64/SVE/ldff1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f bf 84 <unknown>
 
 ldff1h  { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ldff1h  { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x7f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f ff 84 <unknown>
+
+ldff1h  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1h  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff df c4 <unknown>

test/MC/AArch64/SVE/ldff1sb.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 00 84 <unknown>
 
 ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x20,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 40 84 <unknown>
+
+ldff1sb { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1sb { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f c4 <unknown>

test/MC/AArch64/SVE/ldff1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 3f bf 84 <unknown>
 
 ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x3f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 3f ff 84 <unknown>
+
+ldff1sh { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1sh { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf df c4 <unknown>

test/MC/AArch64/SVE/ldff1sw.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f 9f a4 <unknown>
 
 ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 80 a4 <unknown>
+
+ldff1sw { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1sw { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f c5 <unknown>

test/MC/AArch64/SVE/ldff1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f 3f 85 <unknown>
 
 ldff1w  { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-INST: ldff1w  { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-ENCODING: [0xff,0x7f,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f 7f 85 <unknown>
+
+ldff1w  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1w  { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 5f c5 <unknown>