[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector (64bit elts, scaled)) load instructions.

[sdesmalen]

Summary

Patch [5/8] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:

• Patch [1/8]: https://reviews.llvm.org/D45951
• Patch [2/8]: https://reviews.llvm.org/D45952
• Patch [3/8]: https://reviews.llvm.org/D45953
• Patch [4/8]: https://reviews.llvm.org/D45954
• Patch [5/8]: https://reviews.llvm.org/D45955
• Patch [6/8]: https://reviews.llvm.org/D45956
• Patch [7/8]: https://reviews.llvm.org/D45957
• Patch [8/8]: https://reviews.llvm.org/D45958

[sdesmalen]

Replaced by D46023

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm GLDFF1H_D  : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
   defm GLD1SW_D   : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
   defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
   defm GLD1W_D    : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">;
   defm GLDFF1W_D  : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
   defm GLD1D      : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">;
   defm GLDFF1D    : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
 
+  // Gathers using scaled 64-bit offsets, e.g.
+  //    ld1h z32.d, p0/z, [x0, z0.d, lsl #1]
+  defm GLD1SH_D   : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh",   ZPR64ExtLSL16>;
+  defm GLDFF1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0101, "ldff1sh", ZPR64ExtLSL16>;
+  defm GLD1H_D    : sve_mem_64b_gld_sv2_64_scaled<0b0110, "ld1h",    ZPR64ExtLSL16>;
+  defm GLDFF1H_D  : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h",  ZPR64ExtLSL16>;
+  defm GLD1SW_D   : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw",   ZPR64ExtLSL32>;
+  defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
+  defm GLD1W_D    : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w",    ZPR64ExtLSL32>;
+  defm GLDFF1W_D  : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w",  ZPR64ExtLSL32>;
+  defm GLD1D      : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d",    ZPR64ExtLSL64>;
+  defm GLDFF1D    : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d",  ZPR64ExtLSL64>;
+
   // continuous store with immediates
   defm ST1B_IMM   : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
   defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
   defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
   defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
   defm ST1H_IMM   : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
   defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
   defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;

lib/Target/AArch64/SVEInstrFormats.td

def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
                   (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 }
 
 
 //===----------------------------------------------------------------------===//
 // SVE Memory - 64-bit Gather Group
 //===----------------------------------------------------------------------===//
 
+class sve_mem_64b_gld_sv2<bits<4> opc, string asm, RegisterOperand zprext>
+: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+  asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zm;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1100010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22-21} = 0b11;
+  let Inst{20-16} = Zm;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
+                                         RegisterOperand zprext> {
+  def _SCALED_REAL : sve_mem_64b_gld_sv2<opc, asm, zprext>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+                  (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
+}
+
 class sve_mem_64b_gld_vs2<bits<4> opc, string asm>
 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;

test/MC/AArch64/SVE/ld1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d e8 a5 <unknown>
 
 ld1d    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1d    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0xdf,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff df df c5 <unknown>
+
+ld1d    { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-INST: ld1d    { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 cd e8 c5 <unknown>

test/MC/AArch64/SVE/ld1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 5f ff 84 <unknown>
 
 ld1h    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1h    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff df df c4 <unknown>
+
+ld1h    { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ld1h    { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 cd e8 c4 <unknown>

test/MC/AArch64/SVE/ld1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f ff 84 <unknown>
 
 ld1sh   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1sh   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 9f df c4 <unknown>
+
+ld1sh   { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ld1sh   { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 8d e8 c4 <unknown>

test/MC/AArch64/SVE/ld1sw.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 4d 88 a4 <unknown>
 
 ld1sw   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1sw   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 9f 5f c5 <unknown>
+
+ld1sw   { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ld1sw   { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 8d 68 c5 <unknown>

test/MC/AArch64/SVE/ld1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 5f 7f 85 <unknown>
 
 ld1w    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1w    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff df 5f c5 <unknown>
+
+ld1w    { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ld1w    { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 cd 68 c5 <unknown>

test/MC/AArch64/SVE/ldff1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 a5 <unknown>
 
 ldff1d  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1d  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0xdf,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff df c5 <unknown>
+
+ldff1d  { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-INST: ldff1d  { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed e8 c5 <unknown>

test/MC/AArch64/SVE/ldff1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f ff 84 <unknown>
 
 ldff1h  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1h  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff df c4 <unknown>
+
+ldff1h  { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ldff1h  { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed e8 c4 <unknown>

test/MC/AArch64/SVE/ldff1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 3f ff 84 <unknown>
 
 ldff1sh { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1sh { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf df c4 <unknown>
+
+ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ad e8 c4 <unknown>

test/MC/AArch64/SVE/ldff1sw.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 80 a4 <unknown>
 
 ldff1sw { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1sw { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 5f c5 <unknown>
+
+ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0xad,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ad 68 c5 <unknown>

test/MC/AArch64/SVE/ldff1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 7f 7f 85 <unknown>
 
 ldff1w  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1w  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff 5f c5 <unknown>
+
+ldff1w  { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ldff1w  { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 68 c5 <unknown>