[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.

[sdesmalen]

Summary

This is patch [4/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:

• Patch [1/4]: https://reviews.llvm.org/D45687
• Patch [2/4]: https://reviews.llvm.org/D45688
• Patch [3/4]: https://reviews.llvm.org/D45689
• Patch [4/4]: https://reviews.llvm.org/D45690

[sdesmalen]

• NFC: Reordered the position of the instructions in the .td file.

[sdesmalen]

NFC: Removed unused-attribute from DecodeGPR64commonRegisterClass.

[javed.absar]

Hi Sander.
Its good you mention 'patch [4/4] in a series' in commit message. But could you please also link them up by providing link to previous reviews etc.
Might be easy for tracking later.

[sdesmalen]

In D45690#1070865, @javed.absar wrote:

Hi Sander.
Its good you mention 'patch [4/4] in a series' in commit message. But could you please also link them up by providing link to previous reviews etc.
Might be easy for tracking later.

Thanks for the suggestion Javed, I've updated the descriptions with links to other patches in the series.

[fhahn]

LGTM, mechanical change adding support for SVE LD1 (scalar+scalar) instrucitons

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
   defm LD1W_IMM    : sve_mem_cld_si<0b1010, "ld1w",  Z_s, ZPR32>;
   defm LD1W_D_IMM  : sve_mem_cld_si<0b1011, "ld1w",  Z_d, ZPR64>;
   defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
   defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
   defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
   defm LD1D_IMM    : sve_mem_cld_si<0b1111, "ld1d",  Z_d, ZPR64>;
 
+  // continuous load with reg+reg addressing.
+  defm LD1B    : sve_mem_cld_ss<0b0000, "ld1b",  Z_b, ZPR8,  GPR64NoXZRshifted8>;
+  defm LD1B_H  : sve_mem_cld_ss<0b0001, "ld1b",  Z_h, ZPR16, GPR64NoXZRshifted8>;
+  defm LD1B_S  : sve_mem_cld_ss<0b0010, "ld1b",  Z_s, ZPR32, GPR64NoXZRshifted8>;
+  defm LD1B_D  : sve_mem_cld_ss<0b0011, "ld1b",  Z_d, ZPR64, GPR64NoXZRshifted8>;
+  defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
+  defm LD1H    : sve_mem_cld_ss<0b0101, "ld1h",  Z_h, ZPR16, GPR64NoXZRshifted16>;
+  defm LD1H_S  : sve_mem_cld_ss<0b0110, "ld1h",  Z_s, ZPR32, GPR64NoXZRshifted16>;
+  defm LD1H_D  : sve_mem_cld_ss<0b0111, "ld1h",  Z_d, ZPR64, GPR64NoXZRshifted16>;
+  defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>;
+  defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
+  defm LD1W    : sve_mem_cld_ss<0b1010, "ld1w",  Z_s, ZPR32, GPR64NoXZRshifted32>;
+  defm LD1W_D  : sve_mem_cld_ss<0b1011, "ld1w",  Z_d, ZPR64, GPR64NoXZRshifted32>;
+  defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
+  defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;
+  defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;
+  defm LD1D    : sve_mem_cld_ss<0b1111, "ld1d",  Z_d, ZPR64, GPR64NoXZRshifted64>;
+
   // LD(2|3|4) structured loads with reg+immediate
   defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b,   "ld2b", simm4Scale2MulVl>;
   defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b,  "ld3b", simm4Scale3MulVl>;
   defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, ZZZZ_b, "ld4b", simm4Scale4MulVl>;
   defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h,   "ld2h", simm4Scale2MulVl>;
   defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, ZZZ_h,  "ld3h", simm4Scale3MulVl>;
   defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4Scale4MulVl>;
   defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s,   "ld2w", simm4Scale2MulVl>;

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
                                             const void *Decoder);
-LLVM_ATTRIBUTE_UNUSED
 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,

lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
                   (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
                           ZPRRegOp zprty>
 : sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
 
+class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
+                          RegisterOperand VecList>
+: I<(outs VecList:$Zt), iops,
+  asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
+  "",
+  []>, Sched<[]> {
+  bits<5> Zt;
+  bits<3> Pg;
+  bits<5> Rm;
+  bits<5> Rn;
+  let Inst{31-25} = 0b1010010;
+  let Inst{24-21} = dtype;
+  let Inst{20-16} = Rm;
+  let Inst{15-14} = 0b01;
+  let Inst{13}    = ff;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Uses = !if(!eq(ff, 1), [FFR], []);
+  let Defs = !if(!eq(ff, 1), [FFR], []);
+}
+
+multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
+                          ZPRRegOp zprty, RegisterOperand gprty> {
+  def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+                               asm, listty>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+}
+
+
 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, Operand immtype>
 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;

 }
 
 multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                           string asm, Operand immtype> {
   def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
                   (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
-}
+}
 No newline at end of file

test/MC/AArch64/SVE/ld1b-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1b z0.b, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.b, p0/z, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.b, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.b, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1b.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 6f a4 <unknown>
 
 ld1b    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1b    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x65,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 65 a4 <unknown>
+
+ld1b    { z0.b }, p0/z, [sp, x0]
+// CHECK-INST: ld1b    { z0.b }, p0/z, [sp, x0]
+// CHECK-ENCODING: [0xe0,0x43,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 43 00 a4 <unknown>
+
+ld1b    { z0.b }, p0/z, [x0, x0]
+// CHECK-INST: ld1b    { z0.b }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 a4 <unknown>
+
+ld1b    { z0.b }, p0/z, [x0, x0, lsl #0]
+// CHECK-INST: ld1b    { z0.b }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 a4 <unknown>
+
+ld1b    { z5.h }, p3/z, [x17, x16]
+// CHECK-INST: ld1b    { z5.h }, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0x4e,0x30,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 4e 30 a4 <unknown>
+
+ld1b    { z21.s }, p5/z, [x10, x21]
+// CHECK-INST: ld1b    { z21.s }, p5/z, [x10, x21]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 55 a4 <unknown>
+
+ld1b    { z23.d }, p3/z, [x13, x8]
+// CHECK-INST: ld1b    { z23.d }, p3/z, [x13, x8]
+// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d 68 a4 <unknown>

test/MC/AArch64/SVE/ld1d-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1d z0.d, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1d.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf ef a5 <unknown>
 
 ld1d    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1d    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xe5,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 e5 a5 <unknown>
+
+ld1d    { z23.d }, p3/z, [sp, x8, lsl #3]
+// CHECK-INST: ld1d    { z23.d }, p3/z, [sp, x8, lsl #3]
+// CHECK-ENCODING: [0xf7,0x4f,0xe8,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: f7 4f e8 a5 <unknown>
+
+ld1d    { z23.d }, p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d    { z23.d }, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d e8 a5 <unknown>

test/MC/AArch64/SVE/ld1h-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1h z0.h, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.h, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.h, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.h, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.h, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1h.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf ef a4 <unknown>
 
 ld1h    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1h    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xe5,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 e5 a4 <unknown>
+
+ld1h    { z5.h }, p3/z, [sp, x16, lsl #1]
+// CHECK-INST: ld1h    { z5.h }, p3/z, [sp, x16, lsl #1]
+// CHECK-ENCODING: [0xe5,0x4f,0xb0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e5 4f b0 a4 <unknown>
+
+ld1h    { z5.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h    { z5.h }, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x4e,0xb0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 4e b0 a4 <unknown>
+
+ld1h    { z21.s }, p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h    { z21.s }, p5/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 d5 a4 <unknown>
+
+ld1h    { z23.d }, p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h    { z23.d }, p3/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d e8 a4 <unknown>

test/MC/AArch64/SVE/ld1sb-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1sb z0.h, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.h, p0/z, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.h, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.h, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sb.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 8f a5 <unknown>
 
 ld1sb   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x85,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 85 a5 <unknown>
+
+ld1sb    { z0.h }, p0/z, [sp, x0]
+// CHECK-INST: ld1sb    { z0.h }, p0/z, [sp, x0]
+// CHECK-ENCODING: [0xe0,0x43,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 43 c0 a5 <unknown>
+
+ld1sb    { z0.h }, p0/z, [x0, x0]
+// CHECK-INST: ld1sb    { z0.h }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 a5 <unknown>
+
+ld1sb    { z0.h }, p0/z, [x0, x0, lsl #0]
+// CHECK-INST: ld1sb    { z0.h }, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 a5 <unknown>
+
+ld1sb    { z21.s }, p5/z, [x10, x21]
+// CHECK-INST: ld1sb    { z21.s }, p5/z, [x10, x21]
+// CHECK-ENCODING: [0x55,0x55,0xb5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 b5 a5 <unknown>
+
+ld1sb    { z23.d }, p3/z, [x13, x8]
+// CHECK-INST: ld1sb    { z23.d }, p3/z, [x13, x8]
+// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d 88 a5 <unknown>

test/MC/AArch64/SVE/ld1sh-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1sh z0.s, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sh.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 0f a5 <unknown>
 
 ld1sh   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x05,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 05 a5 <unknown>
+
+ld1sh    { z21.s }, p5/z, [sp, x21, lsl #1]
+// CHECK-INST: ld1sh    { z21.s }, p5/z, [sp, x21, lsl #1]
+// CHECK-ENCODING: [0xf5,0x57,0x35,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: f5 57 35 a5 <unknown>
+
+ld1sh    { z21.s }, p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1sh    { z21.s }, p5/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x55,0x55,0x35,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 35 a5 <unknown>
+
+ld1sh    { z23.d }, p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1sh    { z23.d }, p3/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d 08 a5 <unknown>

test/MC/AArch64/SVE/ld1sw-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1sw z0.d, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sw.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 8f a4 <unknown>
 
 ld1sw   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x85,0xa4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 85 a4 <unknown>
+
+ld1sw    { z23.d }, p3/z, [sp, x8, lsl #2]
+// CHECK-INST: ld1sw    { z23.d }, p3/z, [sp, x8, lsl #2]
+// CHECK-ENCODING: [0xf7,0x4f,0x88,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: f7 4f 88 a4 <unknown>
+
+ld1sw    { z23.d }, p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1sw    { z23.d }, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d 88 a4 <unknown>

test/MC/AArch64/SVE/ld1w-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid scalar + scalar addressing modes
+
+ld1w z0.s, p0/z, [x0, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [x0, xzr]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [x0, w0, uxtw]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1w.s

 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff bf 6f a5 <unknown>
 
 ld1w    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1w    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x65,0xa5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 b5 65 a5 <unknown>
+
+ld1w    { z21.s }, p5/z, [sp, x21, lsl #2]
+// CHECK-INST: ld1w    { z21.s }, p5/z, [sp, x21, lsl #2]
+// CHECK-ENCODING: [0xf5,0x57,0x55,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: f5 57 55 a5 <unknown>
+
+ld1w    { z21.s }, p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w    { z21.s }, p5/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 55 a5 <unknown>
+
+ld1w    { z23.d }, p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w    { z23.d }, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 4d 68 a5 <unknown>