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[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
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Authored by sdesmalen on Apr 16 2018, 7:35 AM.

Details

Summary

This is patch [4/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:

Diff Detail

Repository
rL LLVM

Event Timeline

sdesmalen created this revision.Apr 16 2018, 7:35 AM
  • NFC: Reordered the position of the instructions in the .td file.
sdesmalen updated this revision to Diff 142777.Apr 17 2018, 7:51 AM

NFC: Removed unused-attribute from DecodeGPR64commonRegisterClass.

Hi Sander.
Its good you mention 'patch [4/4] in a series' in commit message. But could you please also link them up by providing link to previous reviews etc.
Might be easy for tracking later.

sdesmalen edited the summary of this revision. (Show Details)Apr 19 2018, 12:26 AM

Hi Sander.
Its good you mention 'patch [4/4] in a series' in commit message. But could you please also link them up by providing link to previous reviews etc.
Might be easy for tracking later.

Thanks for the suggestion Javed, I've updated the descriptions with links to other patches in the series.

fhahn accepted this revision.Apr 19 2018, 7:31 AM

LGTM, mechanical change adding support for SVE LD1 (scalar+scalar) instrucitons

This revision is now accepted and ready to land.Apr 19 2018, 7:31 AM
This revision was automatically updated to reflect the committed changes.