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[AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.
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Authored by sdesmalen on Apr 16 2018, 7:34 AM.

Details

Summary

In some cases the shift/extend needs to be explicitly parsed together
with the register, rather than as a separate operand. This is needed
for addressing modes where the instruction as a whole dictates the
scaling/extend, rather than specific bits in the instruction.
By parsing them as a single operand, we avoid the need to pass an
extra operand in all CodeGen patterns (because all operands need to
have an associated value), and we avoid the need to update TableGen to
accept operands that have no associated bits in the instruction.

An added benefit of parsing them together is that the assembler
can give a sensible diagnostic if the scaling is not correct.

This is patch [2/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:

Diff Detail

Repository
rL LLVM

Event Timeline

sdesmalen created this revision.Apr 16 2018, 7:34 AM
sdesmalen edited the summary of this revision. (Show Details)Apr 19 2018, 12:26 AM
SjoerdMeijer accepted this revision.Apr 19 2018, 12:42 AM

Looks reasonable to me.

This revision is now accepted and ready to land.Apr 19 2018, 12:42 AM
fhahn accepted this revision.Apr 19 2018, 7:19 AM

LGTM

lib/Target/AArch64/AArch64RegisterInfo.td
174 ↗(On Diff #142630)

This change seems unrelated to handling "integrated 'shift/extend'", but I do not think it is worth updating the diff just for that.

This revision was automatically updated to reflect the committed changes.