[AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.
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Authored by sdesmalen on Mon, Apr 16, 7:34 AM.

Details

Summary

This is patch [3/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:

Diff Detail

Repository
rL LLVM
sdesmalen created this revision.Mon, Apr 16, 7:34 AM
sdesmalen updated this revision to Diff 142775.Tue, Apr 17, 7:49 AM

Minor clean-up of patch:

  • Removed template argument from 'printRegWithShiftExtend'
  • Added unused attribute to DecodeGPR64commonRegisterClass (will be removed in next patch, but avoids breaking buildbot).
  • Rephrased diagnostic to say 'xzr' instead of 'x31'.
sdesmalen edited the summary of this revision. (Show Details)Thu, Apr 19, 12:26 AM
SjoerdMeijer accepted this revision.Thu, Apr 19, 1:07 AM

Looks good to me, just one nit inlined.

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
972 ↗(On Diff #142775)

Nit: SignExtend and DoShift can be booleans?

989 ↗(On Diff #142775)

Same here?

This revision is now accepted and ready to land.Thu, Apr 19, 1:07 AM
sdesmalen added inline comments.Thu, Apr 19, 6:42 AM
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
972 ↗(On Diff #142775)

Yes they can! I will change that before I commit, thanks for pointing out!

This revision was automatically updated to reflect the committed changes.