Make march/target-cpu print a note with the list of valid values for ARM

[erichkeane]

Summary

When rejecting a march= or target-cpu command line parameter,
the message is quite lacking. This patch adds a note that prints
all possible values for the current target, if the target supports it.

This adds support for the ARM/AArch64 targets (more to come!). These
two also require: https://reviews.llvm.org/D42979

[erichkeane]

LLVM patch here: https://reviews.llvm.org/D42979

[samparker]

No tests?

[fhahn]

I like the idea. However for all backends, except Arm and AArch64, we would have to maintain another list of CPU names. At least for the targets which implement isValidCPUName, we could add an array with valid names and use that. That's still not ideal, but I do not think we should hold back this patch until all targets use the same infrastructure to handle CPUs. As for tests, we should test the note for all backends I think.

test/Misc/target-parser.c

3

drop one set of //

[fhahn]

Also with tests for each backend, this diff will get quite big. As this is opt-in, it might make sense to enable backends separately.

[Hahnfeld]

I think this means that the Clang test needs to be updated whenever somebody adds an architecture to LLVM? Maybe just test that Clang emits a note and don't check which values it prints? These should be checked in the backend...

[fhahn]

In D42978#1001616, @Hahnfeld wrote:

I think this means that the Clang test needs to be updated whenever somebody adds an architecture to LLVM? Maybe just test that Clang emits a note and don't check which values it prints? These should be checked in the backend...

Yes, I agree checking all CPUs names is too fragile and not necessary for AArch64 or ARM, as the list of CPUs is provided by llvm.

It is probably enough to check if we emit the note for AArch64 and ARM and maybe check that it is non-empty or checking that it contains a CPU we know should always be there. Checking the full list may make sense for other backends, as we have to modify Clang directly to add support.

[erichkeane]

That makes sense. I changed the ARM one to check ONLY the first one, since in each case that seems like the oldest anyway. It at least makes sure that the lists are distinct, and avoids this cross-repo fragility.

[erichkeane]

Simplified ARM tests as requested.

[fhahn]

LGTM thanks. Please wait a day or so with committing so others can raise additional concerns.

test/Misc/target-invalid-cpu-note.c

8 ↗

(On Diff #133435)

stray newline? :)

[erichkeane]

Removed extra newline.

[Hahnfeld]

test/Misc/target-invalid-cpu-note.c

1 ↗

(On Diff #133442)

Is there a reason you don't use -verify=<prefix> in this test? That's what I've usually seen for checking errors and notes...

3 ↗

(On Diff #133442)

Is this guaranteed to be first? If not, you might want to add {{.*}} to account for future updates.

(If not using -verify as suggested above, you could also use ARM-SAME on a new-line. This should also allow arbitrary values in between.)

[erichkeane]

test/Misc/target-invalid-cpu-note.c

1 ↗

(On Diff #133442)

Um... wow... TIL.

3 ↗

(On Diff #133442)

Not guaranteed. I'll do this, thanks!

[erichkeane]

test/Misc/target-invalid-cpu-note.c

1 ↗

(On Diff #133442)

Sadly, -verify= doesn't seem to have a way to specify things that happen without a line-number, so I wasn't able to do it :/

[erichkeane]

Relaxed the test further.

[simpal01]

@erichkeane Could you please tell me why this was done only for -cc1 and if there is any plan to add this to the driver in general ?

include/clang/Basic/Cuda.h

enum class CudaArch {
   SM_50,
   SM_52,
   SM_53,
   SM_60,
   SM_61,
   SM_62,
   SM_70,
   SM_72,
+  LAST,
 };
 const char *CudaArchToString(CudaArch A);
 
 // The input should have the form "sm_20".
 CudaArch StringToCudaArch(llvm::StringRef S);
 
 enum class CudaVirtualArch {
   UNKNOWN,

include/clang/Basic/DiagnosticCommonKinds.td

 def note_invalid_subexpr_in_const_expr : Note<
   "subexpression not valid in a constant expression">;
 
 // Targets
 
 def err_target_unknown_triple : Error<
   "unknown target triple '%0', please use -triple or -arch">;
 def err_target_unknown_cpu : Error<"unknown target CPU '%0'">;
+def note_valid_options : Note<"valid target CPU values are: %0">;
 def err_target_unsupported_cpu_for_micromips : Error<
   "micromips is not supported for target CPU '%0'">;
 def err_target_unknown_abi : Error<"unknown target ABI '%0'">;
 def err_target_unsupported_abi : Error<"ABI '%0' is not supported on CPU '%1'">;
 def err_target_unsupported_abi_for_triple : Error<
   "ABI '%0' is not supported for '%1'">;
 def err_target_unknown_fpmath : Error<"unknown FP unit '%0'">;
 def err_target_unsupported_fpmath : Error<

include/clang/Basic/TargetInfo.h

public:
 
   /// \brief Target the specified CPU.
   ///
   /// \return  False on error (invalid CPU name).
   virtual bool setCPU(const std::string &Name) {
     return false;
   }
 
+  /// Fill a SmallVectorImpl with the valid values to setCPU.
+  virtual void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {}
+
   /// brief Determine whether this TargetInfo supports the given CPU name.
   virtual bool isValidCPUName(StringRef Name) const {
     return true;
   }
 
   /// \brief Use the specified ABI.
   ///
   /// \return False on error (invalid ABI name).

lib/Basic/Cuda.cpp

const char *CudaVersionToString(CudaVersion V) {
   case CudaVersion::CUDA_91:
     return "9.1";
   }
   llvm_unreachable("invalid enum");
 }
 
 const char *CudaArchToString(CudaArch A) {
   switch (A) {
+  case CudaArch::LAST:
+    break;
   case CudaArch::UNKNOWN:
     return "unknown";
   case CudaArch::SM_20:
     return "sm_20";
   case CudaArch::SM_21:
     return "sm_21";
   case CudaArch::SM_30:
     return "sm_30";
return llvm::StringSwitch<CudaVirtualArch>(S)
       .Case("compute_62", CudaVirtualArch::COMPUTE_62)
       .Case("compute_70", CudaVirtualArch::COMPUTE_70)
       .Case("compute_72", CudaVirtualArch::COMPUTE_72)
       .Default(CudaVirtualArch::UNKNOWN);
 }
 
 CudaVirtualArch VirtualArchForCudaArch(CudaArch A) {
   switch (A) {
+  case CudaArch::LAST:
+    break;
   case CudaArch::UNKNOWN:
     return CudaVirtualArch::UNKNOWN;
   case CudaArch::SM_20:
   case CudaArch::SM_21:
     return CudaVirtualArch::COMPUTE_20;
   case CudaArch::SM_30:
     return CudaVirtualArch::COMPUTE_30;
   case CudaArch::SM_32:
CudaVirtualArch VirtualArchForCudaArch(CudaArch A) {
   case CudaArch::SM_72:
     return CudaVirtualArch::COMPUTE_72;
   }
   llvm_unreachable("invalid enum");
 }
 
 CudaVersion MinVersionForCudaArch(CudaArch A) {
   switch (A) {
+  case CudaArch::LAST:
+    break;
   case CudaArch::UNKNOWN:
     return CudaVersion::UNKNOWN;
   case CudaArch::SM_20:
   case CudaArch::SM_21:
   case CudaArch::SM_30:
   case CudaArch::SM_32:
   case CudaArch::SM_35:
   case CudaArch::SM_37:

lib/Basic/Targets.cpp

 #include "Targets/SPIR.h"
 #include "Targets/Sparc.h"
 #include "Targets/SystemZ.h"
 #include "Targets/TCE.h"
 #include "Targets/WebAssembly.h"
 #include "Targets/X86.h"
 #include "Targets/XCore.h"
 #include "clang/Basic/Diagnostic.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Triple.h"
 
 using namespace clang;
 
 namespace clang {
 namespace targets {
 //===----------------------------------------------------------------------===//
 //  Common code shared among targets.
if (!Target) {
     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
     return nullptr;
   }
   Target->TargetOpts = Opts;
 
   // Set the target CPU if specified.
   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
+    SmallVector<StringRef, 32> ValidList;
+    Target->fillValidCPUList(ValidList);
+    if (!ValidList.empty())
+      Diags.Report(diag::note_valid_options) << llvm::join(ValidList, ",");
     return nullptr;
   }
 
   // Set the target ABI if specified.
   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
     return nullptr;
   }

lib/Basic/Targets/AArch64.h

 
 public:
   AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
 
   StringRef getABI() const override;
   bool setABI(const std::string &Name) override;
 
   bool isValidCPUName(StringRef Name) const override;
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
   bool setCPU(const std::string &Name) override;
 
   bool useFP16ConversionIntrinsics() const override {
     return false;
   }
 
   void getTargetDefinesARMV81A(const LangOptions &Opts,
                                MacroBuilder &Builder) const;

lib/Basic/Targets/AArch64.cpp

bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
   return Name == "generic" ||
          llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
 }
 
 bool AArch64TargetInfo::setCPU(const std::string &Name) {
   return isValidCPUName(Name);
 }
 
+void AArch64TargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  llvm::AArch64::fillValidCPUArchList(Values);
+}
+
 void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
                                                 MacroBuilder &Builder) const {
   Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
 }
 
 void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
                                                 MacroBuilder &Builder) const {
   // Also include the ARMv8.1 defines

lib/Basic/Targets/AMDGPU.h

public:
 
   bool isValidCPUName(StringRef Name) const override {
     if (getTriple().getArch() == llvm::Triple::amdgcn)
       return GK_NONE != parseAMDGCNName(Name);
     else
       return GK_NONE != parseR600Name(Name);
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override {
     if (getTriple().getArch() == llvm::Triple::amdgcn)
       GPU = parseAMDGCNName(Name);
     else
       GPU = parseR600Name(Name);
 
     return GPU != GK_NONE;
   }

lib/Basic/Targets/AMDGPU.cpp

return llvm::StringSwitch<GPUKind>(Name)
       .Case("stoney", GK_GFX8)
       .Case("gfx900", GK_GFX9)
       .Case("gfx901", GK_GFX9)
       .Case("gfx902", GK_GFX9)
       .Case("gfx903", GK_GFX9)
       .Default(GK_NONE);
 }
 
+void AMDGPUTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  if (getTriple().getArch() == llvm::Triple::amdgcn)
+    Values.append({"gfx600",    "tahiti", "gfx601",  "pitcairn", "verde",
+                   "oland",     "hainan", "gfx700",  "bonaire",  "kaveri",
+                   "gfx701",    "hawaii", "gfx702",  "gfx703",   "kabini",
+                   "mullins",   "gfx800", "iceland", "gfx801",   "carrizo",
+                   "gfx802",    "tonga",  "gfx803",  "fiji",     "polaris10",
+                   "polaris11", "gfx804", "gfx810",  "stoney",   "gfx900",
+                   "gfx901",    "gfx902", "gfx903"});
+  else
+    Values.append({"r600",  "rv610",   "rv620",   "rv630",   "rv635",
+                   "rs780", "rs880",   "rv670",   "rv710",   "rv730",
+                   "rv740", "rv770",   "palm",    "cedar",   "sumo",
+                   "sumo2", "redwood", "juniper", "hemlock", "cypress",
+                   "barts", "turks",   "caicos",  "cayman",  "aruba"});
+}
+
 void AMDGPUTargetInfo::setAddressSpaceMap(bool DefaultIsPrivate) {
   if (isGenericZero(getTriple())) {
     AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap
                                     : &AMDGPUGenIsZeroDefIsGenMap;
   } else {
     AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap
                                     : &AMDGPUPrivIsZeroDefIsGenMap;
   }

lib/Basic/Targets/ARM.h

initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
                  const std::vector<std::string> &FeaturesVec) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasFeature(StringRef Feature) const override;
 
   bool isValidCPUName(StringRef Name) const override;
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override;
 
   bool setFPMath(StringRef Name) override;
 
   bool useFP16ConversionIntrinsics() const override {
     return false;
   }
 

lib/Basic/Targets/ARM.cpp

return llvm::StringSwitch<bool>(Feature)
       .Default(false);
 }
 
 bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
   return Name == "generic" ||
          llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
 }
 
+void ARMTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
+  llvm::ARM::fillValidCPUArchList(Values);
+}
+
 bool ARMTargetInfo::setCPU(const std::string &Name) {
   if (Name != "generic")
     setArchInfo(llvm::ARM::parseCPUArch(Name));
 
   if (ArchKind == llvm::ARM::ArchKind::INVALID)
     return false;
   setAtomic();
   CPU = Name;

lib/Basic/Targets/AVR.h

public:
   IntType getLeastIntTypeByWidth(unsigned BitWidth, bool IsSigned) const final {
     // AVR uses int for int_least16_t and int_fast16_t.
     return BitWidth == 16
                ? (IsSigned ? SignedInt : UnsignedInt)
                : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
   }
 
   bool isValidCPUName(StringRef Name) const override;
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
   bool setCPU(const std::string &Name) override {
     bool isValid = isValidCPUName(Name);
     if (isValid)
       CPU = Name;
     return isValid;
   }
 
 protected:
   std::string CPU;
 };
 
 } // namespace targets
 } // namespace clang
 
 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_AVR_H

lib/Basic/Targets/AVR.cpp

bool AVRTargetInfo::isValidCPUName(StringRef Name) const {
 
   bool IsMCU =
       std::find_if(AVRMcus.begin(), AVRMcus.end(), [&](const MCUInfo &Info) {
         return Info.Name == Name;
       }) != AVRMcus.end();
   return IsFamily || IsMCU;
 }
 
+void AVRTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
+  Values.append({"avr1", "avr2", "avr25", "avr3", "avr31", "avr35", "avr4",
+                 "avr5", "avr51", "avr6", "avrxmega1", "avrxmega2", "avrxmega3",
+                 "avrxmega4", "avrxmega5", "avrxmega6", "avrxmega7",
+                 "avrtiny"});
+}
+
 void AVRTargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
   Builder.defineMacro("AVR");
   Builder.defineMacro("__AVR");
   Builder.defineMacro("__AVR__");
 
   if (!this->CPU.empty()) {
     auto It =
         std::find_if(AVRMcus.begin(), AVRMcus.end(), [&](const MCUInfo &Info) {
           return Info.Name == this->CPU;
         });
 
     if (It != AVRMcus.end())
       Builder.defineMacro(It->DefineName);
   }
 }

lib/Basic/Targets/BPF.h

public:
 
   bool isValidCPUName(StringRef Name) const override {
     if (Name == "generic" || Name == "v1" ||
         Name == "v2" || Name == "probe")
       return true;
     return false;
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override {
+    Values.append({"generic", "v1", "v2", "probe"});
+  }
+
   bool setCPU(const std::string &Name) override {
     StringRef CPUName(Name);
     return isValidCPUName(CPUName);
   }
 };
 } // namespace targets
 } // namespace clang
 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_BPF_H

lib/Basic/Targets/Hexagon.h

public:
   const char *getClobbers() const override { return ""; }
 
   static const char *getHexagonCPUSuffix(StringRef Name);
 
   bool isValidCPUName(StringRef Name) const override {
     return getHexagonCPUSuffix(Name);
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override {
     if (!isValidCPUName(Name))
       return false;
     CPU = Name;
     return true;
   }
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     return RegNo < 2 ? RegNo : -1;
   }
 };
 } // namespace targets
 } // namespace clang
 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H

lib/Basic/Targets/Hexagon.cpp

return llvm::StringSwitch<const char *>(Name)
       .Case("hexagonv5", "5")
       .Case("hexagonv55", "55")
       .Case("hexagonv60", "60")
       .Case("hexagonv62", "62")
       .Case("hexagonv65", "65")
       .Default(nullptr);
 }
 
+void HexagonTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.append({"hexagonv4", "hexagonv5", "hexagonv55", "hexagonv60",
+                 "hexagonv62", "hexagonv65"});
+}
+
 ArrayRef<Builtin::Info> HexagonTargetInfo::getTargetBuiltins() const {
   return llvm::makeArrayRef(BuiltinInfo, clang::Hexagon::LastTSBuiltin -
                                              Builtin::FirstTSBuiltin);
 }

lib/Basic/Targets/Lanai.h

LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
     MinGlobalAlign = 32;
   }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
 
   bool isValidCPUName(StringRef Name) const override;
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override;
 
   bool hasFeature(StringRef Feature) const override;
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 

lib/Basic/Targets/Lanai.cpp

 
 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
 bool LanaiTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::StringSwitch<bool>(Name).Case("v11", true).Default(false);
 }
+void LanaiTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.emplace_back("v11");
+}
 
 bool LanaiTargetInfo::setCPU(const std::string &Name) {
   CPU = llvm::StringSwitch<CPUKind>(Name).Case("v11", CK_V11).Default(CK_NONE);
 
   return CPU != CK_NONE;
 }
 
 bool LanaiTargetInfo::hasFeature(StringRef Feature) const {

lib/Basic/Targets/Mips.h

void setN32ABITypes() {
     IntMaxType = Int64Type;
     LongWidth = LongAlign = 32;
     PointerWidth = PointerAlign = 32;
     PtrDiffType = SignedInt;
     SizeType = UnsignedInt;
   }
 
   bool isValidCPUName(StringRef Name) const override;
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
 
   bool setCPU(const std::string &Name) override {
     CPU = Name;
     return isValidCPUName(Name);
   }
 
   const std::string &getCPU() const { return CPU; }
   bool

lib/Basic/Targets/Mips.cpp

return llvm::StringSwitch<bool>(Name)
       .Case("mips64r3", true)
       .Case("mips64r5", true)
       .Case("mips64r6", true)
       .Case("octeon", true)
       .Case("p5600", true)
       .Default(false);
 }
 
+void MipsTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.append({"mips1", "mips2", "mips3", "mips4", "mips5", "mips32",
+                 "mips32r2", "mips32r3", "mips32r5", "mips32r6", "mips64",
+                 "mips64r2", "mips64r3", "mips64r5", "mips64r6", "octeon",
+                 "p5600"});
+}
+
 void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
                                       MacroBuilder &Builder) const {
   if (BigEndian) {
     DefineStd(Builder, "MIPSEB", Opts);
     Builder.defineMacro("_MIPSEB");
   } else {
     DefineStd(Builder, "MIPSEL", Opts);
     Builder.defineMacro("_MIPSEL");

lib/Basic/Targets/NVPTX.h

BuiltinVaListKind getBuiltinVaListKind() const override {
     // FIXME: implement
     return TargetInfo::CharPtrBuiltinVaList;
   }
 
   bool isValidCPUName(StringRef Name) const override {
     return StringToCudaArch(Name) != CudaArch::UNKNOWN;
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override {
+    for (int i = static_cast<int>(CudaArch::SM_20);
+         i < static_cast<int>(CudaArch::LAST); ++i)
+      Values.emplace_back(CudaArchToString(static_cast<CudaArch>(i)));
+  }
+
   bool setCPU(const std::string &Name) override {
     GPU = StringToCudaArch(Name);
     return GPU != CudaArch::UNKNOWN;
   }
 
   void setSupportedOpenCLOpts() override {
     auto &Opts = getSupportedOpenCLOpts();
     Opts.support("cl_clang_storage_class_specifiers");

lib/Basic/Targets/NVPTX.cpp

 void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__PTX__");
   Builder.defineMacro("__NVPTX__");
   if (Opts.CUDAIsDevice) {
     // Set __CUDA_ARCH__ for the GPU specified.
     std::string CUDAArchCode = [this] {
       switch (GPU) {
+      case CudaArch::LAST:
+        break;
       case CudaArch::UNKNOWN:
         assert(false && "No GPU arch when compiling CUDA device code.");
         return "";
       case CudaArch::SM_20:
         return "200";
       case CudaArch::SM_21:
         return "210";
       case CudaArch::SM_30:

lib/Basic/Targets/Nios2.h

bool setABI(const std::string &Name) override {
     }
     return false;
   }
 
   bool isValidCPUName(StringRef Name) const override {
     return Name == "nios2r1" || Name == "nios2r2";
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override {
+    Values.append({"nios2r1", "nios2r2"});
+  }
+
   bool setCPU(const std::string &Name) override {
     if (isValidCPUName(Name)) {
       CPU = Name;
       return true;
     }
     return false;
   }
 

lib/Basic/Targets/PPC.h

public:
   // Set the language option for altivec based on our value.
   void adjust(LangOptions &Opts) override;
 
   // Note: GCC recognizes the following additional cpus:
   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
   //  titan, rs64.
   bool isValidCPUName(StringRef Name) const override;
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
 
   bool setCPU(const std::string &Name) override {
     bool CPUKnown = isValidCPUName(Name);
     if (CPUKnown)
       CPU = Name;
     return CPUKnown;
   }
 

lib/Basic/Targets/PPC.cpp

return llvm::StringSwitch<bool>(Name)
       .Case("ppc", true)
       .Case("powerpc64", true)
       .Case("ppc64", true)
       .Case("powerpc64le", true)
       .Case("ppc64le", true)
       .Default(false);
 }
 
+void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
+  Values.append(
+      {"generic", "440",   "450",       "601",   "602",         "603",
+       "603e",    "603ev", "604",       "604e",  "620",         "630",
+       "g3",      "7400",  "g4",        "7450",  "g4+",         "750",
+       "970",     "g5",    "a2",        "a2q",   "e500mc",      "e5500",
+       "power3",  "pwr3",  "power4",    "pwr4",  "power5",      "pwr5",
+       "power5x", "pwr5x", "power6",    "pwr6",  "power6x",     "pwr6x",
+       "power7",  "pwr7",  "power8",    "pwr8",  "power9",      "pwr9",
+       "powerpc", "ppc",   "powerpc64", "ppc64", "powerpc64le", "ppc64le"});
+}
+
 void PPCTargetInfo::adjust(LangOptions &Opts) {
   if (HasAltivec)
     Opts.AltiVec = 1;
   TargetInfo::adjust(Opts);
 }
 
 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
   return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin -
                                              Builtin::FirstTSBuiltin);
 }

lib/Basic/Targets/Sparc.h

public:
   }
 
   CPUKind getCPUKind(StringRef Name) const;
 
   bool isValidCPUName(StringRef Name) const override {
     return getCPUKind(Name) != CK_GENERIC;
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override {
     CPU = getCPUKind(Name);
     return CPU != CK_GENERIC;
   }
 };
 
 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
 class LLVM_LIBRARY_VISIBILITY SparcV8TargetInfo : public SparcTargetInfo {
public:
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
 
   bool isValidCPUName(StringRef Name) const override {
     return getCPUGeneration(SparcTargetInfo::getCPUKind(Name)) == CG_V9;
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override {
     if (!SparcTargetInfo::setCPU(Name))
       return false;
     return getCPUGeneration(CPU) == CG_V9;
   }
 };
 } // namespace targets
 } // namespace clang
 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_SPARC_H

lib/Basic/Targets/Sparc.cpp

return llvm::StringSwitch<CPUKind>(Name)
       .Case("leon3", CK_LEON3)
       .Case("ut699", CK_LEON3_UT699)
       .Case("gr712rc", CK_LEON3_GR712RC)
       .Case("leon4", CK_LEON4)
       .Case("gr740", CK_LEON4_GR740)
       .Default(CK_GENERIC);
 }
 
+void SparcTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.append(
+      {"v8",           "supersparc", "sparclite", "f934",      "hypersparc",
+       "sparclite86x", "sparclet",   "tsc701",    "v9",        "ultrasparc",
+       "ultrasparc3",  "niagara",    "niagara2",  "niagara3",  "niagara4",
+       "ma2100",       "ma2150",     "ma2155",    "ma2450",    "ma2455",
+       "ma2x5x",       "ma2080",     "ma2085",    "ma2480",    "ma2485",
+       "ma2x8x",       "myriad2",    "myriad2.1", "myriad2.2", "myriad2.3",
+       "leon2",        "at697e",     "at697f",    "leon3",     "ut699",
+       "gr712rc",      "leon4",      "gr740"});
+}
+
 void SparcTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   DefineStd(Builder, "sparc", Opts);
   Builder.defineMacro("__REGISTER_PREFIX__", "");
 
   if (SoftFloat)
     Builder.defineMacro("SOFT_FLOAT", "1");
 }
void SparcV9TargetInfo::getTargetDefines(const LangOptions &Opts,
   Builder.defineMacro("__arch64__");
   // Solaris doesn't need these variants, but the BSDs do.
   if (getTriple().getOS() != llvm::Triple::Solaris) {
     Builder.defineMacro("__sparc64__");
     Builder.defineMacro("__sparc_v9__");
     Builder.defineMacro("__sparcv9__");
   }
 }
+void SparcV9TargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.append({"v9", "ultrasparc", "ultrasparc3", "niagra", "niagra2",
+                 "niagra3", "niagra4"});
+}

lib/Basic/Targets/SystemZ.h

public:
   }
 
   int getISARevision(const StringRef &Name) const;
 
   bool isValidCPUName(StringRef Name) const override {
     return getISARevision(Name) != -1;
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override {
     CPU = Name;
     ISARevision = getISARevision(CPU);
     return ISARevision != -1;
   }
 
   bool
   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,

lib/Basic/Targets/SystemZ.cpp

return llvm::StringSwitch<int>(Name)
       .Cases("arch8", "z10", 8)
       .Cases("arch9", "z196", 9)
       .Cases("arch10", "zEC12", 10)
       .Cases("arch11", "z13", 11)
       .Cases("arch12", "z14", 12)
       .Default(-1);
 }
 
+void SystemZTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.append({"arch8", "arch9", "arch10", "arch11", "arch12", "z10", "z196",
+                 "zEC12", "z13", "z14"});
+}
+
 bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("systemz", true)
       .Case("arch8", ISARevision >= 8)
       .Case("arch9", ISARevision >= 9)
       .Case("arch10", ISARevision >= 10)
       .Case("arch11", ISARevision >= 11)
       .Case("arch12", ISARevision >= 12)

lib/Basic/Targets/WebAssembly.h

private:
   }
 
   bool hasFeature(StringRef Feature) const final;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) final;
 
   bool isValidCPUName(StringRef Name) const final;
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const final;
 
   bool setCPU(const std::string &Name) final { return isValidCPUName(Name); }
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const final;
 
   BuiltinVaListKind getBuiltinVaListKind() const final {
     return VoidPtrBuiltinVaList;
   }

lib/Basic/Targets/WebAssembly.cpp

 bool WebAssemblyTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::StringSwitch<bool>(Name)
       .Case("mvp", true)
       .Case("bleeding-edge", true)
       .Case("generic", true)
       .Default(false);
 }
 
+void WebAssemblyTargetInfo::fillValidCPUList(
+    SmallVectorImpl<StringRef> &Values) const {
+  Values.append({"mvp", "bleeding-edge", "generic"});
+}
+
 void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts,
                                              MacroBuilder &Builder) const {
   defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
   if (SIMDLevel >= SIMD128)
     Builder.defineMacro("__wasm_simd128__");
 }
 
 bool WebAssemblyTargetInfo::handleTargetFeatures(

lib/Basic/Targets/X86.h

if (getTriple().getArch() == llvm::Triple::x86 &&
       return "no-mmx";
     return "";
   }
 
   bool isValidCPUName(StringRef Name) const override {
     return checkCPUKind(getCPUKind(Name));
   }
 
+  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
+
   bool setCPU(const std::string &Name) override {
     return checkCPUKind(CPU = getCPUKind(Name));
   }
 
   bool supportsMultiVersioning() const override {
     return getTriple().isOSBinFormatELF();
   }
   unsigned multiVersionSortPriority(StringRef Name) const override;

lib/Basic/Targets/X86.cpp

 // This file implements X86 TargetInfo objects.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86.h"
 #include "clang/Basic/Builtins.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/TargetBuiltins.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/TargetParser.h"
 
 namespace clang {
 namespace targets {
 
 const Builtin::Info BuiltinInfoX86[] = {
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
   default:
     return std::string(1, *Constraint);
   }
 }
 
 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
   // Perform any per-CPU checks necessary to determine if this CPU is
   // acceptable.
-  // FIXME: This results in terrible diagnostics. Clang just says the CPU is
-  // invalid without explaining *why*.
   switch (Kind) {
   case CK_Generic:
     // No processor selected!
     return false;
 #define PROC(ENUM, STRING, IS64BIT)                                            \
   case CK_##ENUM:                                                              \
     return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
 #include "clang/Basic/X86Target.def"
   }
   llvm_unreachable("Unhandled CPU kind");
 }
 
+void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
+#define PROC(ENUM, STRING, IS64BIT) Values.emplace_back(STRING);
+#define PROC_ALIAS(ENUM, ALIAS)  Values.emplace_back(ALIAS);
+#include "clang/Basic/X86Target.def"
+}
+
 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
   return llvm::StringSwitch<CPUKind>(CPU)
 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
 #include "clang/Basic/X86Target.def"
       .Default(CK_Generic);
 }
 

test/Misc/target-parser.c

 // RUN: not %clang_cc1 -triple armv7--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s
 // CHECK: error: unknown target CPU 'not-a-cpu'
+// //CHECK: note: valid target CPU values are: