[PowerPC] Fix bugs in sign-/zero-extension elimination

[stefanp]

Summary

This patch fixes the following two bugs in PPCInstrInfo::isSignOrZeroExtended helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.

• Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
• Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).

To handle the first case, the parameter for the helpers is changed from MachineInstr to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.

[nemanjai]

To be honest, this code seems even more counter-intuitive to me now. I initially thought that this should essentially be a known-bits calculation on virtual registers and suggested that. With these changes, the code even more closely resembles that, but in a very roundabout fashion. Seems like it would be much simpler to implement and follow this if we just built and maintained a map from virtual registers to known zero/sign bits. Then all we need to check in order to decide if we want to get rid of an EXTS[BHW] is whether the correct number of leading bits are known to be sign bits. Similarly, we'd know if it is safe to remove a CLRLDI/RLWINM/... if the correct number of leading bits are known to be zero. Furthermore, with this approach we wouldn't need to consider the depth that we look through.

Of course, we can leave that as a future simplification.

The reason I've requested changes is to get rid of the debugging code and change the names of the functions.

lib/Target/PowerPC/PPCInstrInfo.cpp

2164–2172

Similarly to isZeroExtendingOp(), this name no longer makes sense.

2215–2223

This name no longer makes sense. This is really a query for whether or not the virtual register contains a value that is zero-extended.

lib/Target/PowerPC/PPCMIPeephole.cpp

227

This whole section needs to be cleaned up. Lines too long. Code commented-out. Pre-processor conditions. Presumably leftovers from debugging during development.

Actually, on second look, this injects trap instructions for debugging and should probably just be removed.

[inouehrs]

• addressed comments from @nemanjai
• rebased to the latest code base and fixed merge conflict

[inouehrs]

lib/Target/PowerPC/PPCInstrInfo.cpp

2164–2172

I changed the method name. Do you have idea on an alternative name?

lib/Target/PowerPC/PPCMIPeephole.cpp

227

Thank you so much for pointing this out. I removed debug code section.

[inouehrs]

• fixed a bug

[hfinkel]

lib/Target/PowerPC/PPCInstrInfo.h

306

Comment out of date?

313

Comment out of date.

[jtony]

As you mentioned some registers defined by ORIS/ANDIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). Can you provide some details (maybe in a comment) about how they depend on the immediate? This would be helpful for future maintainers.

lib/Target/PowerPC/PPCInstrInfo.cpp

2164–2172

We need to update this function name.

2201

Can you put a comment here to explain why only when the the immediate is great or equal than 33 the value is sign-extended?

[inouehrs]

• rebased on the latest code

[inouehrs]

update MIR test case to comply with the recent change in the sigil for MIR physical register

[nemanjai]

lib/Target/PowerPC/PPCInstrInfo.cpp

2173

I think the number of opcodes here is large enough to warrant storing them in a data structure with efficient searching such as a dense set. In addition to readability at the point where you're querying this, it can be very clear from the name what the data structure contains.

For example, if you have a container called OpcodesZExt32To64, it is very clear what it is for and any future code that needs such functionality can easily access that container rather than re-writing this whole list.

Of course, the same applies to the similar list for zero extending ops.

2374

Seems a bit misleading to have a depth parameter that is not actually respected if we're looking through a chain of copies. Although of course, deep chains of copies shouldn't happen in practice.

2379–2380

Why does the register input matter for and-immediate?

2386

This recursive call as well as the next also don't check the depth, right? I realize that these immediate-form binary logical ops won't be chained, but it's still good to add a comment explaining we don't need to limit the depth on such ops.

2442

Comment with the assert.

lib/Target/PowerPC/PPCInstrInfo.h

302–304

I still think this setup with separate queries for sign/zero/any extend seems unnecessarily complex. Seems like it would be clearer if we had an enum for the extension type (sign, zero, none) and we just have a single query that will return this. Therefore no need for Boolean parameters, no need for multiple functions, etc.

[inouehrs]

addressed comments

[inouehrs]

lib/Target/PowerPC/PPCInstrInfo.cpp

2374

I changed the names of variable and constant to indicate they shows the depth of binary operators.

2379–2380

Good catch. I fixed.

2442

I added comment, but I feel this assert is not necessary.

lib/Target/PowerPC/PPCInstrInfo.h

302–304

I agree that the single query approach is cleaner. But I am afraid that it will increase the cost of compilation slightly since it always checks for both sign- and zero-extensions. Do you think the potential increase in compilation cost does not matter too much here?

[nemanjai]

lib/Target/PowerPC/PPCInstrInfo.h

302–304

It seems to me that the checks are not costly except in chained operations cases (which we traverse the chain as it is). Or am I missing something. What is the worst case complexity of the computations for each?

[inouehrs]

• changed the return value of isSignOrZeroExtended to std::pair<bool, bool>

[inouehrs]

lib/Target/PowerPC/PPCInstrInfo.h

302–304

Thanks. I modified the helper to return std::pair<bool, bool>.
Do you prefer an enum?

[inouehrs]

• rebased to the latest tree and ran tests again
• fix formatting

[inouehrs]

• rebased to the latest source (fix conflicts and update unit tests)

[amyk]

Hi @inouehrs, I will be commandeering this revision since we are revisiting this patch.

[inouehrs]

@amyk I see. Please let me know you need some help.

[amyk]

• Rebased to the latest source (fix conflicts, ran functional tests)
• Fixed llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll to remove redundant sign extend instruction
• Added the following check in PPCMIPeephole.cpp to only perform the LWZ->LWA transformation when the displacement is a multiple of 4

// The transformation from a zero-extending load to a sign-extending
// load is only legal when the displacement is a multiple of 4.
// If the displacement is not at least 4 byte aligned, don't perform
// the transformation.
if (SrcMI->getOperand(1).isGlobal() &&
    SrcMI->getOperand(1).getGlobal()->getAlignment() < 4)
  break;

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3848 ↗

(On Diff #201651)

The bitwise or seems like an odd choice here since IsSExt/IsZExt shouldn't possibly be true here and also I think logical or seems more natural for bool variables.
The change to logical or doesn't require another revision.

3859 ↗

(On Diff #201651)

These can probably be logical or's as well. Same with the below ones.

3901 ↗

(On Diff #201651)

Please remove this todo.

[stefanp]

Taking over this patch to rebase it on top of current code and to see if it can be eventually checked in.

[stefanp]

Rebased the patch to top of trunk.
A number of test cases had to be re-generated. This rebase shouldn't really
change what the patch does.

[stefanp]

Fixed some formatting issues.

[stefanp]

Found that POPCNTW instruction does not ensure that the upper 32 bits
are cleared. As a result I have removed it from the list.

[stefanp]

Fixed a typo in the handling of the PPC::AND.

[stefanp]

Added more early breaks to make sure that we do not convert from a zero extending
load to a sign extending load with an invalid displacement.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5092 ↗

(On Diff #397308)

Question: should we update this to say if the register and not machine instruction since it is changed to Reg for the parameter?
Or should it stay as machine instruction since you're checking for the different MachineInstr opcodes in this function?
The same question I have applies to definedByZeroExtendingOp().

5129 ↗

(On Diff #397308)

5314 ↗

(On Diff #397308)

If the change to logical or still applies, we should probably update these accordingly.

[stefanp]

Updated a couple of comments and changed the OR.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5092 ↗

(On Diff #397308)

I think it should probably say "machine instruction that defines this register" because that is what we are really interested in. We want to make sure that this register is already sign extended by the instruction that defines it. I'm going to re-write the comment to make it clear.

5314 ↗

(On Diff #397308)

Sure. I can change it to logical.

[stefanp]

Rebased this patch to the top of main and retested.

[stefanp]

Need to rebase this patch again. Will request another review once I have done that.

[stefanp]

Rebased patch to top of trunk.

[stefanp]

Fairly significant changes have been made since I took over this patch and I would prefer to have another set of eyes take a look.
I will request a new review.

[nemanjai]

Sorry, I had some comments that I haven't submitted because I had not gotten through the entire patch. I am not sure if they all still apply but thought I'd submit them before restarting the review.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5091–5094 ↗

(On Diff #409971)

I think all explanations of what sign-extending means should be removed and you should just note that this is a test explicitly for sign extension from 32 to 64 bits.

5105 ↗

(On Diff #409971)

Rather than having tables of these opcodes in the C++ code, we should probably just add a couple of flags in our .td files for the two types of extension. Perhaps isSExt32To64, isZExt32To64. Then we can simply query that on the MI.

Of course, the ones below this set probably have to stay because they have further constraints.

5119 ↗

(On Diff #409971)

Is there no DenseSet<>::count()?

5288 ↗

(On Diff #409971)

This block ends up getting very deeply nested and hard to follow. Can we flip the conditions and do early exits? Something like:

if (SrcReg != PPC::X3)
  return ...
...
if previous instr is not the stack adjust or the one before is not a call...
  return ...

and so on.

5313 ↗

(On Diff #409971)

This code might need to move up if we are flipping the previous condition.

llvm/lib/Target/PowerPC/PPCInstrInfo.h

602–603 ↗

(On Diff #409971)

// Return true if the register is sign-extended from 32 to 64 bits.

609–610 ↗

(On Diff #409971)

// Return true if the register is zero-extended from 32 to 64 bits.

[stefanp]

Added two new flags ZExt32To64 and SExt32To64.
Marked instructions that zero extend or sign extend in the TD files with those
flags.
Fixed a few comments as well.
Tried to extract an if statement to reduce the indentation a little.

[stefanp]

Rebased the patch to top of trunk again.

[stefanp]

Rebased to top of main branch.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrFormats.td

48 ↗

(On Diff #423390)

53 ↗

(On Diff #423390)

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5139 ↗

(On Diff #423390)

5139 ↗

(On Diff #430795)

A minor nit on this comment.

5180 ↗

(On Diff #430795)

Question: This is something super minor, but is it better to put the check for isZExt32To64() earlier in the function?

I know it may not matter, but I am just wondering in case it may be better to do this prior to all of the different opcode checks, and since the definedBySignExtendingOp also put it's isSExt32To64() pretty early in the function.

In any case, this is just a question so if it's not applicable, you can feel free to disregard this.

[stefanp]

Rebased the patch to top of main branch.
Updated a couple of typos.
Moved a check earlier in the function.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5180 ↗

(On Diff #430795)

Question: This is something super minor, but is it better to put the check for isZExt32To64() earlier in the function?

I know it may not matter, but I am just wondering in case it may be better to do this prior to all of the different opcode checks, and since the definedBySignExtendingOp also put it's isSExt32To64() pretty early in the function.

In any case, this is just a question so if it's not applicable, you can feel free to disregard this.

I don't think it matters in this case. For this check we need to get TII so maybe it's better to check other things first that don't require the instruction info? That may save us from having to get the additional information in a limited number of cases. On the other hand we are just checking a single flag for a large number of instructions.
Anyway, I really don't feel strongly about it one way or another. I'm going to move it up just because it is nicer style to have the two functions a little more similar.

[amyk]

Thanks for addressing my previous comments, Stefan.
I don't believe I have any other further comments. Unless if Nemanja has any additional comments, this personally LGTM.

[nemanjai]

As tends to be the case with huge patches such as this, it is difficult to get this patch to converge and it still needs a bit of work. But I think it is pretty close overall.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

897 ↗

(On Diff #423390)

I don't follow why this is only marked as zero-extended (whereas for example, andi. is marked as both). The 32-bit sign bit can only be a zero, so a sign-extend from 32-bits (extsw) is guaranteed to essentially be a nop.

962 ↗

(On Diff #423390)

Similar comment as for the word versions regarding sign extension..

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3859 ↗

(On Diff #201651)

Is there a reason this comment was not addressed and these are still bitwise OR's?

5119 ↗

(On Diff #423390)

s/masked/masked out

5180–5183 ↗

(On Diff #423390)

Just for consistency, this check is first in the sign extending check... You should probably move it up in this function so it is consistent with that.

5234 ↗

(On Diff #433142)

I still don't like the deep nesting in this block. It seems like we can get rid of all that deep nesting by rewriting this block as:

case PPC::COPY: {
  Register SrcReg = MI->getOperand(1).getReg();

  // In both ELFv1 and v2 ABI, method parameters and the return value
  // are sign- or zero-extended.
  const MachineFunction *MF = MI->getMF();

  if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
    // If this is a copy from another register, we recursively check source.
    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
    return std::pair<bool, bool>(SrcExt.first || IsSExt,
                                 SrcExt.second || IsZExt);
  }

  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
  // We check the ZExt/SExt flags for a method parameter.
  if (MI->getParent()->getBasicBlock() ==
      &MF->getFunction().getEntryBlock()) {
    Register VReg = MI->getOperand(0).getReg();
    if (MF->getRegInfo().isLiveIn(VReg)) {
      IsSExt |= FuncInfo->isLiveInSExt(VReg);
      IsZExt |= FuncInfo->isLiveInZExt(VReg);
      return std::pair<bool, bool>(IsSExt, IsZExt);
    }
  }

  // For a method return value, we check the ZExt/SExt flags in attribute.
  // We assume the following code sequence for method call.
  //   ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
  //   BL8_NOP @func,...
  //   ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
  //   %5 = COPY %x3; G8RC:%5
  if (SrcReg != PPC::X3) {
    // If this is a copy from another register, we recursively check source.
    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
    return std::pair<bool, bool>(SrcExt.first || IsSExt,
                                 SrcExt.second || IsZExt);
  }

  const MachineBasicBlock *MBB = MI->getParent();
  MachineBasicBlock::const_instr_iterator II =
      MachineBasicBlock::const_instr_iterator(MI);
  if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP)
    return std::pair<bool, bool>(IsSExt, IsZExt);

  const MachineInstr &CallMI = *(--II);
  if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
    return std::pair<bool, bool>(IsSExt, IsZExt);

  const Function *CalleeFn =
      dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
  if (!CalleeFn)
    return std::pair<bool, bool>(IsSExt, IsZExt);

  const IntegerType *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
  if (IntTy && IntTy->getBitWidth() <= 32) {
    const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
    IsSExt |= Attrs.hasAttribute(Attribute::SExt);
    IsZExt |= Attrs.hasAttribute(Attribute::ZExt);
  }
  return std::pair<bool, bool>(IsSExt, IsZExt);
}

I have neither compiled nor tested this, so please scrutinize it carefully rather than assuming that my suggestion is verified.

5290–5292 ↗

(On Diff #433142)

Can any of this ever produce anything useful? If I am reading this correctly, this is basically:

• The copy is from X3
• We check if the definition of X3 is sign/zero extended

But this seems pointless since we won't track anything about what defined X3 here.

Edit: actually, the above is so deeply nested that I missed the fact that this code is for non-SVR4 ABI's.

5335 ↗

(On Diff #433142)

I understand that these names predate this patch, but since we are modifying it, can we give them more descriptive names? Perhaps OperandEnd, OperandStride?

llvm/lib/Target/PowerPC/PPCInstrP10.td

1322 ↗

(On Diff #433142)

Did you mean to mark all of these as ZExt32To64? The possible results are 0/1 for these. So I suppose they are technically both sign and zero extending.
Furthermore, the negative forms (setnbc/setnbcr) are not marked as sign extending even though the values are possible values are -1/0.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1303 ↗

(On Diff #433142)

It would seem that the vextu[bhw][lr]x family of instructions have been missed and they're all zero extending.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

787–800 ↗

(On Diff #433142)

This code is so unnecessarily lambda-ey. Can you please commit an NFC patch (I don't care if it is before or after this patch) to flatten this out?

804–807 ↗

(On Diff #433142)

Why? LHA is D-Form (not DS-Form) and LHAX of course doesn't care since it is X-Form.

862–865 ↗

(On Diff #433142)

This is true if we are transforming it to the DS-Form lwa. It shouldn't matter for the X-Form lwax. Perhaps this code should just set a bool variable IsWordAligned or something similar and then below, we break out:

if (IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))

[stefanp]

Fixed the zero extend / sign extend flags on a number of instructions.
Tried to flatten out PPCInstrInfo::isSignOrZeroExtended a little.
Removed the restriction on LHA, LHAX, and LWAX.

I will address the issues with too many lambdas in the code in a separate patch.

[stefanp]

Removed the zero extend and sign extend from popcntw and popcntb and I added
them incorrectly.

[nemanjai]

The remaining comments are minor nits that can be addressed on the commit. Please don't forget the follow-up I requested at https://reviews.llvm.org/D40554#inline-1239933.
Other than those, LGTM.

Thanks for your patience with this patch.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5199–5203 ↗

(On Diff #443028)

Since we repeat this code (the subword part), maybe it would be cleaner to extract it into a static local function - something like:

static bool isOpZeroOfSubwordPreincLoad(const MachineInstr &MI)

Of course, since you still need the LWZU variants, it may not be worth it.
This is a minor stylistic comment that shouldn't delay approval.

5284 ↗

(On Diff #443028)

I am a little unclear on the use of BinOpDepth in this function. It seems very inconsistent. Wouldn't it make sense to always add one for the recursive call as well as to check whether it has been exceeded prior to the call? We seem to do that when checking for reg+reg instructions but not for reg+imm instructions. Is that because a single recursive call avoids exponential recursion whereas the two calls for reg+reg instructions don't? If so, can you please add a comment to that end at the top of the function?

5308–5313 ↗

(On Diff #443028)

Since the comment above this block describes the code below, maybe just move this block above the comment.

5318 ↗

(On Diff #443028)

Super minor nit: since we construct the same pair in 3 different early exits as well as at the end, maybe just construct it once and return it in each location (lines 5320, 5324, 5329, 5340).
There is no functional or performance difference, but it is very clear that what we are returning is the exact same thing and couldn't have changed.

5327 ↗

(On Diff #443028)

I think it may be possible for CallMI.getOperand(0).getGlobal() to return null under some odd circumstances. It would probably be safer to use dyn_cast_if_present here rather than dyn_cast.

5339 ↗

(On Diff #443028)

This comment is out of date now.

[stefanp]

Rebased the patch to top of trunk.
Addressed final comments from reviewer.
This is mostly adding or fixing comments and code cleanup.

[stefanp]

Did a final format fix.

lib/Target/PowerPC/PPC.h

#endif
   bool LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
                                          MCOperand &OutMO, AsmPrinter &AP,
                                          bool isDarwin);
 
   void initializePPCVSXFMAMutatePass(PassRegistry&);
   void initializePPCBoolRetToIntPass(PassRegistry&);
   void initializePPCExpandISELPass(PassRegistry &);
   void initializePPCTLSDynamicCallPass(PassRegistry &);
+  void initializePPCMIPeepholePass(PassRegistry&);
   extern char &PPCVSXFMAMutateID;
 
   namespace PPCII {
     
   /// Target Operand Flag enum.
   enum TOF {
     //===------------------------------------------------------------------===//
     // PPC Specific MachineOperand flags.

lib/Target/PowerPC/PPCInstrInfo.h

public:
   static bool isVRRegister(unsigned Reg) {
     return Reg >= PPC::V0 && Reg <= PPC::V31;
   }
   const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
   static int getRecordFormOpcode(unsigned Opcode);
 
   bool isTOCSaveMI(const MachineInstr &MI) const;
 
-  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
-                            const unsigned PhiDepth) const;
+  bool isSignOrZeroExtended(const unsigned Reg, bool SignExt,
+                            const unsigned PhiDepth,
+                            const MachineRegisterInfo *MRI) const;
 
   /// Return true if the output of the instruction is always a sign-extended,
   /// i.e. 0 to 31-th bits are same as 32-th bit.
-  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
-    return isSignOrZeroExtended(MI, true, depth);
+  bool isSignExtended(const unsigned Reg,
+                      const MachineRegisterInfo *MRI) const {
+    return isSignOrZeroExtended(Reg, true, 0, MRI);
   }
 
   /// Return true if the output of the instruction is always zero-extended,
   /// i.e. 0 to 31-th bits are all zeros
-  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
-   return isSignOrZeroExtended(MI, false, depth);
+  bool isZeroExtended(const unsigned Reg,
+                      const MachineRegisterInfo *MRI) const {
+    return isSignOrZeroExtended(Reg, false, 0, MRI);
   }
 };
 
 }
 
 #endif

lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
   // Get the unique definition of SrcReg.
   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
   if (!MI) return false;
 
   bool equalityOnly = false;
   bool noSub = false;
   if (isPPC64) {
     if (is32BitSignedCompare) {
-      // We can perform this optimization only if MI is sign-extending.
-      if (isSignExtended(*MI))
+      // We can perform this optimization only if SrcReg is sign-extending.
+      if (isSignExtended(SrcReg, MRI))
         noSub = true;
       else
         return false;
     } else if (is32BitUnsignedCompare) {
-      // We can perform this optimization, equality only, if MI is
+      // We can perform this optimization, equality only, if SrcReg is
       // zero-extending.
-      if (isZeroExtended(*MI)) {
+      if (isZeroExtended(SrcReg, MRI)) {
         noSub = true;
         equalityOnly = true;
       } else
         return false;
     } else
       equalityOnly = is64BitUnsignedCompare;
   } else
     equalityOnly = is32BitUnsignedCompare;

 
 int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
   return PPC::getRecordFormOpcode(Opcode);
 }
 
 // This function returns true if the machine instruction
 // always outputs a value by sign-extending a 32 bit value,
 // i.e. 0 to 31-th bits are same as 32-th bit.
-static bool isSignExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
+static bool definedBySignExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
+  if (!TargetRegisterInfo::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI) return false;
+
+  int Opcode = MI->getOpcode();
   if (Opcode == PPC::LI     || Opcode == PPC::LI8     ||
       Opcode == PPC::LIS    || Opcode == PPC::LIS8    ||
       Opcode == PPC::SRAW   || Opcode == PPC::SRAWo   ||
       Opcode == PPC::SRAWI  || Opcode == PPC::SRAWIo  ||
       Opcode == PPC::LWA    || Opcode == PPC::LWAX    ||
       Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
       Opcode == PPC::LHA    || Opcode == PPC::LHAX    ||
       Opcode == PPC::LHA8   || Opcode == PPC::LHAX8   ||
       Opcode == PPC::LBZ    || Opcode == PPC::LBZX    ||
       Opcode == PPC::LBZ8   || Opcode == PPC::LBZX8   ||
-      Opcode == PPC::LBZU   || Opcode == PPC::LBZUX   ||
-      Opcode == PPC::LBZU8  || Opcode == PPC::LBZUX8  ||
       Opcode == PPC::LHZ    || Opcode == PPC::LHZX    ||
       Opcode == PPC::LHZ8   || Opcode == PPC::LHZX8   ||
-      Opcode == PPC::LHZU   || Opcode == PPC::LHZUX   ||
-      Opcode == PPC::LHZU8  || Opcode == PPC::LHZUX8  ||
       Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBo  ||
       Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHo  ||
       Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8  ||
       Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWo  ||
       Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
       Opcode == PPC::EXTSB8_32_64)
     return true;
 
-  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+  // The first def of LBZU/LHZU is sign extended.
+  if ((Opcode == PPC::LBZU  || Opcode == PPC::LBZUX  ||
+       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
+       Opcode == PPC::LHZU  || Opcode == PPC::LHZUX  ||
+       Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) &&
+      MI->getOperand(0).getReg() == Reg)
+    return true;
+
+  if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33)
     return true;
 
   if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
        Opcode == PPC::RLWNM  || Opcode == PPC::RLWNMo) &&
-      MI.getOperand(3).getImm() > 0 &&
-      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+      MI->getOperand(3).getImm() > 0 &&
+      MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return true;
 
   return false;
 }
 
 // This function returns true if the machine instruction
 // always outputs zeros in higher 32 bits.
-static bool isZeroExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
+static bool definedByZeroExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
+  if (!TargetRegisterInfo::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI) return false;
+
+  int Opcode = MI->getOpcode();
   // The 16-bit immediate is sign-extended in li/lis.
   // If the most significant bit is zero, all higher bits are zero.
   if (Opcode == PPC::LI  || Opcode == PPC::LI8 ||
       Opcode == PPC::LIS || Opcode == PPC::LIS8) {
-    int64_t Imm = MI.getOperand(1).getImm();
+    int64_t Imm = MI->getOperand(1).getImm();
     if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
       return true;
   }
 
   // We have some variations of rotate-and-mask instructions
   // that clear higher 32-bits.
   if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
        Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo  ||
        Opcode == PPC::RLDICL_32_64) &&
-      MI.getOperand(3).getImm() >= 32)
+      MI->getOperand(3).getImm() >= 32)
     return true;
 
   if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
-      MI.getOperand(3).getImm() >= 32 &&
-      MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+      MI->getOperand(3).getImm() >= 32 &&
+      MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
     return true;
 
   if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
        Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
-      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+      MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return true;
 
   // There are other instructions that clear higher 32-bits.
   if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
       Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
       Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
       Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
       Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo ||
       Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
       Opcode == PPC::SLW     || Opcode == PPC::SLWo    ||
       Opcode == PPC::SRW     || Opcode == PPC::SRWo    ||
       Opcode == PPC::SLW8    || Opcode == PPC::SRW8    ||
       Opcode == PPC::SLWI    || Opcode == PPC::SLWIo   ||
       Opcode == PPC::SRWI    || Opcode == PPC::SRWIo   ||
       Opcode == PPC::LWZ     || Opcode == PPC::LWZX    ||
-      Opcode == PPC::LWZU    || Opcode == PPC::LWZUX   ||
       Opcode == PPC::LWBRX   || Opcode == PPC::LHBRX   ||
       Opcode == PPC::LHZ     || Opcode == PPC::LHZX    ||
-      Opcode == PPC::LHZU    || Opcode == PPC::LHZUX   ||
       Opcode == PPC::LBZ     || Opcode == PPC::LBZX    ||
-      Opcode == PPC::LBZU    || Opcode == PPC::LBZUX   ||
       Opcode == PPC::LWZ8    || Opcode == PPC::LWZX8   ||
-      Opcode == PPC::LWZU8   || Opcode == PPC::LWZUX8  ||
       Opcode == PPC::LWBRX8  || Opcode == PPC::LHBRX8  ||
       Opcode == PPC::LHZ8    || Opcode == PPC::LHZX8   ||
-      Opcode == PPC::LHZU8   || Opcode == PPC::LHZUX8  ||
       Opcode == PPC::LBZ8    || Opcode == PPC::LBZX8   ||
-      Opcode == PPC::LBZU8   || Opcode == PPC::LBZUX8  ||
       Opcode == PPC::ANDIo   || Opcode == PPC::ANDISo  ||
       Opcode == PPC::ROTRWI  || Opcode == PPC::ROTRWIo ||
       Opcode == PPC::EXTLWI  || Opcode == PPC::EXTLWIo ||
       Opcode == PPC::MFVSRWZ)
     return true;
 
+  // The first def of LBZU/LHZU/LWZU are zero extended.
+  if ((Opcode == PPC::LBZU  || Opcode == PPC::LBZUX  ||
+       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
+       Opcode == PPC::LHZU  || Opcode == PPC::LHZUX  ||
+       Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
+       Opcode == PPC::LWZU  || Opcode == PPC::LWZUX  ||
+       Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) &&
+      MI->getOperand(0).getReg() == Reg)
+    return true;
+
   return false;
 }
 
 // This function returns true if the input MachineInstr is a TOC save
 // instruction.
 bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
   if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
     return false;
   unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
   unsigned StackOffset = MI.getOperand(1).getImm();
   unsigned StackReg = MI.getOperand(2).getReg();
   if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
     return true;
 
   return false;
 }
 
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid exsessive cost.
 const unsigned MAX_DEPTH = 1;
 
 bool
-PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
-                                   const unsigned Depth) const {
-  const MachineFunction *MF = MI.getParent()->getParent();
-  const MachineRegisterInfo *MRI = &MF->getRegInfo();
+PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg, bool SignExt,
+                                   const unsigned Depth,
+                                   const MachineRegisterInfo *MRI) const {
+  if (!TargetRegisterInfo::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI) return false;
 
   // If we know this instruction returns sign- or zero-extended result,
   // return true.
-  if (SignExt ? isSignExtendingOp(MI):
-                isZeroExtendingOp(MI))
+  if (SignExt ? definedBySignExtendingOp(Reg, MRI):
+                definedByZeroExtendingOp(Reg, MRI))
     return true;
 
-  switch (MI.getOpcode()) {
+  switch (MI->getOpcode()) {
   case PPC::COPY: {
-    unsigned SrcReg = MI.getOperand(1).getReg();
+    unsigned SrcReg = MI->getOperand(1).getReg();
 
     // In both ELFv1 and v2 ABI, method parameters and the return value
     // are sign- or zero-extended.
+    const MachineFunction *MF = MI->getParent()->getParent();
     if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
       const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
       // We check the ZExt/SExt flags for a method parameter.
-      if (MI.getParent()->getBasicBlock() ==
+      if (MI->getParent()->getBasicBlock() ==
           &MF->getFunction()->getEntryBlock()) {
-        unsigned VReg = MI.getOperand(0).getReg();
+        unsigned VReg = MI->getOperand(0).getReg();
         if (MF->getRegInfo().isLiveIn(VReg))
           return SignExt ? FuncInfo->isLiveInSExt(VReg) :
                            FuncInfo->isLiveInZExt(VReg);
       }
 
       // For a method return value, we check the ZExt/SExt flags in attribute.
       // We assume the following code sequence for method call.
       //   ADJCALLSTACKDOWN 32, %r1<imp-def,dead>, %r1<imp-use>
       //   BL8_NOP <ga:@func>,...
       //   ADJCALLSTACKUP 32, 0, %r1<imp-def,dead>, %r1<imp-use>
       //   %vreg5<def> = COPY %x3; G8RC:%vreg5
       if (SrcReg == PPC::X3) {
-        const MachineBasicBlock *MBB = MI.getParent();
+        const MachineBasicBlock *MBB = MI->getParent();
         MachineBasicBlock::const_instr_iterator II =
-          MachineBasicBlock::const_instr_iterator(&MI);
+          MachineBasicBlock::const_instr_iterator(MI);
         if (II != MBB->instr_begin() &&
             (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
           const MachineInstr &CallMI = *(--II);
           if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
             const Function *CalleeFn =
               dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
             if (!CalleeFn)
               return false;
             const IntegerType *IntTy =
               dyn_cast<IntegerType>(CalleeFn->getReturnType());
             const AttributeSet &Attrs =
               CalleeFn->getAttributes().getRetAttributes();
             if (IntTy && IntTy->getBitWidth() <= 32)
               return Attrs.hasAttribute(SignExt ? Attribute::SExt :
                                                   Attribute::ZExt);
           }
         }
       }
     }
 
     // If this is a copy from another register, we recursively check source.
-    if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
-      return false;
-    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-    if (SrcMI != NULL)
-      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
-    return false;
+    return isSignOrZeroExtended(SrcReg, SignExt, Depth, MRI);
   }
 
+  // Logical operation with 16-bit immediate does not change the upper 48 bits.
+  // So, we track the operand register as we do for register copy.
   case PPC::ANDIo:
-  case PPC::ANDISo:
   case PPC::ORI:
-  case PPC::ORIS:
   case PPC::XORI:
-  case PPC::XORIS:
   case PPC::ANDIo8:
-  case PPC::ANDISo8:
   case PPC::ORI8:
+  case PPC::XORI8: {
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    return isSignOrZeroExtended(SrcReg, SignExt, Depth, MRI);
+  }
+
+  // Logical operation with shifted 16-bit immediate does not change the upper
+  // 32 bits. So, we track the operand register only for zero extension.
+  case PPC::ANDISo:
+  case PPC::ORIS:
+  case PPC::XORIS:
+  case PPC::ANDISo8:
   case PPC::ORIS8:
-  case PPC::XORI8:
   case PPC::XORIS8: {
-    // logical operation with 16-bit immediate does not change the upper bits.
-    // So, we track the operand register as we do for register copy.
-    unsigned SrcReg = MI.getOperand(1).getReg();
-    if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
-      return false;
-    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-    if (SrcMI != NULL)
-      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
+    if (SignExt) {
+      uint16_t Imm = MI->getOperand(2).getImm();
+      if (Imm & 0x8000)
         return false;
     }
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    return isSignOrZeroExtended(SrcReg, SignExt, Depth, MRI);
+  }
 
   // If all incoming values are sign-/zero-extended,
   // the output of OR, ISEL or PHI is also sign-/zero-extended.
   case PPC::OR:
   case PPC::OR8:
   case PPC::ISEL:
   case PPC::PHI: {
     if (Depth >= MAX_DEPTH)
       return false;
 
     // The input registers for PHI are operand 1, 3, ...
     // The input registers for others are operand 1 and 2.
     unsigned E = 3, D = 1;
-    if (MI.getOpcode() == PPC::PHI) {
-      E = MI.getNumOperands();
+    if (MI->getOpcode() == PPC::PHI) {
+      E = MI->getNumOperands();
       D = 2;
     }
 
     for (unsigned I = 1; I != E; I += D) {
-      if (MI.getOperand(I).isReg()) {
-        unsigned SrcReg = MI.getOperand(I).getReg();
-        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
-          return false;
-        const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-        if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
-          return false;
-      }
-      else
+      if (!MI->getOperand(I).isReg())
+
+      unsigned SrcReg = MI->getOperand(I).getReg();
+      if (!isSignOrZeroExtended(SrcReg, SignExt, Depth+1, MRI))
         return false;
     }
     return true;
   }
 
   // If at least one of the incoming values of an AND is zero extended
   // then the output is also zero-extended. If both of the incoming values
   // are sign-extended then the output is also sign extended.
   case PPC::AND:
   case PPC::AND8: {
     if (Depth >= MAX_DEPTH)
        return false;
 
-    assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
-
-    unsigned SrcReg1 = MI.getOperand(1).getReg();
-    unsigned SrcReg2 = MI.getOperand(2).getReg();
+    assert(MI->getOperand(1).isReg() && MI->getOperand(2).isReg());
 
-    if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
-        !TargetRegisterInfo::isVirtualRegister(SrcReg2))
-       return false;
-
-    const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
-    const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
-    if (!MISrc1 || !MISrc2)
-        return false;
+    unsigned SrcReg1 = MI->getOperand(1).getReg();
+    unsigned SrcReg2 = MI->getOperand(2).getReg();
 
     if(SignExt)
-        return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
-               isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+        return isSignOrZeroExtended(SrcReg1, SignExt, Depth+1, MRI) &&
+               isSignOrZeroExtended(SrcReg2, SignExt, Depth+1, MRI);
     else
-        return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
-               isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+        return isSignOrZeroExtended(SrcReg1, SignExt, Depth+1, MRI) ||
+               isSignOrZeroExtended(SrcReg2, SignExt, Depth+1, MRI);
   }
 
   default:
     break;
   }
   return false;
 }

lib/Target/PowerPC/PPCMIPeephole.cpp

EnableSExtElimination("ppc-eliminate-signext",
                           cl::desc("enable elimination of sign-extensions"),
                           cl::init(false), cl::Hidden);
 
 static cl::opt<bool>
     EnableZExtElimination("ppc-eliminate-zeroext",
                           cl::desc("enable elimination of zero-extensions"),
                           cl::init(false), cl::Hidden);
 
-namespace llvm {
-  void initializePPCMIPeepholePass(PassRegistry&);
-}
-
 namespace {
 
 struct PPCMIPeephole : public MachineFunctionPass {
 
   static char ID;
   const PPCInstrInfo *TII;
   MachineFunction *MF;
   MachineRegisterInfo *MRI;
if (!TargetRegisterInfo::isVirtualRegister(Reg))
     return nullptr;
 
   return MRI->getVRegDef(Reg);
 }
 
 // This function returns number of known zero bits in output of MI
 // starting from the most significant bit.
 static unsigned
-getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
+getKnownLeadingZeroCount(const unsigned Reg, const PPCInstrInfo *TII,
+                         const MachineRegisterInfo *MRI) {
+  MachineInstr *MI = MRI->getVRegDef(Reg);
   unsigned Opcode = MI->getOpcode();
   if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
       Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo)
     return MI->getOperand(3).getImm();
 
   if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
        MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
     return MI->getOperand(3).getImm();
if (Opcode == PPC::LHZ   || Opcode == PPC::LHZX  ||
     return 48;
 
   if (Opcode == PPC::LBZ   || Opcode == PPC::LBZX  ||
       Opcode == PPC::LBZ8  || Opcode == PPC::LBZX8 ||
       Opcode == PPC::LBZU  || Opcode == PPC::LBZUX ||
       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
     return 56;
 
-  if (TII->isZeroExtended(*MI))
+  if (TII->isZeroExtended(Reg, MRI))
     return 32;
 
   return 0;
 }
 
 // This function maintains a map for the pairs <TOC Save Instr, Keep>
 // Each time a new TOC save is encountered, it checks if any of the exisiting
 // ones are dominated by the new one. If so, it marks the exisiting one as
for (MachineInstr &MI : MBB) {
         ToErase->eraseFromParent();
         ToErase = nullptr;
       }
 
       // Ignore debug instructions.
       if (MI.isDebugValue())
         continue;
 
       // Per-opcode peepholes.
       switch (MI.getOpcode()) {
 
       default:
         break;
 
       case PPC::STD: {
         MachineFrameInfo &MFI = MF->getFrameInfo();
         if (MFI.hasVarSizedObjects() ||
for (MachineInstr &MI : MBB) {
           DEBUG(MI.dump());
           DEBUG(dbgs() << "are merged into sign-extending load\n");
           SrcMI->setDesc(TII->get(Opc));
           SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           ToErase = &MI;
           Simplified = true;
           NumEliminatedSExt++;
         } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
-                   TII->isSignExtended(*SrcMI)) {
+                   TII->isSignExtended(NarrowReg, MRI)) {
           // We can eliminate EXTSW if the input is known to be already
           // sign-extended.
           DEBUG(dbgs() << "Removing redundant sign-extension\n");
           unsigned TmpReg =
             MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
                   TmpReg);
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
for (MachineInstr &MI : MBB) {
 
         SrcMI = SubRegMI;
         if (SubRegMI->getOpcode() == PPC::COPY) {
           unsigned CopyReg = SubRegMI->getOperand(1).getReg();
           if (TargetRegisterInfo::isVirtualRegister(CopyReg))
             SrcMI = MRI->getVRegDef(CopyReg);
         }
 
-        unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
+        SrcReg = SrcMI->getOperand(0).getReg();
+        unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcReg, TII, MRI);
         if (MI.getOperand(3).getImm() <= KnownZeroCount) {
           DEBUG(dbgs() << "Removing redundant zero-extension\n");
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .addReg(SrcReg);
           ToErase = &MI;
           Simplified = true;
           NumEliminatedZExt++;

lib/Target/PowerPC/PPCTargetMachine.cpp

extern "C" void LLVMInitializePowerPCTarget() {
   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializePPCBoolRetToIntPass(PR);
   initializePPCExpandISELPass(PR);
   initializePPCTLSDynamicCallPass(PR);
+  initializePPCMIPeepholePass(PR);
 }
 
 /// Return the datalayout string of a subtarget.
 static std::string getDataLayoutString(const Triple &T) {
   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
   std::string Ret;
 
   // Most PPC* platforms are big endian, PPC64LE is little endian.

test/CodeGen/PowerPC/sext_elimination.mir

+# test for BB-local register copy elimination
+# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64le-unknown-linux-gnu"
+  define i8* @func(i8* %a) {
+  entry:
+    ret i8* %a
+  }
+  
+...
+---
+name:            func
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x3', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x3
+
+    ; CHECK-LABEL: bb.0.entry:
+    ; CHECK: %4:g8rc = EXTSW_32_64 %3
+    ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
+    ; CHECK: %7:g8rc = EXTSW_32_64 %6
+    ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
+    ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
+    ; CHECK: %14:g8rc = COPY %1
+
+    %0:g8rc_nox0 = COPY %x3
+    %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
+    %3:gprc = COPY %2:g8rc_nox0
+    %4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
+    %5:g8rc = EXTSW_32_64 %1:gprc
+
+    %6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated
+    %7:g8rc = EXTSW_32_64 %6:gprc
+
+    %8:gprc = ORIS %1:gprc, 32767
+    %9:g8rc = EXTSW_32_64 %8:gprc
+
+    %10:gprc = ORI %1:gprc, 32768
+    %11:g8rc = EXTSW_32_64 %10:gprc
+
+    %12:g8rc = IMPLICIT_DEF
+    %13:g8rc = INSERT_SUBREG %12:g8rc, %1:gprc, %subreg.sub_32
+    %14:g8rc = RLDICL %13:g8rc, 0, 32
+
+...