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gyiu (Graham Yiu)
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User Since
Jun 12 2017, 12:15 PM (96 w, 3 d)

Recent Activity

Sat, Apr 13

xiangzhai awarded D38190: Partial Inlining with multi-region outlining based on PGO information a Like token.
Sat, Apr 13, 11:11 PM · Restricted Project

Aug 3 2018

gyiu committed rL338896: [Partial Inlining] Fix small bug in detecting if we did something.
[Partial Inlining] Fix small bug in detecting if we did something
Aug 3 2018, 7:43 AM
gyiu committed rL338895: Fix asm label testcase flaw.
Fix asm label testcase flaw
Aug 3 2018, 7:37 AM
gyiu committed rC338895: Fix asm label testcase flaw.
Fix asm label testcase flaw
Aug 3 2018, 7:37 AM

Nov 29 2017

gyiu committed rL319399: - Removed unused lamba (IsReturnBlock) causing build bots to fail for r319398.
- Removed unused lamba (IsReturnBlock) causing build bots to fail for r319398
Nov 29 2017, 7:37 PM
gyiu committed rL319398: With PGO information, we can do more aggressive outlining of cold regions in….
With PGO information, we can do more aggressive outlining of cold regions in…
Nov 29 2017, 6:42 PM
gyiu closed D38190: Partial Inlining with multi-region outlining based on PGO information by committing rL319398: With PGO information, we can do more aggressive outlining of cold regions in….
Nov 29 2017, 6:42 PM · Restricted Project
gyiu updated the summary of D40477: Enable Partial Inlining by default.
Nov 29 2017, 3:58 PM
gyiu updated the summary of D40477: Enable Partial Inlining by default.
Nov 29 2017, 3:47 PM
gyiu updated the summary of D40477: Enable Partial Inlining by default.
Nov 29 2017, 1:30 PM
gyiu added a comment to D40477: Enable Partial Inlining by default.

This definitely needs numbers - across multiple platforms. Both performance and size of resultant binaries.

Nov 29 2017, 1:19 PM
gyiu added a comment to D40477: Enable Partial Inlining by default.

@nemanjai Good eye, but actually there's already an option disable partial inlining somewhere else (options to enable and disable are in different files, go figure). Defined in 'lib/Transforms/IPO/PartialInlining.cpp', called '-disable-partial-inlining'.

Nov 29 2017, 12:25 PM

Nov 26 2017

gyiu created D40477: Enable Partial Inlining by default.
Nov 26 2017, 9:54 PM

Nov 21 2017

gyiu updated the diff for D38190: Partial Inlining with multi-region outlining based on PGO information.
  • Added new multi-outlined-region testcase.
  • Removed unnecessary traces and moved useful ones to 'ifndef NDEBUG' macro.
  • Modified/added ORE messages according to suggestions.
  • General clean-up using clang-format.
Nov 21 2017, 6:57 PM · Restricted Project

Nov 7 2017

gyiu committed rL317613: Use new vector insert half-word and byte instructions when we see insertelement….
Use new vector insert half-word and byte instructions when we see insertelement…
Nov 7 2017, 12:56 PM
gyiu closed D34630: [Power9] Add additional patterns to recognize and transform insertelt/extractelt to vinsert[h|b]/vextractu[h|b] instructions. by committing rL317613: Use new vector insert half-word and byte instructions when we see insertelement….
Nov 7 2017, 12:56 PM

Nov 6 2017

gyiu updated the diff for D38190: Partial Inlining with multi-region outlining based on PGO information.
  • Added testcase.
  • Remove the requirement for a conditional branch as the terminator of the entry block, for multi-region outlining specifically.
Nov 6 2017, 6:39 PM · Restricted Project
gyiu committed rL317508: Fix buildbot breakages from r317503. Add parentheses to assignment when using….
Fix buildbot breakages from r317503. Add parentheses to assignment when using…
Nov 6 2017, 1:05 PM
gyiu committed rL317503: Adds code to PPC ISEL lowering to recognize byte inserts from vector_shuffles….
Adds code to PPC ISEL lowering to recognize byte inserts from vector_shuffles…
Nov 6 2017, 12:19 PM
gyiu closed D34497: [Power9] Exploit vinsertb instruction by committing rL317503: Adds code to PPC ISEL lowering to recognize byte inserts from vector_shuffles….
Nov 6 2017, 12:19 PM

Nov 1 2017

gyiu committed rL317111: Adds code to PPC ISEL lowering to recognize half-word inserts from….
Adds code to PPC ISEL lowering to recognize half-word inserts from…
Nov 1 2017, 11:07 AM
gyiu closed D34160: [Power9] Exploit vinserth instruction by committing rL317111: Adds code to PPC ISEL lowering to recognize half-word inserts from….
Nov 1 2017, 11:07 AM

Oct 31 2017

gyiu updated the diff for D38190: Partial Inlining with multi-region outlining based on PGO information.

Updated based on latest comments. Still missing testcase that I'm working on currently. Will update patch when ready.

Oct 31 2017, 10:47 AM · Restricted Project

Oct 25 2017

gyiu added inline comments to D38190: Partial Inlining with multi-region outlining based on PGO information.
Oct 25 2017, 7:24 PM · Restricted Project

Oct 24 2017

gyiu added inline comments to D34160: [Power9] Exploit vinserth instruction.
Oct 24 2017, 8:29 AM

Oct 19 2017

gyiu committed rL316174: The cost of splitting a large vector instruction is not being taken into….
The cost of splitting a large vector instruction is not being taken into…
Oct 19 2017, 11:17 AM
gyiu closed D38961: [PowerPC] Increase the user cost of vector instructions by their legalization cost by committing rL316174: The cost of splitting a large vector instruction is not being taken into….
Oct 19 2017, 11:16 AM

Oct 11 2017

gyiu updated the diff for D38190: Partial Inlining with multi-region outlining based on PGO information.
  • Updated code based on review comments.
  • Also added check for candidate region outputs. If cold region has an output (ie. a live exit variable) then we could be blocking some code motion in the caller after it has been outlined.
  • Also added code to mark outlined functions/callsites with coldCC.
Oct 11 2017, 12:44 PM · Restricted Project

Oct 10 2017

gyiu added inline comments to D38190: Partial Inlining with multi-region outlining based on PGO information.
Oct 10 2017, 8:33 AM · Restricted Project

Oct 5 2017

gyiu added a comment to D38563: [MachineBlockPlacement] Make sure PreferredLoopExit is cleared everytime new loop is processed.

@trentxintong Hello, this change is actually causing the assert to trigger in 15 SPEC2006 benchmarks on PPC64LE with '-O3 -mcpu=pwr8 -m64 -fprofile-use -flto=thin'. Failures are during the link step.

Oct 5 2017, 3:57 PM
gyiu added a comment to rL314937: [MachineBlockPlacement] Make sure PreferredLoopExit is cleared everytime new….

@trentxintong Hello, this change is actually causing the assert to trigger in 15 SPEC2006 benchmarks on PPC64LE with '-O3 -mcpu=pwr8 -m64 -fprofile-use -flto=thin'. Failures are during the link step.

Oct 5 2017, 3:55 PM

Oct 4 2017

gyiu updated the diff for D38517: Enabling new pass manager in LTO (and thinLTO) link step via -fexperimental-new-pass-manager option.

Add new testcase to make sure plugin-opt is passed to gold linker to enable new pass manager.

Oct 4 2017, 8:52 AM

Oct 3 2017

gyiu removed a reviewer for D38517: Enabling new pass manager in LTO (and thinLTO) link step via -fexperimental-new-pass-manager option: jpaquette.
Oct 3 2017, 6:34 PM
gyiu created D38517: Enabling new pass manager in LTO (and thinLTO) link step via -fexperimental-new-pass-manager option.
Oct 3 2017, 2:39 PM

Oct 2 2017

gyiu added inline comments to D38190: Partial Inlining with multi-region outlining based on PGO information.
Oct 2 2017, 7:22 PM · Restricted Project
gyiu added inline comments to D38190: Partial Inlining with multi-region outlining based on PGO information.
Oct 2 2017, 6:55 PM · Restricted Project

Sep 25 2017

gyiu created D38190: Partial Inlining with multi-region outlining based on PGO information.
Sep 25 2017, 5:02 AM · Restricted Project

Aug 30 2017

gyiu updated the diff for D34630: [Power9] Add additional patterns to recognize and transform insertelt/extractelt to vinsert[h|b]/vextractu[h|b] instructions..
  • Removed extract element patterns as changes from 'https://reviews.llvm.org/D34032' generate better code in terms of total cycles. Also it catches more cases than the vextractu[hb] instructions, as it's only beneficial when operating on dword[1] of the vector register.
Aug 30 2017, 7:59 AM
gyiu updated the diff for D34160: [Power9] Exploit vinserth instruction.

Changed my mind, removed changes related to this comment:

Aug 30 2017, 7:01 AM

Aug 29 2017

gyiu added a comment to D34160: [Power9] Exploit vinserth instruction.

Note that I was able to re-implement Nemanja's suggestion of generalizing the case when both inputs are the same vector because the registers used in code-gen are now consistent. Not sure if it was a real problem that I saw previously, or a transient issue that was fixed with newer levels of LLVM.

Aug 29 2017, 8:38 PM
gyiu updated the diff for D34160: [Power9] Exploit vinserth instruction.
  • Refactored NFCs to another patch to be committed.
  • Made changes to remove restriction on only recognizing shuffles of halfword element 3 (4 in LE mode) when both input vectors are the same vector. That is, we can now recognize all single element shuffles in this situation.
Aug 29 2017, 8:32 PM

Aug 23 2017

gyiu added a comment to D34630: [Power9] Add additional patterns to recognize and transform insertelt/extractelt to vinsert[h|b]/vextractu[h|b] instructions..

@nemanjai @kbarton I believe the code sequences that 'https://reviews.llvm.org/D34032' generate have equal or less than the number of cycles these 'vextractu[h|b] + mfvsrd' sequences. Also, they are more general and can handle more cases. Therefore I don't think the extract portion of this patch is useful anymore. However, the insertelement patterns are still good to have IMO.

Aug 23 2017, 11:32 AM
gyiu added inline comments to D34160: [Power9] Exploit vinserth instruction.
Aug 23 2017, 10:35 AM

Jul 21 2017

gyiu added inline comments to D32249: [PartialInl] Enhance partial inliner to handle more complex conditions.
Jul 21 2017, 12:23 PM

Jun 26 2017

gyiu created D34630: [Power9] Add additional patterns to recognize and transform insertelt/extractelt to vinsert[h|b]/vextractu[h|b] instructions..
Jun 26 2017, 9:59 AM
gyiu updated the diff for D34160: [Power9] Exploit vinserth instruction.
  • Added breaks to stop searching for the pattern once I've found a candidate.
Jun 26 2017, 9:15 AM
gyiu added a comment to D34160: [Power9] Exploit vinserth instruction.
  • I'll open a separate item to address Nemenja's comments as I will not get a chance to do another enchancement.
Jun 26 2017, 8:07 AM

Jun 23 2017

gyiu added inline comments to D34160: [Power9] Exploit vinserth instruction.
Jun 23 2017, 11:49 AM

Jun 21 2017

gyiu added inline comments to D34160: [Power9] Exploit vinserth instruction.
Jun 21 2017, 9:58 PM
gyiu updated the diff for D34160: [Power9] Exploit vinserth instruction.
  • Addressed comments about my comments (grammar, periods, etc).
  • Removed irrelevant comments in PPCISelLowering.h
Jun 21 2017, 9:44 PM
gyiu created D34497: [Power9] Exploit vinsertb instruction.
Jun 21 2017, 9:34 PM

Jun 19 2017

gyiu updated the diff for D34160: [Power9] Exploit vinserth instruction.
  • Added -O0 to LIT tests to test corner case of undef 2nd operand of vector shuffle.
  • Refactored VINSERTH code to avoid boolean parameters and return value.
  • Merged loops for 2nd operand undefined case and both operands defined.
Jun 19 2017, 11:12 AM
gyiu added inline comments to D34160: [Power9] Exploit vinserth instruction.
Jun 19 2017, 8:05 AM

Jun 15 2017

gyiu updated the diff for D34160: [Power9] Exploit vinserth instruction.
  • Added comments and demangled function names for LIT tests
  • Added period to comment
  • Fixed issue when one operand of the shufflevector is 'undef', in which case the PPCISDs we generate will use only the defined one.
  • Initialize 'Swap' boolean
Jun 15 2017, 6:39 PM
gyiu added inline comments to D34245: [PowerPC] Refine the checking for emiting TOC restore nops and Tail-Call eligibility..
Jun 15 2017, 1:08 PM
gyiu added a comment to D34160: [Power9] Exploit vinserth instruction.

This patch (potentially) increase the number of vector instructions (permutation -> shift + insert). Is my understanding correct?

Jun 15 2017, 8:41 AM

Jun 13 2017

gyiu created D34160: [Power9] Exploit vinserth instruction.
Jun 13 2017, 12:51 PM