Other than inline comments, LGTM.

In D105560#2862938, @thomasjohns wrote:

In D105560#2862905, @gyiu wrote:

Do we also need a LIT testcase for this under llvm/test/CodeGen/ARC?

This change is only aiming to get the disassembly working (and thus the llvm/test/MC/Disassembler/ARC case). Our plan is to get the code-gen side of the CLZ intrinsic working in a follow up patch, and then we'll add the codegen LIT testcase there. Does this sound okay?

Do we also need a LIT testcase for this under llvm/test/CodeGen/ARC?

@hiraditya This is very similar to the PartialInlining pass based on PSI that can outline multiple cold regions in a function, something I implemented a couple of years ago. Is there a chance we can merge these two passes into one?

In D40477#939587, @echristo wrote:

This definitely needs numbers - across multiple platforms. Both performance and size of resultant binaries.

@nemanjai Good eye, but actually there's already an option disable partial inlining somewhere else (options to enable and disable are in different files, go figure). Defined in 'lib/Transforms/IPO/PartialInlining.cpp', called '-disable-partial-inlining'.

• Added new multi-outlined-region testcase.
• Removed unnecessary traces and moved useful ones to 'ifndef NDEBUG' macro.
• Modified/added ORE messages according to suggestions.
• General clean-up using clang-format.

• Added testcase.
• Remove the requirement for a conditional branch as the terminator of the entry block, for multi-region outlining specifically.

Updated based on latest comments. Still missing testcase that I'm working on currently. Will update patch when ready.

• Updated code based on review comments.
• Also added check for candidate region outputs. If cold region has an output (ie. a live exit variable) then we could be blocking some code motion in the caller after it has been outlined.
• Also added code to mark outlined functions/callsites with coldCC.

@trentxintong Hello, this change is actually causing the assert to trigger in 15 SPEC2006 benchmarks on PPC64LE with '-O3 -mcpu=pwr8 -m64 -fprofile-use -flto=thin'. Failures are during the link step.

@trentxintong Hello, this change is actually causing the assert to trigger in 15 SPEC2006 benchmarks on PPC64LE with '-O3 -mcpu=pwr8 -m64 -fprofile-use -flto=thin'. Failures are during the link step.

Add new testcase to make sure plugin-opt is passed to gold linker to enable new pass manager.

• Removed extract element patterns as changes from 'https://reviews.llvm.org/D34032' generate better code in terms of total cycles. Also it catches more cases than the vextractu[hb] instructions, as it's only beneficial when operating on dword[1] of the vector register.

Changed my mind, removed changes related to this comment:

Note that I was able to re-implement Nemanja's suggestion of generalizing the case when both inputs are the same vector because the registers used in code-gen are now consistent. Not sure if it was a real problem that I saw previously, or a transient issue that was fixed with newer levels of LLVM.

• Refactored NFCs to another patch to be committed.
• Made changes to remove restriction on only recognizing shuffles of halfword element 3 (4 in LE mode) when both input vectors are the same vector. That is, we can now recognize all single element shuffles in this situation.

@nemanjai @kbarton I believe the code sequences that 'https://reviews.llvm.org/D34032' generate have equal or less than the number of cycles these 'vextractu[h|b] + mfvsrd' sequences. Also, they are more general and can handle more cases. Therefore I don't think the extract portion of this patch is useful anymore. However, the insertelement patterns are still good to have IMO.

• Added breaks to stop searching for the pattern once I've found a candidate.

• I'll open a separate item to address Nemenja's comments as I will not get a chance to do another enchancement.

• Addressed comments about my comments (grammar, periods, etc).
• Removed irrelevant comments in PPCISelLowering.h

• Added -O0 to LIT tests to test corner case of undef 2nd operand of vector shuffle.
• Refactored VINSERTH code to avoid boolean parameters and return value.
• Merged loops for 2nd operand undefined case and both operands defined.

• Added comments and demangled function names for LIT tests
• Added period to comment
• Fixed issue when one operand of the shufflevector is 'undef', in which case the PPCISDs we generate will use only the defined one.
• Initialize 'Swap' boolean

In D34160#779972, @inouehrs wrote:

This patch (potentially) increase the number of vector instructions (permutation -> shift + insert). Is my understanding correct?