[PowerPC] Fix bugs in sign-/zero-extension elimination

[stefanp]

Summary

This patch fixes the following two bugs in PPCInstrInfo::isSignOrZeroExtended helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.

• Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
• Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).

To handle the first case, the parameter for the helpers is changed from MachineInstr to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.

[nemanjai]

To be honest, this code seems even more counter-intuitive to me now. I initially thought that this should essentially be a known-bits calculation on virtual registers and suggested that. With these changes, the code even more closely resembles that, but in a very roundabout fashion. Seems like it would be much simpler to implement and follow this if we just built and maintained a map from virtual registers to known zero/sign bits. Then all we need to check in order to decide if we want to get rid of an EXTS[BHW] is whether the correct number of leading bits are known to be sign bits. Similarly, we'd know if it is safe to remove a CLRLDI/RLWINM/... if the correct number of leading bits are known to be zero. Furthermore, with this approach we wouldn't need to consider the depth that we look through.

Of course, we can leave that as a future simplification.

The reason I've requested changes is to get rid of the debugging code and change the names of the functions.

lib/Target/PowerPC/PPCInstrInfo.cpp

2164 ↗

(On Diff #124562)

Similarly to isZeroExtendingOp(), this name no longer makes sense.

2215 ↗

(On Diff #124562)

This name no longer makes sense. This is really a query for whether or not the virtual register contains a value that is zero-extended.

lib/Target/PowerPC/PPCMIPeephole.cpp

196 ↗

(On Diff #124562)

This whole section needs to be cleaned up. Lines too long. Code commented-out. Pre-processor conditions. Presumably leftovers from debugging during development.

Actually, on second look, this injects trap instructions for debugging and should probably just be removed.

[inouehrs]

• addressed comments from @nemanjai
• rebased to the latest code base and fixed merge conflict

[inouehrs]

lib/Target/PowerPC/PPCInstrInfo.cpp

2164 ↗

(On Diff #124562)

I changed the method name. Do you have idea on an alternative name?

lib/Target/PowerPC/PPCMIPeephole.cpp

196 ↗

(On Diff #124562)

Thank you so much for pointing this out. I removed debug code section.

[inouehrs]

• fixed a bug

[hfinkel]

lib/Target/PowerPC/PPCInstrInfo.h

306 ↗

(On Diff #125162)

Comment out of date?

313 ↗

(On Diff #125162)

Comment out of date.

[jtony]

As you mentioned some registers defined by ORIS/ANDIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). Can you provide some details (maybe in a comment) about how they depend on the immediate? This would be helpful for future maintainers.

lib/Target/PowerPC/PPCInstrInfo.cpp

2164 ↗

(On Diff #125162)

We need to update this function name.

2201 ↗

(On Diff #125162)

Can you put a comment here to explain why only when the the immediate is great or equal than 33 the value is sign-extended?

[inouehrs]

• rebased on the latest code

[inouehrs]

update MIR test case to comply with the recent change in the sigil for MIR physical register

[nemanjai]

lib/Target/PowerPC/PPCInstrInfo.cpp

3048 ↗

(On Diff #132808)

I think the number of opcodes here is large enough to warrant storing them in a data structure with efficient searching such as a dense set. In addition to readability at the point where you're querying this, it can be very clear from the name what the data structure contains.

For example, if you have a container called OpcodesZExt32To64, it is very clear what it is for and any future code that needs such functionality can easily access that container rather than re-writing this whole list.

Of course, the same applies to the similar list for zero extending ops.

3249 ↗

(On Diff #132808)

Seems a bit misleading to have a depth parameter that is not actually respected if we're looking through a chain of copies. Although of course, deep chains of copies shouldn't happen in practice.

3254 ↗

(On Diff #132808)

Why does the register input matter for and-immediate?

3261 ↗

(On Diff #132808)

This recursive call as well as the next also don't check the depth, right? I realize that these immediate-form binary logical ops won't be chained, but it's still good to add a comment explaining we don't need to limit the depth on such ops.

3317 ↗

(On Diff #132808)

Comment with the assert.

lib/Target/PowerPC/PPCInstrInfo.h

343 ↗

(On Diff #132808)

I still think this setup with separate queries for sign/zero/any extend seems unnecessarily complex. Seems like it would be clearer if we had an enum for the extension type (sign, zero, none) and we just have a single query that will return this. Therefore no need for Boolean parameters, no need for multiple functions, etc.

[inouehrs]

addressed comments

[inouehrs]

lib/Target/PowerPC/PPCInstrInfo.cpp

3249 ↗

(On Diff #132808)

I changed the names of variable and constant to indicate they shows the depth of binary operators.

3254 ↗

(On Diff #132808)

Good catch. I fixed.

3317 ↗

(On Diff #132808)

I added comment, but I feel this assert is not necessary.

lib/Target/PowerPC/PPCInstrInfo.h

343 ↗

(On Diff #132808)

I agree that the single query approach is cleaner. But I am afraid that it will increase the cost of compilation slightly since it always checks for both sign- and zero-extensions. Do you think the potential increase in compilation cost does not matter too much here?

[nemanjai]

lib/Target/PowerPC/PPCInstrInfo.h

343 ↗

(On Diff #132808)

It seems to me that the checks are not costly except in chained operations cases (which we traverse the chain as it is). Or am I missing something. What is the worst case complexity of the computations for each?

[inouehrs]

• changed the return value of isSignOrZeroExtended to std::pair<bool, bool>

[inouehrs]

lib/Target/PowerPC/PPCInstrInfo.h

343 ↗

(On Diff #132808)

Thanks. I modified the helper to return std::pair<bool, bool>.
Do you prefer an enum?

[inouehrs]

• rebased to the latest tree and ran tests again
• fix formatting

[inouehrs]

• rebased to the latest source (fix conflicts and update unit tests)

[amyk]

Hi @inouehrs, I will be commandeering this revision since we are revisiting this patch.

[inouehrs]

@amyk I see. Please let me know you need some help.

[amyk]

• Rebased to the latest source (fix conflicts, ran functional tests)
• Fixed llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll to remove redundant sign extend instruction
• Added the following check in PPCMIPeephole.cpp to only perform the LWZ->LWA transformation when the displacement is a multiple of 4

// The transformation from a zero-extending load to a sign-extending
// load is only legal when the displacement is a multiple of 4.
// If the displacement is not at least 4 byte aligned, don't perform
// the transformation.
if (SrcMI->getOperand(1).isGlobal() &&
    SrcMI->getOperand(1).getGlobal()->getAlignment() < 4)
  break;

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5317

The bitwise or seems like an odd choice here since IsSExt/IsZExt shouldn't possibly be true here and also I think logical or seems more natural for bool variables.
The change to logical or doesn't require another revision.

5356

These can probably be logical or's as well. Same with the below ones.

5395

Please remove this todo.

[stefanp]

Taking over this patch to rebase it on top of current code and to see if it can be eventually checked in.

[stefanp]

Rebased the patch to top of trunk.
A number of test cases had to be re-generated. This rebase shouldn't really
change what the patch does.

[stefanp]

Fixed some formatting issues.

[stefanp]

Found that POPCNTW instruction does not ensure that the upper 32 bits
are cleared. As a result I have removed it from the list.

[stefanp]

Fixed a typo in the handling of the PPC::AND.

[stefanp]

Added more early breaks to make sure that we do not convert from a zero extending
load to a sign extending load with an invalid displacement.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5131–5132

Question: should we update this to say if the register and not machine instruction since it is changed to Reg for the parameter?
Or should it stay as machine instruction since you're checking for the different MachineInstr opcodes in this function?
The same question I have applies to definedByZeroExtendingOp().

5164

5317

If the change to logical or still applies, we should probably update these accordingly.

[stefanp]

Updated a couple of comments and changed the OR.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5131–5132

I think it should probably say "machine instruction that defines this register" because that is what we are really interested in. We want to make sure that this register is already sign extended by the instruction that defines it. I'm going to re-write the comment to make it clear.

5317

Sure. I can change it to logical.

[stefanp]

Rebased this patch to the top of main and retested.

[stefanp]

Need to rebase this patch again. Will request another review once I have done that.

[stefanp]

Rebased patch to top of trunk.

[stefanp]

Fairly significant changes have been made since I took over this patch and I would prefer to have another set of eyes take a look.
I will request a new review.

[nemanjai]

Sorry, I had some comments that I haven't submitted because I had not gotten through the entire patch. I am not sure if they all still apply but thought I'd submit them before restarting the review.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5132–5157

I think all explanations of what sign-extending means should be removed and you should just note that this is a test explicitly for sign extension from 32 to 64 bits.

5146

Rather than having tables of these opcodes in the C++ code, we should probably just add a couple of flags in our .td files for the two types of extension. Perhaps isSExt32To64, isZExt32To64. Then we can simply query that on the MI.

Of course, the ones below this set probably have to stay because they have further constraints.

5160

Is there no DenseSet<>::count()?

5288–5289

This block ends up getting very deeply nested and hard to follow. Can we flip the conditions and do early exits? Something like:

if (SrcReg != PPC::X3)
  return ...
...
if previous instr is not the stack adjust or the one before is not a call...
  return ...

and so on.

5308–5315

This code might need to move up if we are flipping the previous condition.

llvm/lib/Target/PowerPC/PPCInstrInfo.h

703–704

// Return true if the register is sign-extended from 32 to 64 bits.

709–710

// Return true if the register is zero-extended from 32 to 64 bits.

[stefanp]

Added two new flags ZExt32To64 and SExt32To64.
Marked instructions that zero extend or sign extend in the TD files with those
flags.
Fixed a few comments as well.
Tried to extract an if statement to reduce the indentation a little.

[stefanp]

Rebased the patch to top of trunk again.

[stefanp]

Rebased to top of main branch.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrFormats.td

48

53

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5184–5207

5184–5207

A minor nit on this comment.

5233

Question: This is something super minor, but is it better to put the check for isZExt32To64() earlier in the function?

I know it may not matter, but I am just wondering in case it may be better to do this prior to all of the different opcode checks, and since the definedBySignExtendingOp also put it's isSExt32To64() pretty early in the function.

In any case, this is just a question so if it's not applicable, you can feel free to disregard this.

[stefanp]

Rebased the patch to top of main branch.
Updated a couple of typos.
Moved a check earlier in the function.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5233

Question: This is something super minor, but is it better to put the check for isZExt32To64() earlier in the function?

I know it may not matter, but I am just wondering in case it may be better to do this prior to all of the different opcode checks, and since the definedBySignExtendingOp also put it's isSExt32To64() pretty early in the function.

In any case, this is just a question so if it's not applicable, you can feel free to disregard this.

I don't think it matters in this case. For this check we need to get TII so maybe it's better to check other things first that don't require the instruction info? That may save us from having to get the additional information in a limited number of cases. On the other hand we are just checking a single flag for a large number of instructions.
Anyway, I really don't feel strongly about it one way or another. I'm going to move it up just because it is nicer style to have the two functions a little more similar.

[amyk]

Thanks for addressing my previous comments, Stefan.
I don't believe I have any other further comments. Unless if Nemanja has any additional comments, this personally LGTM.

[nemanjai]

As tends to be the case with huge patches such as this, it is difficult to get this patch to converge and it still needs a bit of work. But I think it is pretty close overall.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

901–902

I don't follow why this is only marked as zero-extended (whereas for example, andi. is marked as both). The 32-bit sign bit can only be a zero, so a sign-extend from 32-bits (extsw) is guaranteed to essentially be a nop.

967–968

Similar comment as for the word versions regarding sign extension..

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5169

s/masked/masked out

5233–5234

Just for consistency, this check is first in the sign extending check... You should probably move it up in this function so it is consistent with that.

5282

I still don't like the deep nesting in this block. It seems like we can get rid of all that deep nesting by rewriting this block as:

case PPC::COPY: {
  Register SrcReg = MI->getOperand(1).getReg();

  // In both ELFv1 and v2 ABI, method parameters and the return value
  // are sign- or zero-extended.
  const MachineFunction *MF = MI->getMF();

  if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
    // If this is a copy from another register, we recursively check source.
    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
    return std::pair<bool, bool>(SrcExt.first || IsSExt,
                                 SrcExt.second || IsZExt);
  }

  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
  // We check the ZExt/SExt flags for a method parameter.
  if (MI->getParent()->getBasicBlock() ==
      &MF->getFunction().getEntryBlock()) {
    Register VReg = MI->getOperand(0).getReg();
    if (MF->getRegInfo().isLiveIn(VReg)) {
      IsSExt |= FuncInfo->isLiveInSExt(VReg);
      IsZExt |= FuncInfo->isLiveInZExt(VReg);
      return std::pair<bool, bool>(IsSExt, IsZExt);
    }
  }

  // For a method return value, we check the ZExt/SExt flags in attribute.
  // We assume the following code sequence for method call.
  //   ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
  //   BL8_NOP @func,...
  //   ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
  //   %5 = COPY %x3; G8RC:%5
  if (SrcReg != PPC::X3) {
    // If this is a copy from another register, we recursively check source.
    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
    return std::pair<bool, bool>(SrcExt.first || IsSExt,
                                 SrcExt.second || IsZExt);
  }

  const MachineBasicBlock *MBB = MI->getParent();
  MachineBasicBlock::const_instr_iterator II =
      MachineBasicBlock::const_instr_iterator(MI);
  if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP)
    return std::pair<bool, bool>(IsSExt, IsZExt);

  const MachineInstr &CallMI = *(--II);
  if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
    return std::pair<bool, bool>(IsSExt, IsZExt);

  const Function *CalleeFn =
      dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
  if (!CalleeFn)
    return std::pair<bool, bool>(IsSExt, IsZExt);

  const IntegerType *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
  if (IntTy && IntTy->getBitWidth() <= 32) {
    const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
    IsSExt |= Attrs.hasAttribute(Attribute::SExt);
    IsZExt |= Attrs.hasAttribute(Attribute::ZExt);
  }
  return std::pair<bool, bool>(IsSExt, IsZExt);
}

I have neither compiled nor tested this, so please scrutinize it carefully rather than assuming that my suggestion is verified.

5316–5346

Can any of this ever produce anything useful? If I am reading this correctly, this is basically:

• The copy is from X3
• We check if the definition of X3 is sign/zero extended

But this seems pointless since we won't track anything about what defined X3 here.

Edit: actually, the above is so deeply nested that I missed the fact that this code is for non-SVR4 ABI's.

5356

Is there a reason this comment was not addressed and these are still bitwise OR's?

5388–5389

I understand that these names predate this patch, but since we are modifying it, can we give them more descriptive names? Perhaps OperandEnd, OperandStride?

llvm/lib/Target/PowerPC/PPCInstrP10.td

1322–1323

Did you mean to mark all of these as ZExt32To64? The possible results are 0/1 for these. So I suppose they are technically both sign and zero extending.
Furthermore, the negative forms (setnbc/setnbcr) are not marked as sign extending even though the values are possible values are -1/0.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1303

It would seem that the vextu[bhw][lr]x family of instructions have been missed and they're all zero extending.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

787–800

This code is so unnecessarily lambda-ey. Can you please commit an NFC patch (I don't care if it is before or after this patch) to flatten this out?

804–807

Why? LHA is D-Form (not DS-Form) and LHAX of course doesn't care since it is X-Form.

847–850

This is true if we are transforming it to the DS-Form lwa. It shouldn't matter for the X-Form lwax. Perhaps this code should just set a bool variable IsWordAligned or something similar and then below, we break out:

if (IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))

[stefanp]

Fixed the zero extend / sign extend flags on a number of instructions.
Tried to flatten out PPCInstrInfo::isSignOrZeroExtended a little.
Removed the restriction on LHA, LHAX, and LWAX.

I will address the issues with too many lambdas in the code in a separate patch.

[stefanp]

Removed the zero extend and sign extend from popcntw and popcntb and I added
them incorrectly.

[nemanjai]

The remaining comments are minor nits that can be addressed on the commit. Please don't forget the follow-up I requested at https://reviews.llvm.org/D40554#inline-1239933.
Other than those, LGTM.

Thanks for your patience with this patch.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

5203–5207

Since we repeat this code (the subword part), maybe it would be cleaner to extract it into a static local function - something like:

static bool isOpZeroOfSubwordPreincLoad(const MachineInstr &MI)

Of course, since you still need the LWZU variants, it may not be worth it.
This is a minor stylistic comment that shouldn't delay approval.

5291

I am a little unclear on the use of BinOpDepth in this function. It seems very inconsistent. Wouldn't it make sense to always add one for the recursive call as well as to check whether it has been exceeded prior to the call? We seem to do that when checking for reg+reg instructions but not for reg+imm instructions. Is that because a single recursive call avoids exponential recursion whereas the two calls for reg+reg instructions don't? If so, can you please add a comment to that end at the top of the function?

5315–5320

Since the comment above this block describes the code below, maybe just move this block above the comment.

5319

Super minor nit: since we construct the same pair in 3 different early exits as well as at the end, maybe just construct it once and return it in each location (lines 5320, 5324, 5329, 5340).
There is no functional or performance difference, but it is very clear that what we are returning is the exact same thing and couldn't have changed.

5328

I think it may be possible for CallMI.getOperand(0).getGlobal() to return null under some odd circumstances. It would probably be safer to use dyn_cast_if_present here rather than dyn_cast.

5340

This comment is out of date now.

[stefanp]

Rebased the patch to top of trunk.
Addressed final comments from reviewer.
This is mostly adding or fixing comments and code cleanup.

[stefanp]

Did a final format fix.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
   return BB;
 }
 
 static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) {
   switch(MI.getOpcode()) {
   default:
     return false;
   case PPC::COPY:
-    return TII->isSignExtended(MI);
+    return TII->isSignExtended(MI.getOperand(1).getReg(),
+                               &MI.getMF()->getRegInfo());
   case PPC::LHA:
   case PPC::LHA8:
   case PPC::LHAU:
   case PPC::LHAU8:
   case PPC::LHAUX:
   case PPC::LHAUX8:
   case PPC::LHAX:
   case PPC::LHAX8:

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 let PPC970_Unit = 1 in {  // FXU Operations.
 let Interpretation64Bit = 1 in {
 let hasSideEffects = 0 in {
 let isCodeGenOnly = 1 in {
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
 def LI8  : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
                       "li $rD, $imm", IIC_IntSimple,
-                      [(set i64:$rD, imm64SExt16:$imm)]>;
+                      [(set i64:$rD, imm64SExt16:$imm)]>, SExt32To64;
 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
                       "lis $rD, $imm", IIC_IntSimple,
-                      [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
+                      [(set i64:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64;
 }
 
 // Logical ops.
 let isCommutable = 1 in {
 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      "nand", "$rA, $rS, $rB", IIC_IntSimple,
                      [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
 defm AND8 : XForm_6r<31,  28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
 } // let isCommutable = 1
 
 // Logical ops with immediate.
 let Defs = [CR0] in {
 def ANDI8_rec  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "andi. $dst, $src1, $src2", IIC_IntGeneral,
                       [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
-                      isRecordForm;
+                      isRecordForm, SExt32To64, ZExt32To64;
 def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                      "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
-                     isRecordForm;
+                     isRecordForm, ZExt32To64;
 }
 def ORI8    : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "ori $dst, $src1, $src2", IIC_IntSimple,
                       [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
 def ORIS8   : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "oris $dst, $src1, $src2", IIC_IntSimple,
                     [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
 def XORI8   : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
defm SRD  : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
                      "srd", "$rA, $rS, $rB", IIC_IntRotateD,
                      [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
                       "srad", "$rA, $rS, $rB", IIC_IntRotateD,
                       [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 defm CNTLZW8 : XForm_11r<31,  26, (outs g8rc:$rA), (ins g8rc:$rS),
-                        "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
+                        "cntlzw", "$rA, $rS", IIC_IntGeneral, []>,
+                        ZExt32To64, SExt32To64;
 defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS),
                         "cnttzw", "$rA, $rS", IIC_IntGeneral, []>,
-               Requires<[IsISA3_0]>;
+               Requires<[IsISA3_0]>, ZExt32To64, SExt32To64;
 
 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
                         "extsb", "$rA, $rS", IIC_IntSimple,
-                        [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
+                        [(set i64:$rA, (sext_inreg i64:$rS, i8))]>, SExt32To64;
 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
                         "extsh", "$rA, $rS", IIC_IntSimple,
-                        [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
+                        [(set i64:$rA, (sext_inreg i64:$rS, i16))]>, SExt32To64;
 
 defm SLW8  : XForm_6r<31,  24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
-                      "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
+                      "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64;
 defm SRW8  : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
-                      "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
+                      "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64;
 } // Interpretation64Bit
 
 // For fast-isel:
 let isCodeGenOnly = 1 in {
 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
-                           "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
+                           "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64,
+                           SExt32To64;
 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
-                           "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
+                           "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64,
+                           SExt32To64;
 } // isCodeGenOnly for fast-isel
 
 defm EXTSW  : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
                         "extsw", "$rA, $rS", IIC_IntSimple,
-                        [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
+                        [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64,
+                        SExt32To64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
                              "extsw", "$rA, $rS", IIC_IntSimple,
-                             [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
+                             [(set i64:$rA, (sext i32:$rS))]>, isPPC64,
+                             SExt32To64;
 let isCodeGenOnly = 1 in
 def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
                         "extsw $rA, $rS", IIC_IntSimple,
                         []>, isPPC64;
 
 defm SRADI  : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
                          "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
                          [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;

 
 // For fast-isel:
 let isCodeGenOnly = 1, Defs = [CARRY] in
 def SRADI_32  : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH),
                          "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64;
 
 defm CNTLZD : XForm_11r<31,  58, (outs g8rc:$rA), (ins g8rc:$rS),
                         "cntlzd", "$rA, $rS", IIC_IntGeneral,
-                        [(set i64:$rA, (ctlz i64:$rS))]>;
+                        [(set i64:$rA, (ctlz i64:$rS))]>,
+                        ZExt32To64, SExt32To64;
 defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
                         "cnttzd", "$rA, $rS", IIC_IntGeneral,
-                        [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
+                        [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>,
+                        ZExt32To64, SExt32To64;
 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
                        "popcntd $rA, $rS", IIC_IntGeneral,
-                       [(set i64:$rA, (ctpop i64:$rS))]>;
+                       [(set i64:$rA, (ctpop i64:$rS))]>,
+                       ZExt32To64, SExt32To64;
 def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      "bpermd $rA, $rS, $rB", IIC_IntGeneral,
                      [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>,
                      isPPC64, Requires<[HasBPERMD]>;
 
 let isCodeGenOnly = 1, isCommutable = 1 in
 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                     "cmpb $rA, $rS, $rB", IIC_IntGeneral,
def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
                        isPPC64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
   def MADDLD8 : VAForm_1a<51, 
                        (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
                        [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
                        isPPC64;
   def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
-                       "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
+                       "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64;
 }
 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
                      "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modsd $rT, $rA, $rB", IIC_IntDivW,
                         [(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
 def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modud $rT, $rA, $rB", IIC_IntDivW,

 
 
 // Sign extending loads.
 let PPC970_Unit = 2 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
                   "lha $rD, $src", IIC_LdStLHA,
                   [(set i64:$rD, (sextloadi16 DForm:$src))]>,
-                  PPC970_DGroup_Cracked;
+                  PPC970_DGroup_Cracked, SExt32To64;
 def LWA  : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
                     "lwa $rD, $src", IIC_LdStLWA,
                     [(set i64:$rD,
                           (sextloadi32 DSForm:$src))]>, isPPC64,
-                    PPC970_DGroup_Cracked;
+                    PPC970_DGroup_Cracked, SExt32To64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src),
                         "lhax $rD, $src", IIC_LdStLHA,
                         [(set i64:$rD, (sextloadi16 XForm:$src))]>,
-                        PPC970_DGroup_Cracked;
+                        PPC970_DGroup_Cracked, SExt32To64;
 def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src),
                         "lwax $rD, $src", IIC_LdStLHA,
                         [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64,
-                        PPC970_DGroup_Cracked;
+                        PPC970_DGroup_Cracked, SExt32To64;
 // For fast-isel:
 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
 def LWA_32  : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
                       "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
-                      PPC970_DGroup_Cracked;
+                      PPC970_DGroup_Cracked, SExt32To64;
 def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src),
                             "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
-                            PPC970_DGroup_Cracked;
+                            PPC970_DGroup_Cracked, SExt32To64;
 } // end fast-isel isCodeGenOnly
 
 // Update forms.
 let mayLoad = 1, hasSideEffects = 0 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
                     (ins memri:$addr),
                     "lhau $rD, $addr", IIC_LdStLHAU,

 }
 }
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 // Zero extending loads.
 let PPC970_Unit = 2 in {
 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
                   "lbz $rD, $src", IIC_LdStLoad,
-                  [(set i64:$rD, (zextloadi8 DForm:$src))]>;
+                  [(set i64:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64,
+                  SExt32To64;
 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
                   "lhz $rD, $src", IIC_LdStLoad,
-                  [(set i64:$rD, (zextloadi16 DForm:$src))]>;
+                  [(set i64:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64,
+                  SExt32To64;
 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
                   "lwz $rD, $src", IIC_LdStLoad,
-                  [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64;
+                  [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64,
+                  ZExt32To64;
 
 def LBZX8 : XForm_1_memOp<31,  87, (outs g8rc:$rD), (ins memrr:$src),
                           "lbzx $rD, $src", IIC_LdStLoad,
-                          [(set i64:$rD, (zextloadi8 XForm:$src))]>;
+                          [(set i64:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64,
+                          SExt32To64;
 def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src),
                           "lhzx $rD, $src", IIC_LdStLoad,
-                          [(set i64:$rD, (zextloadi16 XForm:$src))]>;
+                          [(set i64:$rD, (zextloadi16 XForm:$src))]>,
+                          ZExt32To64, SExt32To64;
 def LWZX8 : XForm_1_memOp<31,  23, (outs g8rc:$rD), (ins memrr:$src),
                           "lwzx $rD, $src", IIC_LdStLoad,
-                          [(set i64:$rD, (zextloadi32 XForm:$src))]>;
+                          [(set i64:$rD, (zextloadi32 XForm:$src))]>,
+                          ZExt32To64;
                    
                    
 // Update forms.
 let mayLoad = 1, hasSideEffects = 0 in {
 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
                     (ins memri:$addr),
                     "lbzu $rD, $addr", IIC_LdStLoadUpd,
                     []>, RegConstraint<"$addr.reg = $ea_result">,

 let Predicates = [IsISA2_06] in {
 def LDBRX : XForm_1_memOp<31,  532, (outs g8rc:$rD), (ins memrr:$src),
                           "ldbrx $rD, $src", IIC_LdStLoad,
                           [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64;
 }
 
 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
 def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
-                          "lhbrx $rD, $src", IIC_LdStLoad, []>;
+                          "lhbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64;
 def LWBRX8 : XForm_1_memOp<31,  534, (outs g8rc:$rD), (ins memrr:$src),
-                          "lwbrx $rD, $src", IIC_LdStLoad, []>;
+                          "lwbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64;
 }
 
 let mayLoad = 1, hasSideEffects = 0 in {
 def LDU  : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
                     (ins memrix:$addr),
                     "ldu $rD, $addr", IIC_LdStLDU,
                     []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
                     NoEncode<"$ea_result">;

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 // Vector Extract Unsigned
 def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
 def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
 def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
 def VEXTRACTD  : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
 
 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
 let hasSideEffects = 0 in {
-def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
-def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
-def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
-def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
-def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
-def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
+def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>, ZExt32To64;
+def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>, ZExt32To64;
+def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>, ZExt32To64;
+def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>, ZExt32To64;
+def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>, ZExt32To64;
+def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>, ZExt32To64;
 }
 
 // Vector Insert Element Instructions
 def VINSERTB : VXForm_1<781, (outs vrrc:$vD),
                         (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB),
                         "vinsertb $vD, $vB, $UIM", IIC_VecGeneral,
                         [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB,
                                                       imm32SExt16:$UIM))]>,

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
 
   // Indicate that this instruction is of type X-Form Load or Store
   bits<1> XFormMemOp = 0;
   let TSFlags{6}  = XFormMemOp;
 
   // Indicate that this instruction is prefixed.
   bits<1> Prefixed = 0;
   let TSFlags{7}  = Prefixed;
   
+  // Indicate that this instruction produces a result that is sign extended from
+  // 32 bits to 64 bits.
+  bits<1> SExt32To64 = 0;
+  let TSFlags{8} = SExt32To64;
+
+  // Indicate that this instruction produces a result that is zero extended from
+  // 32 bits to 64 bits.
+  bits<1> ZExt32To64 = 0;
+  let TSFlags{9} = ZExt32To64;
+
   // Fields used for relation models.
   string BaseName = "";
 
   // For cases where multiple instruction definitions really represent the
   // same underlying instruction but with one definition for 64-bit arguments
   // and one for 32-bit arguments, this bit breaks the degeneracy between
   // the two forms and allows TableGen to generate mapping tables.
   bit Interpretation64Bit = 0;

 class PPC970_Unit_LSU      { bits<3> PPC970_Unit = 2;   }
 class PPC970_Unit_FPU      { bits<3> PPC970_Unit = 3;   }
 class PPC970_Unit_CRU      { bits<3> PPC970_Unit = 4;   }
 class PPC970_Unit_VALU     { bits<3> PPC970_Unit = 5;   }
 class PPC970_Unit_VPERM    { bits<3> PPC970_Unit = 6;   }
 class PPC970_Unit_BRU      { bits<3> PPC970_Unit = 7;   }
 
 class XFormMemOp { bits<1> XFormMemOp = 1; }
+class SExt32To64 { bits<1> SExt32To64 = 1; }
+class ZExt32To64 { bits<1> ZExt32To64 = 1; }
 
 // Two joined instructions; used to emit two adjacent instructions as one.
 // The itinerary from the first instruction is used for scheduling and
 // classification.
 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin>
         : Instruction {
   field bits<64> Inst;

llvm/lib/Target/PowerPC/PPCInstrInfo.h

 
 enum {
   /// Shift count to bypass PPC970 flags
   NewDef_Shift = 6,
 
   /// This instruction is an X-Form memory operation.
   XFormMemOp = 0x1 << NewDef_Shift,
   /// This instruction is prefixed.
-  Prefixed = 0x1 << (NewDef_Shift+1)
+  Prefixed = 0x1 << (NewDef_Shift + 1),
+  /// This instruction produced a sign extended result.
+  SExt32To64 = 0x1 << (NewDef_Shift + 2),
+  /// This instruction produced a zero extended result.
+  ZExt32To64 = 0x1 << (NewDef_Shift + 3)
 };
 } // end namespace PPCII
 
 // Instructions that have an immediate form might be convertible to that
 // form if the correct input is a result of a load immediate. In order to
 // know whether the transformation is special, we might need to know some
 // of the details of the two forms.
 struct ImmInstrInfo {
public:
   const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 
   bool isXFormMemOp(unsigned Opcode) const {
     return get(Opcode).TSFlags & PPCII::XFormMemOp;
   }
   bool isPrefixed(unsigned Opcode) const {
     return get(Opcode).TSFlags & PPCII::Prefixed;
   }
+  bool isSExt32To64(unsigned Opcode) const {
+    return get(Opcode).TSFlags & PPCII::SExt32To64;
+  }
+  bool isZExt32To64(unsigned Opcode) const {
+    return get(Opcode).TSFlags & PPCII::ZExt32To64;
+  }
 
   /// Check if Opcode corresponds to a call instruction that should be marked
   /// with the NOTOC relocation.
   bool isNoTOCCallInstr(unsigned Opcode) const {
     if (!get(Opcode).isCall())
       return false;
 
     switch (Opcode) {
#endif
   static bool isVRRegister(unsigned Reg) {
     return Reg >= PPC::V0 && Reg <= PPC::V31;
   }
   const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
   static int getRecordFormOpcode(unsigned Opcode);
 
   bool isTOCSaveMI(const MachineInstr &MI) const;
 
-  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
-                            const unsigned PhiDepth) const;
-
-  /// Return true if the output of the instruction is always a sign-extended,
-  /// i.e. 0 to 31-th bits are same as 32-th bit.
-  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
-    return isSignOrZeroExtended(MI, true, depth);
+  std::pair<bool, bool>
+  isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
+                       const MachineRegisterInfo *MRI) const;
+
+  // Return true if the register is sign-extended from 32 to 64 bits.
+  bool isSignExtended(const unsigned Reg,
+                      const MachineRegisterInfo *MRI) const {
+    return isSignOrZeroExtended(Reg, 0, MRI).first;
   }
 
-  /// Return true if the output of the instruction is always zero-extended,
-  /// i.e. 0 to 31-th bits are all zeros
-  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
-   return isSignOrZeroExtended(MI, false, depth);
+  // Return true if the register is zero-extended from 32 to 64 bits.
+  bool isZeroExtended(const unsigned Reg,
+                      const MachineRegisterInfo *MRI) const {
+    return isSignOrZeroExtended(Reg, 0, MRI).second;
   }
 
   bool convertToImmediateForm(MachineInstr &MI,
                               MachineInstr **KilledDef = nullptr) const;
   bool foldFrameOffset(MachineInstr &MI) const;
   bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
   bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
   bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

 
 #include "PPCInstrInfo.h"
 #include "MCTargetDesc/PPCPredicates.h"
 #include "PPC.h"
 #include "PPCHazardRecognizers.h"
 #include "PPCInstrBuilder.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCTargetMachine.h"
+#include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
   // Get the unique definition of SrcReg.
   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
   if (!MI) return false;
 
   bool equalityOnly = false;
   bool noSub = false;
   if (isPPC64) {
     if (is32BitSignedCompare) {
-      // We can perform this optimization only if MI is sign-extending.
-      if (isSignExtended(*MI))
+      // We can perform this optimization only if SrcReg is sign-extending.
+      if (isSignExtended(SrcReg, MRI))
         noSub = true;
       else
         return false;
     } else if (is32BitUnsignedCompare) {
-      // We can perform this optimization, equality only, if MI is
+      // We can perform this optimization, equality only, if SrcReg is
       // zero-extending.
-      if (isZeroExtended(*MI)) {
+      if (isZeroExtended(SrcReg, MRI)) {
         noSub = true;
         equalityOnly = true;
       } else
         return false;
     } else
       equalityOnly = is64BitUnsignedCompare;
   } else
     equalityOnly = is32BitUnsignedCompare;
PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
   if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
     return &PPC::VSRCRegClass;
   return RC;
 }
 
 int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
   return PPC::getRecordFormOpcode(Opcode);
 }
 
-// This function returns true if the machine instruction
-// always outputs a value by sign-extending a 32 bit value,
-// i.e. 0 to 31-th bits are same as 32-th bit.
-static bool isSignExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
-  if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS ||
-      Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec ||
-      Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA ||
-      Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
-      Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 ||
-      Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
-      Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU ||
-      Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
-      Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 ||
-      Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
-      Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB ||
-      Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH ||
-      Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 ||
-      Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW ||
-      Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
-      Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
-      Opcode == PPC::EXTSB8_32_64)
+static bool isOpZeroOfSubwordPreincLoad(int Opcode) {
+  return (Opcode == PPC::LBZU || Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 ||
+          Opcode == PPC::LBZUX8 || Opcode == PPC::LHZU ||
+          Opcode == PPC::LHZUX || Opcode == PPC::LHZU8 ||
+          Opcode == PPC::LHZUX8);
+}
+
+// This function checks for sign extension from 32 bits to 64 bits.
+static bool definedBySignExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
+  if (!Register::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI)
+    return false;
+
+  int Opcode = MI->getOpcode();
+  const PPCInstrInfo *TII =
+      MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+  if (TII->isSExt32To64(Opcode))
     return true;
 
-  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+  // The first def of LBZU/LHZU is sign extended.
+  if (isOpZeroOfSubwordPreincLoad(Opcode) && MI->getOperand(0).getReg() == Reg)
     return true;
 
+  // RLDICL generates sign-extended output if it clears at least
+  // 33 bits from the left (MSB).
+  if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33)
+    return true;
+
+  // If at least one bit from left in a lower word is masked out,
+  // all of 0 to 32-th bits of the output are cleared.
+  // Hence the output is already sign extended.
   if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
        Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) &&
-      MI.getOperand(3).getImm() > 0 &&
-      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+      MI->getOperand(3).getImm() > 0 &&
+      MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
+    return true;
+
+  // If the most significant bit of immediate in ANDIS is zero,
+  // all of 0 to 32-th bits are cleared.
+  if (Opcode == PPC::ANDIS_rec || Opcode == PPC::ANDIS8_rec) {
+    uint16_t Imm = MI->getOperand(2).getImm();
+    if ((Imm & 0x8000) == 0)
       return true;
+  }
 
   return false;
 }
 
-// This function returns true if the machine instruction
-// always outputs zeros in higher 32 bits.
-static bool isZeroExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
+// This function checks the machine instruction that defines the input register
+// Reg. If that machine instruction always outputs a value that has only zeros
+// in the higher 32 bits then this function will return true.
+static bool definedByZeroExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
+  if (!Register::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI)
+    return false;
+
+  int Opcode = MI->getOpcode();
+  const PPCInstrInfo *TII =
+      MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+  if (TII->isZExt32To64(Opcode))
+    return true;
+
+  // The first def of LBZU/LHZU/LWZU are zero extended.
+  if ((isOpZeroOfSubwordPreincLoad(Opcode) || Opcode == PPC::LWZU ||
+       Opcode == PPC::LWZUX || Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) &&
+      MI->getOperand(0).getReg() == Reg)
+    return true;
+
   // The 16-bit immediate is sign-extended in li/lis.
   // If the most significant bit is zero, all higher bits are zero.
   if (Opcode == PPC::LI  || Opcode == PPC::LI8 ||
       Opcode == PPC::LIS || Opcode == PPC::LIS8) {
-    int64_t Imm = MI.getOperand(1).getImm();
+    int64_t Imm = MI->getOperand(1).getImm();
     if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
       return true;
   }
 
   // We have some variations of rotate-and-mask instructions
   // that clear higher 32-bits.
   if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
        Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec ||
        Opcode == PPC::RLDICL_32_64) &&
-      MI.getOperand(3).getImm() >= 32)
+      MI->getOperand(3).getImm() >= 32)
     return true;
 
   if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
-      MI.getOperand(3).getImm() >= 32 &&
-      MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+      MI->getOperand(3).getImm() >= 32 &&
+      MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
     return true;
 
   if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
        Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
-      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
-    return true;
-
-  // There are other instructions that clear higher 32-bits.
-  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
-      Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
-      Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
-      Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
-      Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec ||
-      Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
-      Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
-      Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI ||
-      Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI ||
-      Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
-      Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX ||
-      Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
-      Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ ||
-      Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
-      Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 ||
-      Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
-      Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 ||
-      Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
-      Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
-      Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec ||
-      Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec ||
-      Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec ||
-      Opcode == PPC::MFVSRWZ)
+      MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return true;
 
   return false;
 }
 
 // This function returns true if the input MachineInstr is a TOC save
 // instruction.
 bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
   if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
     return false;
   unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
   unsigned StackOffset = MI.getOperand(1).getImm();
   Register StackReg = MI.getOperand(2).getReg();
   Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
   if (StackReg == SPReg && StackOffset == TOCSaveOffset)
     return true;
 
   return false;
 }
 
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid excessive cost.
-const unsigned MAX_DEPTH = 1;
+const unsigned MAX_BINOP_DEPTH = 1;
+// The isSignOrZeroExtended function is recursive. The parameter BinOpDepth
+// does not count all of the recursions. The parameter BinOpDepth is incremented
+// only when isSignOrZeroExtended calls itself more than once. This is done to
+// prevent expontential recursion. There is no parameter to track linear
+// recursion.
+std::pair<bool, bool>
+PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg,
+                                   const unsigned BinOpDepth,
+                                   const MachineRegisterInfo *MRI) const {
+  if (!Register::isVirtualRegister(Reg))
+    return std::pair<bool, bool>(false, false);
 
-bool
-PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
-                                   const unsigned Depth) const {
-  const MachineFunction *MF = MI.getParent()->getParent();
-  const MachineRegisterInfo *MRI = &MF->getRegInfo();
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI)
+    return std::pair<bool, bool>(false, false);
 
-  // If we know this instruction returns sign- or zero-extended result,
-  // return true.
-  if (SignExt ? isSignExtendingOp(MI):
-                isZeroExtendingOp(MI))
-    return true;
+  bool IsSExt = definedBySignExtendingOp(Reg, MRI);
+  bool IsZExt = definedByZeroExtendingOp(Reg, MRI);
 
-  switch (MI.getOpcode()) {
+  // If we know the instruction always returns sign- and zero-extended result,
+  // return here.
+  if (IsSExt && IsZExt)
+    return std::pair<bool, bool>(IsSExt, IsZExt);
+
+  switch (MI->getOpcode()) {
   case PPC::COPY: {
-    Register SrcReg = MI.getOperand(1).getReg();
+    Register SrcReg = MI->getOperand(1).getReg();
 
     // In both ELFv1 and v2 ABI, method parameters and the return value
     // are sign- or zero-extended.
-    if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
-      const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
-      // We check the ZExt/SExt flags for a method parameter.
-      if (MI.getParent()->getBasicBlock() ==
-          &MF->getFunction().getEntryBlock()) {
-        Register VReg = MI.getOperand(0).getReg();
-        if (MF->getRegInfo().isLiveIn(VReg))
-          return SignExt ? FuncInfo->isLiveInSExt(VReg) :
-                           FuncInfo->isLiveInZExt(VReg);
-      }
+    const MachineFunction *MF = MI->getMF();
+
+    if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
+      // If this is a copy from another register, we recursively check source.
+      auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+      return std::pair<bool, bool>(SrcExt.first || IsSExt,
+                                   SrcExt.second || IsZExt);
+    }
+
+    // From here on everything is SVR4ABI
+    if (MI->getParent()->getBasicBlock() ==
+      Register VReg = MI->getOperand(0).getReg();
+      if (MF->getRegInfo().isLiveIn(VReg)) {
+        IsSExt |= FuncInfo->isLiveInSExt(VReg);
+        IsZExt |= FuncInfo->isLiveInZExt(VReg);
+        return std::pair<bool, bool>(IsSExt, IsZExt);
+      }
+    }
+
+    if (SrcReg != PPC::X3) {
+      // If this is a copy from another register, we recursively check source.
+      auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+      return std::pair<bool, bool>(SrcExt.first || IsSExt,
+                                   SrcExt.second || IsZExt);
 
-      // For a method return value, we check the ZExt/SExt flags in attribute.
-      // We assume the following code sequence for method call.
-      //   ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
-      //   BL8_NOP @func,...
-      //   ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
-      //   %5 = COPY %x3; G8RC:%5
-      if (SrcReg == PPC::X3) {
-        const MachineBasicBlock *MBB = MI.getParent();
-        MachineBasicBlock::const_instr_iterator II =
-          MachineBasicBlock::const_instr_iterator(&MI);
-        if (II != MBB->instr_begin() &&
-            (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
-          const MachineInstr &CallMI = *(--II);
-          if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
-            const Function *CalleeFn =
-              dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
-            if (!CalleeFn)
-              return false;
-            const IntegerType *IntTy =
-              dyn_cast<IntegerType>(CalleeFn->getReturnType());
-            const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
-            if (IntTy && IntTy->getBitWidth() <= 32)
-              return Attrs.hasAttribute(SignExt ? Attribute::SExt :
-                                                  Attribute::ZExt);
-          }
-        }
-      }
-    }
-
-    // If this is a copy from another register, we recursively check source.
-    if (!Register::isVirtualRegister(SrcReg))
-      return false;
-    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-    if (SrcMI != nullptr)
-      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
+    const MachineBasicBlock *MBB = MI->getParent();
+    std::pair<bool, bool> IsExtendPair = std::pair<bool, bool>(IsSExt, IsZExt);
+        MachineBasicBlock::const_instr_iterator(MI);
+    if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP)
+      return IsExtendPair;
+
+    if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
+      return IsExtendPair;
+
+        dyn_cast_if_present<Function>(CallMI.getOperand(0).getGlobal());
+      return IsExtendPair;
+    const IntegerType *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
+    if (IntTy && IntTy->getBitWidth() <= 32) {
+      IsSExt |= Attrs.hasAttribute(Attribute::SExt);
+      IsZExt |= Attrs.hasAttribute(Attribute::ZExt);
+      return std::pair<bool, bool>(IsSExt, IsZExt);
 
-    return false;
+    return IsExtendPair;
   }
 
-  case PPC::ANDI_rec:
-  case PPC::ANDIS_rec:
+  // OR, XOR with 16-bit immediate does not change the upper 48 bits.
+  // So, we track the operand register as we do for register copy.
   case PPC::ORI:
-  case PPC::ORIS:
   case PPC::XORI:
-  case PPC::XORIS:
-  case PPC::ANDI8_rec:
-  case PPC::ANDIS8_rec:
   case PPC::ORI8:
+  case PPC::XORI8: {
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+    return std::pair<bool, bool>(SrcExt.first || IsSExt,
+                                 SrcExt.second || IsZExt);
+  }
+
+  // OR, XOR with shifted 16-bit immediate does not change the upper
+  // 32 bits. So, we track the operand register for zero extension.
+  // For sign extension when the MSB of the immediate is zero, we also
+  // track the operand register since the upper 33 bits are unchanged.
+  case PPC::ORIS:
+  case PPC::XORIS:
   case PPC::ORIS8:
-  case PPC::XORI8:
   case PPC::XORIS8: {
-    // logical operation with 16-bit immediate does not change the upper bits.
-    // So, we track the operand register as we do for register copy.
-    Register SrcReg = MI.getOperand(1).getReg();
-    if (!Register::isVirtualRegister(SrcReg))
-      return false;
-    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-    if (SrcMI != nullptr)
-      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
-    return false;
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+    uint16_t Imm = MI->getOperand(2).getImm();
+    if (Imm & 0x8000)
+      return std::pair<bool, bool>(false, SrcExt.second || IsZExt);
+    else
+      return std::pair<bool, bool>(SrcExt.first || IsSExt,
+                                   SrcExt.second || IsZExt);
   }
 
   // If all incoming values are sign-/zero-extended,
   // the output of OR, ISEL or PHI is also sign-/zero-extended.
   case PPC::OR:
   case PPC::OR8:
   case PPC::ISEL:
   case PPC::PHI: {
-    if (Depth >= MAX_DEPTH)
-      return false;
+    if (BinOpDepth >= MAX_BINOP_DEPTH)
+      return std::pair<bool, bool>(false, false);
 
     // The input registers for PHI are operand 1, 3, ...
     // The input registers for others are operand 1 and 2.
-    unsigned E = 3, D = 1;
-    if (MI.getOpcode() == PPC::PHI) {
-      E = MI.getNumOperands();
-      D = 2;
-    }
-
-    for (unsigned I = 1; I != E; I += D) {
-      if (MI.getOperand(I).isReg()) {
-        Register SrcReg = MI.getOperand(I).getReg();
-        if (!Register::isVirtualRegister(SrcReg))
-          return false;
-        const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-        if (SrcMI == nullptr ||
-            !isSignOrZeroExtended(*SrcMI, SignExt, Depth + 1))
-          return false;
-      }
-      else
-        return false;
-    }
-    return true;
+    unsigned OperandEnd = 3, OperandStride = 1;
+    if (MI->getOpcode() == PPC::PHI) {
+      OperandEnd = MI->getNumOperands();
+      OperandStride = 2;
+    }
+
+    IsSExt = true;
+    IsZExt = true;
+    for (unsigned I = 1; I != OperandEnd; I += OperandStride) {
+      if (!MI->getOperand(I).isReg())
+        return std::pair<bool, bool>(false, false);
+
+      unsigned SrcReg = MI->getOperand(I).getReg();
+      auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth + 1, MRI);
+      IsSExt &= SrcExt.first;
+      IsZExt &= SrcExt.second;
+    return std::pair<bool, bool>(IsSExt, IsZExt);
   }
 
   // If at least one of the incoming values of an AND is zero extended
   // then the output is also zero-extended. If both of the incoming values
   // are sign-extended then the output is also sign extended.
   case PPC::AND:
   case PPC::AND8: {
-    if (Depth >= MAX_DEPTH)
-       return false;
-
-    assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
-
-    Register SrcReg1 = MI.getOperand(1).getReg();
-    Register SrcReg2 = MI.getOperand(2).getReg();
-
-    if (!Register::isVirtualRegister(SrcReg1) ||
-        !Register::isVirtualRegister(SrcReg2))
-      return false;
+    if (BinOpDepth >= MAX_BINOP_DEPTH)
+      return std::pair<bool, bool>(false, false);
 
-    const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
-    const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
-    if (!MISrc1 || !MISrc2)
-        return false;
-
-    if(SignExt)
-        return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
-               isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
-    else
-        return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
-               isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+    unsigned SrcReg1 = MI->getOperand(1).getReg();
+    unsigned SrcReg2 = MI->getOperand(2).getReg();
+    auto Src1Ext = isSignOrZeroExtended(SrcReg1, BinOpDepth + 1, MRI);
+    auto Src2Ext = isSignOrZeroExtended(SrcReg2, BinOpDepth + 1, MRI);
+    return std::pair<bool, bool>(Src1Ext.first && Src2Ext.first,
+                                 Src1Ext.second || Src2Ext.second);
   }
 
   default:
     break;
   }
-  return false;
+  return std::pair<bool, bool>(IsSExt, IsZExt);
 }
 
 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
   return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));
 }
 
 namespace {
 class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //
 
 // Unindexed (r+i) Loads.
 let PPC970_Unit = 2 in {
 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
                   "lbz $rD, $src", IIC_LdStLoad,
-                  [(set i32:$rD, (zextloadi8 DForm:$src))]>;
+                  [(set i32:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64,
+                  SExt32To64;
 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
                   "lha $rD, $src", IIC_LdStLHA,
                   [(set i32:$rD, (sextloadi16 DForm:$src))]>,
-                  PPC970_DGroup_Cracked;
+                  PPC970_DGroup_Cracked, SExt32To64;
 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
                   "lhz $rD, $src", IIC_LdStLoad,
-                  [(set i32:$rD, (zextloadi16 DForm:$src))]>;
+                  [(set i32:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64,
+                  SExt32To64;
 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
                   "lwz $rD, $src", IIC_LdStLoad,
-                  [(set i32:$rD, (load DForm:$src))]>;
+                  [(set i32:$rD, (load DForm:$src))]>, ZExt32To64;
 
 let Predicates = [HasFPU] in {
 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
                   "lfs $rD, $src", IIC_LdStLFD,
                   [(set f32:$rD, (load DForm:$src))]>;
 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
                   "lfd $rD, $src", IIC_LdStLFD,
                   [(set f64:$rD, (load DForm:$src))]>;

 }
 }
 
 // Indexed (r+r) Loads.
 //
 let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
 def LBZX : XForm_1_memOp<31,  87, (outs gprc:$rD), (ins memrr:$src),
                    "lbzx $rD, $src", IIC_LdStLoad,
-                   [(set i32:$rD, (zextloadi8 XForm:$src))]>;
+                   [(set i32:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64,
+                   SExt32To64;
 def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src),
                    "lhax $rD, $src", IIC_LdStLHA,
                    [(set i32:$rD, (sextloadi16 XForm:$src))]>,
-                   PPC970_DGroup_Cracked;
+                   PPC970_DGroup_Cracked, SExt32To64;
 def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src),
                    "lhzx $rD, $src", IIC_LdStLoad,
-                   [(set i32:$rD, (zextloadi16 XForm:$src))]>;
+                   [(set i32:$rD, (zextloadi16 XForm:$src))]>, ZExt32To64,
+                   SExt32To64;
 def LWZX : XForm_1_memOp<31,  23, (outs gprc:$rD), (ins memrr:$src),
                    "lwzx $rD, $src", IIC_LdStLoad,
-                   [(set i32:$rD, (load XForm:$src))]>;
+                   [(set i32:$rD, (load XForm:$src))]>, ZExt32To64;
 def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src),
                    "lhbrx $rD, $src", IIC_LdStLoad,
-                   [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>;
+                   [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>, ZExt32To64;
 def LWBRX : XForm_1_memOp<31,  534, (outs gprc:$rD), (ins memrr:$src),
                    "lwbrx $rD, $src", IIC_LdStLoad,
-                   [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>;
+                   [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>, ZExt32To64;
 
 let Predicates = [HasFPU] in {
 def LFSX   : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src),
                       "lfsx $frD, $src", IIC_LdStLFD,
                       [(set f32:$frD, (load XForm:$src))]>;
 def LFDX   : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src),
                       "lfdx $frD, $src", IIC_LdStLFD,
                       [(set f64:$frD, (load XForm:$src))]>;

 let Defs = [CARRY] in
 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
                      "subfic $rD, $rA, $imm", IIC_IntGeneral,
                      [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
   def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
                        "li $rD, $imm", IIC_IntSimple,
-                       [(set i32:$rD, imm32SExt16:$imm)]>;
+                       [(set i32:$rD, imm32SExt16:$imm)]>, SExt32To64;
   def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
                        "lis $rD, $imm", IIC_IntSimple,
-                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
+                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64;
 }
 }
 
 def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;
 def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
 def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andi. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
-                    isRecordForm;
+                    isRecordForm, ZExt32To64, SExt32To64;
 def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
-                    isRecordForm;
+                    isRecordForm, ZExt32To64;
 }
 def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "ori $dst, $src1, $src2", IIC_IntSimple,
                     [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
 def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "oris $dst, $src1, $src2", IIC_IntSimple,
                     [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
 def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                      "eqv", "$rA, $rS, $rB", IIC_IntSimple,
                      [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
 defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                      "xor", "$rA, $rS, $rB", IIC_IntSimple,
                      [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
 } // isCommutable
 defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                      "slw", "$rA, $rS, $rB", IIC_IntGeneral,
-                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
+                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>, ZExt32To64;
 defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                      "srw", "$rA, $rS, $rB", IIC_IntGeneral,
-                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
+                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>, ZExt32To64;
 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                       "sraw", "$rA, $rS, $rB", IIC_IntShift,
-                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
+                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>, SExt32To64;
 }
 
 def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
 def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;
 
 def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
 def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;
 
 def : InstAlias<"nop", (ORI R0, R0, 0)>;
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 let hasSideEffects = 0 in {
 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
                         "srawi", "$rA, $rS, $SH", IIC_IntShift,
-                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
+                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>,
+                        SExt32To64;
 defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
                         "cntlzw", "$rA, $rS", IIC_IntGeneral,
-                        [(set i32:$rA, (ctlz i32:$rS))]>;
+                        [(set i32:$rA, (ctlz i32:$rS))]>, ZExt32To64;
 defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
                         "cnttzw", "$rA, $rS", IIC_IntGeneral,
-                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
+                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>,
+                        ZExt32To64;
 defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
                         "extsb", "$rA, $rS", IIC_IntSimple,
-                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
+                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>, SExt32To64;
 defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
                         "extsh", "$rA, $rS", IIC_IntSimple,
-                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
+                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>, SExt32To64;
 
 let isCommutable = 1 in
 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                    "cmpb $rA, $rS, $rB", IIC_IntGeneral,
                    [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
 }
 let isCompare = 1, hasSideEffects = 0 in {
   def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),

 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm",
                           (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 
 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
-                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
+                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,
+                          ZExt32To64;
 def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
-                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
+                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,
+                           ZExt32To64;
 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
-                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
 def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
-                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
-                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
 def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n",
-                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
-                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
 def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n",
-                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;

 
 // Message Synchronize
 def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
 
 // Power-Saving Mode Instruction:
 def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
 
 def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
-                       "setb $RT, $BFA", IIC_IntGeneral>;
+                       "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64;
 } // IsISA3_0
 
 let Predicates = [IsISA3_0] in {
 def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)),
           (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>;
 }
 def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)),
           (i32 (MULHW $a, $b))>;

llvm/lib/Target/PowerPC/PPCInstrP10.td

def XXSPLTI32DX :
                              [(set v2i64:$XT,
                                    (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
                                                    i32:$IMM32))]>,
                              RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
 }
 
 let Predicates = [IsISA3_1] in {
   def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
-                            "setbc $RT, $BI", IIC_IntCompare, []>;
+                            "setbc $RT, $BI", IIC_IntCompare, []>,
+                            SExt32To64, ZExt32To64;
   def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
-                             "setbcr $RT, $BI", IIC_IntCompare, []>;
+                             "setbcr $RT, $BI", IIC_IntCompare, []>,
+                             SExt32To64, ZExt32To64;
   def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
-                             "setnbc $RT, $BI", IIC_IntCompare, []>;
+                             "setnbc $RT, $BI", IIC_IntCompare, []>,
+                             SExt32To64;
   def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
-                              "setnbcr $RT, $BI", IIC_IntCompare, []>;
+                              "setnbcr $RT, $BI", IIC_IntCompare, []>,
+                              SExt32To64;
 
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
-                               "setbc $RT, $BI", IIC_IntCompare, []>;
+                               "setbc $RT, $BI", IIC_IntCompare, []>,
+                               SExt32To64, ZExt32To64;
     def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
-                                "setbcr $RT, $BI", IIC_IntCompare, []>;
+                                "setbcr $RT, $BI", IIC_IntCompare, []>,
+                                SExt32To64, ZExt32To64;
     def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
-                                "setnbc $RT, $BI", IIC_IntCompare, []>;
+                                "setnbc $RT, $BI", IIC_IntCompare, []>,
+                                SExt32To64;
     def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
-                                 "setnbcr $RT, $BI", IIC_IntCompare, []>;
+                                 "setnbcr $RT, $BI", IIC_IntCompare, []>,
+                                 SExt32To64;
   }
 
   def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
                                 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
                                 "vsldbi $VRT, $VRA, $VRB, $SH",
                                 IIC_VecGeneral,
                                 [(set v16i8:$VRT,
                                       (int_ppc_altivec_vsldbi v16i8:$VRA,
def VINSDRX :
     VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
              "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
               [(set v2i64:$vD,
                     (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
               RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
   def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextractbm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
-                                      (int_ppc_altivec_vextractbm v16i8:$vB))]>;
+                                      (int_ppc_altivec_vextractbm v16i8:$vB))]>,
+                                      ZExt32To64;
   def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextracthm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
-                                      (int_ppc_altivec_vextracthm v8i16:$vB))]>;
+                                      (int_ppc_altivec_vextracthm v8i16:$vB))]>,
+                                      ZExt32To64;
   def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextractwm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
-                                      (int_ppc_altivec_vextractwm v4i32:$vB))]>;
+                                      (int_ppc_altivec_vextractwm v4i32:$vB))]>,
+                                      ZExt32To64;
   def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextractdm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
-                                      (int_ppc_altivec_vextractdm v2i64:$vB))]>;
+                                      (int_ppc_altivec_vextractdm v2i64:$vB))]>,
+                                      ZExt32To64;
   def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextractqm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
                                       (int_ppc_altivec_vextractqm v1i128:$vB))]>;
   def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
                                      "vexpandbm $vD, $vB", IIC_VecGeneral,
                                      [(set v16i8:$vD, (int_ppc_altivec_vexpandbm
                                            v16i8:$vB))]>;

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Predicates = [HasVSX, HasP8Vector] in {
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let isCodeGenOnly = 1, hasSideEffects = 1 in
   def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
                              "mfvsrd $rA, $XT", IIC_VecGeneral,
                              []>,
       Requires<[In64BitMode]>;
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
-                               [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
+                               [(set i32:$rA, (PPCmfvsr f64:$XT))]>, ZExt32To64;
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let isCodeGenOnly = 1, hasSideEffects = 1 in
   def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                []>;
   def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
                               "mtvsrd $XT, $rA", IIC_VecGeneral,
                               [(set f64:$XT, (PPCmtvsra i64:$rA))]>,

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

 
 static cl::opt<bool>
 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
               cl::desc("Convert eligible reg+reg instructions to reg+imm"));
 
 static cl::opt<bool>
     EnableSExtElimination("ppc-eliminate-signext",
                           cl::desc("enable elimination of sign-extensions"),
-                          cl::init(false), cl::Hidden);
+                          cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableZExtElimination("ppc-eliminate-zeroext",
                           cl::desc("enable elimination of zero-extensions"),
-                          cl::init(false), cl::Hidden);
+                          cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableTrapOptimization("ppc-opt-conditional-trap",
                            cl::desc("enable optimization of conditional traps"),
                            cl::init(false), cl::Hidden);
 
 namespace {
 
static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
   if (!Register::isVirtualRegister(Reg))
     return nullptr;
 
   return MRI->getVRegDef(Reg);
 }
 
 // This function returns number of known zero bits in output of MI
 // starting from the most significant bit.
-static unsigned
-getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
+static unsigned getKnownLeadingZeroCount(const unsigned Reg,
+                                         const PPCInstrInfo *TII,
+                                         const MachineRegisterInfo *MRI) {
+  MachineInstr *MI = MRI->getVRegDef(Reg);
   unsigned Opcode = MI->getOpcode();
   if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
       Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
     return MI->getOperand(3).getImm();
 
   if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
       MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
     return MI->getOperand(3).getImm();
if (Opcode == PPC::LHZ   || Opcode == PPC::LHZX  ||
     return 48;
 
   if (Opcode == PPC::LBZ   || Opcode == PPC::LBZX  ||
       Opcode == PPC::LBZ8  || Opcode == PPC::LBZX8 ||
       Opcode == PPC::LBZU  || Opcode == PPC::LBZUX ||
       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
     return 56;
 
-  if (TII->isZeroExtended(*MI))
+  if (TII->isZeroExtended(Reg, MRI))
     return 32;
 
   return 0;
 }
 
 // This function maintains a map for the pairs <TOC Save Instr, Keep>
 // Each time a new TOC save is encountered, it checks if any of the existing
 // ones are dominated by the new one. If so, it marks the existing one as
for (MachineInstr &MI : MBB) {
 
         MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
         // If we've used a zero-extending load that we will sign-extend,
         // just do a sign-extending load.
         if (SrcMI->getOpcode() == PPC::LHZ ||
             SrcMI->getOpcode() == PPC::LHZX) {
           if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
             break;
-          auto is64Bit = [] (unsigned Opcode) {
-            return Opcode == PPC::EXTSH8;
+          auto is64Bit = [](unsigned Opcode) {
+            return Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSH8_32_64;
           };
           auto isXForm = [] (unsigned Opcode) {
             return Opcode == PPC::LHZX;
           };
           auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
             if (is64Bit)
               if (isXForm) return PPC::LHAX8;
               else         return PPC::LHA8;
             else
               if (isXForm) return PPC::LHAX;
               else         return PPC::LHA;
           };
           unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
                                        isXForm(SrcMI->getOpcode()));
+
           LLVM_DEBUG(dbgs() << "Zero-extending load\n");
           LLVM_DEBUG(SrcMI->dump());
           LLVM_DEBUG(dbgs() << "and sign-extension\n");
           LLVM_DEBUG(MI.dump());
           LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
           SrcMI->setDesc(TII->get(Opc));
           SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           ToErase = &MI;
           Simplified = true;
           NumEliminatedSExt++;
         }
         break;
for (MachineInstr &MI : MBB) {
           auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
             if (is64Bit)
               if (isXForm) return PPC::LWAX;
               else         return PPC::LWA;
             else
               if (isXForm) return PPC::LWAX_32;
               else         return PPC::LWA_32;
           };
+
+          // The transformation from a zero-extending load to a sign-extending
+          // load is only legal when the displacement is a multiple of 4.
+          // If the displacement is not at least 4 byte aligned, don't perform
+          // the transformation.
+          bool IsWordAligned = false;
+          if (SrcMI->getOperand(1).isGlobal()) {
+            const GlobalObject *GO =
+                dyn_cast<GlobalObject>(SrcMI->getOperand(1).getGlobal());
+            if (GO && GO->getAlignment() >= 4)
+              IsWordAligned = true;
+          } else if (SrcMI->getOperand(1).isImm()) {
+            int64_t Value = SrcMI->getOperand(1).getImm();
+            if (Value % 4 == 0)
+              IsWordAligned = true;
+          }
+
           unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
                                        isXForm(SrcMI->getOpcode()));
+
+          if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
+            break;
+
           LLVM_DEBUG(dbgs() << "Zero-extending load\n");
           LLVM_DEBUG(SrcMI->dump());
           LLVM_DEBUG(dbgs() << "and sign-extension\n");
           LLVM_DEBUG(MI.dump());
           LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
           SrcMI->setDesc(TII->get(Opc));
           SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           ToErase = &MI;
           Simplified = true;
           NumEliminatedSExt++;
         } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
-                   TII->isSignExtended(*SrcMI)) {
+                   TII->isSignExtended(NarrowReg, MRI)) {
           // We can eliminate EXTSW if the input is known to be already
           // sign-extended.
           LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
           Register TmpReg =
               MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
                   TmpReg);
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
for (MachineInstr &MI : MBB) {
         if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
 
         SrcMI = SubRegMI;
         if (SubRegMI->getOpcode() == PPC::COPY) {
           Register CopyReg = SubRegMI->getOperand(1).getReg();
           if (Register::isVirtualRegister(CopyReg))
             SrcMI = MRI->getVRegDef(CopyReg);
         }
+        if (!SrcMI->getOperand(0).isReg())
+          break;
 
-        unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
+        unsigned KnownZeroCount =
+            getKnownLeadingZeroCount(SrcMI->getOperand(0).getReg(), TII, MRI);
         if (MI.getOperand(3).getImm() <= KnownZeroCount) {
           LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .addReg(SrcReg);
           ToErase = &MI;
           Simplified = true;
           NumEliminatedZExt++;

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 ; ASM32PWR4-DAG:   lwz [[REG5:[0-9]+]], 72(1)
 ; ASM32PWR4-DAG:   lwz [[REG6:[0-9]+]], 76(1)
 ; ASM32PWR4-DAG:   lwz [[REG7:[0-9]+]], 80(1)
 ; ASM32PWR4-DAG:   lwz [[REG8:[0-9]+]], 84(1)
 ; ASM32PWR4-DAG:   lwz [[REG9:[0-9]+]], 88(1)
 ; ASM32PWR4-DAG:   lwz [[REG10:[0-9]+]], 92(1)
 
 ; ASM64PWR4-DAG:   ld [[REG1:[0-9]+]], 112(1)
-; ASM64PWR4-DAG:   lwz [[REG2:[0-9]+]], 124(1)
+; ASM64PWR4-DAG:   lwa [[REG2:[0-9]+]], 124(1)
 ; ASM64PWR4-DAG:   lwz [[REG3:[0-9]+]], 132(1)
 ; ASM64PWR4-DAG:   lwz [[REG4:[0-9]+]], 140(1)
 ; ASM64PWR4-DAG:   lwa [[REG5:[0-9]+]], 148(1)
 ; ASM64PWR4-DAG:   ld [[REG6:[0-9]+]], 152(1)
 ; ASM64PWR4-DAG:   lwz [[REG7:[0-9]+]], 164(1)
 ; ASM64PWR4-DAG:   lwa [[REG8:[0-9]+]], 172(1)
 
 @ll1 = common global i64 0, align 8

llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll

 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_0_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_align16_int16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_align32_int16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_align64_int16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_reg_int16_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_or_int16_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i16
   ret i16 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_not_disjoint16_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_disjoint_align16_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_not_disjoint32_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_not_disjoint64_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_disjoint_align64_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_cst_align16_int16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_cst_align32_int16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_cst_align64_int16_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align16_uint16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align32_uint16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align64_uint16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_reg_uint16_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_or_uint16_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i16
   ret i16 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align16_uint16_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align32_uint16_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plhz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align64_uint16_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_reg_uint16_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_or_uint16_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   ret i16 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   ret i16 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   ret i16 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_uint32_t(i64 %ptr) {

llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll

 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_0_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align16_int32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align32_int32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align64_int32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_reg_int32_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_or_int32_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint16_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align16_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint32_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint64_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align64_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align16_int32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align32_int32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align64_int32_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_0_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align16_int32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align32_int32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plhz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align64_int32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_reg_int32_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_or_int32_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint16_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align16_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint32_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint64_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align64_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align16_int32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align32_int32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align64_int32_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_0_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align16_int32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 8(r3)
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align32_int32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plwz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    extsw r3, r3
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align64_int32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_reg_int32_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_or_int32_t_uint32_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint16_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align16_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 24(r3)
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 8
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint32_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align32_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plwz r3, 999990000(r3), 0
 ; CHECK-P10-NEXT:    extsw r3, r3
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint32_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    extsw r3, r3
+; CHECK-P9-NEXT:    lwax r3, r3, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint32_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    extsw r3, r3
+; CHECK-P8-NEXT:    lwax r3, r3, r4
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 16
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint64_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align64_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4096
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align16_int32_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 4080(0)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
   ret i32 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align32_int32_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align32_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, -27108(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
   ret i32 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align64_int32_t_uint32_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
   ret i32 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_0_int32_t_uint64_t(i64 %ptr) {
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plhz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_int16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 8(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_int16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_int16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plhz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    extsh r3, r3
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_int16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lhax r3, r3, r4
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_int16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_int16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lhax r3, r3, r4
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_int16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lhax r3, r3, r4
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_int16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lhax r3, r3, r4
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_int16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = sext i16 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 24(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv

 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_int16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    extsh r3, r3
+; CHECK-P9-NEXT:    lhax r3, r3, r4
 ; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_int16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    extsh r3, r3
+; CHECK-P8-NEXT:    lhax r3, r3, r4
 ; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_int16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lha r3, 0(r3)
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_int16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lha r3, 0(r3)
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_int16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lhax r3, r3, r4
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_int16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lhax r3, r3, r4
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = sext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_int16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 4080(0)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_int16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, -27108(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_int16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_int16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lha r3, 0(r3)
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_int16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lha r3, 0(r3)
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plwz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_uint32_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 8
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 16
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4096
   ret i32 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
   ret i32 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
   ret i32 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint32_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
   ret i32 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_uint64_t(i64 %ptr) {

llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll

 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_int64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_int64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_int64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_int64_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_int64_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_int64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_int64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_int64_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_int64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_int64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plhz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_int64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_int64_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_int64_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_int64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_int64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_int64_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_int64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_int64_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_int64_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plwz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_int64_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_int64_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_int64_t_uint32_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv1 = zext i32 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_int64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_int64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 8
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_int64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint32_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint32_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 16
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_int64_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_int64_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4096
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_int64_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_int64_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align32_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_int64_t_uint32_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_int64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_int64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 8(r3)
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_int64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plwz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    extsw r3, r3
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_int64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_int64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_int64_t_int32_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv1 = sext i32 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_int64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_int64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 24(r3)
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 8
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_int64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }

 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_int32_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    extsw r3, r3
+; CHECK-P9-NEXT:    lwax r3, r3, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_int32_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    extsw r3, r3
+; CHECK-P8-NEXT:    lwax r3, r3, r4
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 16
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_int64_t_int32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_int64_t_int32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4096
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_int64_t_int32_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 4080(0)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_int64_t_int32_t() {
 ; CHECK-LABEL: ld_cst_align32_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, -27108(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_int64_t_int32_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_uint64_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_uint64_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_uint64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_uint64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_uint64_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_uint64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_uint64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plhz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_uint64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_uint64_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_uint64_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_uint64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_uint64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_uint64_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_uint64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_uint64_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_uint64_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plwz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_uint64_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_uint64_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_uint64_t_uint32_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv1 = zext i32 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_uint64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_uint64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 8
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_uint64_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint32_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint32_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 16
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_uint64_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_uint64_t_uint32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4096
   %conv = zext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_uint64_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_uint64_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align32_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_uint64_t_uint32_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_uint32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_uint64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 8(r3)
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_uint64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plwz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    extsw r3, r3
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_uint64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_uint64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_uint64_t_int32_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv1 = sext i32 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 24(r3)
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 8
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }

 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_int32_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    extsw r3, r3
+; CHECK-P9-NEXT:    lwax r3, r3, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_int32_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    extsw r3, r3
+; CHECK-P8-NEXT:    lwax r3, r3, r4
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 16
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i32*
   %1 = load atomic i32, i32* %0 monotonic, align 4096
   %conv = sext i32 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_uint64_t_int32_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 4080(0)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_uint64_t_int32_t() {
 ; CHECK-LABEL: ld_cst_align32_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, -27108(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_uint64_t_int32_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_int32_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_int32_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn

llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll

entry:
   ret i8 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_0_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_align16_uint8_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_align32_uint8_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plbz r3, 99999000(r3), 0
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_align64_uint8_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_reg_uint8_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_or_uint8_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 

 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align16_uint8_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align32_uint8_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align64_uint8_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_0_uint8_t_uint16_t(i64 %ptr) {

llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-P9
 
 define dso_local i64 @test_invalid(<16 x i8> %a) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_invalid:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v2, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+un
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_invalid:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v2, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %a) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local <16 x i8> @test_add(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_unnamed_addr #0 {
entry:
   ret <16 x i8> %0
 }
 
 define dso_local i64 @test_add_ofl(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_add_ofl:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdadd. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+un
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_add_ofl:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdadd. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdadd.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local <16 x i8> @test_sub(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_unnamed_addr #0 {
entry:
   ret <16 x i8> %0
 }
 
 define dso_local i64 @test_sub_ofl(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_sub_ofl:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+un
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_sub_ofl:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local i64 @test_cmplt(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_cmplt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+lt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmplt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 25, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 2, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local i64 @test_cmpgt(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_cmpgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+gt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmpgt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 26, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 4, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local i64 @test_cmpeq(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_cmpeq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+eq
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmpeq:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 27, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 0, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local i64 @test_cmpge(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_cmpge:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbcr r3, 4*cr6+lt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmpge:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 25, 31, 31
 ; CHECK-P9-NEXT:    xori r3, r3, 1
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 3, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 define dso_local i64 @test_cmple(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_cmple:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbcr r3, 4*cr6+gt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmple:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 26, 31, 31
 ; CHECK-P9-NEXT:    xori r3, r3, 1
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 5, <16 x i8> %a, <16 x i8> %b) #2
   %conv.i = sext i32 %0 to i64
   ret i64 %conv.i
 }
 
 declare i32 @llvm.ppc.bcdsub.p(i32 immarg, <16 x i8>, <16 x i8>) #1
 declare i32 @llvm.ppc.bcdadd.p(i32 immarg, <16 x i8>, <16 x i8>) #1
 declare <16 x i8> @llvm.ppc.bcdadd(<16 x i8>, <16 x i8>, i32 immarg) #1
 declare <16 x i8> @llvm.ppc.bcdsub(<16 x i8>, <16 x i8>, i32 immarg) #1

llvm/test/CodeGen/PowerPC/csr-split.ll

 ; CHECK-PWR9-NEXT:    bne cr0, .LBB1_3
 ; CHECK-PWR9-NEXT:  # %bb.2: # %if.then2
 ; CHECK-PWR9-NEXT:    bl callVoid
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    mr r3, r30
 ; CHECK-PWR9-NEXT:    bl callNonVoid
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:  .LBB1_3: # %return
-; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    addi r1, r1, 48
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 ;
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry

 ; CHECK-NEXT:  # %bb.2: # %if.then2
 ; CHECK-NEXT:    bl callVoid
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    mr r3, r30
 ; CHECK-NEXT:    bl callNonVoid
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB1_3: # %return
 ; CHECK-NEXT:    ld r30, 112(r1) # 8-byte Folded Reload
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    addi r1, r1, 128
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 entry:
   %tobool = icmp eq i32* %p1, null
   br i1 %tobool, label %return, label %if.end
 

 ; CHECK-PWR9-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
 ; CHECK-PWR9-NEXT:    stdu r1, -64(r1)
 ; CHECK-PWR9-NEXT:    ld r30, 0(r3)
 ; CHECK-PWR9-NEXT:    cmpldi r30, 0
 ; CHECK-PWR9-NEXT:    beq cr0, .LBB2_2
 ; CHECK-PWR9-NEXT:  # %bb.1: # %land.rhs
 ; CHECK-PWR9-NEXT:    mr r29, r3
-; CHECK-PWR9-NEXT:    clrldi r4, r4, 32
 ; CHECK-PWR9-NEXT:    mr r3, r30
 ; CHECK-PWR9-NEXT:    bl bar
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    std r3, 0(r29)
 ; CHECK-PWR9-NEXT:  .LBB2_2: # %land.end
 ; CHECK-PWR9-NEXT:    mr r3, r30
 ; CHECK-PWR9-NEXT:    addi r1, r1, 64
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)

 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld r30, 0(r3)
 ; CHECK-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    cmpldi r30, 0
 ; CHECK-NEXT:    beq cr0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %land.rhs
 ; CHECK-NEXT:    mr r29, r3
-; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    mr r3, r30
 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    std r3, 0(r29)
 ; CHECK-NEXT:  .LBB2_2: # %land.end
 ; CHECK-NEXT:    mr r3, r30
 ; CHECK-NEXT:    ld r30, 128(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r29, 120(r1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll

 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
 define void @foo(i32 zeroext %n, <256 x i1>* %ptr, <256 x i1>* %ptr2) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplwi r3, 0
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
-; CHECK-NEXT:    clrldi r6, r3, 32
-; CHECK-NEXT:    addi r3, r4, 64
-; CHECK-NEXT:    addi r4, r5, 64
-; CHECK-NEXT:    mtctr r6
+; CHECK-NEXT:    addi r4, r4, 64
+; CHECK-NEXT:    addi r5, r5, 64
+; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lxvp vsp34, -64(r3)
-; CHECK-NEXT:    lxvp vsp36, -32(r3)
-; CHECK-NEXT:    lxvp vsp32, 0(r3)
-; CHECK-NEXT:    lxvp vsp38, 32(r3)
-; CHECK-NEXT:    addi r3, r3, 1
-; CHECK-NEXT:    stxvp vsp34, -64(r4)
-; CHECK-NEXT:    stxvp vsp36, -32(r4)
-; CHECK-NEXT:    stxvp vsp32, 0(r4)
-; CHECK-NEXT:    stxvp vsp38, 32(r4)
+; CHECK-NEXT:    lxvp vsp34, -64(r4)
+; CHECK-NEXT:    lxvp vsp36, -32(r4)
+; CHECK-NEXT:    lxvp vsp32, 0(r4)
+; CHECK-NEXT:    lxvp vsp38, 32(r4)
 ; CHECK-NEXT:    addi r4, r4, 1
+; CHECK-NEXT:    stxvp vsp34, -64(r5)
+; CHECK-NEXT:    stxvp vsp36, -32(r5)
+; CHECK-NEXT:    stxvp vsp32, 0(r5)
+; CHECK-NEXT:    stxvp vsp38, 32(r5)
+; CHECK-NEXT:    addi r5, r5, 1
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  # %bb.3: # %for.cond.cleanup
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplwi r3, 0
 ; CHECK-BE-NEXT:    beqlr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %for.body.lr.ph
-; CHECK-BE-NEXT:    clrldi r6, r3, 32
-; CHECK-BE-NEXT:    addi r3, r4, 64
-; CHECK-BE-NEXT:    addi r4, r5, 64
-; CHECK-BE-NEXT:    mtctr r6
+; CHECK-BE-NEXT:    addi r4, r4, 64
+; CHECK-BE-NEXT:    addi r5, r5, 64
+; CHECK-BE-NEXT:    mtctr r3
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_2: # %for.body
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    lxvp vsp34, -64(r3)
-; CHECK-BE-NEXT:    lxvp vsp36, -32(r3)
-; CHECK-BE-NEXT:    lxvp vsp32, 0(r3)
-; CHECK-BE-NEXT:    lxvp vsp38, 32(r3)
-; CHECK-BE-NEXT:    addi r3, r3, 1
-; CHECK-BE-NEXT:    stxvp vsp34, -64(r4)
-; CHECK-BE-NEXT:    stxvp vsp36, -32(r4)
-; CHECK-BE-NEXT:    stxvp vsp32, 0(r4)
-; CHECK-BE-NEXT:    stxvp vsp38, 32(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, -64(r4)
+; CHECK-BE-NEXT:    lxvp vsp36, -32(r4)
+; CHECK-BE-NEXT:    lxvp vsp32, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp38, 32(r4)
 ; CHECK-BE-NEXT:    addi r4, r4, 1
+; CHECK-BE-NEXT:    stxvp vsp34, -64(r5)
+; CHECK-BE-NEXT:    stxvp vsp36, -32(r5)
+; CHECK-BE-NEXT:    stxvp vsp32, 0(r5)
+; CHECK-BE-NEXT:    stxvp vsp38, 32(r5)
+; CHECK-BE-NEXT:    addi r5, r5, 1
 ; CHECK-BE-NEXT:    bdnz .LBB0_2
 ; CHECK-BE-NEXT:  # %bb.3: # %for.cond.cleanup
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp35.not = icmp eq i32 %n, 0
   br i1 %cmp35.not, label %for.cond.cleanup, label %for.body.lr.ph
 
 for.body.lr.ph:

llvm/test/CodeGen/PowerPC/expand-isel.ll

 
 cleanup:
   %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
 ; CHECK: cmplwi r3, 0
 ; CHECK: li r3, 1
-; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
-; CHECK: clrldi r3, r3, 32
-; CHECK: blr
-; CHECK: [[TGT]]
+; CHECK: bnelr cr0
 ; CHECK: xor [[XOR:r[0-9]+]]
 ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
 ; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
 }
 
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/PowerPC/f128-conv.ll

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f1
 ; CHECK-P8-NEXT:    mr r30, r4
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    bl __floatunsikf
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f1
 ; CHECK-P8-NEXT:    mr r30, r4
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    bl __floatunsikf
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0

llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a)  {
 ; CHECK-LABEL: qpConv2uw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpuwz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lxv v3, 16(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpuwz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) {
 ; CHECK-LABEL: qpConv2uhw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uhw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lxv v3, 16(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uhw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) {
 ; CHECK-LABEL: qpConv2ub:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2ub:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lxv v3, 16(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2ub_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
 ; RUN:     -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
 ; RUN:     -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
 ; Function Attrs: nounwind
 define zeroext i8 @_Z6testcff(float %arg) {
 ; CHECK-LABEL: _Z6testcff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i8 @_Z6testcdd(double %arg) {
 ; CHECK-LABEL: _Z6testcdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i8 @_Z7testucff(float %arg) {
 ; CHECK-LABEL: _Z7testucff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i8 @_Z7testucdd(double %arg) {
 ; CHECK-LABEL: _Z7testucdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i16 @_Z7testusff(float %arg) {
 ; CHECK-LABEL: _Z7testusff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptoui float %0 to i16
   ret i16 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i16 @_Z7testusdd(double %arg) {
 ; CHECK-LABEL: _Z7testusdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptoui double %0 to i16
   ret i16 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i32 @_Z7testuiff(float %arg) {
 ; CHECK-LABEL: _Z7testuiff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptoui float %0 to i32
   ret i32 %conv
 }

 
 ; Function Attrs: nounwind
 define zeroext i32 @_Z7testuidd(double %arg) {
 ; CHECK-LABEL: _Z7testuidd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptoui double %0 to i32
   ret i32 %conv
 }

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: q_to_u32:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    xscvqpuwz v2, v2
 ; P9-NEXT:    mfvsrwz r3, v2
-; P9-NEXT:    clrldi r3, r3, 32
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: q_to_u32:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    .cfi_def_cfa_offset 32

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

entry:
   ret i64 %conv
 }
 
 define zeroext i32 @d_to_u32(double %m) #0 {
 ; CHECK-LABEL: d_to_u32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: d_to_u32:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    fctiwuz f0, f1
 ; NOVSX-NEXT:    addi r3, r1, -4
 ; NOVSX-NEXT:    stfiwx f0, 0, r3
 ; NOVSX-NEXT:    lwz r3, -4(r1)
entry:
   ret i64 %conv
 }
 
 define zeroext i32 @f_to_u32(float %m) #0 {
 ; CHECK-LABEL: f_to_u32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: f_to_u32:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    fctiwuz f0, f1
 ; NOVSX-NEXT:    addi r3, r1, -4
 ; NOVSX-NEXT:    stfiwx f0, 0, r3
 ; NOVSX-NEXT:    lwz r3, -4(r1)

llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
 ; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-32
 
 define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vcmpgtsw. 2, 2, 3
 ; CHECK-NEXT:    bge 6, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %land.rhs
 ; CHECK-NEXT:    vcmpgtsw. 2, 4, 3
 ; CHECK-NEXT:    mfocrf 3, 2
 ; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-64-LABEL: test:
 ; CHECK-AIX-64:       # %bb.0: # %entry
 ; CHECK-AIX-64-NEXT:    vcmpgtsw. 2, 2, 3
 ; CHECK-AIX-64-NEXT:    bge 6, L..BB0_2
 ; CHECK-AIX-64-NEXT:  # %bb.1: # %land.rhs
 ; CHECK-AIX-64-NEXT:    vcmpgtsw. 2, 4, 3
 ; CHECK-AIX-64-NEXT:    mfocrf 3, 2
 ; CHECK-AIX-64-NEXT:    rlwinm 3, 3, 25, 31, 31
-; CHECK-AIX-64-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-64-NEXT:    blr
 ; CHECK-AIX-64-NEXT:  L..BB0_2:
 ; CHECK-AIX-64-NEXT:    li 3, 0
 ; CHECK-AIX-64-NEXT:    blr
 ;
 ; CHECK-AIX-32-LABEL: test:
 ; CHECK-AIX-32:       # %bb.0: # %entry
 ; CHECK-AIX-32-NEXT:    vcmpgtsw. 2, 2, 3

llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll

 define i64 @foo(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r4, 1
 ; CHECK-NEXT:    blt cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    addi r6, r3, 5
 ; CHECK-NEXT:    addi r3, r4, -1
-; CHECK-NEXT:    extsw r5, r5
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_2: # %for.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    ld r4, 0(r6)

 ; }
 
 define zeroext i8 @foo1(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r4, 1
 ; CHECK-NEXT:    blt cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
-; CHECK-NEXT:    extsw r5, r5
 ; CHECK-NEXT:    sub r3, r3, r5
 ; CHECK-NEXT:    addi r6, r3, 1000
 ; CHECK-NEXT:    addi r3, r4, -1
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    .p2align 4

llvm/test/CodeGen/PowerPC/machine-pre.ll

 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    add r28, r3, r28
 ; CHECK-P9-NEXT:  .LBB1_3: # %sw.epilog
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    cmpwi r28, 1025
 ; CHECK-P9-NEXT:    bge cr0, .LBB1_7
 ; CHECK-P9-NEXT:  .LBB1_4: # %while.cond
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    extsw r3, r29
+; CHECK-P9-NEXT:    mr r3, r29
 ; CHECK-P9-NEXT:    bl bar
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    mr r29, r3
-; CHECK-P9-NEXT:    extsw r3, r30
+; CHECK-P9-NEXT:    mr r3, r30
 ; CHECK-P9-NEXT:    bl bar
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    mr r30, r3
 ; CHECK-P9-NEXT:    mulhw r3, r28, r27
 ; CHECK-P9-NEXT:    srwi r4, r3, 31
 ; CHECK-P9-NEXT:    add r3, r3, r4
 ; CHECK-P9-NEXT:    slwi r4, r3, 1
 ; CHECK-P9-NEXT:    add r3, r3, r4

llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

 ; CHECK-NEXT:    ld 6, 0(4)
 ; CHECK-NEXT:    cmpld 5, 6
 ; CHECK-NEXT:    bne 0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    ld 3, 8(3)
 ; CHECK-NEXT:    ld 4, 8(4)
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB1_3
+; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB1_2: # %res_block
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:  .LBB1_3: # %endblock
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
   %not.tobool = icmp ne i32 %call, 0
   %. = zext i1 %not.tobool to i32
   ret i32 %.
 }
 
 ; Check 7 bytes - requires 3 loads for each param.

 ; CHECK-NEXT:    lhz 6, 4(4)
 ; CHECK-NEXT:    cmplw 5, 6
 ; CHECK-NEXT:    bne 0, .LBB2_3
 ; CHECK-NEXT:  # %bb.2: # %loadbb2
 ; CHECK-NEXT:    lbz 3, 6(3)
 ; CHECK-NEXT:    lbz 4, 6(4)
 ; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB2_4
+; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB2_3: # %res_block
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:  .LBB2_4: # %endblock
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
   %not.lnot = icmp ne i32 %call, 0
   %cond = zext i1 %not.lnot to i32
   ret i32 %cond
 }
 
 ; Validate with > 0

llvm/test/CodeGen/PowerPC/optcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    iselgt 6, 3, 4
-; CHECK-NEXT:    sub 4, 3, 4
-; CHECK-NEXT:    extsw 3, 6
-; CHECK-NEXT:    stw 4, 0(5)
+; CHECK-NEXT:    sub 6, 3, 4
+; CHECK-NEXT:    iselgt 3, 3, 4
+; CHECK-NEXT:    stw 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foo:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    sub 6, 3, 4
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB0_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 6, 4, 0
-; CHECK-NO-ISEL-NEXT:    b .LBB0_3
+; CHECK-NO-ISEL-NEXT:    ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT:    b .LBB0_2
 ; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 6, 3, 0
-; CHECK-NO-ISEL-NEXT:  .LBB0_3: # %entry
-; CHECK-NO-ISEL-NEXT:    sub 4, 3, 4
-; CHECK-NO-ISEL-NEXT:    extsw 3, 6
-; CHECK-NO-ISEL-NEXT:    stw 4, 0(5)
+; CHECK-NO-ISEL-NEXT:    stw 6, 0(5)
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %sub = sub nsw i32 %a, %b
   store i32 %sub, i32* %c, align 4
   %cmp = icmp sgt i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 }

llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc0(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc0:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    clrldi r3, r3, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc0:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 0
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc1(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc1:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 1
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc2(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc2:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc2:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 2
   ret i8 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc3(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc3:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc3:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 3
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc4(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc4:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc4:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 4
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc5(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc5:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc5:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 5
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc6(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc6:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc6:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 6
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc7(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    clrldi r3, r3, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc7:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc7:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 7
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc8(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc8:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    clrldi r3, r3, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc8:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 8
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc9(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc9:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc9:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 9
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc10(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc10:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc10:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 10
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc11(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc11:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc11:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 11
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc12(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc12:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc12:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc12:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 12
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc13(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc13:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc13:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc13:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 13
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc14(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc14:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc14:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc14:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 14
   ret i8 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc15(<16 x i8> %vuc) {
 ; CHECK-LABEL: getuc15:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc15:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc15:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 15
   ret i8 %vecext
 
 
 }
 

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus0(<8 x i16> %vus) {
 ; CHECK-LABEL: getus0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus0:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    clrldi r3, r3, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus0:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 0
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus1(<8 x i16> %vus) {
 ; CHECK-LABEL: getus1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus1:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 1
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus2(<8 x i16> %vus) {
 ; CHECK-LABEL: getus2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus2:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus2:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 2
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus3(<8 x i16> %vus) {
 ; CHECK-LABEL: getus3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    clrldi r3, r3, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus3:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus3:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 3
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus4(<8 x i16> %vus) {
 ; CHECK-LABEL: getus4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus4:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    clrldi r3, r3, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus4:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 4
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus5(<8 x i16> %vus) {
 ; CHECK-LABEL: getus5:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus5:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 5
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus6(<8 x i16> %vus) {
 ; CHECK-LABEL: getus6:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus6:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 6
   ret i16 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus7(<8 x i16> %vus) {
 ; CHECK-LABEL: getus7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus7:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus7:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 7
   ret i16 %vecext
 
 
 }
 

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui0(<4 x i32> %vui) {
 ; CHECK-LABEL: getui0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui0:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui0:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxsldwi 0, 34, 34, 3
 ; CHECK-AIX-NEXT:    mffprwz 3, 0
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 0
   ret i32 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui1(<4 x i32> %vui) {
 ; CHECK-LABEL: getui1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui1:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrwz 3, 34
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 1
   ret i32 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui2(<4 x i32> %vui) {
 ; CHECK-LABEL: getui2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui2:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz r3, v2
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui2:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxsldwi 0, 34, 34, 1
 ; CHECK-AIX-NEXT:    mffprwz 3, 0
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 2
   ret i32 %vecext
 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui3(<4 x i32> %vui) {
 ; CHECK-LABEL: getui3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui3:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui3:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprwz 3, 0
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 3
   ret i32 %vecext
 
 
 }
 

llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll

for.body:                                         ; preds = %for.body.preheader, %for.cond
   br i1 %cmp1, label %for.cond, label %cleanup
 
 cleanup:                                          ; preds = %for.body, %for.cond, %entry
   %2 = phi i32 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ]
   ret i32 %2
 ; CHECK-LABEL: limit_loop
 ; CHECK: mtctr
 ; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: bdnz
+; CHECK: bdzlr
 ; CHECK: blr
 }
 
 

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

 ; i32/i16/i8 rather than i64 above
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setb27(i64 %a, i64 %b) {
 ; CHECK-LABEL: setb27:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpd r3, r4
 ; CHECK-NEXT:    setb r3, cr0
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setb27:
 ; CHECK-PWR8:       # %bb.0:
 ; CHECK-PWR8-NEXT:    xor r6, r4, r3
 ; CHECK-PWR8-NEXT:    li r5, -1
 ; CHECK-PWR8-NEXT:    addic r7, r6, -1
 ; CHECK-PWR8-NEXT:    cmpd r3, r4

 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setb28(i64 %a, i64 %b) {
 ; CHECK-LABEL: setb28:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpd r3, r4
 ; CHECK-NEXT:    setb r3, cr0
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setb28:
 ; CHECK-PWR8:       # %bb.0:
 ; CHECK-PWR8-NEXT:    xor r6, r4, r3
 ; CHECK-PWR8-NEXT:    li r5, -1
 ; CHECK-PWR8-NEXT:    addic r7, r6, -1
 ; CHECK-PWR8-NEXT:    cmpd r4, r3

 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbsc1:
 ; CHECK-PWR8:       # %bb.0:
 ; CHECK-PWR8-NEXT:    extsb r4, r4
 ; CHECK-PWR8-NEXT:    extsb r3, r3
 ; CHECK-PWR8-NEXT:    li r5, -1
-; CHECK-PWR8-NEXT:    extsw r4, r4
-; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    sub r6, r4, r3
 ; CHECK-PWR8-NEXT:    cmpw r3, r4
 ; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
 ; CHECK-PWR8-NEXT:    isellt r3, r5, r3
 ; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i8 %a, %b
   %t2 = icmp sgt i8 %a, %b
   %t3 = zext i1 %t2 to i64

 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbsc2:
 ; CHECK-PWR8:       # %bb.0:
 ; CHECK-PWR8-NEXT:    extsb r4, r4
 ; CHECK-PWR8-NEXT:    extsb r3, r3
 ; CHECK-PWR8-NEXT:    li r5, -1
-; CHECK-PWR8-NEXT:    extsw r4, r4
-; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    sub r6, r4, r3
 ; CHECK-PWR8-NEXT:    cmpw r4, r3
 ; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
 ; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
 ; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i8 %b, %a
   %t2 = icmp sgt i8 %a, %b
   %t3 = zext i1 %t2 to i64

 ;
 ; CHECK-PWR8-LABEL: setbsc3:
 ; CHECK-PWR8:       # %bb.0:
 ; CHECK-PWR8-NEXT:    slwi r4, r4, 28
 ; CHECK-PWR8-NEXT:    slwi r3, r3, 28
 ; CHECK-PWR8-NEXT:    li r5, -1
 ; CHECK-PWR8-NEXT:    srawi r4, r4, 28
 ; CHECK-PWR8-NEXT:    srawi r3, r3, 28
-; CHECK-PWR8-NEXT:    extsw r4, r4
-; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    sub r6, r4, r3
 ; CHECK-PWR8-NEXT:    cmpw r3, r4
 ; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
 ; CHECK-PWR8-NEXT:    isellt r3, r5, r3
 ; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i4 %a, %b
   %t2 = icmp slt i4 %b, %a
   %t3 = zext i1 %t2 to i64

llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll

 ; PPC64LE:       # %bb.0: # %entry
 ; PPC64LE-NEXT:    mflr r0
 ; PPC64LE-NEXT:    std r0, 16(r1)
 ; PPC64LE-NEXT:    stdu r1, -32(r1)
 ; PPC64LE-NEXT:    #APP
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    #NO_APP
 ; PPC64LE-NEXT:  .LBB3_1: # %return
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    addi r1, r1, 32
 ; PPC64LE-NEXT:    ld r0, 16(r1)
 ; PPC64LE-NEXT:    mtlr r0
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB3_2: # Block address taken
 ; PPC64LE-NEXT:    # %return_early
 ; PPC64LE-NEXT:    # Label of block must be emitted
 ; PPC64LE-NEXT:    li r3, 0
 ; PPC64LE-NEXT:    b .LBB3_1
 ;
 ; PPC64BE-LABEL: ClobberLR_BR:
 ; PPC64BE:       # %bb.0: # %entry
 ; PPC64BE-NEXT:    mflr r0
 ; PPC64BE-NEXT:    std r0, 16(r1)
 ; PPC64BE-NEXT:    stdu r1, -48(r1)
 ; PPC64BE-NEXT:    #APP
 ; PPC64BE-NEXT:    nop
 ; PPC64BE-NEXT:    #NO_APP
 ; PPC64BE-NEXT:  .LBB3_1: # %return
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    addi r1, r1, 48
 ; PPC64BE-NEXT:    ld r0, 16(r1)
 ; PPC64BE-NEXT:    mtlr r0
 ; PPC64BE-NEXT:    blr
 ; PPC64BE-NEXT:  .LBB3_2: # Block address taken
 ; PPC64BE-NEXT:    # %return_early
 ; PPC64BE-NEXT:    # Label of block must be emitted
 ; PPC64BE-NEXT:    li r3, 0

 
 define dso_local signext i32 @ClobberR5_BR(i32 signext %in) #0 {
 ; PPC64LE-LABEL: ClobberR5_BR:
 ; PPC64LE:       # %bb.0: # %entry
 ; PPC64LE-NEXT:    #APP
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    #NO_APP
 ; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB4_2: # Block address taken
 ; PPC64LE-NEXT:    # %return_early
 ; PPC64LE-NEXT:    # Label of block must be emitted
 ; PPC64LE-NEXT:    li r3, 0
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    blr
 ;
 ; PPC64BE-LABEL: ClobberR5_BR:
 ; PPC64BE:       # %bb.0: # %entry
 ; PPC64BE-NEXT:    #APP
 ; PPC64BE-NEXT:    nop
 ; PPC64BE-NEXT:    #NO_APP
 ; PPC64BE-NEXT:  # %bb.1: # %return
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    blr
 ; PPC64BE-NEXT:  .LBB4_2: # Block address taken
 ; PPC64BE-NEXT:    # %return_early
 ; PPC64BE-NEXT:    # Label of block must be emitted
 ; PPC64BE-NEXT:    li r3, 0
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    blr
 entry:
   callbr void asm sideeffect "nop", "!i,~{r5}"()
           to label %return [label %return_early]
 
 return_early:
   br label %return
 

llvm/test/CodeGen/PowerPC/pr41088.ll

 ; CHECK-NEXT:  .Lfunc_lep0:
 ; CHECK-NEXT:    .localentry test, .Lfunc_lep0-.Lfunc_gep0
 ; CHECK-NEXT:  # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:  # %bb.1: # %bb9
 ; CHECK-NEXT:    bl test5
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    rlwinm r3, r3, 8, 16, 23
+; CHECK-NEXT:    rlwinm r4, r3, 8, 16, 23
 ; CHECK-NEXT:  # %bb.2: # %bb12
-; CHECK-NEXT:    clrldi r4, r3, 32
 ; CHECK-NEXT:    bl test3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 bb:
   switch i64 undef, label %bb21 [

llvm/test/CodeGen/PowerPC/pr47660.ll

 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrlwi r3, r3, 24
 ; CHECK-LE-NEXT:    xxlxor f1, f1, f1
 ; CHECK-LE-NEXT:    mtfprwz f0, r3
 ; CHECK-LE-NEXT:    xscvuxddp f0, f0
 ; CHECK-LE-NEXT:    xsmuldp f0, f0, f1
 ; CHECK-LE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: _Z1f1c:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    clrldi r3, r3, 56
 ; CHECK-BE-NEXT:    std r3, -16(r1)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    lfd f0, -16(r1)
 ; CHECK-BE-NEXT:    lfs f1, .LCPI0_0@toc@l(r3)
 ; CHECK-BE-NEXT:    fcfid f0, f0
 ; CHECK-BE-NEXT:    fmul f0, f0, f1
 ; CHECK-BE-NEXT:    fctiwz f0, f0
 ; CHECK-BE-NEXT:    stfd f0, -8(r1)
 ; CHECK-BE-NEXT:    lwz r3, -4(r1)
-; CHECK-BE-NEXT:    clrldi r3, r3, 32
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = and i24 %g.coerce, 255
   %conv1 = uitofp i24 %0 to double
   %mul = fmul double 0.000000e+00, %conv1
   %conv2 = fptoui double %mul to i8
   %retval.sroa.0.0.insert.ext = zext i8 %conv2 to i24
   ret i24 %retval.sroa.0.0.insert.ext
 }
 
 attributes #0 = { "use-soft-float"="false" }

llvm/test/CodeGen/PowerPC/prefer-dqform.ll

 ; CHECK-P9-NEXT:    slwi r4, r4, 4
 ; CHECK-P9-NEXT:    addze r5, r5
 ; CHECK-P9-NEXT:    sub r4, r4, r10
 ; CHECK-P9-NEXT:    cmpw r3, r4
 ; CHECK-P9-NEXT:    bgtlr cr0
 ; CHECK-P9-NEXT:  # %bb.1: # %_loop_2_do_.lr.ph
 ; CHECK-P9-NEXT:    extswsli r5, r5, 3
 ; CHECK-P9-NEXT:    extsw r10, r4
+; CHECK-P9-NEXT:    lwa r4, 0(r7)
 ; CHECK-P9-NEXT:    add r5, r8, r5
-; CHECK-P9-NEXT:    clrldi r8, r3, 32
-; CHECK-P9-NEXT:    lwa r3, 0(r7)
-; CHECK-P9-NEXT:    addi r4, r8, 1
-; CHECK-P9-NEXT:    addi r5, r5, -8
-; CHECK-P9-NEXT:    lxvdsx vs0, 0, r5
-; CHECK-P9-NEXT:    sub r3, r4, r3
+; CHECK-P9-NEXT:    addi r8, r5, -8
+; CHECK-P9-NEXT:    addi r5, r3, 1
+; CHECK-P9-NEXT:    sub r3, r10, r3
+; CHECK-P9-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-P9-NEXT:    lxvdsx vs0, 0, r8
+; CHECK-P9-NEXT:    sub r4, r5, r4
+; CHECK-P9-NEXT:    sldi r5, r5, 3
+; CHECK-P9-NEXT:    addi r3, r3, 1
 ; CHECK-P9-NEXT:    sldi r4, r4, 3
-; CHECK-P9-NEXT:    sldi r3, r3, 3
-; CHECK-P9-NEXT:    add r4, r9, r4
-; CHECK-P9-NEXT:    add r3, r6, r3
-; CHECK-P9-NEXT:    sub r6, r10, r8
-; CHECK-P9-NEXT:    rldicl r6, r6, 60, 4
-; CHECK-P9-NEXT:    addi r6, r6, 1
-; CHECK-P9-NEXT:    mtctr r6
+; CHECK-P9-NEXT:    add r5, r9, r5
+; CHECK-P9-NEXT:    mtctr r3
+; CHECK-P9-NEXT:    add r4, r6, r4
 ; CHECK-P9-NEXT:    .p2align 4
 ; CHECK-P9-NEXT:  .LBB0_2: # %_loop_2_do_
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    lxv vs1, -16(r4)
-; CHECK-P9-NEXT:    lxv vs2, 0(r4)
-; CHECK-P9-NEXT:    lxv vs3, -16(r3)
-; CHECK-P9-NEXT:    lxv vs4, 0(r3)
-; CHECK-P9-NEXT:    addi r3, r3, 128
+; CHECK-P9-NEXT:    lxv vs1, -16(r5)
+; CHECK-P9-NEXT:    lxv vs2, 0(r5)
+; CHECK-P9-NEXT:    lxv vs3, -16(r4)
+; CHECK-P9-NEXT:    lxv vs4, 0(r4)
+; CHECK-P9-NEXT:    addi r4, r4, 128
 ; CHECK-P9-NEXT:    xvmaddadp vs1, vs3, vs1
-; CHECK-P9-NEXT:    stxv vs1, -16(r4)
+; CHECK-P9-NEXT:    stxv vs1, -16(r5)
 ; CHECK-P9-NEXT:    xvmaddadp vs2, vs4, vs0
-; CHECK-P9-NEXT:    stxv vs2, 0(r4)
-; CHECK-P9-NEXT:    addi r4, r4, 128
+; CHECK-P9-NEXT:    stxv vs2, 0(r5)
+; CHECK-P9-NEXT:    addi r5, r5, 128
 ; CHECK-P9-NEXT:    bdnz .LBB0_2
 ; CHECK-P9-NEXT:  # %bb.3: # %_return_bb
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test:
 ; CHECK-P10:       # %bb.0: # %test_entry
 ; CHECK-P10-NEXT:    lwz r4, 0(r4)
 ; CHECK-P10-NEXT:    andi. r3, r6, 15

 ; CHECK-P10-NEXT:    slwi r4, r4, 4
 ; CHECK-P10-NEXT:    addze r5, r5
 ; CHECK-P10-NEXT:    sub r4, r4, r10
 ; CHECK-P10-NEXT:    cmpw r3, r4
 ; CHECK-P10-NEXT:    bgtlr cr0
 ; CHECK-P10-NEXT:  # %bb.1: # %_loop_2_do_.lr.ph
 ; CHECK-P10-NEXT:    extswsli r5, r5, 3
 ; CHECK-P10-NEXT:    extsw r10, r4
+; CHECK-P10-NEXT:    lwa r4, 0(r7)
 ; CHECK-P10-NEXT:    add r5, r8, r5
-; CHECK-P10-NEXT:    clrldi r8, r3, 32
-; CHECK-P10-NEXT:    lwa r3, 0(r7)
-; CHECK-P10-NEXT:    addi r4, r8, 1
-; CHECK-P10-NEXT:    addi r5, r5, -8
-; CHECK-P10-NEXT:    lxvdsx vs0, 0, r5
-; CHECK-P10-NEXT:    sub r3, r4, r3
+; CHECK-P10-NEXT:    addi r8, r5, -8
+; CHECK-P10-NEXT:    addi r5, r3, 1
+; CHECK-P10-NEXT:    sub r3, r10, r3
+; CHECK-P10-NEXT:    sub r4, r5, r4
+; CHECK-P10-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-P10-NEXT:    sldi r5, r5, 3
+; CHECK-P10-NEXT:    add r5, r9, r5
+; CHECK-P10-NEXT:    lxvdsx vs0, 0, r8
+; CHECK-P10-NEXT:    addi r3, r3, 1
 ; CHECK-P10-NEXT:    sldi r4, r4, 3
-; CHECK-P10-NEXT:    add r4, r9, r4
-; CHECK-P10-NEXT:    sldi r3, r3, 3
-; CHECK-P10-NEXT:    add r3, r6, r3
-; CHECK-P10-NEXT:    sub r6, r10, r8
-; CHECK-P10-NEXT:    rldicl r6, r6, 60, 4
-; CHECK-P10-NEXT:    addi r6, r6, 1
-; CHECK-P10-NEXT:    mtctr r6
+; CHECK-P10-NEXT:    add r4, r6, r4
+; CHECK-P10-NEXT:    mtctr r3
 ; CHECK-P10-NEXT:    .p2align 4
 ; CHECK-P10-NEXT:  .LBB0_2: # %_loop_2_do_
 ; CHECK-P10-NEXT:    #
-; CHECK-P10-NEXT:    lxv vs1, -16(r4)
-; CHECK-P10-NEXT:    lxv vs2, 0(r4)
-; CHECK-P10-NEXT:    lxv vs3, -16(r3)
+; CHECK-P10-NEXT:    lxv vs1, -16(r5)
+; CHECK-P10-NEXT:    lxv vs2, 0(r5)
+; CHECK-P10-NEXT:    lxv vs3, -16(r4)
 ; CHECK-P10-NEXT:    xvmaddadp vs1, vs3, vs1
-; CHECK-P10-NEXT:    lxv vs4, 0(r3)
+; CHECK-P10-NEXT:    lxv vs4, 0(r4)
 ; CHECK-P10-NEXT:    xvmaddadp vs2, vs4, vs0
-; CHECK-P10-NEXT:    addi r3, r3, 128
-; CHECK-P10-NEXT:    stxv vs1, -16(r4)
-; CHECK-P10-NEXT:    stxv vs2, 0(r4)
 ; CHECK-P10-NEXT:    addi r4, r4, 128
+; CHECK-P10-NEXT:    stxv vs1, -16(r5)
+; CHECK-P10-NEXT:    stxv vs2, 0(r5)
+; CHECK-P10-NEXT:    addi r5, r5, 128
 ; CHECK-P10-NEXT:    bdnz .LBB0_2
 ; CHECK-P10-NEXT:  # %bb.3: # %_return_bb
 ; CHECK-P10-NEXT:    blr
 ; FIXME: use pair load/store instructions lxvp/stxvp
 test_entry:
   %_conv5 = ptrtoint [0 x %_elem_type_of_a]* %.a to i64
   %_andi_tmp = and i64 %_conv5, 15
   %_equ_tmp = icmp eq i64 %_andi_tmp, 0

llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll

 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_align16_uint16_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_align32_uint16_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint16_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plfs f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_align64_uint16_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint16_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_reg_uint16_t_float(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfsx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_or_uint16_t_float(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv1 = fptoui float %1 to i16
   ret i16 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lfs f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 8
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plfs f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_float:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lfsx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_float:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lfsx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 16
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint16_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint16_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4096
   %conv = fptoui float %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align16_uint16_t_float() {
 ; CHECK-LABEL: ld_cst_align16_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 4080 to float*), align 16
   %conv = fptoui float %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align32_uint16_t_float() {
 ; CHECK-LABEL: ld_cst_align32_uint16_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lfs f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
   %conv = fptoui float %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align64_uint16_t_float() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
   %conv = fptoui float %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_align16_uint16_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_align32_uint16_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint16_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plfd f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_align64_uint16_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint16_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_reg_uint16_t_double(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_or_uint16_t_double(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv1 = fptoui double %1 to i16
   ret i16 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lfd f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plfd f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_double:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lfdx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_double:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lfdx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 16
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint16_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint16_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 4096
   %conv = fptoui double %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align16_uint16_t_double() {
 ; CHECK-LABEL: ld_cst_align16_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 4080 to double*), align 16
   %conv = fptoui double %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align32_uint16_t_double() {
 ; CHECK-LABEL: ld_cst_align32_uint16_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lfd f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
   %conv = fptoui double %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align64_uint16_t_double() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
   %conv = fptoui double %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly

llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll

 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 8(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plfs f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_float(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfsx f0, r3, r4
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_float(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv1 = fptoui float %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lfs f0, 24(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 8
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plfs f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_float:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lfsx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_float:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lfsx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 16
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4096
   %conv = fptoui float %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_float() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 4080(0)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 4080 to float*), align 16
   %conv = fptoui float %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_float() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lfs f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
   %conv = fptoui float %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_float() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
   %conv = fptoui float %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 8(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plfd f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_double(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_double(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv1 = fptoui double %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lfd f0, 24(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plfd f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_double:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lfdx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_double:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lfdx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 16
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 4096
   %conv = fptoui double %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_double() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 4080(0)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 4080 to double*), align 16
   %conv = fptoui double %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_double() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lfd f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
   %conv = fptoui double %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_double() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
   %conv = fptoui double %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly

llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll

 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_0_uint8_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_align16_uint8_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_align32_uint8_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plfs f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_unalign64_uint8_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_unalign64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    lfsx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_align64_uint8_t_float(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_reg_uint8_t_float(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfsx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_or_uint8_t_float(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv1 = fptoui float %1 to i8
   ret i8 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lfs f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 8
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_float(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plfs f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_float:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lfsx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_float:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lfsx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 16
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_unalign64_uint8_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_unalign64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    lfsx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000001
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_float(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to float*
   %1 = load float, float* %0, align 4096
   %conv = fptoui float %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align16_uint8_t_float() {
 ; CHECK-LABEL: ld_cst_align16_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfs f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 4080 to float*), align 16
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align32_uint8_t_float() {
 ; CHECK-LABEL: ld_cst_align32_uint8_t_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lfs f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_float() {
 ; CHECK-P10-LABEL: ld_cst_unalign64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 232
 ; CHECK-P10-NEXT:    pli r4, 3567587329
 ; CHECK-P10-NEXT:    rldimi r4, r3, 32, 0
 ; CHECK-P10-NEXT:    lfs f0, 0(r4)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r3, 29
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 35, 24
 ; CHECK-PREP10-NEXT:    oris r3, r3, 54437
 ; CHECK-PREP10-NEXT:    ori r3, r3, 4097
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align64_uint8_t_float() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint8_t_float:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_float:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_0_uint8_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_align16_uint8_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_align32_uint8_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    plfd f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_unalign64_uint8_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_unalign64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    lfdx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_align64_uint8_t_double(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_reg_uint8_t_double(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_or_uint8_t_double(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv1 = fptoui double %1 to i8
   ret i8 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lfd f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_double(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    plfd f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_double:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lfdx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_double:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lfdx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 16
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_unalign64_uint8_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_unalign64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    lfdx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000001
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 8
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_double(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to double*
   %1 = load double, double* %0, align 4096
   %conv = fptoui double %1 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align16_uint8_t_double() {
 ; CHECK-LABEL: ld_cst_align16_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 4080 to double*), align 16
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align32_uint8_t_double() {
 ; CHECK-LABEL: ld_cst_align32_uint8_t_double:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lfd f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_double() {
 ; CHECK-P10-LABEL: ld_cst_unalign64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 232
 ; CHECK-P10-NEXT:    pli r4, 3567587329
 ; CHECK-P10-NEXT:    rldimi r4, r3, 32, 0
 ; CHECK-P10-NEXT:    lfd f0, 0(r4)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r3, 29
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 35, 24
 ; CHECK-PREP10-NEXT:    oris r3, r3, 54437
 ; CHECK-PREP10-NEXT:    ori r3, r3, 4097
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align64_uint8_t_double() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint8_t_double:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_double:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly

llvm/test/CodeGen/PowerPC/select-constant-xor.ll

; CHECK-NEXT:    blr
   %s = select i1 %c, i32 2147483647, i32 -2147483648
   ret i32 %s
 }
 
 define i64 @selecti32i64(i32 %a) {
 ; CHECK-LABEL: selecti32i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 3, 3, 31
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 65535
 ; CHECK-NEXT:    xoris 3, 3, 32767
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i64 2147483647, i64 -2147483648
   ret i64 %s
 }
 
; CHECK-NEXT:    blr
   %xor = xor i8 %conv5, 84
   ret i8 %xor
 }
 
 define i32 @selecti32i32(i32 %a) {
 ; CHECK-LABEL: selecti32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 3, 3, 31
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 84
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i32 84, i32 -85
   ret i32 %s
 }
 
 define i8 @selecti32i8(i32 %a) {
 ; CHECK-LABEL: selecti32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 3, 3, 31
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 84
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i8 84, i8 -85
   ret i8 %s
 }
 
 define i32 @selecti8i32(i8 %a) {
 ; CHECK-LABEL: selecti8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    extsb 3, 3
 ; CHECK-NEXT:    srawi 3, 3, 7
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 84
 ; CHECK-NEXT:    blr
   %c = icmp sgt i8 %a, -1
   %s = select i1 %c, i32 84, i32 -85
   ret i32 %s
 }
 
 define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {

llvm/test/CodeGen/PowerPC/sext_elimination.mir

+# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64le-unknown-linux-gnu"
+  define i8* @func(i8* %a) {
+  entry:
+    ret i8* %a
+  }
+  
+...
+---
+name:            func
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x3', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: bb.0.entry:
+    ; CHECK: %4:g8rc = EXTSW_32_64 %3
+    ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
+    ; CHECK: %7:g8rc = EXTSW_32_64 %6
+    ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
+    ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
+    ; CHECK: %14:g8rc = COPY %1
+
+    %0:g8rc_nox0 = COPY $x3
+    %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
+    %3:gprc = COPY %2:g8rc_nox0
+    %4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
+    %5:g8rc = EXTSW_32_64 %1:gprc
+
+    %6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated
+    %7:g8rc = EXTSW_32_64 %6:gprc
+
+    %8:gprc = ORIS %1:gprc, 32767
+    %9:g8rc = EXTSW_32_64 %8:gprc
+
+    %10:gprc = ORI %1:gprc, 32768
+    %11:g8rc = EXTSW_32_64 %10:gprc
+
+    %12:g8rc = IMPLICIT_DEF
+    %13:g8rc = INSERT_SUBREG %12:g8rc, %1:gprc, %subreg.sub_32
+    %14:g8rc = RLDICL %13:g8rc, 0, 32
+
+...

llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll

top:
   %rv.i = atomicrmw min i16* %1, i16 %0 acq_rel
   %rv.i2 = load atomic i16, i16* %1 acquire, align 16
   ret i16 %rv.i2
 }
 
 define i16 @noSEXTLoad(i16 *%p) #0 {
 ; CHECK-LABEL: noSEXTLoad:
 ; CHECK:       # %bb.0: # %top
-; CHECK-NEXT:    lhz 5, 0(3)
+; CHECK-NEXT:    lha 3, 0(3)
 ; CHECK-NEXT:    li 4, 0
-; CHECK-NEXT:    addi 3, 1, -4
 ; CHECK-NEXT:    sth 4, -4(1)
-; CHECK-NEXT:    extsh 4, 5
+; CHECK-NEXT:    addi 4, 1, -4
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB2_1: # %top
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 5, 0, 3
+; CHECK-NEXT:    lharx 5, 0, 4
 ; CHECK-NEXT:    extsh 5, 5
-; CHECK-NEXT:    cmpw 4, 5
+; CHECK-NEXT:    cmpw 3, 5
 ; CHECK-NEXT:    bge 0, .LBB2_3
 ; CHECK-NEXT:  # %bb.2: # %top
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    sthcx. 3, 0, 4
 ; CHECK-NEXT:    bne 0, .LBB2_1
 ; CHECK-NEXT:  .LBB2_3: # %top
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    lhz 3, -4(1)
 ; CHECK-NEXT:    cmpd 7, 3, 3
 ; CHECK-NEXT:    bne- 7, .+4
 ; CHECK-NEXT:    isync
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll

 ; CHECK-NEXT:    bc 4, 20, .LBB0_4
 ; CHECK-NEXT:  # %bb.2: # %if.end5
 ; CHECK-NEXT:    addis 3, 2, .L.str@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .L.str@toc@l
 ; CHECK-NEXT:    bl printf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; CHECK-NEXT:  .LBB0_3: # %return
-; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    # kill: def $r3 killed $r3 def $x3
 ; CHECK-NEXT:    addi 1, 31, 784
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    lwz 12, 8(1)
 ; CHECK-NEXT:    ld 31, -8(1)
 ; CHECK-NEXT:    mtocrf 32, 12
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_4: # %if.then3

 ; BE-NEXT:    bc 4, 20, .LBB0_4
 ; BE-NEXT:  # %bb.2: # %if.end5
 ; BE-NEXT:    addis 3, 2, .L.str@toc@ha
 ; BE-NEXT:    addi 3, 3, .L.str@toc@l
 ; BE-NEXT:    bl printf
 ; BE-NEXT:    nop
 ; BE-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; BE-NEXT:  .LBB0_3: # %return
-; BE-NEXT:    extsw 3, 3
+; BE-NEXT:    # kill: def $r3 killed $r3 def $x3
 ; BE-NEXT:    addi 1, 31, 800
 ; BE-NEXT:    ld 0, 16(1)
 ; BE-NEXT:    lwz 12, 8(1)
 ; BE-NEXT:    ld 31, -8(1)
 ; BE-NEXT:    mtlr 0
 ; BE-NEXT:    mtcrf 32, 12 # cr2
 ; BE-NEXT:    blr
 ; BE-NEXT:  .LBB0_4: # %if.then3

llvm/test/CodeGen/PowerPC/store-forward-be64.ll

 
 ; Function Attrs: nounwind
 define signext i32 @tc43(%struct.ST* noundef byval(%struct.ST) align 8 %s) {
 ; CHECK-LABEL: tc43:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    std 3, 48(1)
 ; CHECK-NEXT:    lwz 3, 48(1)
 ; CHECK-NEXT:    srawi 3, 3, 8
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
 entry:
   %a = getelementptr inbounds %struct.ST, %struct.ST* %s, i32 0, i32 0
   %0 = load i32, i32* %a, align 8
   %shr = ashr i32 %0, 8
   ret i32 %shr
 }
 

llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll

 ; CHECK-NEXT:    .cfi_offset r29, -24
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -64(r1)
 ; CHECK-NEXT:    mr r29, r5
-; CHECK-NEXT:    mr r30, r3
-; CHECK-NEXT:    extsw r28, r4
+; CHECK-NEXT:    mr r30, r4
+; CHECK-NEXT:    mr r28, r3
 ; CHECK-NEXT:    std r2, 24(r1)
 ; CHECK-NEXT:    cmpwi r29, 1
 ; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    cmpwi r4, 11
+; CHECK-NEXT:    cmpwi r30, 11
 ; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_2: # %for.body.us
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    mtctr r30
-; CHECK-NEXT:    mr r3, r28
-; CHECK-NEXT:    mr r12, r30
+; CHECK-NEXT:    mtctr r28
+; CHECK-NEXT:    mr r3, r30
+; CHECK-NEXT:    mr r12, r28
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 24(r1)
 ; CHECK-NEXT:    addi r29, r29, -1
 ; CHECK-NEXT:    cmplwi r29, 0
 ; CHECK-NEXT:    bne cr0, .LBB0_2
 ; CHECK-NEXT:  .LBB0_3: # %for.cond.cleanup
-; CHECK-NEXT:    mtctr r30
-; CHECK-NEXT:    mr r3, r28
-; CHECK-NEXT:    mr r12, r30
+; CHECK-NEXT:    mtctr r28
+; CHECK-NEXT:    mr r3, r30
+; CHECK-NEXT:    mr r12, r28
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 24(r1)
 ; CHECK-NEXT:    addi r1, r1, 64
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr r0