[ARM] Implement execute-only support in CodeGen

[prakhar]

Summary

[ARM] Implement execute-only support in CodeGen

This implements execute-only support for ARM code generation, which
prevents the compiler from generating data accesses to code sections.
The following changes are involved:

• Add the SubtargetFeature "execute-only" to the ARM code generator.
• Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this feature.
• When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2.
• Jump tables are placed in data sections when in execute-only mode.
• The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals.

[rengolin]

Hi Prakhar,

Thanks for working on this, it's a nice functionality. I have a bunch of inline comments, but some generic ones, too.

Hence, execute-only support is only available for targets that support MOVW/MOVT (ARMv7 and above).

Actually, MOVT was introduced in ARMv6T2, but execute-only seems to be an M thing, mostly ARMv7M and ARMv8M. Maybe advertise it that way instead of MOVT-dependent.

I wonder how compatible this is with the GCC implementation. Is this how GCC lays out the ELF object? Can we link GCC objects with LLVM ones and expect perfect cooperation (ex. globals & symbols)?

I'm also adding more people to review this with experience in ELF and constant pools.

cheers,
--renato

include/llvm/CodeGen/TargetLoweringObjectFileImpl.h

36

Initialising with 0 is a bit obvious, but 1 is not. Can you add a comment, please?

include/llvm/MC/SectionKind.h

32

No TABs, please. Use clang-format on your patch to make sure it adheres to the coding standard.

119

To me it seems ExecuteOnly is orthogonal to isText. The problem is that we're using ReadOnly on the same solution space.

I think we should keep the accessors as simple as possible and use isText() || isExecuteOnly() in code.

lib/CodeGen/TargetLoweringObjectFileImpl.cpp

318

Does this mean there is only one pure section on each module?

lib/Target/ARM/ARMInstrThumb2.td

3386

I'm worried about this hijack. Does that mean it won't be used by Thumb2 (v6T2+) any more?

lib/Target/ARM/ARMSubtarget.cpp

179

I'm worried about the silent behaviour here.

If movt is disabled by some other part or user flag, than this should be an error, not a silent change.

181

This assert is wrong. It should be something like:

assert(hasV8MBaselineOps() && "Execute-only supported by ARMv8M only");

And it should only be an assert if there are no combination of user flags that can get you here.

If there are, this should be an error.

lib/Target/ARM/ARMTargetObjectFile.cpp

49

Where is the TextSection initialised if it's not pure? Shouldn't this move to the same place?

test/CodeGen/ARM/constantfp.ll

146

There are plenty of other tests in this file that need to make sure no loads from labels occurred. Please, add the relevant checks.

test/CodeGen/ARM/execute-only-big-stack-frame.ll

11

Whenever adding a NOT pattern, you have to be as generic as possible. It's possible that a label load with a different pattern shows up and you won't pick it up.

Just use:

CHECK-SUBW-ADDW-NOT: ldr

[peter.smith]

I've not looked over the details of the code. I can add some comments on compatibility and to a certain extent naming.

The ARM Compiler 6 documentation for execute-only http://infocenter.arm.com/help/topic/com.arm.doc.dui0774g/vvi1452508645836.html says Link Time Optimization does not honor the armclang -mexecute-only option. If you use the armclang -flto or -Omax options, then the compiler cannot generate execute-only code. Does this still apply, and if it does what should the action be, error message, user beware?

Personally I think it would be better to use the GCC pure-code naming conventions for the test cases and comments. The execute-only name has been favoured by the commercial compilers such as ARM Compiler 5 and ARM Compiler 6. However I think that the majority of the people looking through the code base will be familiar with the GCC pure-code name. Standardising on pure-code would make it easier to equate the support in GCC and llvm and enhance expectations of compatibility. I think that this only means changing comments to refer to pure-code rather than execute-only and changing the file names of the tests to use pure-code rather than execute-only. Or perhaps a comment that equates execute-only with pure-code. I think it is valuable to have both -mexecute-only and -mpure-code as a migration path for both commercial and GCC users.

I've not good a hugely strong opinion about this, I think execute-only is a far better name but I think familiarity with GCC might help more.

To support purecode a toolchain needs linker support. In effect if a section has the SHF_ARM_PURECODE flag it is making the claim that the contents of the section must not be read at run-time. If a program segment contains only SHF_ARM_PURECODE sections then the linker removes the PF_R flag from the ELF file. For compatibility it doesn't matter if the sections come from llvm or gcc, as long as they set the flag they will be treated the same by a linker. There is support in the Version 5-2016-q3-update of the GNU ARM Embedded Toolchain

References:

• http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044f/IHI0044F_aaelf.pdf search for 4.3.3 Section Attribute Flags, you'll find the information SHF_ARM_PURECODE there. Unfortunately in the latest public version the attribute is called SHF_ARM_NOREAD instead of SHF_ARM_PURECODE, this will be changed to SHF_ARM_PURECODE in the next release of the document.

There is a small whitepaper https://community.arm.com/docs/DOC-11666 on Pure Code in GCC

[prakhar]

Actually, MOVT was introduced in ARMv6T2, but execute-only seems to be an M thing, mostly ARMv7M and ARMv8M. Maybe advertise it that way instead of MOVT-dependent.

Execute-only code can be technically generated for any target that supports the MOVT instruction (so Thumb2 and v8-M Baseline targets, which includes v6T2), but is intended for M-class targets that have memory controllers supporting execute-only regions. I'll update the commit message with this.

I wonder how compatible this is with the GCC implementation. Is this how GCC lays out the ELF object? Can we link GCC objects with LLVM ones and expect perfect cooperation (ex. globals & symbols)?

At the object level, there should be no issues with GCC compatibility and the objects should link without issue. For assembly code, LLVM does not yet support GAS's syntax of allowing numeric flags to be used, so I've created patch D27451 for this.

The ARM Compiler 6 documentation for execute-only http://infocenter.arm.com/help/topic/com.arm.doc.dui0774g/vvi1452508645836.html says Link Time Optimization does not honor the armclang -mexecute-only option. If you use the armclang -flto or -Omax options, then the compiler cannot generate execute-only code. Does this still apply, and if it does what should the action be, error message, user beware?

armclang does not appear to generate any warning or error if -flto is specified alongside -mexecute-only.

Personally I think it would be better to use the GCC pure-code naming conventions for the test cases and comments. The execute-only name has been favoured by the commercial compilers such as ARM Compiler 5 and ARM Compiler 6. However I think that the majority of the people looking through the code base will be familiar with the GCC pure-code name. Standardising on pure-code would make it easier to equate the support in GCC and llvm and enhance expectations of compatibility. I think that this only means changing comments to refer to pure-code rather than execute-only and changing the file names of the tests to use pure-code rather than execute-only. Or perhaps a comment that equates execute-only with pure-code. I think it is valuable to have both -mexecute-only and -mpure-code as a migration path for both commercial and GCC users.

Execute-only has already been used in AC5 and AC6 as well as in IAR's compiler, and is a more intuitive name whose purpose is immediately understood. The -mpure-code flag is maintained as an alias for -mexecute-only in clang for compatibility in GCC, and the section header flag is referred to as SHF_ARM_PURECODE as is the case with GCC. The fact that the feature is named execute-only within LLVM is purely an implementation detail, and shouldn't be an issue barring any significant opposition. I can add a source code comment in to explain this if necessary.

include/llvm/MC/SectionKind.h

32

This isn't a tab character. Unless you meant that ExecuteOnly should be placed at the same indent level as Text?

119

As implemented here, an execute-only section is essentially a specialised text section for all purposes, with the added restriction that reads should not be made from it. I'm not sure the two are orthogonal.

lib/CodeGen/TargetLoweringObjectFileImpl.cpp

318

Yes, that's the intention.

lib/Target/ARM/ARMInstrThumb2.td

3386

Thumb2 is a superset of V8MBaselineOps, so this won't be an issue.

lib/Target/ARM/ARMSubtarget.cpp

179

Yes, this should be an error. I've changed this to report an error if NoMovt is enabled or the target doesn't support MOVT. I'll also add a diagnostic to clang for this.

lib/Target/ARM/ARMTargetObjectFile.cpp

49

We cannot change the flags of an existing section, so we create a new text section with the flags set in addition to the default one.

[rengolin]

include/llvm/MC/SectionKind.h

32

yup

lib/Target/ARM/ARMTargetObjectFile.cpp

49

Oh, I see. I think this deserves a nice comment. :)

[prakhar]

Additional tests, error reporting, and explanatory comments

[rengolin]

Right, I'm happy with the changes from the code side, but there were some concerns on IRC if we should support this at all.

We seem to have no ELF code owner, but Jim is the MC code owner, so I'm adding him here to review the generic parts.

I forgot who had concerns on IRC and my history doesn't go that far, so I'll leave for people that really care about this to make their voices heard on this review.

cheers,
--renato

[grosbach]

In D27449#617063, @rengolin wrote:

Right, I'm happy with the changes from the code side, but there were some concerns on IRC if we should support this at all.

Seems a reasonable thing to support in general. Were the concerns about supporting execute-only conceptually or about the design of this approach?

include/llvm/MC/SectionKind.h

119

Yeesh. This file is a bit of a mess. I'd much rather see ExecuteOnly be an attribute of Text rather than a completely distinct Kind. That's not the way the rest of the stuff is represented though, leading to the comment indentation mess Renato commented on.

Bottom line, this is fine as-is here, I'm just grumbling about the overall file. :)

lib/Target/ARM/ARM.td

267 ↗

(On Diff #80748)

Why use a Feature flag for this? This isn't an attribute of the CPU, but rather a code generation option, right?

Would a function attribute be sufficient? At first look, it seems all the decisions to be made are about how to handle any given function's constant data. That would have the added benefit of making LTO "just work" since function attributes propagate naturally.

lib/Target/ARM/ARMSubtarget.cpp

179

The error should be detected earlier and a proper diagnostic issued if at all possible. Using report_fatal_error() for user-facing diagnostics is an option of last resort and an indicator of a layering failure elsewhere.

[rengolin]

In D27449#617363, @grosbach wrote:

Seems a reasonable thing to support in general. Were the concerns about supporting execute-only conceptually or about the design of this approach?

About the concept of unreadable code areas in general, and what benefits this really brings to security and performance of deeply embedded devices.

I honestly think this is a feature that ARM hardware needs support and I'm not a hardware expert to decide what features people need on such an individualised market. With the change itself being reasonably non-intrusive, I can't see why we'd block such a feature on those grounds only.

cheers,
--renato

include/llvm/MC/SectionKind.h

119

Yeah, so, after I saw *all* the other options, I realised this split was the least of our worries. :)

My knowledge of this code is limited, so I'm not sure I could suggest a way to make this separation consistent everywhere else, and I'd certainly dislike proposing something ARM-specific here.

lib/Target/ARM/ARM.td

267 ↗

(On Diff #80748)

Oh, I missed that one! Indeed, this is a codegen attribute, which is dependent on the platform, but not enough to be a sub-target feature.

I think the confusion is that Clang emits "-target-feature" "+execute-only", but those are different things.

lib/Target/ARM/ARMSubtarget.cpp

179

There is an error in Clang (D27450) that detects this. Is there a better way to do this in LLVM itself?

[grosbach]

In D27449#617442, @rengolin wrote:

In D27449#617363, @grosbach wrote:

Seems a reasonable thing to support in general. Were the concerns about supporting execute-only conceptually or about the design of this approach?

About the concept of unreadable code areas in general, and what benefits this really brings to security and performance of deeply embedded devices.

Gotcha. My recollection is that it's generally not to valuable in isolation, but can be used in combination with other measures to provide some legitimate mitigations. Usual caveats apply. I'm not a security expert, blah blah. :)

I honestly think this is a feature that ARM hardware needs support and I'm not a hardware expert to decide what features people need on such an individualised market. With the change itself being reasonably non-intrusive, I can't see why we'd block such a feature on those grounds only.

Agreed.

lib/Target/ARM/ARMSubtarget.cpp

179

If there's a legitimate user-facing way to get here and this be the first time we can diagnose the error, we can use the emitError() method on the LLVMContext to complain about it. If, OTOH, getting here in that state indicates a bug earlier in the pipeline (probably true?), then perhaps this could just be an assert().

[rengolin]

lib/Target/ARM/ARMSubtarget.cpp

179

There shouldn't be a user-facing way to get here, though it may be possible possible with the right combination of flags on llc/llvm-mc.

A quick assert would be of the same value as the one above, I'm ok with that, too.

[grosbach]

lib/Target/ARM/ARMSubtarget.cpp

179

SGTM. I don't think it's too horrible if llc/llvm-mc can trigger asserts. Not ideal, but those aren't (supposed to be) user-facing tools at all.

[prakhar]

lib/Target/ARM/ARM.td

267 ↗

(On Diff #80748)

If I understand the concept correctly, then it sounds like execute-only is something that relates to codegen rather than an attribute of a CPU. How would I go about implementing a codegen option, and is there an example I can follow for this?

lib/Target/ARM/ARMSubtarget.cpp

179

It's possible to reach this point with llc/llvm-mc by specifying +execute-only and +no-movt for -target-feature. As I'll be adding clang diagnostics for -mno-movt being enabled alongside -mexecute-only, I'll revert this back to an assert.

[prakhar]

Changed execute-only/no-movt error back to an assert

[prakhar]

Fixed mistake with assert

[rengolin]

lib/Target/ARM/ARM.td

267 ↗

(On Diff #80748)

Have a look at UseFusedMulOps in ARMSubtarget.cpp. There are other examples in the CPP files that you can also take from.

[prakhar]

Make execute-only a codegen option instead of a subtarget feature

[rengolin]

Thanks for all the changes. LGTM now.

[prakhar]

Closed by commit rL289784

[MaskRay]

lib/MC/MCParser/ELFAsmParser.cpp

297

I am adding an error for non-aarch32 targets in D148386.

include/llvm/CodeGen/TargetLoweringObjectFileImpl.h

namespace llvm {
   class MCSymbol;
   class MCContext;
   class GlobalValue;
   class TargetMachine;
 
 
 class TargetLoweringObjectFileELF : public TargetLoweringObjectFile {
   bool UseInitArray;
-  mutable unsigned NextUniqueID = 0;
+  mutable unsigned NextUniqueID = 1;  // ID 0 is reserved for execute-only sections
 
 protected:
   MCSymbolRefExpr::VariantKind PLTRelativeVariantKind =
       MCSymbolRefExpr::VK_None;
 
 public:
   TargetLoweringObjectFileELF() : UseInitArray(false) {}
 

include/llvm/MC/SectionKind.h

 class SectionKind {
   enum Kind {
     /// Metadata - Debug info sections or other metadata.
     Metadata,
 
     /// Text - Text section, used for functions and other executable code.
     Text,
 
+           /// ExecuteOnly, Text section that is not readable.
+           ExecuteOnly,
+
     /// ReadOnly - Data that is never written to at program runtime by the
     /// program or the dynamic linker.  Things in the top-level readonly
     /// SectionKind are not mergeable.
     ReadOnly,
 
         /// MergableCString - Any null-terminated string which allows merging.
         /// These values are known to end in a nul value of the specified size,
         /// not otherwise contain a nul value, and be mergable.  This allows the
/// to during program runtime.
            /// can write to them.  If it chooses to, the dynamic linker can
            /// mark the pages these globals end up on as read-only after it is
            /// done with its relocation phase.
            ReadOnlyWithRel
   } K : 8;
 public:
 
   bool isMetadata() const { return K == Metadata; }
-  bool isText() const { return K == Text; }
+
+  bool isText() const { return K == Text || K == ExecuteOnly; }
+
+  bool isExecuteOnly() const { return K == ExecuteOnly; }
 
   bool isReadOnly() const {
     return K == ReadOnly || isMergeableCString() ||
            isMergeableConst();
   }
 
   bool isMergeableCString() const {
     return K == Mergeable1ByteCString || K == Mergeable2ByteCString ||
static SectionKind get(Kind K) {
     SectionKind Res;
     Res.K = K;
     return Res;
   }
 public:
 
   static SectionKind getMetadata() { return get(Metadata); }
   static SectionKind getText() { return get(Text); }
+  static SectionKind getExecuteOnly() { return get(ExecuteOnly); }
   static SectionKind getReadOnly() { return get(ReadOnly); }
   static SectionKind getMergeable1ByteCString() {
     return get(Mergeable1ByteCString);
   }
   static SectionKind getMergeable2ByteCString() {
     return get(Mergeable2ByteCString);
   }
   static SectionKind getMergeable4ByteCString() {

include/llvm/Support/ELF.h

enum : unsigned {
   SHF_MIPS_MERGE = 0x20000000,
 
   // Address size to be inferred from section entry size.
   SHF_MIPS_ADDR = 0x40000000,
 
   // Section data is string data by default.
   SHF_MIPS_STRING = 0x80000000,
 
+  // Make code section unreadable when in execute-only mode
+  SHF_ARM_PURECODE = 0x20000000,
+
   SHF_AMDGPU_HSA_GLOBAL = 0x00100000,
   SHF_AMDGPU_HSA_READONLY = 0x00200000,
   SHF_AMDGPU_HSA_CODE = 0x00400000,
   SHF_AMDGPU_HSA_AGENT = 0x00800000
 };
 
 // Section Group Flags
 enum : unsigned {

lib/CodeGen/TargetLoweringObjectFileImpl.cpp

static unsigned getELFSectionFlags(SectionKind K) {
   unsigned Flags = 0;
 
   if (!K.isMetadata())
     Flags |= ELF::SHF_ALLOC;
 
   if (K.isText())
     Flags |= ELF::SHF_EXECINSTR;
 
+  if (K.isExecuteOnly())
+    Flags |= ELF::SHF_ARM_PURECODE;
+
   if (K.isWriteable())
     Flags |= ELF::SHF_WRITE;
 
   if (K.isThreadLocal())
     Flags |= ELF::SHF_TLS;
 
   if (K.isMergeableCString() || K.isMergeableConst())
     Flags |= ELF::SHF_MERGE;
if (EmitUniqueSection && UniqueSectionNames) {
     Name.push_back('.');
     TM.getNameWithPrefix(Name, GO, Mang, true);
   }
   unsigned UniqueID = MCContext::GenericSectionID;
   if (EmitUniqueSection && !UniqueSectionNames) {
     UniqueID = *NextUniqueID;
     (*NextUniqueID)++;
   }
+  // Use 0 as the unique ID for execute-only text
+  if (Kind.isExecuteOnly())
+    UniqueID = 0;
   return Ctx.getELFSection(Name, getELFSectionType(Name, Kind), Flags,
                            EntrySize, Group, UniqueID);
 }
 
 MCSection *TargetLoweringObjectFileELF::SelectSectionForGlobal(
     const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
   unsigned Flags = getELFSectionFlags(Kind);
 

lib/MC/MCContext.cpp

auto IterBool = ELFUniquingMap.insert(
       std::make_pair(ELFSectionKey{Section.str(), Group, UniqueID}, nullptr));
   auto &Entry = *IterBool.first;
   if (!IterBool.second)
     return Entry.second;
 
   StringRef CachedName = Entry.first.SectionName;
 
   SectionKind Kind;
-  if (Flags & ELF::SHF_EXECINSTR)
+  if (Flags & ELF::SHF_ARM_PURECODE)
+    Kind = SectionKind::getExecuteOnly();
+  else if (Flags & ELF::SHF_EXECINSTR)
     Kind = SectionKind::getText();
   else
     Kind = SectionKind::getReadOnly();
 
   MCSymbol *Begin = nullptr;
   if (BeginSymName)
     Begin = createTempSymbol(BeginSymName, false);
 

lib/MC/MCParser/ELFAsmParser.cpp

case 'T':
       flags |= ELF::SHF_TLS;
       break;
     case 'c':
       flags |= ELF::XCORE_SHF_CP_SECTION;
       break;
     case 'd':
       flags |= ELF::XCORE_SHF_DP_SECTION;
       break;
+    case 'y':
+      flags |= ELF::SHF_ARM_PURECODE;
+      break;
     case 'G':
       flags |= ELF::SHF_GROUP;
       break;
     case '?':
       *UseLastGroup = true;
       break;
     default:
       return -1U;

lib/MC/MCSectionELF.cpp

void MCSectionELF::PrintSwitchToSection(const MCAsmInfo &MAI,
   if (Flags & ELF::SHF_TLS)
     OS << 'T';
 
   // If there are target-specific flags, print them.
   if (Flags & ELF::XCORE_SHF_CP_SECTION)
     OS << 'c';
   if (Flags & ELF::XCORE_SHF_DP_SECTION)
     OS << 'd';
+  if (Flags & ELF::SHF_ARM_PURECODE)
+    OS << 'y';
 
   OS << '"';
 
   OS << ',';
 
   // If comment string is '@', e.g. as on ARM - use '%' instead
   if (MAI.getCommentString()[0] == '@')
     OS << '%';

lib/ObjectYAML/ELFYAML.cpp

#define BCase(X) IO.bitSetCase(Value, #X, ELF::X);
   BCase(SHF_MERGE)
   BCase(SHF_STRINGS)
   BCase(SHF_INFO_LINK)
   BCase(SHF_LINK_ORDER)
   BCase(SHF_OS_NONCONFORMING)
   BCase(SHF_GROUP)
   BCase(SHF_TLS)
   switch(Object->Header.Machine) {
+  case ELF::EM_ARM:
+    BCase(SHF_ARM_PURECODE)
+    break;
   case ELF::EM_AMDGPU:
     BCase(SHF_AMDGPU_HSA_GLOBAL)
     BCase(SHF_AMDGPU_HSA_READONLY)
     BCase(SHF_AMDGPU_HSA_CODE)
     BCase(SHF_AMDGPU_HSA_AGENT)
     break;
   case ELF::EM_HEXAGON:
     BCase(SHF_HEX_GPREL)

lib/Target/ARM/ARMAsmPrinter.cpp

case MachineOperand::MO_GlobalAddress: {
     else if (TF & ARMII::MO_HI16)
       O << ":upper16:";
     GetARMGVSymbol(GV, TF)->print(O, MAI);
 
     printOffset(MO.getOffset(), O);
     break;
   }
   case MachineOperand::MO_ConstantPoolIndex:
+    if (Subtarget->genExecuteOnly())
+      llvm_unreachable("execute-only should not generate constant pools");
     GetCPISymbol(MO.getIndex())->print(O, MAI);
     break;
   }
 }
 
 //===--------------------------------------------------------------------===//
 
 MCSymbol *ARMAsmPrinter::

lib/Target/ARM/ARMConstantIslandPass.cpp

bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
   if (isThumb2 && !STI->prefers32BitThumb())
     MadeChange |= optimizeThumb2Instructions();
 
   // Shrink 32-bit branch instructions.
   if (isThumb && STI->hasV8MBaselineOps())
     MadeChange |= optimizeThumb2Branches();
 
   // Optimize jump tables using TBB / TBH.
-  if (GenerateTBB)
+  if (GenerateTBB && !STI->genExecuteOnly())
     MadeChange |= optimizeThumb2JumpTables();
 
   // After a while, this might be made debug-only, but it is not expensive.
   verify();
 
   // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
   // undo the spill / restore of LR if possible.
   if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())

lib/Target/ARM/ARMISelLowering.cpp

SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
   const TargetMachine &TM = getTargetMachine();
   if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
     GV = GA->getBaseObject();
   bool IsRO =
       (isa<GlobalVariable>(GV) && cast<GlobalVariable>(GV)->isConstant()) ||
       isa<Function>(GV);
 
-  if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
+  // promoteToConstantPool only if not generating XO text section
+  if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
     if (SDValue V = promoteToConstantPool(GV, DAG, PtrVT, dl))
       return V;
 
   if (isPositionIndependent()) {
     bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
 
     MachineFunction &MF = DAG.getMachineFunction();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
   SDLoc dl(Op);
 
   EVT PTy = getPointerTy(DAG.getDataLayout());
   JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
   SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
   Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
   Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
   SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
-  if (Subtarget->isThumb2()) {
-    // Thumb2 uses a two-level jump. That is, it jumps into the jump table
+  if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
+    // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
     // which does another jump to the destination. This also makes it easier
-    // to translate it to TBB / TBH later.
+    // to translate it to TBB / TBH later (Thumb2 only).
     // FIXME: This might not work if the function is extremely large.
     return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
                        Addr, Op.getOperand(2), JTI);
   }
   if (isPositionIndependent() || Subtarget->isROPI()) {
     Addr =
         DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
                     MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
   }
 
   unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
   return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
 }
 
 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
                                            const ARMSubtarget *ST) const {
-  if (!ST->hasVFP3())
-    return SDValue();
-
   bool IsDouble = Op.getValueType() == MVT::f64;
   ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
+  const APFloat &FPVal = CFP->getValueAPF();
+
+  // Prevent floating-point constants from using literal loads
+  // when execute-only is enabled.
+  if (ST->genExecuteOnly()) {
+    APInt INTVal = FPVal.bitcastToAPInt();
+    SDLoc DL(CFP);
+    if (IsDouble) {
+      SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
+      SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
+      if (!ST->isLittle())
+        std::swap(Lo, Hi);
+      return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
+    } else {
+      return DAG.getConstant(INTVal, DL, MVT::i32);
+    }
+  }
+
+  if (!ST->hasVFP3())
+    return SDValue();
 
   // Use the default (constant pool) lowering for double constants when we have
   // an SP-only FPU
   if (IsDouble && Subtarget->isFPOnlySP())
     return SDValue();
 
   // Try splatting with a VMOV.f32...
-  const APFloat &FPVal = CFP->getValueAPF();
   int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
 
   if (ImmVal != -1) {
     if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
       // We have code in place to select a valid ConstantFP already, no need to
       // do any mangling.
       return Op;
     }
static SDValue LowerFPOWI(SDValue Op, const ARMSubtarget &Subtarget,
   // Return the chain (the DAG root) if it is a tail call
   return !CI.second.getNode() ? DAG.getRoot() : CI.first;
 }
 
 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   default: llvm_unreachable("Don't know how to custom lower this!");
   case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
-  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
+  case ISD::ConstantPool:
+    if (Subtarget->genExecuteOnly())
+      llvm_unreachable("execute-only should not generate constant pools");
+    return LowerConstantPool(Op, DAG);
   case ISD::BlockAddress:  return LowerBlockAddress(Op, DAG);
   case ISD::GlobalAddress:
     switch (Subtarget->getTargetTriple().getObjectFormat()) {
     default: llvm_unreachable("unknown object format");
     case Triple::COFF:
       return LowerGlobalAddressWindows(Op, DAG);
     case Triple::ELF:
       return LowerGlobalAddressELF(Op, DAG);

lib/Target/ARM/ARMInstrFormats.td

 // PseudoInst that's Thumb-mode only.
 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
                     list<dag> pattern>
   : PseudoInst<oops, iops, itin, pattern> {
   let Size = sz;
   list<Predicate> Predicates = [IsThumb];
 }
 
+// PseudoInst that's in ARMv8-M baseline (Somewhere between Thumb and Thumb2)
+class t2basePseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
+                    list<dag> pattern>
+  : PseudoInst<oops, iops, itin, pattern> {
+  let Size = sz;
+  list<Predicate> Predicates = [IsThumb,HasV8MBaseline];
+}
+
 // PseudoInst that's Thumb2-mode only.
 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
                     list<dag> pattern>
   : PseudoInst<oops, iops, itin, pattern> {
   let Size = sz;
   list<Predicate> Predicates = [IsThumb2];
 }
 

lib/Target/ARM/ARMInstrInfo.td

 def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"
                           "!Subtarget->useNEONForSinglePrecisionFP()">;
 def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
                               "Subtarget->useNEONForSinglePrecisionFP()">;
 
 def IsLE             : Predicate<"MF->getDataLayout().isLittleEndian()">;
 def IsBE             : Predicate<"MF->getDataLayout().isBigEndian()">;
 
+def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
+
 //===----------------------------------------------------------------------===//
 // ARM Flag Definitions.
 
 class RegConstraint<string C> {
   string Constraints = C;
 }
 
 //===----------------------------------------------------------------------===//

lib/Target/ARM/ARMInstrThumb2.td

def t2B   : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,
   let Inst{11} = target{21};
   let Inst{25-16} = target{20-11};
   let Inst{10-0} = target{10-0};
   let DecoderMethod = "DecodeT2BInstruction";
   let AsmMatchConverter = "cvtThumbBranches";
 }
 
 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
-def t2BR_JT : t2PseudoInst<(outs),
+
+// available in both v8-M.Baseline and Thumb2 targets
+def t2BR_JT : t2basePseudoInst<(outs),
           (ins GPR:$target, GPR:$index, i32imm:$jt),
            0, IIC_Br,
           [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
           Sched<[WriteBr]>;
 
 // FIXME: Add a case that can be predicated.
 def t2TBB_JT : t2PseudoInst<(outs),
         (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,

lib/Target/ARM/ARMMCInstLower.cpp

bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
   case MachineOperand::MO_ExternalSymbol:
     MCOp = GetSymbolRef(MO,
                         GetExternalSymbolSymbol(MO.getSymbolName()));
     break;
   case MachineOperand::MO_JumpTableIndex:
     MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
     break;
   case MachineOperand::MO_ConstantPoolIndex:
+    if (Subtarget->genExecuteOnly())
+      llvm_unreachable("execute-only should not generate constant pools");
     MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
     break;
   case MachineOperand::MO_BlockAddress:
     MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
     break;
   case MachineOperand::MO_FPImmediate: {
     APFloat Val = MO.getFPImm()->getValueAPF();
     bool ignored;

lib/Target/ARM/ARMSubtarget.h

protected:
   bool HasDSP = false;
 
   /// NaCl TRAP instruction is generated instead of the regular TRAP.
   bool UseNaClTrap = false;
 
   /// Generate calls via indirect call instructions.
   bool GenLongCalls = false;
 
+  /// Generate code that does not contain data access to code sections.
+  bool GenExecuteOnly = false;
+
   /// Target machine allowed unsafe FP math (such as use of NEON fp)
   bool UnsafeFPMath = false;
 
   /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
   bool UseSjLjEH = false;
 
   /// stackAlignment - The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
public:
   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
   bool hasRetAddrStack() const { return HasRetAddrStack; }
   bool hasMPExtension() const { return HasMPExtension; }
   bool hasDSP() const { return HasDSP; }
   bool useNaClTrap() const { return UseNaClTrap; }
   bool useSjLjEH() const { return UseSjLjEH; }
   bool genLongCalls() const { return GenLongCalls; }
+  bool genExecuteOnly() const { return GenExecuteOnly; }
 
   bool hasFP16() const { return HasFP16; }
   bool hasD16() const { return HasD16; }
   bool hasFullFP16() const { return HasFullFP16; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }

lib/Target/ARM/ARMSubtarget.cpp

 /// so that we can use initializer lists for subtarget initialization.
 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {
   initializeEnvironment();
   initSubtargetFeatures(CPU, FS);
   return *this;
 }
 
+/// EnableExecuteOnly - Enables the generation of execute-only code on supported
+/// targets
+static cl::opt<bool>
+EnableExecuteOnly("arm-execute-only");
+
 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
                                                         StringRef FS) {
   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
   if (STI.isThumb1Only())
     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
 
   return new ARMFrameLowering(STI);
 }
 
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle)
     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
-      TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
+      TM(TM), GenExecuteOnly(EnableExecuteOnly),
+      FrameLowering(initializeFrameLowering(CPU, FS)),
       // At this point initializeSubtargetDependencies has been called so
       // we can query directly.
       InstrInfo(isThumb1Only()
                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
                     : !isThumb()
                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
       TLInfo(TM, *this), GISel() {}
else
       ArchFS = FS;
   }
   ParseSubtargetFeatures(CPUString, ArchFS);
 
   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
+  // Execute only support requires movt support
+  if (genExecuteOnly())
+    assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
+
   // Keep a pointer to static instruction cost data for the specified CPU.
   SchedModel = getSchedModelForCPU(CPUString);
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 
   // FIXME: this is invalid for WindowsCE
   if (isTargetWindows())
bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
 }
 
 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
   // immediates as it is inherently position independent, and may be out of
   // range otherwise.
   return !NoMovt && hasV8MBaselineOps() &&
-         (isTargetWindows() || !MF.getFunction()->optForMinSize());
+         (isTargetWindows() || !MF.getFunction()->optForMinSize() || genExecuteOnly());
 }
 
 bool ARMSubtarget::useFastISel() const {
   // Enable fast-isel for any target, for testing only.
   if (ForceFastISel)
     return true;
 
   // Limit fast-isel to the targets that are or have been tested.
   if (!hasV6Ops())
     return false;
 
   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
   return TM.Options.EnableFastISel &&
          ((isTargetMachO() && !isThumb1Only()) ||
           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
 }

lib/Target/ARM/ARMTargetObjectFile.h

 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 
 namespace llvm {
 
 class MCContext;
 class TargetMachine;
 
 class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {
+  mutable bool genExecuteOnly = false;
 protected:
   const MCSection *AttributesSection;
 public:
   ARMElfTargetObjectFile()
       : TargetLoweringObjectFileELF(), AttributesSection(nullptr) {
     PLTRelativeVariantKind = MCSymbolRefExpr::VK_ARM_PREL31;
   }
 
   void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
 
   const MCExpr *getTTypeGlobalReference(const GlobalValue *GV,
                                         unsigned Encoding,
                                         const TargetMachine &TM,
                                         MachineModuleInfo *MMI,
                                         MCStreamer &Streamer) const override;
 
   /// \brief Describe a TLS variable address within debug info.
   const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override;
+
+  MCSection *getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind,
+                                      const TargetMachine &TM) const override;
+
+  MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind,
+                                    const TargetMachine &TM) const override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/ARM/ARMTargetObjectFile.cpp

 using namespace dwarf;
 
 //===----------------------------------------------------------------------===//
 //                               ELF Target
 //===----------------------------------------------------------------------===//
 
 void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
                                         const TargetMachine &TM) {
-  bool isAAPCS_ABI = static_cast<const ARMTargetMachine &>(TM).TargetABI ==
-                     ARMTargetMachine::ARMABI::ARM_ABI_AAPCS;
+  const ARMTargetMachine &ARM_TM = static_cast<const ARMTargetMachine &>(TM);
+  bool isAAPCS_ABI = ARM_TM.TargetABI == ARMTargetMachine::ARMABI::ARM_ABI_AAPCS;
+  genExecuteOnly = ARM_TM.getSubtargetImpl()->genExecuteOnly();
+
   TargetLoweringObjectFileELF::Initialize(Ctx, TM);
   InitializeELF(isAAPCS_ABI);
 
   if (isAAPCS_ABI) {
     LSDASection = nullptr;
   }
 
   AttributesSection =
       getContext().getELFSection(".ARM.attributes", ELF::SHT_ARM_ATTRIBUTES, 0);
+
+  // Make code section unreadable when in execute-only mode
+  if (genExecuteOnly) {
+    unsigned  Type = ELF::SHT_PROGBITS;
+    unsigned Flags = ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_ARM_PURECODE;
+    // Since we cannot modify flags for an existing section, we create a new
+    // section with the right flags, and use 0 as the unique ID for
+    // execute-only text
+    TextSection = Ctx.getELFSection(".text", Type, Flags, 0, "", 0U);
+  }
 }
 
 const MCExpr *ARMElfTargetObjectFile::getTTypeGlobalReference(
     const GlobalValue *GV, unsigned Encoding, const TargetMachine &TM,
     MachineModuleInfo *MMI, MCStreamer &Streamer) const {
   if (TM.getMCAsmInfo()->getExceptionHandlingType() != ExceptionHandling::ARM)
     return TargetLoweringObjectFileELF::getTTypeGlobalReference(
         GV, Encoding, TM, MMI, Streamer);
 
   assert(Encoding == DW_EH_PE_absptr && "Can handle absptr encoding only");
 
   return MCSymbolRefExpr::create(TM.getSymbol(GV),
                                  MCSymbolRefExpr::VK_ARM_TARGET2, getContext());
 }
 
 const MCExpr *ARMElfTargetObjectFile::
 getDebugThreadLocalSymbol(const MCSymbol *Sym) const {
   return MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_ARM_TLSLDO,
                                  getContext());
 }
+
+MCSection *
+ARMElfTargetObjectFile::getExplicitSectionGlobal(const GlobalObject *GO,
+                                                 SectionKind SK, const TargetMachine &TM) const {
+  // Set execute-only access for the explicit section
+  if (genExecuteOnly && SK.isText())
+    SK = SectionKind::getExecuteOnly();
+
+  return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);
+}
+
+MCSection *
+ARMElfTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO,
+                                               SectionKind SK, const TargetMachine &TM) const {
+  // Place the global in the execute-only text section
+  if (genExecuteOnly && SK.isText())
+    SK = SectionKind::getExecuteOnly();
+
+  return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, SK, TM);
+}

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case AsmToken::Equal: {
     S = Parser.getTok().getLoc();
     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
       return Error(S, "unexpected token in operand");
     Parser.Lex(); // Eat '='
     const MCExpr *SubExprVal;
     if (getParser().parseExpression(SubExprVal))
       return true;
     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+
+    // execute-only: we assume that assembly programmers know what they are
+    // doing and allow literal pool creation here
     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
     return false;
   }
   }
 }
 
 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
 //  :lower16: and :upper16:.

lib/Target/ARM/ThumbRegisterInfo.cpp

 /// in a register using mov / mvn sequences or load the immediate from a
 /// constpool entry.
 static void emitThumbRegPlusImmInReg(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
     const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes,
     bool CanChangeCC, const TargetInstrInfo &TII,
     const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) {
   MachineFunction &MF = *MBB.getParent();
+  const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
   bool isHigh = !isARMLowRegister(DestReg) ||
                 (BaseReg != 0 && !isARMLowRegister(BaseReg));
   bool isSub = false;
   // Subtract doesn't have high register version. Load the negative value
   // if either base or dest register is a high register. Also, if do not
   // issue sub as part of the sequence if condition register is to be
   // preserved.
   if (NumBytes < 0 && !isHigh && CanChangeCC) {
AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
         .setMIFlags(MIFlags);
   } else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
     AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
         .addImm(NumBytes)
         .setMIFlags(MIFlags);
     AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
         .addReg(LdReg, RegState::Kill)
         .setMIFlags(MIFlags);
+  } else if (ST.genExecuteOnly()) {
+    BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg)
+      .addImm(NumBytes).setMIFlags(MIFlags);
   } else
     MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes, ARMCC::AL, 0,
                           MIFlags);
 
   // Emit add / sub.
   int Opc = (isSub) ? ARM::tSUBrr
                     : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);
   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
#endif // NDEBUG
   if (PIdx != -1)
     removeOperands(MI, PIdx);
 
   if (MI.mayLoad()) {
     // Use the destination register to materialize sp + offset.
     unsigned TmpReg = MI.getOperand(0).getReg();
     bool UseRR = false;
     if (Opcode == ARM::tLDRspi) {
-      if (FrameReg == ARM::SP)
+      if (FrameReg == ARM::SP || STI.genExecuteOnly())
         emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
                                  Offset, false, TII, *this);
       else {
         emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
         UseRR = true;
       }
     } else {
       emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
                                 *this);
     }
 
     MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
     MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
     if (UseRR)
       // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
       // register. The offset is already handled in the vreg value.
       MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
                                                      false);
   } else if (MI.mayStore()) {
       VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
       bool UseRR = false;
 
       if (Opcode == ARM::tSTRspi) {
-        if (FrameReg == ARM::SP)
+        if (FrameReg == ARM::SP || STI.genExecuteOnly())
           emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
                                    Offset, false, TII, *this);
         else {
           emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
           UseRR = true;
         }
       } else
         emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,

test/CodeGen/ARM/constantfp.ll

 ; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s
 ; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s
 ; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s
 
+; RUN: llc -mtriple=thumbv7m -mcpu=cortex-m4 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
+
+; RUN: llc -mtriple=thumbv7m -arm-execute-only -mcpu=cortex-m4 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
+
+; RUN: llc -mtriple=thumbv7meb -arm-execute-only -mcpu=cortex-m4 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=fp-armv8 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
+
+; RUN: llc -mtriple=thumbv8m.main -arm-execute-only -mattr=fp-armv8 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
+
+; RUN: llc -mtriple=thumbv8m.maineb -arm-execute-only -mattr=fp-armv8 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s
+
+
 define arm_aapcs_vfpcc float @test_vmov_f32() {
 ; CHECK-LABEL: test_vmov_f32:
 ; CHECK: vmov.f32 d0, #1.0
 
 ; CHECK-NONEONFP: vmov.f32 s0, #1.0
   ret float 1.0
 }
 
 define arm_aapcs_vfpcc float @test_vmov_imm() {
 ; CHECK-LABEL: test_vmov_imm:
 ; CHECK: vmov.i32 d0, #0
 
 ; CHECK-NONEON-LABEL: test_vmov_imm:
 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-NO-XO-LABEL: test_vmov_imm:
+; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-FLOAT-LABEL: test_vmov_imm:
+; CHECK-XO-FLOAT: movs [[REG:r[0-9]+]], #0
+; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]]
+; CHECK-XO-FLOAT-NOT: vldr
   ret float 0.0
 }
 
 define arm_aapcs_vfpcc float @test_vmvn_imm() {
 ; CHECK-LABEL: test_vmvn_imm:
 ; CHECK: vmvn.i32 d0, #0xb0000000
 
 ; CHECK-NONEON-LABEL: test_vmvn_imm:
 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-NO-XO-LABEL: test_vmvn_imm:
+; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-FLOAT-LABEL: test_vmvn_imm:
+; CHECK-XO-FLOAT: mvn [[REG:r[0-9]+]], #-1342177280
+; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]]
+; CHECK-XO-FLOAT-NOT: vldr
   ret float 8589934080.0
 }
 
 define arm_aapcs_vfpcc double @test_vmov_f64() {
 ; CHECK-LABEL: test_vmov_f64:
 ; CHECK: vmov.f64 d0, #1.0
 
 ; CHECK-NONEON-LABEL: test_vmov_f64:
 ; CHECK-NONEON: vmov.f64 d0, #1.0
 
   ret double 1.0
 }
 
 define arm_aapcs_vfpcc double @test_vmov_double_imm() {
 ; CHECK-LABEL: test_vmov_double_imm:
 ; CHECK: vmov.i32 d0, #0
 
 ; CHECK-NONEON-LABEL: test_vmov_double_imm:
 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-NO-XO-LABEL: test_vmov_double_imm:
+; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-DOUBLE-LABEL: test_vmov_double_imm:
+; CHECK-XO-DOUBLE: movs [[REG:r[0-9]+]], #0
+; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
+; CHECK-XO-DOUBLE-NOT: vldr
+
+; CHECK-XO-DOUBLE-BE-LABEL: test_vmov_double_imm:
+; CHECK-XO-DOUBLE-BE: movs [[REG:r[0-9]+]], #0
+; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
+; CHECK-XO-DOUBLE-NOT: vldr
   ret double 0.0
 }
 
 define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
 ; CHECK-LABEL: test_vmvn_double_imm:
 ; CHECK: vmvn.i32 d0, #0xb0000000
 
 ; CHECK-NONEON-LABEL: test_vmvn_double_imm:
 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-NO-XO-LABEL: test_vmvn_double_imm:
+; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-DOUBLE-LABEL: test_vmvn_double_imm:
+; CHECK-XO-DOUBLE: mvn [[REG:r[0-9]+]], #-1342177280
+; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
+; CHECK-XO-DOUBLE-NOT: vldr
+
+; CHECK-XO-DOUBLE-BE-LABEL: test_vmvn_double_imm:
+; CHECK-XO-DOUBLE-BE: mvn [[REG:r[0-9]+]], #-1342177280
+; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
+; CHECK-XO-DOUBLE-BE-NOT: vldr
   ret double 0x4fffffff4fffffff
 }
 
 ; Make sure we don't ignore the high half of 64-bit values when deciding whether
 ; a vmov/vmvn is possible.
 define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
 ; CHECK-LABEL: test_notvmvn_double_imm:
 ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-NONEON-LABEL: test_notvmvn_double_imm:
 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-NO-XO-LABEL: test_notvmvn_double_imm:
+; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-DOUBLE-LABEL: test_notvmvn_double_imm:
+; CHECK-XO-DOUBLE: mvn [[REG1:r[0-9]+]], #-1342177280
+; CHECK-XO-DOUBLE: mov.w [[REG2:r[0-9]+]], #-1
+; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-XO-DOUBLE-NOT: vldr
+
+; CHECK-XO-DOUBLE-BE-LABEL: test_notvmvn_double_imm:
+; CHECK-XO-DOUBLE-BE: mov.w [[REG1:r[0-9]+]], #-1
+; CHECK-XO-DOUBLE-BE: mvn [[REG2:r[0-9]+]], #-1342177280
+; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-XO-DOUBLE-BE-NOT: vldr
   ret double 0x4fffffffffffffff
 }
+
+define arm_aapcs_vfpcc float @lower_const_f32_xo() {
+; CHECK-NO-XO-LABEL: lower_const_f32_xo
+; CHECK-NO-XO: vldr {{s[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-FLOAT-LABEL: lower_const_f32_xo
+; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], #29884
+; CHECK-XO-FLOAT: movt [[REG]], #16083
+; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]]
+; CHECK-XO-FLOAT-NOT: vldr
+  ret float 0x3FDA6E9780000000
+}
+
+define arm_aapcs_vfpcc double @lower_const_f64_xo() {
+; CHECK-NO-XO-LABEL: lower_const_f64_xo
+; CHECK-NO-XO: vldr {{d[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
+
+; CHECK-XO-DOUBLE-LABEL: lower_const_f64_xo
+; CHECK-XO-DOUBLE: movw [[REG1:r[0-9]+]], #6291
+; CHECK-XO-DOUBLE: movw [[REG2:r[0-9]+]], #27263
+; CHECK-XO-DOUBLE: movt [[REG1]], #16340
+; CHECK-XO-DOUBLE: movt [[REG2]], #29884
+; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-XO-DOUBLE-NOT: vldr
+
+; CHECK-XO-DOUBLE-BE-LABEL: lower_const_f64_xo
+; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #27263
+; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #6291
+; CHECK-XO-DOUBLE-BE: movt [[REG1]], #29884
+; CHECK-XO-DOUBLE-BE: movt [[REG2]], #16340
+; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-XO-DOUBLE-BE-NOT: vldr
+  ret double 3.140000e-01
+}

test/CodeGen/ARM/execute-only-big-stack-frame.ll

+; RUN: llc < %s -mtriple=thumbv7m -arm-execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
+; RUN: llc < %s -mtriple=thumbv8m.base -arm-execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
+; RUN: llc < %s -mtriple=thumbv8m.main -arm-execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
+
+define i8 @test_big_stack_frame() {
+; CHECK-SUBW-ADDW-LABEL: test_big_stack_frame:
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       sub.w sp, sp, #65536
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       add.w [[REG1:r[0-9]+]], sp, #255
+; CHECK-SUBW-ADDW:       add.w {{r[0-9]+}}, [[REG1]], #65280
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       add.w lr, sp, #61440
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       add.w sp, sp, #65536
+
+; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG1:r[0-9]+]], #0
+; CHECK-MOVW-MOVT-ADD:       movt [[REG1]], #65535
+; CHECK-MOVW-MOVT-ADD:       add sp, [[REG1]]
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG2:r[0-9]+]], #65532
+; CHECK-MOVW-MOVT-ADD:       movt [[REG2]], #0
+; CHECK-MOVW-MOVT-ADD:       add [[REG2]], sp
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG3:r[0-9]+]], #65532
+; CHECK-MOVW-MOVT-ADD:       movt [[REG3]], #0
+; CHECK-MOVW-MOVT-ADD:       add [[REG3]], sp
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG4:r[0-9]+]], #0
+; CHECK-MOVW-MOVT-ADD:       movt [[REG4]], #1
+; CHECK-MOVW-MOVT-ADD:       add sp, [[REG4]]
+
+entry:
+  %s1 = alloca i8
+  %buffer = alloca [65528 x i8], align 1
+  call void @foo(i8* %s1)
+  %load = load i8, i8* %s1
+  ret i8 %load
+}
+
+declare void @foo(i8*)

test/CodeGen/ARM/execute-only-section.ll

+; RUN: llc < %s -mtriple=thumbv7m -arm-execute-only %s -o - | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8m.base -arm-execute-only %s -o - | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8m.main -arm-execute-only %s -o - | FileCheck %s
+
+; CHECK:     .section .text,"axy",%progbits,unique,0
+; CHECK-NOT: .section
+; CHECK-NOT: .text
+; CHECK:     .globl test_SectionForGlobal
+; CHECK:     .type test_SectionForGlobal,%function
+define void @test_SectionForGlobal() {
+entry:
+  ret void
+}
+
+; CHECK:     .section .test,"axy",%progbits
+; CHECK-NOT: .section
+; CHECK-NOT: .text
+; CHECK:     .globl test_ExplicitSectionForGlobal
+; CHECK:     .type test_ExplicitSectionForGlobal,%function
+define void @test_ExplicitSectionForGlobal() section ".test" {
+entry:
+  ret void
+}

test/CodeGen/ARM/execute-only.ll

+; RUN: llc -mtriple=thumbv8m.base-eabi -arm-execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
+; RUN: llc -mtriple=thumbv7m-eabi      -arm-execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
+; RUN: llc -mtriple=thumbv8m.main-eabi -arm-execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
+
+@var = global i32 0
+
+define i32 @global() minsize {
+; CHECK-LABEL: global:
+; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
+; CHECK: movt [[GLOBDEST]], :upper16:var
+
+  %val = load i32, i32* @var
+  ret i32 %val
+}
+
+define i32 @jump_table(i32 %c, i32 %a, i32 %b) #0 {
+; CHECK-LABEL: jump_table:
+; CHECK-T2: adr.w   [[REG_JT:r[0-9]+]], .LJTI1_0
+; CHECK-T2: add.w   [[REG_ENTRY:r[0-9]+]], [[REG_JT]], {{r[0-9]+}}, lsl #2
+; CHECK-T2: mov     pc, [[REG_ENTRY]]
+
+; CHECK-T2BASE: lsls    [[REG_OFFSET:r[0-9]+]], {{r[0-9]+}}, #2
+; CHECK-T2BASE: adr     [[REG_JT:r[0-9]+]], .LJTI1_0
+; CHECK-T2BASE: adds    [[REG_ENTRY:r[0-9]+]], [[REG_OFFSET]], [[REG_JT]]
+; CHECK-T2BASE: mov     pc, [[REG_ENTRY]]
+
+; CHECK-LABEL: .LJTI1_0:
+; CHECK-NEXT: b.w
+; CHECK-NEXT: b.w
+; CHECK-NEXT: b.w
+; CHECK-NEXT: b.w
+; CHECK-NEXT: b.w
+; CHECK-NEXT: b.w
+
+entry:
+  switch i32 %c, label %return [
+    i32 1, label %sw.bb
+    i32 2, label %sw.bb1
+    i32 3, label %sw.bb3
+    i32 4, label %sw.bb4
+    i32 5, label %sw.bb6
+    i32 6, label %sw.bb8
+  ]
+
+sw.bb:                                            ; preds = %entry
+  %add = add nsw i32 %a, 6
+  br label %return
+
+sw.bb1:                                           ; preds = %entry
+  %add2 = add nsw i32 %a, 4
+  br label %return
+
+sw.bb3:                                           ; preds = %entry
+  %sub = add nsw i32 %a, -3
+  br label %return
+
+sw.bb4:                                           ; preds = %entry
+  %add5 = add nsw i32 %b, 5
+  br label %return
+
+sw.bb6:                                           ; preds = %entry
+  %add7 = add nsw i32 %a, 1
+  br label %return
+
+sw.bb8:                                           ; preds = %entry
+  %add9 = add nsw i32 %a, 2
+  br label %return
+
+return:                                           ; preds = %entry, %sw.bb8, %sw.bb6, %sw.bb4, %sw.bb3, %sw.bb1, %sw.bb
+  %retval.0 = phi i32 [ %add9, %sw.bb8 ], [ %add7, %sw.bb6 ], [ %add5, %sw.bb4 ], [ %sub, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+@.str = private unnamed_addr constant [4 x i8] c"FOO\00", align 1
+
+define hidden i8* @string_literal() {
+entry:
+; CHECK-LABEL: string_literal:
+; CHECK-NOT: .asciz
+; CHECK: .fnend
+    ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0)
+}

test/MC/ELF/ARM/execute-only-section.s

+// RUN: llvm-mc -filetype=obj -triple thumbv7m-arm-linux-gnu %s -o - \
+// RUN: | llvm-readobj -s -t | FileCheck %s
+
+        .section        .text,"axy",%progbits,unique,0
+        .globl  foo
+        .align  2
+        .type   foo,%function
+        .code   16
+        .thumb_func
+foo:
+        .fnstart
+        bx      lr
+.Lfunc_end0:
+        .size   foo, .Lfunc_end0-foo
+        .fnend
+
+        .section        ".note.GNU-stack","",%progbits
+
+
+// CHECK:      Section {
+// CHECK:        Name: .text (16)
+// CHECK-NEXT:   Type: SHT_PROGBITS (0x1)
+// CHECK-NEXT:   Flags [ (0x6)
+// CHECK-NEXT:     SHF_ALLOC (0x2)
+// CHECK-NEXT:     SHF_EXECINSTR (0x4)
+// CHECK-NEXT:   ]
+// CHECK:        Size: 0
+// CHECK:      }
+
+// CHECK:      Section {
+// CHECK:        Name: .text (16)
+// CHECK-NEXT:   Type: SHT_PROGBITS (0x1)
+// CHECK-NEXT:   Flags [ (0x20000006)
+// CHECK-NEXT:     SHF_ALLOC (0x2)
+// CHECK-NEXT:     SHF_ARM_PURECODE (0x20000000)
+// CHECK-NEXT:     SHF_EXECINSTR (0x4)
+// CHECK-NEXT:   ]
+// CHECK:        Size: 2
+// CHECK:      }
+
+// CHECK: Symbol {
+// CHECK:   Name: foo (22)
+// CHECK:   Section: .text (0x3)
+// CHECK: }

tools/llvm-readobj/ELFDumper.cpp

 
 static const EnumEntry<unsigned> ElfAMDGPUSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_GLOBAL),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_READONLY),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_CODE),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_AGENT)
 };
 
+static const EnumEntry<unsigned> ElfARMSectionFlags[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_ARM_PURECODE)
+};
+
 static const EnumEntry<unsigned> ElfHexagonSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_HEX_GPREL)
 };
 
 static const EnumEntry<unsigned> ElfMipsSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NODUPES),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NAMES  ),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_LOCAL  ),
W.printHex("Type",
                Sec.sh_type);
     std::vector<EnumEntry<unsigned>> SectionFlags(std::begin(ElfSectionFlags),
                                                   std::end(ElfSectionFlags));
     switch (Obj->getHeader()->e_machine) {
     case EM_AMDGPU:
       SectionFlags.insert(SectionFlags.end(), std::begin(ElfAMDGPUSectionFlags),
                           std::end(ElfAMDGPUSectionFlags));
       break;
+    case EM_ARM:
+      SectionFlags.insert(SectionFlags.end(), std::begin(ElfARMSectionFlags),
+                          std::end(ElfARMSectionFlags));
+      break;
     case EM_HEXAGON:
       SectionFlags.insert(SectionFlags.end(),
                           std::begin(ElfHexagonSectionFlags),
                           std::end(ElfHexagonSectionFlags));
       break;
     case EM_MIPS:
       SectionFlags.insert(SectionFlags.end(), std::begin(ElfMipsSectionFlags),
                           std::end(ElfMipsSectionFlags));