[ARM] generate armv6m eXecute Only (XO) code

[stuij]

Summary

[ARM] generate armv6m eXecute Only (XO) code for immediates, globals

Previously eXecute Only (XO) support was implemented for targets that support
MOVW/MOVT (~armv7+). See: https://reviews.llvm.org/D27449

XO prevents the compiler from generating data accesses to code sections. This
patch implements XO codegen for armv6-M, which does not support MOVW/MOVT, and
must resort to the following general pattern to avoid loads:

movs    r3, :upper8_15:foo
lsls    r3, #8
adds    r3, :upper0_7:foo
lsls    r3, #8
adds    r3, :lower8_15:foo
lsls    r3, #8
adds    r3, :lower0_7:foo
ldr     r3, [r3]

This is equivalent to the code pattern generated by GCC.

The above relocations are new to LLVM and have been implemented in a parent
patch: https://reviews.llvm.org/D149443.

This patch limits itself to implementing codegen for this pattern and enabling
XO for armv6-M in the backend.

Separate patches will follow for:

• switch tables
• replacing specific loads from constant islands which are spread out over the ARM backend codebase. Amongst others: FastISel, call lowering, stack frames.

[stuij]

moved some code from ARMSubtarget.cpp from D149444 to here

[stuij]

fix remaining known bug and clean up code

[john.brawn]

llvm/lib/Target/ARM/ARMISelLowering.cpp

3962

This should be genExecuteOnly, as it's not thumb1-specific that we want to avoid generating a constant pool, it's just that up until now execute-only implied useMovt.

llvm/lib/Target/ARM/ARMInstrThumb.td

1613

This should be tMOVi32imm for consistency with everything else (all other 16-bit thumb instructions, or pseudoinstructions that expand to 16-bit thumb instructions, are named tSomething).

llvm/lib/Target/ARM/ARMPredicates.td

227–228

I don't think having a genT1ExecuteOnly predicate is a good idea, as it combines a bunch of things which makes things less clear when looking at the tablegen files. I think what we need is:

• DontGenExecuteOnly which is just the negation of GenExecuteOnly
• Patterns that are Requires<[GenT1ExecuteOnly]> are instead Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>
• tLDRLIT_ga_abs should have Requires<[IsThumb, DontUseMovt, DontGenExecuteOnly]>

[stuij]

address review comments

[stuij]

llvm/lib/Target/ARM/ARMISelLowering.cpp

3962

right, thanks! I'm guessing you meant just changing genT1ExecuteOnly to genExecuteOnly, as we still want to generate MOVW/MOVT for efficiency.

llvm/lib/Target/ARM/ARMInstrThumb.td

1613

Thanks. Yes, I had that initially, but then opted for t1, as it's just clearer. I do agree in hindsight that following convention is better here.

llvm/lib/Target/ARM/ARMPredicates.td

227–228

The reason why I decided to create GenT1ExecuteOnly, was actually because UseMovt itself is using a bunch of things which make sense for the specific use case of using MOVT, but it can't be used for just the negation of the MOVT instruction being there:

bool ARMSubtarget::useMovt() const {
  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
  // immediates as it is inherently position independent, and may be out of
  // range otherwise.
  return !NoMovt && hasV8MBaselineOps() &&
         (isTargetWindows() || !OptMinSize || genExecuteOnly());
}

It becomes confusing to use useMovt in for example this case where people will conflate useMovt with the MOVT instruction being there or not. And in this case, we're pulling things in that we might not. Things like isTargetWindows aren't relevant here and genXO is orthogonal in our use case.

I would myself prefer being clear about our intent: generating XO for T1, which is captured by GenT1ExecuteOnly. It's not obvious to someone looking at the code that the clauses which make up the decision for generating t1 code are related (I bet not everyone knows the check for armv8m.base is there because it is mostly T1, but does include movw/movt). Just looking at the predicate list doesn't make these details clear.

[jhenderson]

Did you mean to change llvm/test/tools/llvm-objcopy/ELF/strip-preserve-atime.test in this patch?

[stuij]

In D152795#4437081, @jhenderson wrote:

Did you mean to change llvm/test/tools/llvm-objcopy/ELF/strip-preserve-atime.test in this patch?

No I did not! Will remove.

[stuij]

remove strip-preserve-atime.test changes

[john.brawn]

llvm/lib/Target/ARM/ARMPredicates.td

227–228

Is see. In that case keeping GenT1ExecuteOnly is fine, but I think the logic should move into the predicate itself, i.e.

def GenT1ExecuteOnly : Predicate<"Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()>"

229

This isn't needed as it isn't used anywhere.

[stuij]

address review comments

[stuij]

llvm/lib/Target/ARM/ARMPredicates.td

227–228

done!

[john.brawn]

LGTM, though please run clang-format on this patch before committing (pre-merge is showing a failure for this in ARMExpandPseudoInsts.cpp).

[RKSimon]

@stuij This is breaking on EXPENSIVE_CHECKS builds - please can you take a look? https://lab.llvm.org/buildbot/#/builders/104/builds/12276

[stuij]

@RKSimon: I've disabled the test for now while I figure out what's going on: https://reviews.llvm.org/rG5ddd561cb5e2

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

 void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
                                        raw_ostream &O) {
   assert(MO.isGlobal() && "caller should check MO.isGlobal");
   unsigned TF = MO.getTargetFlags();
   if (TF & ARMII::MO_LO16)
     O << ":lower16:";
   else if (TF & ARMII::MO_HI16)
     O << ":upper16:";
+  else if (TF & ARMII::MO_LO_0_7)
+    O << ":lower0_7:";
+  else if (TF & ARMII::MO_LO_8_15)
+    O << ":lower8_15:";
+  else if (TF & ARMII::MO_HI_0_7)
+    O << ":upper0_7:";
+  else if (TF & ARMII::MO_HI_8_15)
+    O << ":upper8_15:";
+
   GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
   printOffset(MO.getOffset(), O);
 }
 
 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                  raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNum);
 
void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
   }
   case MachineOperand::MO_Immediate: {
     O << '#';
     unsigned TF = MO.getTargetFlags();
     if (TF == ARMII::MO_LO16)
       O << ":lower16:";
     else if (TF == ARMII::MO_HI16)
       O << ":upper16:";
+    else if (TF == ARMII::MO_LO_0_7)
+      O << ":lower0_7:";
+    else if (TF == ARMII::MO_LO_8_15)
+      O << ":lower8_15:";
+    else if (TF == ARMII::MO_HI_0_7)
+      O << ":upper0_7:";
+    else if (TF == ARMII::MO_HI_8_15)
+      O << ":upper8_15:";
     O << MO.getImm();
     break;
   }
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress: {
     PrintSymbolOperand(MO, O);

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
   return true;
 }
 
 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
                                      Register Reg,
                                      MachineRegisterInfo *MRI) const {
   // Fold large immediates into add, sub, or, xor.
   unsigned DefOpc = DefMI.getOpcode();
-  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
+  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm &&
+      DefOpc != ARM::tMOVi32imm)
     return false;
   if (!DefMI.getOperand(1).isImm())
     // Could be t2MOVi32imm @xx
     return false;
 
   if (!MRI->hasOneNonDBGUse(Reg))
     return false;
 
ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
   return std::make_pair(TF & Mask, TF & ~Mask);
 }
 
 ArrayRef<std::pair<unsigned, const char *>>
 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
   using namespace ARMII;
 
   static const std::pair<unsigned, const char *> TargetFlags[] = {
-      {MO_LO16, "arm-lo16"}, {MO_HI16, "arm-hi16"}};
+      {MO_LO16, "arm-lo16"},       {MO_HI16, "arm-hi16"},
+      {MO_LO_0_7, "arm-lo-0-7"},   {MO_HI_0_7, "arm-hi-0-7"},
+      {MO_LO_8_15, "arm-lo-8-15"}, {MO_HI_8_15, "arm-hi-8-15"},
+  };
   return ArrayRef(TargetFlags);
 }
 
 ArrayRef<std::pair<unsigned, const char *>>
 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace ARMII;
 
   static const std::pair<unsigned, const char *> TargetFlags[] = {

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

bool ExpandMI(MachineBasicBlock &MBB,
                   MachineBasicBlock::iterator &NextMBBI);
     bool ExpandMBB(MachineBasicBlock &MBB);
     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
     void ExpandVST(MachineBasicBlock::iterator &MBBI);
     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
                     unsigned Opc, bool IsExt);
     void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI);
+    void ExpandTMOV32BitImm(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator &MBBI);
     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator &MBBI);
     void CMSEClearGPRegs(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
                          const SmallVectorImpl<unsigned> &ClearRegs,
                          unsigned ClobberReg);
     MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MBBI);

 }
 
 static MachineOperand makeImplicit(const MachineOperand &MO) {
   MachineOperand NewMO = MO;
   NewMO.setImplicit();
   return NewMO;
 }
 
+void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
+                                         MachineBasicBlock::iterator &MBBI) {
+  MachineInstr &MI = *MBBI;
+  Register DstReg = MI.getOperand(0).getReg();
+  bool DstIsDead = MI.getOperand(0).isDead();
+  const MachineOperand &MO = MI.getOperand(1);
+  MachineInstrBuilder Upper8_15, LSL_U8_15, Upper0_7, Lower8_15, Lower0_7;
+  unsigned MIFlags = MI.getFlags();
+
+  LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
+
+  Upper8_15 =
+      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tMOVi8), DstReg)
+          .addReg(ARM::CPSR, RegState::Kill);
+
+  LSL_U8_15 =
+      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
+          .addReg(ARM::CPSR, RegState::Kill)
+          .addReg(DstReg)
+          .addImm(8)
+          .add(predOps(ARMCC::AL))
+          .setMIFlags(MIFlags);
+
+  Upper0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
+                 .addReg(ARM::CPSR, RegState::Kill)
+                 .addReg(DstReg);
+
+  MachineInstr *LSL_U0_7 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
+  MBB.insert(MBBI, LSL_U0_7);
+
+  Lower8_15 =
+      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
+          .addReg(ARM::CPSR, RegState::Kill)
+          .addReg(DstReg);
+
+  MachineInstr *LSL_L8_15 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
+  MBB.insert(MBBI, LSL_L8_15);
+
+  Lower0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8))
+                 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+                 .addReg(ARM::CPSR, RegState::Kill)
+                 .addReg(DstReg);
+
+  Upper8_15.setMIFlags(MIFlags);
+  Upper0_7.setMIFlags(MIFlags);
+  Lower8_15.setMIFlags(MIFlags);
+  Lower0_7.setMIFlags(MIFlags);
+
+  switch (MO.getType()) {
+  case MachineOperand::MO_Immediate: {
+    unsigned Imm = MO.getImm();
+    unsigned Hi8_15 = (Imm >> 24) & 0xff;
+    unsigned Hi0_7 = (Imm >> 16) & 0xff;
+    unsigned Lo8_15 = (Imm >> 8) & 0xff;
+    unsigned Lo0_7 = Imm & 0xff;
+    Upper8_15 = Upper8_15.addImm(Hi8_15);
+    Upper0_7 = Upper0_7.addImm(Hi0_7);
+    Lower8_15 = Lower8_15.addImm(Lo8_15);
+    Lower0_7 = Lower0_7.addImm(Lo0_7);
+    break;
+  }
+  case MachineOperand::MO_ExternalSymbol: {
+    const char *ES = MO.getSymbolName();
+    unsigned TF = MO.getTargetFlags();
+    Upper8_15 = Upper8_15.addExternalSymbol(ES, TF | ARMII::MO_HI_8_15);
+    Upper0_7 = Upper0_7.addExternalSymbol(ES, TF | ARMII::MO_HI_0_7);
+    Lower8_15 = Lower8_15.addExternalSymbol(ES, TF | ARMII::MO_LO_8_15);
+    Lower0_7 = Lower0_7.addExternalSymbol(ES, TF | ARMII::MO_LO_0_7);
+    break;
+  }
+  default: {
+    const GlobalValue *GV = MO.getGlobal();
+    unsigned TF = MO.getTargetFlags();
+    Upper8_15 =
+        Upper8_15.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI_8_15);
+    Upper0_7 =
+        Upper0_7.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI_0_7);
+    Lower8_15 =
+        Lower8_15.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO_8_15);
+    Lower0_7 =
+        Lower0_7.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO_0_7);
+    break;
+  }
+  }
+
+  Upper8_15 = Upper8_15.add(predOps(ARMCC::AL));
+  Upper0_7 = Upper0_7.add(predOps(ARMCC::AL));
+  Lower8_15 = Lower8_15.add(predOps(ARMCC::AL));
+  Lower0_7 = Lower0_7.add(predOps(ARMCC::AL));
+
+  MI.eraseFromParent();
+  LLVM_DEBUG(dbgs() << "To:        "; Upper8_15.getInstr()->dump(););
+  LLVM_DEBUG(dbgs() << "And:       "; LSL_U8_15.getInstr()->dump(););
+  LLVM_DEBUG(dbgs() << "And:       "; Upper0_7.getInstr()->dump(););
+  LLVM_DEBUG(dbgs() << "And:       "; LSL_U0_7->dump(););
+  LLVM_DEBUG(dbgs() << "And:       "; Lower8_15.getInstr()->dump(););
+  LLVM_DEBUG(dbgs() << "And:       "; LSL_L8_15->dump(););
+  LLVM_DEBUG(dbgs() << "And:       "; Lower0_7.getInstr()->dump(););
+}
+
 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator &MBBI) {
   MachineInstr &MI = *MBBI;
   unsigned Opcode = MI.getOpcode();
   Register PredReg;
   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
switch (Opcode) {
 
     case ARM::MOVi32imm:
     case ARM::MOVCCi32imm:
     case ARM::t2MOVi32imm:
     case ARM::t2MOVCCi32imm:
       ExpandMOV32BitImm(MBB, MBBI);
       return true;
 
+    case ARM::tMOVi32imm:
+      ExpandTMOV32BitImm(MBB, MBBI);
+      return true;
+
     case ARM::SUBS_PC_LR: {
       MachineInstrBuilder MIB =
           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
               .addReg(ARM::LR)
               .add(MI.getOperand(0))
               .add(MI.getOperand(1))
               .add(MI.getOperand(2))
               .addReg(ARM::CPSR, RegState::Undef);

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

case ISD::SUB:
     // Select special operations if SUB node forms integer ABS pattern
     if (tryABSOp(N))
       return;
     // Other cases are autogenerated.
     break;
   case ISD::Constant: {
     unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
     // If we can't materialize the constant we need to use a literal pool
-    if (ConstantMaterializationCost(Val, Subtarget) > 2) {
+    if (ConstantMaterializationCost(Val, Subtarget) > 2 &&
+        !Subtarget->genExecuteOnly()) {
       SDValue CPIdx = CurDAG->getTargetConstantPool(
           ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
           TLI->getPointerTy(CurDAG->getDataLayout()));
 
       SDNode *ResNode;
       if (Subtarget->isThumb()) {
         SDValue Ops[] = {
           CPIdx,

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (Subtarget->useMovt()) {
           MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
     }
     SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
     SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
     return Result;
   }
 
   // If we have T2 ops, we can materialize the address directly via movt/movw
-  // pair. This is always cheaper.
-  if (Subtarget->useMovt()) {
+  // pair. This is always cheaper. If need to generate Execute Only code, and we
+  // only have Thumb1 available, we can't use a constant pool and are forced to
+  // use immediate relocations.
+  if (Subtarget->useMovt() || Subtarget->genExecuteOnly()) {
+    if (Subtarget->useMovt())
       ++NumMovwMovt;
     // FIXME: Once remat is capable of dealing with instructions with register
     // operands, expand this into two nodes.
     return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
                        DAG.getTargetGlobalAddress(GV, dl, PtrVT));
   } else {
     SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
     CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
     return DAG.getLoad(

llvm/lib/Target/ARM/ARMInstrThumb.td

def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
                                   [(set tGPR:$dst,
                                         (ARMWrapperPIC tglobaladdr:$addr))]>,
                        Requires<[IsThumb, DontUseMovtInPic]>;
 
 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
                                 IIC_iLoad_i,
                                 [(set tGPR:$dst,
                                       (ARMWrapper tglobaladdr:$src))]>,
-                     Requires<[IsThumb, DontUseMovt]>;
+                     Requires<[IsThumb, DontUseMovt, DontGenExecuteOnly]>;
+
+// 32-bit immediate using mov/add with the 4 :lower0_7: to :upper8_15:
+// relocations.
+// This is a single pseudo instruction to make it re-materializable.
+// FIXME: Remove this when we can do generalized remat.
+let isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
+def tMOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,
+                            [(set rGPR:$dst, (i32 imm:$src))]>,
+                            Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>;
+
+def : ARMPat<(ARMWrapper  tglobaladdr :$dst), (tMOVi32imm tglobaladdr :$dst)>,
+            Requires<[GenT1ExecuteOnly]>;
+def : ARMPat<(ARMWrapper texternalsym :$dst), (tMOVi32imm texternalsym :$dst)>,
+            Requires<[GenT1ExecuteOnly]>;
+
 
 // TLS globals
 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
           (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
       Requires<[IsThumb, DontUseMovtInPic]>;
 def : Pat<(ARMWrapper tglobaltlsaddr:$addr),
           (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>,
       Requires<[IsThumb, DontUseMovt]>;

llvm/lib/Target/ARM/ARMMCInstLower.cpp

Expr =
         MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
     Expr = ARMMCExpr::createLower16(Expr, OutContext);
     break;
   case ARMII::MO_HI16:
     Expr =
         MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
     Expr = ARMMCExpr::createUpper16(Expr, OutContext);
     break;
+  case ARMII::MO_LO_0_7:
+    Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
+    Expr = ARMMCExpr::createLower0_7(Expr, OutContext);
+    break;
+  case ARMII::MO_LO_8_15:
+    Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
+    Expr = ARMMCExpr::createLower8_15(Expr, OutContext);
+    break;
+  case ARMII::MO_HI_0_7:
+    Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
+    Expr = ARMMCExpr::createUpper0_7(Expr, OutContext);
+    break;
+  case ARMII::MO_HI_8_15:
+    Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
+    Expr = ARMMCExpr::createUpper8_15(Expr, OutContext);
+    break;
   }
 
   if (!MO.isJTI() && MO.getOffset())
     Expr = MCBinaryExpr::createAdd(Expr,
                                    MCConstantExpr::create(MO.getOffset(),
                                                           OutContext),
                                    OutContext);
   return MCOperand::createExpr(Expr);

llvm/lib/Target/ARM/ARMPredicates.td

def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
                               "Subtarget->useNEONForSinglePrecisionFP()">;
 
 let RecomputePerFunction = 1 in {
   def IsLE             : Predicate<"MF->getDataLayout().isLittleEndian()">;
   def IsBE             : Predicate<"MF->getDataLayout().isBigEndian()">;
 }
 
 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
+def DontGenExecuteOnly : Predicate<"!Subtarget->genExecuteOnly()">;
+def GenT1ExecuteOnly : Predicate<"Subtarget->genExecuteOnly() && "
+                                 "Subtarget->isThumb1Only() && "
+                                 "!Subtarget->hasV8MBaselineOps()">;
 
 // Armv8.5-A extensions
 def HasSB            : Predicate<"Subtarget->hasSB()">,
                        AssemblerPredicate<(all_of FeatureSB), "sb">;
 
 // Armv8.9-A/9.4-A 2022 Architecture extensions
 def HasCLRBHB        : Predicate<"Subtarget->hasCLRBHB()">,
                        AssemblerPredicate<(all_of FeatureCLRBHB), "clrbhb">;

llvm/lib/Target/ARM/ARMSubtarget.cpp

else
       ArchFS = std::string(FS);
   }
   ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
 
   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
+    // Execute only support for >= v8-M Baseline requires movt support
+    if (hasV8MBaselineOps())
       NoMovt = false;
-    assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
+    if (!hasV6MOps())
+      report_fatal_error("Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
   SchedModel = getSchedModelForCPU(CPUString);
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 

llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

enum TOF {
     MO_LO16 = 0x1,
 
     /// MO_HI16 - On a symbol operand, this represents a relocation containing
     /// higher 16 bit of the address. Used only via movt instruction.
     MO_HI16 = 0x2,
 
     /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
     /// just that part of the flag set.
-    MO_OPTION_MASK = 0x3,
+    MO_OPTION_MASK = 0xf03,
 
     /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
     /// reference is actually to the ".refptr.FOO" symbol.  This is used for
     /// stub symbols on windows.
     MO_COFFSTUB = 0x4,
 
     /// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
     MO_GOT = 0x8,
enum TOF {
 
     /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
     /// represents a symbol which, if indirect, will get special Darwin mangling
     /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
     /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
     /// example).
     MO_NONLAZY = 0x80,
 
-    // It's undefined behaviour if an enum overflows the range between its
-    // smallest and largest values, but since these are |ed together, it can
-    // happen. Put a sentinel in (values of this enum are stored as "unsigned
-    // char").
-    MO_UNUSED_MAXIMUM = 0xff
+    /// MO_LO_0_7 - On a symbol operand, this represents a relocation containing
+    /// bits 0 through 7 of the address. Used only with Thumb1 MOV and ADD
+    // instructions.
+    MO_LO_0_7 = 0x100,
+
+    /// MO_LO_8_15 - On a symbol operand, this represents a relocation
+    /// containing
+    /// bits 8 through 15 of the address. Used only with Thumb1 MOV and ADD
+    // instructions.
+    MO_LO_8_15 = 0x200,
+
+    /// MO_HI_0_7 - On a symbol operand, this represents a relocation containing
+    /// bits 16 through 23 of the address. Used only with Thumb1 MOV and ADD
+    // instructions.
+    MO_HI_0_7 = 0x400,
+
+    /// MO_HI_8_15 - On a symbol operand, this represents a relocation
+    /// containing
+    /// bits 24 through 31 of the address. Used only with Thumb1 MOV and ADD
+    // instructions.
+    MO_HI_8_15 = 0x800
   };
 
   enum {
     //===------------------------------------------------------------------===//
     // Instruction Flags.
 
     //===------------------------------------------------------------------===//
     // This four-bit field describes the addressing mode used.

llvm/test/CodeGen/ARM/execute-only-section.ll

+; RUN: llc < %s -mtriple=thumbv6m -mattr=+execute-only %s -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv7m -mattr=+execute-only %s -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv8m.base -mattr=+execute-only %s -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv8m.main -mattr=+execute-only %s -o - | FileCheck %s
 
 ; CHECK:     .section .text,"axy",%progbits,unique,0
 ; CHECK-NOT: .section
 ; CHECK-NOT: .text

llvm/test/CodeGen/ARM/execute-only.ll

 ; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv7m-eabi      -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
 ; RUN: llc -mtriple=thumbv8m.main-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
+; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK-T1 %s
 
 ; CHECK-NOT: {{^ *}}.text{{$}}
 ; CHECK: .section .text,"axy",%progbits,unique,0
 
 @var = global i32 0
 
 define i32 @global() minsize {
 ; CHECK-LABEL: global:
 ; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
-; CHECK: movt [[GLOBDEST]], :upper16:var
+; CHECK-NEXT: movt [[GLOBDEST]], :upper16:var
+; CHECK-T1-LABEL: global:
+; CHECK-T1: movs [[GLOBDEST:r[0-9]+]], :upper8_15:var
+; CHECK-T1-NEXT: lsls [[GLOBDEST]], [[GLOBDEST]], #8
+; CHECK-T1-NEXT: adds [[GLOBDEST]], :upper0_7:var
+; CHECK-T1-NEXT: lsls [[GLOBDEST]], [[GLOBDEST]], #8
+; CHECK-T1-NEXT: adds [[GLOBDEST]], :lower8_15:var
+; CHECK-T1-NEXT: lsls [[GLOBDEST]], [[GLOBDEST]], #8
+; CHECK-T1-NEXT: adds [[GLOBDEST]], :lower0_7:var
 
   %val = load i32, ptr @var
   ret i32 %val
 }
 
 define i32 @jump_table(i32 %c, i32 %a, i32 %b) #0 {
 ; CHECK-LABEL: jump_table:
 ; CHECK-T2: adr.w   [[REG_JT:r[0-9]+]], .LJTI1_0
return:                                           ; preds = %entry, %sw.bb8, %sw.bb6, %sw.bb4, %sw.bb3, %sw.bb1, %sw.bb
   ret i32 %retval.0
 }
 
 @.str = private unnamed_addr constant [4 x i8] c"FOO\00", align 1
 
 define hidden ptr @string_literal() {
 entry:
 ; CHECK-LABEL: string_literal:
-; CHECK-NOT: .asciz
-; CHECK: .fnend
+; CHECK: movw [[STRLIT:r[0-9]+]], :lower16:.L.str
+; CHECK-NEXT: movt [[STRLIT]], :upper16:.L.str
+; CHECK-T1-LABEL: string_literal:
+; CHECK-T1: movs [[STRLIT:r[0-9]+]], :upper8_15:.L.str
+; CHECK-T1-NEXT: lsls [[STRLIT]], [[STRLIT]], #8
+; CHECK-T1-NEXT: adds [[STRLIT]], :upper0_7:.L.str
+; CHECK-T1-NEXT: lsls [[STRLIT]], [[STRLIT]], #8
+; CHECK-T1-NEXT: adds [[STRLIT]], :lower8_15:.L.str
+; CHECK-T1-NEXT: lsls [[STRLIT]], [[STRLIT]], #8
+; CHECK-T1-NEXT: adds [[STRLIT]], :lower0_7:.L.str
+
     ret ptr @.str
 }
+
+@external_global = external global i32
+define i32 @test_external_global() {
+entry:
+; CHECK-LABEL: external_global:
+; CHECK: movw [[EXTGLOB:r[0-9]+]], :lower16:external_global
+; CHECK-NEXT: movt [[EXTGLOB]], :upper16:external_global
+; CHECK-T1-LABEL: external_global:
+; CHECK-T1: movs [[EXTGLOB:r[0-9]+]], :upper8_15:external_global
+; CHECK-T1-NEXT: lsls [[EXTGLOB]], [[EXTGLOB]], #8
+; CHECK-T1-NEXT: adds [[EXTGLOB]], :upper0_7:external_global
+; CHECK-T1-NEXT: lsls [[EXTGLOB]], [[EXTGLOB]], #8
+; CHECK-T1-NEXT: adds [[EXTGLOB]], :lower8_15:external_global
+; CHECK-T1-NEXT: lsls [[EXTGLOB]], [[EXTGLOB]], #8
+; CHECK-T1-NEXT: adds [[EXTGLOB]], :lower0_7:external_global
+
+  %v = load i32, ptr @external_global
+  ret i32 %v
+}