[globalisel] Tablegen-erate current Register Bank Information

[dsanders]

Summary

Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.

[dsanders]

Small correction to fix a use-after-free that only manifested when asan was disabled.

[dsanders]

Rebase

[rovka]

Just a few nitpicks, other than that LGTM (but you should probably wait for someone more experienced to approve).

lib/Target/AArch64/AArch64RegisterBankInfo.h

19 ↗

(On Diff #80417)

I think it's nicer to use a macro that describes what we're trying to include rather than where we're including it, e.g. GET_REGBANK_DECLS or something of the sort. This also seems to be the style used in GenRegisterInfo.inc, GenSubtargetInfo.inc etc.

utils/TableGen/RegisterBankEmitter.cpp

202 ↗

(On Diff #80417)

How about visitRegisterBankClasses? The comment is clear enough on what something like that would mean :)

233 ↗

(On Diff #80417)

I think it would be cleaner to generate a comment instead of a moot assertion if Begin == End or Begin + 1 == End (and then you can also remove the I != End check in the loop).

304 ↗

(On Diff #80417)

Are the calls to .str() really necessary?

309 ↗

(On Diff #80417)

" not first "

[dsanders]

Updated following review:

• Use more descriptive macros when #include'ing tablegen-erated files
• Rename visitor function
• assert Begin!=End and simplify related for-loop.
• Remove redundant .str()'s
• getEnumeratorName() no longer returns a reference to an implicitly constructed local StringRef. This showed up when removing the .str()'s
• last -> first

[dsanders]

Thanks. I've updated the patch.

utils/TableGen/RegisterBankEmitter.cpp

202 ↗

(On Diff #80417)

As you can tell, I struggled to name this one :-). It doesn't really fit with 'overlapping', 'subclasses', 'subsets', etc.

I'll go with visitRegisterBankClasses()

233 ↗

(On Diff #80417)

The caller filters out the Begin == End case on line 303 (since Bank.hasPartialMappings() is a test for Begin != End). I think it's good to explicitly assert that here which leads to the same simplification you suggest.

Is that ok?

304 ↗

(On Diff #80417)

I thought I needed them for type-conversion but apparently not. I've gone through the other .str()'s too.

[rovka]

Thanks, I like the names a lot better now.

utils/TableGen/RegisterBankEmitter.cpp

233 ↗

(On Diff #80417)

Right, good point :)

[ab]

This seems reasonable, but:

• I don't think the PartialMapping exclusion mechanism is necessary. What about adding the missing mappings manually before landing this patch? Alternatively, replace the manual code with a copy of the generated mappings (once you have those) before any tablegen changes? That lets us split the generalization from the NFC tablegen changes without requiring hacks in-between.
• I'm not sure it's useful to generate the asserts: I think the intent was to check 1) the correctness of the manual description, and 2) it being consistent with the eventual tablegen output. Have you considered keeping them in AArch64RegisterBankInfo? I suppose generating them lets all targets have them. @qcolombet: what do you think?
• Also, can you extract the RegisterBank code to a shared location? (CodeGenRegBank? maybe rename it to CodeGenRegisters) ? That'll let us reuse it from the selector emitter backend. We can do that separately though.

utils/TableGen/RegisterBankEmitter.cpp

343 ↗

(On Diff #80593)

<Record *>

[ab]

utils/TableGen/RegisterBankEmitter.cpp

362 ↗

(On Diff #80593)

emitSourceFileHeader ?

[dsanders]

In D27338#618721, @ab wrote:

This seems reasonable, but:

• I don't think the PartialMapping exclusion mechanism is necessary. What about adding the missing mappings manually before landing this patch? Alternatively, replace the manual code with a copy of the generated mappings (once you have those) before any tablegen changes? That lets us split the generalization from the NFC tablegen changes without requiring hacks in-between.

It should be easy enough to add FPR's 8 and 16 mapping and CCR's 32 mapping. I'm not sure about FPR's 192 and 384 mappings though. There's definitely some code that assumes the sizes are a power of 2 (e.g. getRegBankBaseIdxOffset()) but I'm not sure how widespread that assumption is. I'd have to investigate.

• I'm not sure it's useful to generate the asserts: I think the intent was to check 1) the correctness of the manual description, and 2) it being consistent with the eventual tablegen output. Have you considered keeping them in AArch64RegisterBankInfo? I suppose generating them lets all targets have them. @qcolombet: what do you think?

I suppose it depends which direction you look at it. It makes sense to me to have the manual description check that the tablegen part meets its assumptions, but I also think it makes sense to have the tablegen-erated code check that it meets the assumptions of the manual code it's replacing.

For the assertions about PMI_* values, I think the majority of these will become unnecessary once the remaining pieces of AArch64GenRegisterBankInfo.def are tablegen-erated. Once that's done, I think it will all be internal to the tablegen-erated code except for the assumption that PMI_First* can be used to specify the register bank and I think we ought to use *RegBankID's for that instead.

For the assertions that call RB.covers(). I think this can be checked in either direction but it's a bit easier for tablegen to check that all the expected classes have been added since it's easy to forget a particular class when listing them manually.

For the assertions that call RB.getSize(). I think both places are equally good.

• Also, can you extract the RegisterBank code to a shared location? (CodeGenRegBank? maybe rename it to CodeGenRegisters) ? That'll let us reuse it from the selector emitter backend. We can do that separately though.

That makes sense to me. Is it ok if I do that as another patch at the end of my current patch-series? I could insert one before this one too but adding it to the end should save me some rebasing.

utils/TableGen/RegisterBankEmitter.cpp

343 ↗

(On Diff #80593)

Ok

362 ↗

(On Diff #80593)

Ok

[ab]

In D27338#619757, @dsanders wrote:

In D27338#618721, @ab wrote:

This seems reasonable, but:

• I don't think the PartialMapping exclusion mechanism is necessary. What about adding the missing mappings manually before landing this patch? Alternatively, replace the manual code with a copy of the generated mappings (once you have those) before any tablegen changes? That lets us split the generalization from the NFC tablegen changes without requiring hacks in-between.

It should be easy enough to add FPR's 8 and 16 mapping and CCR's 32 mapping. I'm not sure about FPR's 192 and 384 mappings though. There's definitely some code that assumes the sizes are a power of 2 (e.g. getRegBankBaseIdxOffset()) but I'm not sure how widespread that assumption is. I'd have to investigate.

Yeah, I was worried about that too, but I figured we'll have to generalize that logic at some point anyway, so we might as well clean up the C++ and have a drop-in NFC tablegen replacement.

• I'm not sure it's useful to generate the asserts: I think the intent was to check 1) the correctness of the manual description, and 2) it being consistent with the eventual tablegen output. Have you considered keeping them in AArch64RegisterBankInfo? I suppose generating them lets all targets have them. @qcolombet: what do you think?

I suppose it depends which direction you look at it. It makes sense to me to have the manual description check that the tablegen part meets its assumptions, but I also think it makes sense to have the tablegen-erated code check that it meets the assumptions of the manual code it's replacing.

For the assertions about PMI_* values, I think the majority of these will become unnecessary once the remaining pieces of AArch64GenRegisterBankInfo.def are tablegen-erated. Once that's done, I think it will all be internal to the tablegen-erated code except for the assumption that PMI_First* can be used to specify the register bank and I think we ought to use *RegBankID's for that instead.

For the assertions that call RB.covers(). I think this can be checked in either direction but it's a bit easier for tablegen to check that all the expected classes have been added since it's easy to forget a particular class when listing them manually.

For the assertions that call RB.getSize(). I think both places are equally good.

SGTM, let's reevaluate once .def is gone.

• Also, can you extract the RegisterBank code to a shared location? (CodeGenRegBank? maybe rename it to CodeGenRegisters) ? That'll let us reuse it from the selector emitter backend. We can do that separately though.

That makes sense to me. Is it ok if I do that as another patch at the end of my current patch-series? I could insert one before this one too but adding it to the end should save me some rebasing.

Sure, I'll rebase my patches on top and will copy the regbank code somewhere else for now.

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

46 ↗

(On Diff #80593)

How about:

• introduce an intermediate class, 'AArch64GenRegisterBankInfo'
• make the RegBanks array a member
• replace initGeneratedInfo with the ctor
• remove the AlreadyInit logic
• consolidate the now-redundant GET_REGBANK_*IFACE* into a single GET_REGBANK_IMPLEMENTATION to avoid having everything in the header

WDYT?

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

46 ↗

(On Diff #80593)

That makes sense to me.

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

46 ↗

(On Diff #80593)

consolidate the now-redundant GET_REGBANK_*IFACE* into a single GET_REGBANK_IMPLEMENTATION to avoid having everything in the header

On thinking about it a bit more, this step doesn't quite work. We can't merge the declaration and implementation together without putting the implementation in the header. I'll keep the declaration of AArch64GenRegisterBankInfo and the implementation separate to avoid putting everything in the header.

[qcolombet]

Hi Daniel,

Mostly looks good to me, I would however suggest two changes:

1. Drop the partial mapping support.
2. Add all the register classes covered by a RegisterBank statically.

For #1, I think that part should belong to something related to instruction pattern emitter.

For #2, the call to addRegBankCoverage still does a bunch of stuff at runtime whereas all doable at compile time. Indeed, I expect the tablegen backend to just populate the bit vector at compile time. Ultimately, I would like to change the representation of the covered register class into an array of uint32_t, so that we just get rid of the complexity of the BitVector. You can have a look at SubClassMask in TargetRegisterInfo and how we generate it to have an idea of what I am talking about.

Cheers,
-Quentin

include/llvm/Target/GlobalISel/RegisterBank.td

19 ↗

(On Diff #80593)

This seems gross.
I would rather patch the manual mapping than having to add this distinction.
Namely, right now we use clever tricks to access the element in the array, but I could totally see an enum or an array doing that mapping.
The reason why I did this was because it was the fastest thing to do :P.

The bottom line is, let us clean that up!

utils/TableGen/RegisterBankEmitter.cpp

38 ↗

(On Diff #80593)

Partial mappings are more a consequence of instruction patterns than register bank. I wouldn't expect this to happen here.

202 ↗

(On Diff #80417)

Right now, this method is used only once. Are there any plan to reuse it with a different functor?
If not, let us name it addSubRegisterClasses.

[dsanders]

Thanks. I'm going to put this patch on hold for the moment and post separate patches to lay the necessary groundwork to account for for the changes Ahmed and Quentin requested. I'll then work on updating this patch.

[dsanders]

Rewrote patch to work with the new static table based patch series and the related refactoring.

[dsanders]

@rengolin: Thanks. I hadn't noticed that @rovka was missing from this one.

[qcolombet]

Hi Daniel,

Nitpick stuff, the base is indeed sound and I expect we converge on the final patch quickly.

Thanks,
-Quentin

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

19 ↗

(On Diff #82088)

I would move that into AArch64RegisterBankInfo.cpp, right before the include of the .def.
Eventually, the .def will be removed so let us move all the useful code in the cpp.

38 ↗

(On Diff #82088)

Update the "// Idx: " in the comments to match the actual index.

45 ↗

(On Diff #82088)

Ditto.

89 ↗

(On Diff #82088)

Why do we need three of them instead of none previously?

At the very least I would have expected that we need just one of this input.

lib/Target/AArch64/AArch64RegisterBankInfo.h

20 ↗

(On Diff #82088)

We probably want GET_TARGET_REGBANK_CLASS as well, aren't we?
BTW, do we want to make this distinction?
Or put differently, shouldn't we guard all of those under GET_REGBANKINFO_HEADER so that we have an option to get everything needed without having to put all the macros down?

26 ↗

(On Diff #82088)

This shouldn't be "AArch64GenRegisterBankInfo : public RegisterBankInfo"
But "AArch64RegisterBankInfo : public AArch64GenRegisterBankInfo"

lib/Target/AArch64/AArch64RegisterBanks.td

11 ↗

(On Diff #82088)

I would expect an include of AArch64RegisterInfo.td, otherwise GPR64all and such won't be defined.

utils/TableGen/RegisterBankEmitter.cpp

32 ↗

(On Diff #82088)

Which StringRef are you referring to here?

44 ↗

(On Diff #82088)

I can see that for debug purposes it is good to get the name of the class with the largest size. Could you update the comment to get rid of the reference to the partial mapping and ExcludePartialMappings stuff, though?

155 ↗

(On Diff #82088)

I would add "iff any of this applies:"

159 ↗

(On Diff #82088)

You can add (a.k.a. subreg-class)

162 ↗

(On Diff #82088)

Add a comment explaining what is RC, Kind, and visitFn.

172 ↗

(On Diff #82088)

Period.

178 ↗

(On Diff #82088)

Period.

178 ↗

(On Diff #82088)

To be a bit more explicit here (or in the comment of the function) we could call out what it means to be a subreg-class:
PossibleSubclass is a subreg-class iff it exists a sub register index SubIdx such that for each register Reg in RC, Reg:SubIdx is in PossibleSubclass.

220 ↗

(On Diff #82088)

Before emitting the structure, could we emit a line with a comment with the general structure of each line?
E.g.,
<< "// ID, Name, MaxSize, CoveredRegClasses"

221 ↗

(On Diff #82088)

Following the other review, this should change to directly populate the register banks.

226 ↗

(On Diff #82088)

Could you add an assert that the current index in the array is equal to the expected value of the enumerator of the Bank?

232 ↗

(On Diff #82088)

Following the other review, I would rather have a simple TargetName for the namespace of the register banks.

235 ↗

(On Diff #82088)

With the direct initialization of the RegisterBank, we shouldn't need that section anymore, right?

262 ↗

(On Diff #82088)

Like I mentioned in my previous review, visitRegisterBankClasses is only used with this visitFn, thus, it seems to me like we could drop this parameter and call the proper function directly in visitRegisterBankClasses.

While here, we could rename it addSubClassesAndSubregClasses or something more explicitly like this.

[dsanders]

Rebased onto the new D27339 and re-worked to account for the changes to earlier patches in the series.

Removed the hard-coded 200 register class limit deferred from earlier patches in the series.

Updated to account for most of Quentin's comments. There's a couple I need to ask about.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

89 ↗

(On Diff #82088)

We should have had the three of them at the end of the table but got away without them because FPR was last and the missing elements weren't accessed. Now that FPR is first we need them to pad GPR's mappings out to the right indices.

I've added comments indicating the invalid mappings they correspond to.

lib/Target/AArch64/AArch64RegisterBankInfo.h

20 ↗

(On Diff #82088)

We probably want GET_TARGET_REGBANK_CLASS as well, aren't we?

Yes, but it needs to be inside the class declaration for the moment (see below).

BTW, do we want to make this distinction?

When everything is tablegen-erated: Probably not. I don't think there will be a need to keep them separate.

For the moment, PartialMappingIdx is the main blocking factor that prevents us from tablegen-erating the whole class and merging these two include points. There are enumerators missing (e.g. FPR192) at the moment.

26 ↗

(On Diff #82088)

No, this is the declaration of AArch64GenRegisterBankInfo which will eventually be fully tablegen-erated. AArch64RegisterBankInfo is declared next (line 95 at the moment) as class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo.

lib/Target/AArch64/AArch64RegisterBanks.td

11 ↗

(On Diff #82088)

This file is included by AArch64.td which includes AArch64RegisterInfo.td on the line before.

FWIW, I'm not very keen on all the tablegen files starting from AArch64.td as they currently do. It's wasteful to parse lots of classes and defs that never contribute to the output. We'll need to fix that in tablegen() in our CMake rules before we can start unpicking the dependencies here.

utils/TableGen/RegisterBankEmitter.cpp

32 ↗

(On Diff #82088)

I've forgotten to update the comment (and one just below). This used to be a std::vector<std::pair<const CodeGenRegisterClass *, StringRef>> back when the pass emitted assertions for membership. The reason for including a class is now printed in the -debug output.

220 ↗

(On Diff #82088)

This table has disappeared in the re-worked patches but I've added similar comments to the generated constructors instead.

235 ↗

(On Diff #82088)

That's right. This section has disappeared following that re-work.

262 ↗

(On Diff #82088)

The main reason I wrote it this way was to keep the high-level intent (add all the relevant classes) separate from the complexity of how we determine that a given register class is a member. I also needed to factor the current contents of visitFn() into a function (or triplicate it) and I thought it made most sense to put it here rather than in a static function off to the side.

I'm happy to fold it into visitRegisterBankClasses() and rename that if that's what you prefer.

[qcolombet]

LGTM.

lib/Target/AArch64/AArch64RegisterBankInfo.h

20 ↗

(On Diff #82088)

Ok.

26 ↗

(On Diff #82088)

Ah right, I missed the second declaration.

lib/Target/AArch64/AArch64RegisterBanks.td

11 ↗

(On Diff #82088)

Good point. Agreed.

utils/TableGen/RegisterBankEmitter.cpp

262 ↗

(On Diff #82088)

Up to you.
I found it easier to have the name of the function directly in the visit method instead of having to look at the call site, but your argument works as well.

[qcolombet]

LGTM.

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

89 ↗

(On Diff #82088)

Can't we update the indices or formulae so that we don't need those invalid entries at all?
If that's too complicated, I am fine with moving along with the current version. It will be table generated as some point any way.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

89 ↗

(On Diff #82088)

It doesn't look too complicated. We can stop getCopyMapping() needing the invalid entries by dropping the relevant size to index-offset mappings from getRegBankBaseIdxOffset(). However, getValueMapping() also uses that so we'd need to duplicate the function first before trimming the getCopyMapping() version.

It would be easiest for me to do this as a follow-up patch but I can insert it into the series if you prefer.

[qcolombet]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

89 ↗

(On Diff #82088)

Just move forward with the current version. It'll get clean up with the related tablegen support when we add that eventually.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

89 ↗

(On Diff #82088)

Ok, Thanks.

[ab]

lib/Target/AArch64/AArch64RegisterBankInfo.h

26 ↗

(On Diff #82088)

So, here's an alternative approach (more in line with what Quentin and I were thinking, I suspect): from day one, generate the entire AArch64GenRegisterBankInfo class. If something currently needs to be manually written code, keep it in AArch64RegisterBankInfo. When tablegen gains support for it, move it from the subclass to the generated base. Because AArch64RegisterBankInfo is-a AArch64GenRegisterBankInfo, all of these changes should be NFC. WDYT?

[dsanders]

Fix a couple stray 'AArch64' strings that should have been TargetName.

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.h

26 ↗

(On Diff #82088)

Is there an advantage to re-factoring the patch series that way? It seems equal to the current patch series to me in which case I'm leaning towards the current patches.

[ab]

lib/Target/AArch64/AArch64RegisterBankInfo.h

26 ↗

(On Diff #82088)

I suspect it helps make the changes easier to reason about (it's hard to keep track of the moving pieces); other than that, not really, no. Either way is fine by me!

[dsanders]

Refresh before commit

[dsanders]

Several buildbots encountered crashes when this was committed. Investigating

[ab]

lib/Target/AArch64/CMakeLists.txt

3 ↗

(On Diff #84289)

I didn't notice before, but now that you mention buildbot crashes: this should be in the if(LLVM_BUILD_GLOBAL_ISEL) block below.

[dsanders]

lib/Target/AArch64/CMakeLists.txt

3 ↗

(On Diff #84289)

Thanks. It hadn't occurred to me that I had too many buildbots complaining and had started looking for memory bugs. I don't think any GlobalISel bots failed so this is probably it.

llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h

private:
   /// initialized yet.
   static const unsigned InvalidID;
 
   /// Only the RegisterBankInfo can initialize RegisterBank properly.
   friend RegisterBankInfo;
 
 public:
   RegisterBank(unsigned ID, const char *Name, unsigned Size,
-               const uint32_t *ContainedRegClasses);
+               const uint32_t *ContainedRegClasses, unsigned NumRegClasses);
 
   /// Get the identifier of this register bank.
   unsigned getID() const { return ID; }
 
   /// Get a user friendly name of this register bank.
   /// Should be used only for debugging purposes.
   const char *getName() const { return Name; }
 

llvm/trunk/include/llvm/Target/GlobalISel/RegisterBank.td

+//===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+class RegisterBank<string name, list<RegisterClass> classes> {
+  string Name = name;
+  list<RegisterClass> RegisterClasses = classes;
+}

llvm/trunk/include/llvm/Target/Target.td

 //===----------------------------------------------------------------------===//
 // Pull in the common support for DAG isel generation.
 //
 include "llvm/Target/TargetSelectionDAG.td"
 
 //===----------------------------------------------------------------------===//
 // Pull in the common support for Global ISel generation.
 //
+include "llvm/Target/GlobalISel/RegisterBank.td"
 include "llvm/Target/TargetGlobalISel.td"

llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp

 #include "llvm/Target/TargetRegisterInfo.h"
 
 #define DEBUG_TYPE "registerbank"
 
 using namespace llvm;
 
 const unsigned RegisterBank::InvalidID = UINT_MAX;
 
-RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
-                           const uint32_t *CoveredClasses)
+RegisterBank::RegisterBank(
+    unsigned ID, const char *Name, unsigned Size,
+    const uint32_t *CoveredClasses, unsigned NumRegClasses)
     : ID(ID), Name(Name), Size(Size) {
-  ContainedRegClasses.resize(200);
+  ContainedRegClasses.resize(NumRegClasses);
   ContainedRegClasses.setBitsInMask(CoveredClasses);
 }
 
 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
   assert(isValid() && "Invalid register bank");
   for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
 

llvm/trunk/lib/Target/AArch64/AArch64.td

 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
+include "AArch64RegisterBanks.td"
 include "AArch64CallingConvention.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "AArch64Schedule.td"
 include "AArch64InstrInfo.td"

llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def

 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
 namespace llvm {
-namespace AArch64 {
-
-const uint32_t GPRCoverageData[] = {
-    // Classes 0-31
-    (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |
-        (1u << AArch64::GPR32spRegClassID) |
-        (1u << AArch64::GPR32commonRegClassID) |
-        (1u << AArch64::GPR32sponlyRegClassID) |
-        (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |
-        (1u << AArch64::GPR64spRegClassID) |
-        (1u << AArch64::GPR64commonRegClassID) |
-        (1u << AArch64::tcGPR64RegClassID) |
-        (1u << AArch64::GPR64sponlyRegClassID),
-    // Classes 32-63
-    0,
-    // FIXME: The entries below this point can be safely removed once this is
-    // tablegenerated. It's only needed because of the hardcoded register class
-    // limit.
-    // Classes 64-96
-    0,
-    // Classes 97-128
-    0,
-    // Classes 129-160
-    0,
-    // Classes 161-192
-    0,
-    // Classes 193-224
-    0,
-};
-
-const uint32_t FPRCoverageData[] = {
-    // Classes 0-31
-    (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |
-        (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |
-        (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |
-        (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |
-        (1u << AArch64::DDDDRegClassID),
-    // Classes 32-63
-    (1u << (AArch64::QQRegClassID - 32)) |
-        (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
-        (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
-        (1u
-         << (AArch64::
-                 QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
-             32)) |
-        (1u << (AArch64::QQQQRegClassID - 32)) |
-        (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
-        (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
-        (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
-        (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
-        (1u
-         << (AArch64::
-                 QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
-             32)) |
-        (1u
-         << (AArch64::
-                 QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID -
-             32)) |
-        (1u << (AArch64::QQQRegClassID - 32)) |
-        (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
-        (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
-        (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
-        (1u
-         << (AArch64::
-                 QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID -
-             32)),
-    // FIXME: The entries below this point can be safely removed once this
-    // is tablegenerated. It's only needed because of the hardcoded register
-    // class limit.
-    // Classes 64-96
-    0,
-    // Classes 97-128
-    0,
-    // Classes 129-160
-    0,
-    // Classes 161-192
-    0,
-    // Classes 193-224
-    0,
-};
-
-const uint32_t CCRCoverageData[] = {
-    // Classes 0-31
-    1u << AArch64::CCRRegClassID,
-    // Classes 32-63
-    0,
-    // FIXME: The entries below this point can be safely removed once this
-    // is tablegenerated. It's only needed because of the hardcoded register
-    // class limit.
-    // Classes 64-96
-    0,
-    // Classes 97-128
-    0,
-    // Classes 129-160
-    0,
-    // Classes 161-192
-    0,
-    // Classes 193-224
-    0,
-};
-
-RegisterBank GPRRegBank(AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData);
-RegisterBank FPRRegBank(AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData);
-RegisterBank CCRRegBank(AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData);
-} // end namespace AArch64
-
-RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
-    &AArch64::GPRRegBank, &AArch64::FPRRegBank, &AArch64::CCRRegBank};
-
 RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
     /* StartIdx, Length, RegBank */
-    // 0: GPR 32-bit value.
-    {0, 32, AArch64::GPRRegBank},
-    // 1: GPR 64-bit value.
-    {0, 64, AArch64::GPRRegBank},
-    // 2: FPR 32-bit value.
+    // 0: FPR 32-bit value.
     {0, 32, AArch64::FPRRegBank},
-    // 3: FPR 64-bit value.
+    // 1: FPR 64-bit value.
     {0, 64, AArch64::FPRRegBank},
-    // 4: FPR 128-bit value.
+    // 2: FPR 128-bit value.
     {0, 128, AArch64::FPRRegBank},
-    // 5: FPR 256-bit value.
+    // 3: FPR 256-bit value.
     {0, 256, AArch64::FPRRegBank},
-    // 6: FPR 512-bit value.
-    {0, 512, AArch64::FPRRegBank}};
+    // 4: FPR 512-bit value.
+    {0, 512, AArch64::FPRRegBank},
+    // 5: GPR 32-bit value.
+    {0, 32, AArch64::GPRRegBank},
+    // 6: GPR 64-bit value.
+    {0, 64, AArch64::GPRRegBank},
+};
 
 // ValueMappings.
 RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
     /* BreakDown, NumBreakDowns */
     // 3-operands instructions (all binary operations should end up with one of
     // those mapping).
-    // 0: GPR 32-bit value. <-- This must match First3OpsIdx.
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
-    // 3: GPR 64-bit value.
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
-    // 6: FPR 32-bit value.
+    // 0: FPR 32-bit value. <-- This must match First3OpsIdx.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
-    // 9: FPR 64-bit value.
+    // 3: FPR 64-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
-    // 12: FPR 128-bit value.
+    // 6: FPR 128-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
-    // 15: FPR 256-bit value.
+    // 9: FPR 256-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
-    // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.
+    // 12: FPR 512-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
+    // 15: GPR 32-bit value.
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    // 18: GPR 64-bit value. <-- This must match Last3OpsIdx.
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     // Cross register bank copies.
-    // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match
+    // 21: FPR 32-bit value to GPR 32-bit value. <-- This must match
     //                                               FirstCrossRegCpyIdx.
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
-    // 23: GPR 64-bit value to FPR 64-bit value.
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    // 23: FPR 64-bit value to GPR 64-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
-    // 25: FPR 32-bit value to GPR 32-bit value.
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    // 25: FPR 128-bit value to GPR 128-bit value (invalid)
+    {nullptr, 1},
+    {nullptr, 1},
+    // 27: FPR 256-bit value to GPR 256-bit value (invalid)
+    {nullptr, 1},
+    {nullptr, 1},
+    // 29: FPR 512-bit value to GPR 512-bit value (invalid)
+    {nullptr, 1},
+    {nullptr, 1},
+    // 31: GPR 32-bit value to FPR 32-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
-    // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+    // 33: GPR 64-bit value to FPR 64-bit value. <-- This must match
     //                                               LastCrossRegCpyIdx.
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}
 };
 
 bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
                                                  unsigned ValStartIdx,
                                                  unsigned ValLength,
                                                  const RegisterBank &RB) {
   const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
   return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
   assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
          "Mapping out of bound");
 
   return &ValMappings[ValMappingIdx];
 }
 
 AArch64GenRegisterBankInfo::PartialMappingIdx
     AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
-        PMI_FirstGPR, // GPR
-        PMI_FirstFPR, // FPR
         PMI_None,     // CCR
+        PMI_FirstFPR, // FPR
+        PMI_FirstGPR, // GPR
     };
 
 const RegisterBankInfo::ValueMapping *
 AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
                                            unsigned SrcBankID, unsigned Size) {
   assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
   assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
   PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];

llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h

 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
 
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 
+#define GET_REGBANK_DECLARATIONS
+#include "AArch64GenRegisterBank.inc"
+
 namespace llvm {
 
 class TargetRegisterInfo;
 
-namespace AArch64 {
-enum {
-  GPRRegBankID = 0, /// General Purpose Registers: W, X.
-  FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
-  CCRRegBankID = 2, /// Conditional register: NZCV.
-  NumRegisterBanks
-};
-} // End AArch64 namespace.
-
 class AArch64GenRegisterBankInfo : public RegisterBankInfo {
-private:
-  static RegisterBank *RegBanks[];
-
 protected:
-  AArch64GenRegisterBankInfo();
 
   enum PartialMappingIdx {
     PMI_None = -1,
-    PMI_GPR32 = 1,
-    PMI_GPR64,
-    PMI_FPR32,
+    PMI_FPR32 = 1,
     PMI_FPR64,
     PMI_FPR128,
     PMI_FPR256,
     PMI_FPR512,
+    PMI_GPR32,
+    PMI_GPR64,
     PMI_FirstGPR = PMI_GPR32,
     PMI_LastGPR = PMI_GPR64,
     PMI_FirstFPR = PMI_FPR32,
     PMI_LastFPR = PMI_FPR512,
-    PMI_Min = PMI_FirstGPR,
+    PMI_Min = PMI_FirstFPR,
   };
 
   static RegisterBankInfo::PartialMapping PartMappings[];
   static RegisterBankInfo::ValueMapping ValMappings[];
   static PartialMappingIdx BankIDToCopyMapIdx[];
 
   enum ValueMappingIdx {
     First3OpsIdx = 0,
     Last3OpsIdx = 18,
     DistanceBetweenRegBanks = 3,
     FirstCrossRegCpyIdx = 21,
-    LastCrossRegCpyIdx = 27,
+    LastCrossRegCpyIdx = 33,
     DistanceBetweenCrossRegCpy = 2
   };
 
   static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
                               unsigned ValLength, const RegisterBank &RB);
   static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
                                 unsigned Size, unsigned Offset);
   static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
protected:
   static const RegisterBankInfo::ValueMapping *
   getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
 
   /// Get the pointer to the ValueMapping of the operands of a copy
   /// instruction from the \p SrcBankID register bank to the \p DstBankID
   /// register bank with a size of \p Size.
   static const RegisterBankInfo::ValueMapping *
   getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
+
+#define GET_TARGET_REGBANK_CLASS
+#include "AArch64GenRegisterBank.inc"
 };
 
 /// This class provides the information for the target register banks.
 class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
   /// See RegisterBankInfo::applyMapping.
   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
 
   /// Get an instruction mapping where all the operands map to

llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

 #include "AArch64InstrInfo.h" // For XXXRegClassID.
 #include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
+#define GET_TARGET_REGBANK_IMPL
+#include "AArch64GenRegisterBank.inc"
+
 // This file will be TableGen'ed at some point.
 #include "AArch64GenRegisterBankInfo.def"
 
 using namespace llvm;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
-AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
-    : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {}
-
 AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
     : AArch64GenRegisterBankInfo() {
   static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (AArch64::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.

llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td

+//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+/// General Purpose Registers: W, X.
+def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
+
+/// Floating Point/Vector Registers: B, H, S, D, Q.
+def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
+
+/// Conditional register: NZCV.
+def CCRRegBank : RegisterBank<"CCR", [CCR]>;

llvm/trunk/lib/Target/AArch64/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS AArch64.td)
 
 tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
 tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
 tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
 tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
 if(LLVM_BUILD_GLOBAL_ISEL)
+  tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
   tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
 endif()
 
 add_public_tablegen_target(AArch64CommonTableGen)
 
 # List of all GlobalISel files.
 set(GLOBAL_ISEL_FILES
       AArch64CallLowering.cpp

llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp

const uint32_t GPRCoverageData[] = {
     // Classes 129-160
     0,
     // Classes 161-192
     0,
     // Classes 193-224
     0,
 };
 
-RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
+// FIXME: The 200 will be replaced by the number of register classes when this is
+//        tablegenerated.
+RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData, 200);
 RegisterBank *RegBanks[] = {&GPRRegBank};
 
 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
 
 RegisterBankInfo::ValueMapping ValueMappings[] = {
     {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}};
 } // end namespace arm
 } // end namespace llvm

llvm/trunk/llvm/Target/GlobalISel/RegisterBank.td

+//===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+class RegisterBank<string name, list<RegisterClass> classes> {
+  string Name = name;
+  list<RegisterClass> RegisterClasses = classes;
+}

llvm/trunk/utils/TableGen/CMakeLists.txt

add_tablegen(llvm-tblgen LLVM
   DisassemblerEmitter.cpp
   FastISelEmitter.cpp
   FixedLenDecoderEmitter.cpp
   GlobalISelEmitter.cpp
   InstrInfoEmitter.cpp
   IntrinsicEmitter.cpp
   OptParserEmitter.cpp
   PseudoLoweringEmitter.cpp
+  RegisterBankEmitter.cpp
   RegisterInfoEmitter.cpp
   SearchableTableEmitter.cpp
   SubtargetEmitter.cpp
   SubtargetFeatureInfo.cpp
   TableGen.cpp
   Types.cpp
   X86DisassemblerTables.cpp
   X86ModRMFilters.cpp
   X86RecognizableInstr.cpp
   CTagsEmitter.cpp
   )

llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp

+//===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend is responsible for emitting a description of a target
+// register bank for a code generator.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/BitVector.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+#include "CodeGenRegisters.h"
+
+#define DEBUG_TYPE "register-bank-emitter"
+
+using namespace llvm;
+
+namespace {
+class RegisterBank {
+
+  /// A vector of register classes that are included in the register bank.
+  typedef std::vector<const CodeGenRegisterClass *> RegisterClassesTy;
+
+private:
+  const Record &TheDef;
+
+  /// The register classes that are covered by the register bank.
+  RegisterClassesTy RCs;
+
+  /// The register class with the largest register size.
+  const CodeGenRegisterClass *RCWithLargestRegsSize;
+
+public:
+  RegisterBank(const Record &TheDef)
+      : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
+
+  /// Get the human-readable name for the bank.
+  std::string getName() const { return TheDef.getValueAsString("Name"); }
+  /// Get the name of the enumerator in the ID enumeration.
+  std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
+
+  /// Get the name of the array holding the register class coverage data;
+  std::string getCoverageArrayName() const {
+    return (TheDef.getName() + "CoverageData").str();
+  }
+
+  /// Get the name of the global instance variable.
+  StringRef getInstanceVarName() const { return TheDef.getName(); }
+
+  const Record &getDef() const { return TheDef; }
+
+  /// Get the register classes listed in the RegisterBank.RegisterClasses field.
+  std::vector<const CodeGenRegisterClass *>
+  getExplictlySpecifiedRegisterClasses(
+      CodeGenRegBank &RegisterClassHierarchy) const {
+    std::vector<const CodeGenRegisterClass *> RCs;
+    for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
+      RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
+    return RCs;
+  }
+
+  /// Add a register class to the bank without duplicates.
+  void addRegisterClass(const CodeGenRegisterClass *RC) {
+    if (std::find_if(RCs.begin(), RCs.end(),
+                     [&RC](const CodeGenRegisterClass *X) {
+                       return X == RC;
+                     }) != RCs.end())
+      return;
+
+    // FIXME? We really want the register size rather than the spill size
+    //        since the spill size may be bigger on some targets with
+    //        limited load/store instructions. However, we don't store the
+    //        register size anywhere (we could sum the sizes of the subregisters
+    //        but there may be additional bits too) and we can't derive it from
+    //        the VT's reliably due to Untyped.
+    if (RCWithLargestRegsSize == nullptr)
+      RCWithLargestRegsSize = RC;
+    else if (RCWithLargestRegsSize->SpillSize < RC->SpillSize)
+      RCWithLargestRegsSize = RC;
+    assert(RCWithLargestRegsSize && "RC was nullptr?");
+
+    RCs.emplace_back(RC);
+  }
+
+  const CodeGenRegisterClass *getRCWithLargestRegsSize() const {
+    return RCWithLargestRegsSize;
+  }
+
+  iterator_range<typename RegisterClassesTy::const_iterator>
+  register_classes() const {
+    return llvm::make_range(RCs.begin(), RCs.end());
+  }
+};
+
+class RegisterBankEmitter {
+private:
+  RecordKeeper &Records;
+  CodeGenRegBank RegisterClassHierarchy;
+
+  void emitHeader(raw_ostream &OS, const StringRef TargetName,
+                  const std::vector<RegisterBank> &Banks);
+  void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
+                               const std::vector<RegisterBank> &Banks);
+  void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
+                                   std::vector<RegisterBank> &Banks);
+
+public:
+  RegisterBankEmitter(RecordKeeper &R)
+      : Records(R), RegisterClassHierarchy(Records) {}
+
+  void run(raw_ostream &OS);
+};
+
+} // end anonymous namespace
+
+/// Emit code to declare the ID enumeration and external global instance
+/// variables.
+void RegisterBankEmitter::emitHeader(raw_ostream &OS,
+                                     const StringRef TargetName,
+                                     const std::vector<RegisterBank> &Banks) {
+  // <Target>RegisterBankInfo.h
+  OS << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n"
+     << "enum {\n";
+  for (const auto &Bank : Banks)
+    OS << "  " << Bank.getEnumeratorName() << ",\n";
+  OS << "  NumRegisterBanks,\n"
+     << "};\n"
+     << "} // end namespace " << TargetName << "\n"
+     << "} // end namespace llvm\n";
+}
+
+/// Emit declarations of the <Target>GenRegisterBankInfo class.
+void RegisterBankEmitter::emitBaseClassDefinition(
+    raw_ostream &OS, const StringRef TargetName,
+    const std::vector<RegisterBank> &Banks) {
+  OS << "private:\n"
+     << "  static RegisterBank *RegBanks[];\n\n"
+     << "protected:\n"
+     << "  " << TargetName << "GenRegisterBankInfo();\n"
+     << "\n";
+}
+
+/// Visit each register class belonging to the given register bank.
+///
+/// A class belongs to the bank iff any of these apply:
+/// * It is explicitly specified
+/// * It is a subclass of a class that is a member.
+/// * It is a class containing subregisters of the registers of a class that
+///   is a member. This is known as a subreg-class.
+///
+/// This function must be called for each explicitly specified register class.
+///
+/// \param RC The register class to search.
+/// \param Kind A debug string containing the path the visitor took to reach RC.
+/// \param VisitFn The action to take for each class visited. It may be called
+///                multiple times for a given class if there are multiple paths
+///                to the class.
+static void visitRegisterBankClasses(
+    CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
+    const Twine Kind,
+    std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn) {
+  // Visit each explicitly named class.
+  VisitFn(RC, Kind.str());
+
+  for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
+    Twine TmpKind = Kind + " (" + PossibleSubclass.getName() + ")";
+
+    // Visit each subclass of an explicitly named class.
+    if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
+      visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
+                               TmpKind + " " + RC->getName() + " subclass",
+                               VisitFn);
+
+    // Visit each class that contains only subregisters of RC with a common
+    // subregister-index.
+    //
+    // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
+    // PossibleSubclass for all registers Reg from RC using any
+    // subregister-index SubReg
+    for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
+      BitVector BV(RegisterClassHierarchy.getRegClasses().size());
+      PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
+      if (BV.test(RC->EnumValue)) {
+        Twine TmpKind2 = TmpKind + " " + RC->getName() +
+                         " class-with-subregs: " + RC->getName();
+        VisitFn(&PossibleSubclass, TmpKind2.str());
+      }
+    }
+  }
+}
+
+void RegisterBankEmitter::emitBaseClassImplementation(
+    raw_ostream &OS, StringRef TargetName,
+    std::vector<RegisterBank> &Banks) {
+
+  OS << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n";
+  for (const auto &Bank : Banks) {
+    std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
+        (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
+
+    for (const auto &RC : Bank.register_classes())
+      RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);
+
+    OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
+    unsigned LowestIdxInWord = 0;
+    for (const auto &RCs : RCsGroupedByWord) {
+      OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
+      for (const auto &RC : RCs) {
+        Twine QualifiedRegClassID =
+            TargetName + "::" + RC->getName() + "RegClassID";
+        OS << "    (1u << (" << QualifiedRegClassID << " - "
+           << LowestIdxInWord << ")) |\n";
+      }
+      OS << "    0,\n";
+      LowestIdxInWord += 32;
+    }
+    OS << "};\n";
+  }
+  OS << "\n";
+
+  for (const auto &Bank : Banks) {
+    Twine QualifiedBankID = TargetName + "::" + Bank.getEnumeratorName();
+    unsigned Size = Bank.getRCWithLargestRegsSize()->SpillSize;
+    OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
+       << QualifiedBankID << ", /* Name */ \"" << Bank.getName()
+       << "\", /* Size */ " << Size << ", "
+       << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
+       << ", /* NumRegClasses */ "
+       << RegisterClassHierarchy.getRegClasses().size() << ");\n";
+  }
+  OS << "} // end namespace " << TargetName << "\n"
+     << "\n";
+
+  OS << "RegisterBank *" << TargetName
+     << "GenRegisterBankInfo::RegBanks[] = {\n";
+  for (const auto &Bank : Banks)
+    OS << "    &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";
+  OS << "};\n\n";
+
+  OS << TargetName << "GenRegisterBankInfo::" << TargetName
+     << "GenRegisterBankInfo()\n"
+     << "    : RegisterBankInfo(RegBanks, " << TargetName
+     << "::NumRegisterBanks) {\n"
+     << "  // Assert that RegBank indices match their ID's\n"
+     << "  unsigned Index = 0;\n"
+     << "#ifndef NDEBUG\n"
+     << "  for (const auto &RB : RegBanks)\n"
+     << "    assert(Index++ == RB->getID() && \"Index != ID\");\n"
+     << "#endif // NDEBUG\n"
+     << "}\n"
+     << "} // end namespace llvm\n";
+}
+
+void RegisterBankEmitter::run(raw_ostream &OS) {
+  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
+  if (Targets.size() != 1)
+    PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
+  StringRef TargetName = Targets[0]->getName();
+
+  std::vector<RegisterBank> Banks;
+  for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
+    RegisterBank Bank(*V);
+
+    for (const CodeGenRegisterClass *RC :
+         Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+      visitRegisterBankClasses(
+          RegisterClassHierarchy, RC, "explicit",
+          [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
+            DEBUG(dbgs() << "Added " << RC->getName() << "(" << Kind << ")\n");
+            Bank.addRegisterClass(RC);
+          });
+    }
+
+    Banks.push_back(Bank);
+  }
+
+  emitSourceFileHeader("Register Bank Source Fragments", OS);
+  OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
+     << "#undef GET_REGBANK_DECLARATIONS\n";
+  emitHeader(OS, TargetName, Banks);
+  OS << "#endif // GET_REGBANK_DECLARATIONS\n\n"
+     << "#ifdef GET_TARGET_REGBANK_CLASS\n"
+     << "#undef GET_TARGET_REGBANK_CLASS\n";
+  emitBaseClassDefinition(OS, TargetName, Banks);
+  OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n"
+     << "#ifdef GET_TARGET_REGBANK_IMPL\n"
+     << "#undef GET_TARGET_REGBANK_IMPL\n";
+  emitBaseClassImplementation(OS, TargetName, Banks);
+  OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
+}
+
+namespace llvm {
+
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS) {
+  RegisterBankEmitter(RK).run(OS);
+}
+
+} // end namespace llvm

llvm/trunk/utils/TableGen/TableGen.cpp

enum ActionType {
   GenTgtIntrinsic,
   PrintEnums,
   PrintSets,
   GenOptParserDefs,
   GenCTags,
   GenAttributes,
   GenSearchableTables,
   GenGlobalISel,
+  GenRegisterBank,
 };
 
 namespace {
   cl::opt<ActionType>
   Action(cl::desc("Action to perform:"),
          cl::values(clEnumValN(PrintRecords, "print-records",
                                "Print all records to stdout (default)"),
                     clEnumValN(GenEmitter, "gen-emitter",
Action(cl::desc("Action to perform:"),
                                "Generate option definitions"),
                     clEnumValN(GenCTags, "gen-ctags",
                                "Generate ctags-compatible index"),
                     clEnumValN(GenAttributes, "gen-attrs",
                                "Generate attributes"),
                     clEnumValN(GenSearchableTables, "gen-searchable-tables",
                                "Generate generic binary-searchable table"),
                     clEnumValN(GenGlobalISel, "gen-global-isel",
-                               "Generate GlobalISel selector")));
+                               "Generate GlobalISel selector"),
+                    clEnumValN(GenRegisterBank, "gen-register-bank",
+                               "Generate registers bank descriptions")));
 
   cl::opt<std::string>
   Class("class", cl::desc("Print Enum list for this class"),
           cl::value_desc("class name"));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
   case PrintRecords:
bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   case GenAttributes:
     EmitAttributes(Records, OS);
     break;
   case GenSearchableTables:
     EmitSearchableTables(Records, OS);
     break;
   case GenGlobalISel:
     EmitGlobalISel(Records, OS);
+  case GenRegisterBank:
+    EmitRegisterBank(Records, OS);
     break;
   }
 
   return false;
 }
 }
 
 int main(int argc, char **argv) {

llvm/trunk/utils/TableGen/TableGenBackends.h

 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS);
 void EmitMapTable(RecordKeeper &RK, raw_ostream &OS);
 void EmitOptParser(RecordKeeper &RK, raw_ostream &OS);
 void EmitCTags(RecordKeeper &RK, raw_ostream &OS);
 void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);
 void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
 
 } // End llvm namespace
 
 #endif