[globalisel][arm] Tablegen-erate current Register Bank Information.

[dsanders]

Summary

This patch tablegen-erates the ARM register bank information so that the
static tables added in D27807 no longer need to be maintained.

Depends on D27338

[dsanders]

ping

[rovka]

LGTM, thanks.

lib/Target/ARM/ARM.td

def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
                                                          FeatureFPAO]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "ARMRegisterInfo.td"
 
+include "ARMRegisterBanks.td"
+
 include "ARMCallingConv.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "ARMInstrInfo.td"
 

lib/Target/ARM/ARMRegisterBankInfo.h

 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
 
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 
+#define GET_REGBANK_DECLARATIONS
+#include "ARMGenRegisterBank.inc"
+
 namespace llvm {
 
 class TargetRegisterInfo;
 
-namespace ARM {
-enum {
-  GPRRegBankID = 0, // General purpose registers
-  NumRegisterBanks,
+class ARMGenRegisterBankInfo : public RegisterBankInfo {
+#define GET_TARGET_REGBANK_CLASS
+#include "ARMGenRegisterBank.inc"
 };
-} // end namespace ARM
 
 /// This class provides the information for the target register banks.
-class ARMRegisterBankInfo final : public RegisterBankInfo {
+class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
 public:
   ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
 
   const RegisterBank &
   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 
   InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
 };
 } // End llvm namespace.
 #endif

lib/Target/ARM/ARMRegisterBankInfo.cpp

 
 #include "ARMRegisterBankInfo.h"
 #include "ARMInstrInfo.h" // For the register classes
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
+#define GET_TARGET_REGBANK_IMPL
+#include "ARMGenRegisterBank.inc"
+
 using namespace llvm;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
 // FIXME: TableGen this.
 // If it grows too much and TableGen still isn't ready to do the job, extract it
 // into an ARMGenRegisterBankInfo.def (similar to AArch64).
 namespace llvm {
 namespace ARM {
-const uint32_t GPRCoverageData[] = {
-    // Classes 0-31
-    (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
-        (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
-        (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
-        (1u << ARM::GPRnopc_and_hGPRRegClassID) |
-        (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
-        (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
-        (1u << ARM::hGPR_and_tcGPRRegClassID),
-    // Classes 32-63
-    0,
-    // Classes 64-96
-    (1u << (ARM::DQuadSpc_with_ssub_0RegClassID - 64)) |
-        (1u << (ARM::DQuadSpc_with_dsub_4_then_ssub_0RegClassID - 64)) |
-        (1u << (ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID - 64)) |
-        (1u << (ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID - 64)) |
-        (1u << (ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID - 64)) |
-        (1u << (ARM::DQuadRegClassID - 64)) |
-        (1u << (ARM::DQuad_with_ssub_0RegClassID - 64)) |
-        (1u << (ARM::DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID - 64)) |
-        (1u << (ARM::DQuad_with_dsub_1_in_DPR_8RegClassID - 64)) |
-        (1u << (ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID - 64)) |
-        (1u << (ARM::DQuad_with_dsub_2_in_DPR_8RegClassID - 64)) |
-        (1u
-         << (ARM::
-                 DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID -
-             64)) |
-        (1u << (ARM::DQuad_with_dsub_3_in_DPR_8RegClassID - 64)) |
-        (1u
-         << (ARM::
-                 DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID -
-             64)) |
-        (1u << (ARM::DQuad_with_qsub_0_in_QPR_8RegClassID - 64)) |
-        (1u << (ARM::DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID - 64)) |
-        (1u << (ARM::DQuad_with_qsub_1_in_QPR_8RegClassID - 64)) |
-        (1u
-         << (ARM::
-                 DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID -
-             64)) |
-        (1u << (ARM::QQQQPRRegClassID - 64)) |
-        (1u << (ARM::QQQQPR_with_ssub_0RegClassID - 64)) |
-        (1u << (ARM::QQQQPR_with_dsub_2_then_ssub_0RegClassID - 64)) |
-        (1u << (ARM::QQQQPR_with_dsub_7_then_ssub_0RegClassID - 64)),
-    (1u << (ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID - 96)) |
-        (1u << (ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID - 96)) |
-        (1u << (ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID - 96)),
-    // FIXME: Some of the entries below this point can be safely removed once
-    // this is tablegenerated. It's only needed because of the hardcoded
-    // register class limit.
-    // Classes 97-128
-    0,
-    // Classes 129-160
-    0,
-    // Classes 161-192
-    0,
-    // Classes 193-224
-    0,
-};
-
-// FIXME: The 200 will be replaced by the number of register classes when this is
-//        tablegenerated.
-RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData, 200);
-RegisterBank *RegBanks[] = {&GPRRegBank};
-
 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
 
 RegisterBankInfo::ValueMapping ValueMappings[] = {
     {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}};
 } // end namespace arm
 } // end namespace llvm
 
 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
-    : RegisterBankInfo(ARM::RegBanks, ARM::NumRegisterBanks) {
+    : ARMGenRegisterBankInfo() {
   static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (ARM::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.
   if (AlreadyInit)
     return;

lib/Target/ARM/ARMRegisterBanks.td

+//=- ARMRegisterBank.td - Describe the AArch64 Banks ---------*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;

lib/Target/ARM/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS ARM.td)
 
+tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)