[globalisel] Tablegen-erate current Register Bank Information

[dsanders]

Summary

Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.

[dsanders]

Small correction to fix a use-after-free that only manifested when asan was disabled.

[dsanders]

Rebase

[rovka]

Just a few nitpicks, other than that LGTM (but you should probably wait for someone more experienced to approve).

lib/Target/AArch64/AArch64RegisterBankInfo.h

19

I think it's nicer to use a macro that describes what we're trying to include rather than where we're including it, e.g. GET_REGBANK_DECLS or something of the sort. This also seems to be the style used in GenRegisterInfo.inc, GenSubtargetInfo.inc etc.

utils/TableGen/RegisterBankEmitter.cpp

203

How about visitRegisterBankClasses? The comment is clear enough on what something like that would mean :)

234

I think it would be cleaner to generate a comment instead of a moot assertion if Begin == End or Begin + 1 == End (and then you can also remove the I != End check in the loop).

305

Are the calls to .str() really necessary?

310

" not first "

[dsanders]

Updated following review:

• Use more descriptive macros when #include'ing tablegen-erated files
• Rename visitor function
• assert Begin!=End and simplify related for-loop.
• Remove redundant .str()'s
• getEnumeratorName() no longer returns a reference to an implicitly constructed local StringRef. This showed up when removing the .str()'s
• last -> first

[dsanders]

Thanks. I've updated the patch.

utils/TableGen/RegisterBankEmitter.cpp

203

As you can tell, I struggled to name this one :-). It doesn't really fit with 'overlapping', 'subclasses', 'subsets', etc.

I'll go with visitRegisterBankClasses()

234

The caller filters out the Begin == End case on line 303 (since Bank.hasPartialMappings() is a test for Begin != End). I think it's good to explicitly assert that here which leads to the same simplification you suggest.

Is that ok?

305

I thought I needed them for type-conversion but apparently not. I've gone through the other .str()'s too.

[rovka]

Thanks, I like the names a lot better now.

utils/TableGen/RegisterBankEmitter.cpp

234

Right, good point :)

[ab]

This seems reasonable, but:

• I don't think the PartialMapping exclusion mechanism is necessary. What about adding the missing mappings manually before landing this patch? Alternatively, replace the manual code with a copy of the generated mappings (once you have those) before any tablegen changes? That lets us split the generalization from the NFC tablegen changes without requiring hacks in-between.
• I'm not sure it's useful to generate the asserts: I think the intent was to check 1) the correctness of the manual description, and 2) it being consistent with the eventual tablegen output. Have you considered keeping them in AArch64RegisterBankInfo? I suppose generating them lets all targets have them. @qcolombet: what do you think?
• Also, can you extract the RegisterBank code to a shared location? (CodeGenRegBank? maybe rename it to CodeGenRegisters) ? That'll let us reuse it from the selector emitter backend. We can do that separately though.

utils/TableGen/RegisterBankEmitter.cpp

344

<Record *>

[ab]

utils/TableGen/RegisterBankEmitter.cpp

363

emitSourceFileHeader ?

[dsanders]

In D27338#618721, @ab wrote:

This seems reasonable, but:

• I don't think the PartialMapping exclusion mechanism is necessary. What about adding the missing mappings manually before landing this patch? Alternatively, replace the manual code with a copy of the generated mappings (once you have those) before any tablegen changes? That lets us split the generalization from the NFC tablegen changes without requiring hacks in-between.

It should be easy enough to add FPR's 8 and 16 mapping and CCR's 32 mapping. I'm not sure about FPR's 192 and 384 mappings though. There's definitely some code that assumes the sizes are a power of 2 (e.g. getRegBankBaseIdxOffset()) but I'm not sure how widespread that assumption is. I'd have to investigate.

• I'm not sure it's useful to generate the asserts: I think the intent was to check 1) the correctness of the manual description, and 2) it being consistent with the eventual tablegen output. Have you considered keeping them in AArch64RegisterBankInfo? I suppose generating them lets all targets have them. @qcolombet: what do you think?

I suppose it depends which direction you look at it. It makes sense to me to have the manual description check that the tablegen part meets its assumptions, but I also think it makes sense to have the tablegen-erated code check that it meets the assumptions of the manual code it's replacing.

For the assertions about PMI_* values, I think the majority of these will become unnecessary once the remaining pieces of AArch64GenRegisterBankInfo.def are tablegen-erated. Once that's done, I think it will all be internal to the tablegen-erated code except for the assumption that PMI_First* can be used to specify the register bank and I think we ought to use *RegBankID's for that instead.

For the assertions that call RB.covers(). I think this can be checked in either direction but it's a bit easier for tablegen to check that all the expected classes have been added since it's easy to forget a particular class when listing them manually.

For the assertions that call RB.getSize(). I think both places are equally good.

• Also, can you extract the RegisterBank code to a shared location? (CodeGenRegBank? maybe rename it to CodeGenRegisters) ? That'll let us reuse it from the selector emitter backend. We can do that separately though.

That makes sense to me. Is it ok if I do that as another patch at the end of my current patch-series? I could insert one before this one too but adding it to the end should save me some rebasing.

utils/TableGen/RegisterBankEmitter.cpp

344

Ok

363

Ok

[ab]

In D27338#619757, @dsanders wrote:

In D27338#618721, @ab wrote:

This seems reasonable, but:

• I don't think the PartialMapping exclusion mechanism is necessary. What about adding the missing mappings manually before landing this patch? Alternatively, replace the manual code with a copy of the generated mappings (once you have those) before any tablegen changes? That lets us split the generalization from the NFC tablegen changes without requiring hacks in-between.

It should be easy enough to add FPR's 8 and 16 mapping and CCR's 32 mapping. I'm not sure about FPR's 192 and 384 mappings though. There's definitely some code that assumes the sizes are a power of 2 (e.g. getRegBankBaseIdxOffset()) but I'm not sure how widespread that assumption is. I'd have to investigate.

Yeah, I was worried about that too, but I figured we'll have to generalize that logic at some point anyway, so we might as well clean up the C++ and have a drop-in NFC tablegen replacement.

• I'm not sure it's useful to generate the asserts: I think the intent was to check 1) the correctness of the manual description, and 2) it being consistent with the eventual tablegen output. Have you considered keeping them in AArch64RegisterBankInfo? I suppose generating them lets all targets have them. @qcolombet: what do you think?

I suppose it depends which direction you look at it. It makes sense to me to have the manual description check that the tablegen part meets its assumptions, but I also think it makes sense to have the tablegen-erated code check that it meets the assumptions of the manual code it's replacing.

For the assertions about PMI_* values, I think the majority of these will become unnecessary once the remaining pieces of AArch64GenRegisterBankInfo.def are tablegen-erated. Once that's done, I think it will all be internal to the tablegen-erated code except for the assumption that PMI_First* can be used to specify the register bank and I think we ought to use *RegBankID's for that instead.

For the assertions that call RB.covers(). I think this can be checked in either direction but it's a bit easier for tablegen to check that all the expected classes have been added since it's easy to forget a particular class when listing them manually.

For the assertions that call RB.getSize(). I think both places are equally good.

SGTM, let's reevaluate once .def is gone.

• Also, can you extract the RegisterBank code to a shared location? (CodeGenRegBank? maybe rename it to CodeGenRegisters) ? That'll let us reuse it from the selector emitter backend. We can do that separately though.

That makes sense to me. Is it ok if I do that as another patch at the end of my current patch-series? I could insert one before this one too but adding it to the end should save me some rebasing.

Sure, I'll rebase my patches on top and will copy the regbank code somewhere else for now.

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

46–48

How about:

• introduce an intermediate class, 'AArch64GenRegisterBankInfo'
• make the RegBanks array a member
• replace initGeneratedInfo with the ctor
• remove the AlreadyInit logic
• consolidate the now-redundant GET_REGBANK_*IFACE* into a single GET_REGBANK_IMPLEMENTATION to avoid having everything in the header

WDYT?

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

46–48

That makes sense to me.

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

46–48

consolidate the now-redundant GET_REGBANK_*IFACE* into a single GET_REGBANK_IMPLEMENTATION to avoid having everything in the header

On thinking about it a bit more, this step doesn't quite work. We can't merge the declaration and implementation together without putting the implementation in the header. I'll keep the declaration of AArch64GenRegisterBankInfo and the implementation separate to avoid putting everything in the header.

[qcolombet]

Hi Daniel,

Mostly looks good to me, I would however suggest two changes:

1. Drop the partial mapping support.
2. Add all the register classes covered by a RegisterBank statically.

For #1, I think that part should belong to something related to instruction pattern emitter.

For #2, the call to addRegBankCoverage still does a bunch of stuff at runtime whereas all doable at compile time. Indeed, I expect the tablegen backend to just populate the bit vector at compile time. Ultimately, I would like to change the representation of the covered register class into an array of uint32_t, so that we just get rid of the complexity of the BitVector. You can have a look at SubClassMask in TargetRegisterInfo and how we generate it to have an idea of what I am talking about.

Cheers,
-Quentin

include/llvm/Target/GlobalISel/RegisterBank.td

20

This seems gross.
I would rather patch the manual mapping than having to add this distinction.
Namely, right now we use clever tricks to access the element in the array, but I could totally see an enum or an array doing that mapping.
The reason why I did this was because it was the fastest thing to do :P.

The bottom line is, let us clean that up!

utils/TableGen/RegisterBankEmitter.cpp

39

Partial mappings are more a consequence of instruction patterns than register bank. I wouldn't expect this to happen here.

203

Right now, this method is used only once. Are there any plan to reuse it with a different functor?
If not, let us name it addSubRegisterClasses.

[dsanders]

Thanks. I'm going to put this patch on hold for the moment and post separate patches to lay the necessary groundwork to account for for the changes Ahmed and Quentin requested. I'll then work on updating this patch.

[dsanders]

Rewrote patch to work with the new static table based patch series and the related refactoring.

[dsanders]

@rengolin: Thanks. I hadn't noticed that @rovka was missing from this one.

[qcolombet]

Hi Daniel,

Nitpick stuff, the base is indeed sound and I expect we converge on the final patch quickly.

Thanks,
-Quentin

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

19

I would move that into AArch64RegisterBankInfo.cpp, right before the include of the .def.
Eventually, the .def will be removed so let us move all the useful code in the cpp.

20–21

Ditto.

24

Update the "// Idx: " in the comments to match the actual index.

29

Why do we need three of them instead of none previously?

At the very least I would have expected that we need just one of this input.

lib/Target/AArch64/AArch64RegisterBankInfo.h

20

We probably want GET_TARGET_REGBANK_CLASS as well, aren't we?
BTW, do we want to make this distinction?
Or put differently, shouldn't we guard all of those under GET_REGBANKINFO_HEADER so that we have an option to get everything needed without having to put all the macros down?

25–26

This shouldn't be "AArch64GenRegisterBankInfo : public RegisterBankInfo"
But "AArch64RegisterBankInfo : public AArch64GenRegisterBankInfo"

lib/Target/AArch64/AArch64RegisterBanks.td

12

I would expect an include of AArch64RegisterInfo.td, otherwise GPR64all and such won't be defined.

utils/TableGen/RegisterBankEmitter.cpp

33

Which StringRef are you referring to here?

45

I can see that for debug purposes it is good to get the name of the class with the largest size. Could you update the comment to get rid of the reference to the partial mapping and ExcludePartialMappings stuff, though?

156

I would add "iff any of this applies:"

160

You can add (a.k.a. subreg-class)

163

Add a comment explaining what is RC, Kind, and visitFn.

173

Period.

179

Period.

179

To be a bit more explicit here (or in the comment of the function) we could call out what it means to be a subreg-class:
PossibleSubclass is a subreg-class iff it exists a sub register index SubIdx such that for each register Reg in RC, Reg:SubIdx is in PossibleSubclass.

221

Before emitting the structure, could we emit a line with a comment with the general structure of each line?
E.g.,
<< "// ID, Name, MaxSize, CoveredRegClasses"

222

Following the other review, this should change to directly populate the register banks.

227

Could you add an assert that the current index in the array is equal to the expected value of the enumerator of the Bank?

233

Following the other review, I would rather have a simple TargetName for the namespace of the register banks.

236

With the direct initialization of the RegisterBank, we shouldn't need that section anymore, right?

263

Like I mentioned in my previous review, visitRegisterBankClasses is only used with this visitFn, thus, it seems to me like we could drop this parameter and call the proper function directly in visitRegisterBankClasses.

While here, we could rename it addSubClassesAndSubregClasses or something more explicitly like this.

[dsanders]

Rebased onto the new D27339 and re-worked to account for the changes to earlier patches in the series.

Removed the hard-coded 200 register class limit deferred from earlier patches in the series.

Updated to account for most of Quentin's comments. There's a couple I need to ask about.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

29

We should have had the three of them at the end of the table but got away without them because FPR was last and the missing elements weren't accessed. Now that FPR is first we need them to pad GPR's mappings out to the right indices.

I've added comments indicating the invalid mappings they correspond to.

lib/Target/AArch64/AArch64RegisterBankInfo.h

20

We probably want GET_TARGET_REGBANK_CLASS as well, aren't we?

Yes, but it needs to be inside the class declaration for the moment (see below).

BTW, do we want to make this distinction?

When everything is tablegen-erated: Probably not. I don't think there will be a need to keep them separate.

For the moment, PartialMappingIdx is the main blocking factor that prevents us from tablegen-erating the whole class and merging these two include points. There are enumerators missing (e.g. FPR192) at the moment.

25–26

No, this is the declaration of AArch64GenRegisterBankInfo which will eventually be fully tablegen-erated. AArch64RegisterBankInfo is declared next (line 95 at the moment) as class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo.

lib/Target/AArch64/AArch64RegisterBanks.td

12

This file is included by AArch64.td which includes AArch64RegisterInfo.td on the line before.

FWIW, I'm not very keen on all the tablegen files starting from AArch64.td as they currently do. It's wasteful to parse lots of classes and defs that never contribute to the output. We'll need to fix that in tablegen() in our CMake rules before we can start unpicking the dependencies here.

utils/TableGen/RegisterBankEmitter.cpp

33

I've forgotten to update the comment (and one just below). This used to be a std::vector<std::pair<const CodeGenRegisterClass *, StringRef>> back when the pass emitted assertions for membership. The reason for including a class is now printed in the -debug output.

221

This table has disappeared in the re-worked patches but I've added similar comments to the generated constructors instead.

236

That's right. This section has disappeared following that re-work.

263

The main reason I wrote it this way was to keep the high-level intent (add all the relevant classes) separate from the complexity of how we determine that a given register class is a member. I also needed to factor the current contents of visitFn() into a function (or triplicate it) and I thought it made most sense to put it here rather than in a static function off to the side.

I'm happy to fold it into visitRegisterBankClasses() and rename that if that's what you prefer.

[qcolombet]

LGTM.

lib/Target/AArch64/AArch64RegisterBankInfo.h

20

Ok.

25–26

Ah right, I missed the second declaration.

lib/Target/AArch64/AArch64RegisterBanks.td

12

Good point. Agreed.

utils/TableGen/RegisterBankEmitter.cpp

263

Up to you.
I found it easier to have the name of the function directly in the visit method instead of having to look at the call site, but your argument works as well.

[qcolombet]

LGTM.

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

29

Can't we update the indices or formulae so that we don't need those invalid entries at all?
If that's too complicated, I am fine with moving along with the current version. It will be table generated as some point any way.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

29

It doesn't look too complicated. We can stop getCopyMapping() needing the invalid entries by dropping the relevant size to index-offset mappings from getRegBankBaseIdxOffset(). However, getValueMapping() also uses that so we'd need to duplicate the function first before trimming the getCopyMapping() version.

It would be easiest for me to do this as a follow-up patch but I can insert it into the series if you prefer.

[qcolombet]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

29

Just move forward with the current version. It'll get clean up with the related tablegen support when we add that eventually.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

29

Ok, Thanks.

[ab]

lib/Target/AArch64/AArch64RegisterBankInfo.h

25–26

So, here's an alternative approach (more in line with what Quentin and I were thinking, I suspect): from day one, generate the entire AArch64GenRegisterBankInfo class. If something currently needs to be manually written code, keep it in AArch64RegisterBankInfo. When tablegen gains support for it, move it from the subclass to the generated base. Because AArch64RegisterBankInfo is-a AArch64GenRegisterBankInfo, all of these changes should be NFC. WDYT?

[dsanders]

Fix a couple stray 'AArch64' strings that should have been TargetName.

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.h

25–26

Is there an advantage to re-factoring the patch series that way? It seems equal to the current patch series to me in which case I'm leaning towards the current patches.

[ab]

lib/Target/AArch64/AArch64RegisterBankInfo.h

25–26

I suspect it helps make the changes easier to reason about (it's hard to keep track of the moving pieces); other than that, not really, no. Either way is fine by me!

[dsanders]

Refresh before commit

[dsanders]

Several buildbots encountered crashes when this was committed. Investigating

[ab]

lib/Target/AArch64/CMakeLists.txt

3

I didn't notice before, but now that you mention buildbot crashes: this should be in the if(LLVM_BUILD_GLOBAL_ISEL) block below.

[dsanders]

lib/Target/AArch64/CMakeLists.txt

3

Thanks. It hadn't occurred to me that I had too many buildbots complaining and had started looking for memory bugs. I don't think any GlobalISel bots failed so this is probably it.

include/llvm/Target/GlobalISel/RegisterBank.td

+//===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+class RegisterBank<string name, list<RegisterClass> classes> {
+  string Name = name;
+  list<RegisterClass> RegisterClasses = classes;
+  // FIXME: The PartialMapping enum omits a small number of sizes at the
+  //        moment. This lists the sizes that ought to exist according to the
+  //        register classes but currently don't.
+  list<int> ExcludePartialMappings = [];
+}

include/llvm/Target/Target.td

 // Pull in the common support for calling conventions.
 //
 include "llvm/Target/TargetCallingConv.td"
 
 //===----------------------------------------------------------------------===//
 // Pull in the common support for DAG isel generation.
 //
 include "llvm/Target/TargetSelectionDAG.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for GlobalISel.
+//
+include "llvm/Target/GlobalISel/RegisterBank.td"

lib/Target/AArch64/AArch64.td

 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
+include "AArch64RegisterBanks.td"
 include "AArch64CallingConvention.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "AArch64Schedule.td"
 include "AArch64InstrInfo.td"

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
 namespace llvm {
 namespace AArch64 {
 
-RegisterBank GPRRegBank;
-RegisterBank FPRRegBank;
-RegisterBank CCRRegBank;
-
-RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
-
 // PartialMappings.
 enum PartialMappingIdx {
   None = -1,
   GPR32 = 1,
   GPR64,
   FPR32,
   FPR64,
   FPR128,
   FPR256,
   FPR512,
   FirstGPR = GPR32,
   LastGPR = GPR64,
   FirstFPR = FPR32,
   LastFPR = FPR512,
   PartialMappingIdx_Min = FirstGPR,
 };
 

lib/Target/AArch64/AArch64RegisterBankInfo.h

 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
 
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 
+#define TBLGEN_REGISTERBANKINFO_H
+#include "AArch64GenRegisterBank.inc"
+
 namespace llvm {
 
 class TargetRegisterInfo;
 
-namespace AArch64 {
-enum {
-  GPRRegBankID = 0, /// General Purpose Registers: W, X.
-  FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
-  CCRRegBankID = 2, /// Conditional register: NZCV.
-  NumRegisterBanks
-};
-
-extern RegisterBank GPRRegBank;
-extern RegisterBank FPRRegBank;
-extern RegisterBank CCRRegBank;
-} // End AArch64 namespace.
-
 /// This class provides the information for the target register banks.
 class AArch64RegisterBankInfo final : public RegisterBankInfo {
   /// See RegisterBankInfo::applyMapping.
   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
 
   /// Get an instruction mapping where all the operands map to
   /// the same register bank and have similar size.
   ///
   /// \pre MI.getNumOperands() <= 3
public:
   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 
   /// Get the alternative mappings for \p MI.
   /// Alternative in the sense different from getInstrMapping.
   InstructionMappings
   getInstrAlternativeMappings(const MachineInstr &MI) const override;
 
   InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
+
+private:
+#define TBLGEN_REGISTERBANKINFO_PRIVATE_H
+#include "AArch64GenRegisterBank.inc"
 };
 } // End llvm namespace.
 #endif

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 // This file will be TableGen'ed at some point.
 #include "AArch64GenRegisterBankInfo.def"
+#define TBLGEN_REGISTERBANKINFO_CPP
+#include "AArch64GenRegisterBank.inc"
 
 using namespace llvm;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
 AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
     : RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) {
   static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (AArch64::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.
   if (AlreadyInit)
     return;
   AlreadyInit = true;
-  // Initialize the GPR bank.
-  createRegisterBank(AArch64::GPRRegBankID, "GPR");
-  // The GPR register bank is fully defined by all the registers in
-  // GR64all + its subclasses.
-  addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
+  initGeneratedInfo(TRI);
+// Now, the content.
+// Check partial mapping.
   const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
   (void)RBGPR;
-  assert(&AArch64::GPRRegBank == &RBGPR &&
-         "The order in RegBanks is messed up");
-  assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
-         "Subclass not added?");
-  assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
-
-  // Initialize the FPR bank.
-  createRegisterBank(AArch64::FPRRegBankID, "FPR");
-  // The FPR register bank is fully defined by all the registers in
-  // GR64all + its subclasses.
-  addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
   const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
   (void)RBFPR;
-  assert(&AArch64::FPRRegBank == &RBFPR &&
-         "The order in RegBanks is messed up");
-  assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
-         "Subclass not added?");
-  assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
-         "Subclass not added?");
-  assert(RBFPR.getSize() == 512 &&
-         "FPRs should hold up to 512-bit via QQQQ sequence");
-
-  // Initialize the CCR bank.
-  createRegisterBank(AArch64::CCRRegBankID, "CCR");
-  addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
-  const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
-  (void)RBCCR;
-  assert(&AArch64::CCRRegBank == &RBCCR &&
-         "The order in RegBanks is messed up");
-  assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
-         "Class not added?");
-  assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
-
-  // Check that the TableGen'ed like file is in sync we our expectations.
-  // First, the Idx.
-  assert(AArch64::PartialMappingIdx::GPR32 ==
-             AArch64::PartialMappingIdx::FirstGPR &&
-         "GPR32 index not first in the GPR list");
-  assert(AArch64::PartialMappingIdx::GPR64 ==
-             AArch64::PartialMappingIdx::LastGPR &&
-         "GPR64 index not last in the GPR list");
-  assert(AArch64::PartialMappingIdx::FirstGPR <=
-             AArch64::PartialMappingIdx::LastGPR &&
-         "GPR list is backward");
-  assert(AArch64::PartialMappingIdx::FPR32 ==
-             AArch64::PartialMappingIdx::FirstFPR &&
-         "FPR32 index not first in the FPR list");
-  assert(AArch64::PartialMappingIdx::FPR512 ==
-             AArch64::PartialMappingIdx::LastFPR &&
-         "FPR512 index not last in the FPR list");
-  assert(AArch64::PartialMappingIdx::FirstFPR <=
-             AArch64::PartialMappingIdx::LastFPR &&
-         "FPR list is backward");
-  assert(AArch64::PartialMappingIdx::FPR32 + 1 ==
-             AArch64::PartialMappingIdx::FPR64 &&
-         AArch64::PartialMappingIdx::FPR64 + 1 ==
-             AArch64::PartialMappingIdx::FPR128 &&
-         AArch64::PartialMappingIdx::FPR128 + 1 ==
-             AArch64::PartialMappingIdx::FPR256 &&
-         AArch64::PartialMappingIdx::FPR256 + 1 ==
-             AArch64::PartialMappingIdx::FPR512 &&
-         "FPR indices not properly ordered");
-// Now, the content.
-// Check partial mapping.
 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)                      \
   do {                                                                         \
     const PartialMapping &Map =                                                \
         AArch64::PartMappings[AArch64::Idx - AArch64::PartialMappingIdx_Min];  \
     (void) Map;                                                                \
     assert(Map.StartIdx == ValStartIdx && Map.Length == ValLength &&           \
            Map.RegBank == &RB && #Idx " is incorrectly initialized");          \
   } while (0)

lib/Target/AArch64/AArch64RegisterBanks.td

+//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+/// General Purpose Registers: W, X.
+def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
+
+/// Floating Point/Vector Registers: B, H, S, D, Q.
+def FPRRegBank : RegisterBank<"FPR", [QQQQ]> {
+  let ExcludePartialMappings = [8, 16, 192, 384];
+}
+
+/// Conditional register: NZCV.
+def CCRRegBank : RegisterBank<"CCR", [CCR]> {
+  let ExcludePartialMappings = [32];
+}

lib/Target/AArch64/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS AArch64.td)
 
+tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
 tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)

utils/TableGen/CMakeLists.txt

add_tablegen(llvm-tblgen LLVM
   DFAPacketizerEmitter.cpp
   DisassemblerEmitter.cpp
   FastISelEmitter.cpp
   FixedLenDecoderEmitter.cpp
   InstrInfoEmitter.cpp
   IntrinsicEmitter.cpp
   OptParserEmitter.cpp
   PseudoLoweringEmitter.cpp
+  RegisterBankEmitter.cpp
   RegisterInfoEmitter.cpp
   SearchableTableEmitter.cpp
   SubtargetEmitter.cpp
   SubtargetFeatureInfo.cpp
   TableGen.cpp
   X86DisassemblerTables.cpp
   X86ModRMFilters.cpp
   X86RecognizableInstr.cpp
   CTagsEmitter.cpp
   )

utils/TableGen/RegisterBankEmitter.cpp

+//===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend is responsible for emitting a description of a target
+// register bank for a code generator.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/BitVector.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+
+#include "CodeGenRegisters.h"
+
+using namespace llvm;
+
+namespace {
+class RegisterBank {
+public:
+  typedef std::vector<int32_t> PartialMappingsTy;
+
+  /// A vector of register classes. The StringRef indicates why the register
+  /// class is included in the register bank.
+  typedef std::vector<std::pair<const CodeGenRegisterClass *, const StringRef>>
+      RegisterClassesTy;
+
+private:
+  const Record &TheDef;
+
+  /// This is just enough information to emit an assertion correctly. We don't
+  /// handle partial mappings yet.
+  PartialMappingsTy PartialMappings;
+
+  /// The register classes that are covered by the register bank.
+  RegisterClassesTy RCs;
+
+  /// Used to report the register class associated with the min/max partial
+  /// mapping. It should be replaced when ExcludePartialMappings is removed.
+  const CodeGenRegisterClass *RCWithLargestRegsSize;
+
+  /// Used to report the register class associated with the min/max partial
+  /// mapping. It should be replaced when ExcludePartialMappings is removed.
+  const CodeGenRegisterClass *RCWithSmallestRegsSize;
+
+  void definePartialMapping(unsigned Size) {
+     PartialMappings.emplace_back(Size);
+  }
+
+public:
+  RegisterBank(const Record &TheDef)
+      : TheDef(TheDef), PartialMappings(), RCs(),
+        RCWithLargestRegsSize(nullptr), RCWithSmallestRegsSize(nullptr) {}
+  RegisterBank(const Record *TheDef) : RegisterBank(*TheDef) {}
+
+  /// Get the human-readable name for the bank.
+  std::string getName() const { return TheDef.getValueAsString("Name"); }
+
+  /// Get the name of the enumerator in the ID enumeration.
+  Twine getEnumeratorName() const { return TheDef.getName() + "ID"; }
+
+  /// Get the name of the global instance variable.
+  StringRef getInstanceVarName() const { return TheDef.getName(); }
+
+  const Record &getDef() const { return TheDef; }
+
+  /// Get the register classes listed in the RegisterBank.RegisterClasses field.
+  std::vector<const CodeGenRegisterClass *>
+  getExplictlySpecifiedRegisterClasses(
+      CodeGenRegBank &RegisterClassHierarchy) const {
+    std::vector<const CodeGenRegisterClass *> RCs;
+    for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
+      RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
+    return RCs;
+  }
+
+  /// Add a register class to the bank.
+  void addRegisterClass(const CodeGenRegisterClass *RC, const StringRef Kind) {
+    // FIXME? We really want the register size rather than the spill size
+    //        since the spill size may be bigger on some targets with
+    //        limited load/store instructions. However, we don't store the
+    //        register size anywhere (we could sum the sizes of the subregisters
+    //        but there may be additional bits too) and we can't derive it from
+    //        the VT's reliably due to Untyped.
+    const auto &Exclude =
+        getDef().getValueAsListOfInts("ExcludePartialMappings");
+    if (std::find(Exclude.begin(), Exclude.end(), RC->SpillSize) ==
+        Exclude.end()) {
+      if (RCWithLargestRegsSize == nullptr)
+        RCWithLargestRegsSize = RC;
+      else if (RCWithLargestRegsSize->SpillSize < RC->SpillSize)
+        RCWithLargestRegsSize = RC;
+
+      if (RCWithSmallestRegsSize == nullptr)
+        RCWithSmallestRegsSize = RC;
+      else if (RCWithSmallestRegsSize->SpillSize > RC->SpillSize)
+        RCWithSmallestRegsSize = RC;
+
+      definePartialMapping(RC->SpillSize);
+    }
+
+    RCs.emplace_back(RC, Kind);
+  }
+  const CodeGenRegisterClass *getRCWithLargestRegsSize() const {
+    return RCWithLargestRegsSize;
+  }
+  const CodeGenRegisterClass *getRCWithSmallestRegsSize() const {
+    return RCWithSmallestRegsSize;
+  }
+  iterator_range<typename RegisterClassesTy::const_iterator>
+  register_classes() const {
+    return llvm::make_range(RCs.begin(), RCs.end());
+  }
+
+  void finalizePartialMappings() {
+    std::sort(PartialMappings.begin(), PartialMappings.end());
+    PartialMappings.erase(
+        std::unique(PartialMappings.begin(), PartialMappings.end()),
+        PartialMappings.end());
+  }
+
+  bool hasPartialMappings() const {
+    return partial_mappings().begin() != partial_mappings().end();
+  }
+
+  /// This range is not valid if finalizePartialMappings() has not been
+  /// called.
+  iterator_range<typename PartialMappingsTy::const_iterator>
+  partial_mappings() const {
+    return llvm::make_range(PartialMappings.begin(), PartialMappings.end());
+  }
+};
+
+class RegisterBankEmitter {
+private:
+  RecordKeeper &Records;
+  CodeGenRegBank RegisterClassHierarchy;
+
+  void emitHeader(raw_ostream &OS, const StringRef TargetName,
+                  const std::vector<RegisterBank> &Banks);
+  void emitRegisterBankInfoPrivateMembers(raw_ostream &OS);
+  void
+  emitRegisterBankInfoImplementation(raw_ostream &OS,
+                                     const StringRef TargetName,
+                                     std::vector<RegisterBank> &Banks);
+
+public:
+  RegisterBankEmitter(RecordKeeper &R)
+      : Records(R), RegisterClassHierarchy(Records) {}
+
+  void run(raw_ostream &OS);
+};
+
+} // end anonymous namespace
+
+/// Emit code to declare the ID enumeration and external global instance
+/// variables.
+void RegisterBankEmitter::emitHeader(raw_ostream &OS,
+                                     const StringRef TargetName,
+                                     const std::vector<RegisterBank> &Banks) {
+  // <Target>RegisterBankInfo.h
+  OS << "#ifdef TBLGEN_REGISTERBANKINFO_H\n"
+     << "#undef TBLGEN_REGISTERBANKINFO_H\n"
+     << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n"
+     << "enum {\n";
+  for (const auto &Bank : Banks)
+    OS << "  " << Bank.getEnumeratorName().str() << ",\n";
+  OS << "  NumRegisterBanks,\n"
+     << "  NoRegisterBankID = ~0U,\n";
+  OS << "};\n"
+     << "\n"
+     << "extern RegisterBank NoRegisterBank;\n";
+  for (const auto &Bank : Banks)
+    OS << "extern RegisterBank " << Bank.getInstanceVarName() << ";\n";
+  OS << "} // end namespace " << TargetName << "\n"
+     << "} // end namespace llvm\n"
+     << "#endif // TBLGEN_REGISTERBANKINFO_H\n\n";
+}
+
+/// Emit declarations of tablegen-erated members of RegisterBankInfo.
+void RegisterBankEmitter::emitRegisterBankInfoPrivateMembers(raw_ostream &OS) {
+  // <Target>RegisterBankInfo private members
+  OS << "#ifdef TBLGEN_REGISTERBANKINFO_PRIVATE_H\n"
+     << "#undef TBLGEN_REGISTERBANKINFO_PRIVATE_H\n"
+     << "void initGeneratedInfo(const TargetRegisterInfo &TRI);\n"
+     << "#endif // TBLGEN_REGISTERBANKINFO_PRIVATE_H\n\n";
+}
+
+/// Visit each register class belonging to the given register bank.
+///
+/// A class belongs to the bank iff:
+/// * It is explicitly specified
+/// * It is a subclass of a class that is a member.
+/// * It is a class containing subregisters of the registers of a class that
+///   is a member.
+static void visitSelfAndSubclassesAndClassesWithSubRegs(
+    CodeGenRegBank &RegisterClassHierarchy, const RegisterBank &Bank,
+    std::function<void(const CodeGenRegisterClass *, StringRef)> visitFn) {
+  for (const CodeGenRegisterClass *RC :
+       Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+    // Visit each explicitly named class.
+    visitFn(RC, "self");
+
+    for (const auto &PossibleSubclass :
+         RegisterClassHierarchy.getRegClasses()) {
+      // Visit each subclass of an explicitly named class
+      if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
+        visitFn(&PossibleSubclass, "Subclass");
+
+      // Visit each class that has a subregister of RC
+      for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
+        BitVector BV(RegisterClassHierarchy.getRegClasses().size());
+        PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
+        if (BV.test(RC->EnumValue))
+          visitFn(&PossibleSubclass, "Class with subregs");
+      }
+    }
+  }
+}
+
+/// Emit an assertion that enumerator values are consecutive and in the same
+/// order as the iterator.
+static void emitPartialMappingSortedAssertion(
+    raw_ostream &OS, RegisterBank::PartialMappingsTy::const_iterator Begin,
+    RegisterBank::PartialMappingsTy::const_iterator End,
+    StringRef Enumeration, StringRef EnumeratorPrefix) {
+  OS << "    assert(";
+  for (RegisterBank::PartialMappingsTy::const_iterator I = Begin;
+       I != End && I + 1 != End; ++I) {
+    OS << Enumeration << "::" << EnumeratorPrefix << *I
+       << " + 1 == " << Enumeration << "::" << EnumeratorPrefix << *(I + 1)
+       << " &&\n           ";
+  }
+  OS << "\"" << EnumeratorPrefix << " indices not properly ordered\");\n";
+}
+
+void RegisterBankEmitter::emitRegisterBankInfoImplementation(
+    raw_ostream &OS, StringRef TargetName,
+    std::vector<RegisterBank> &Banks) {
+  // <Target>RegisterBankInfo.cpp
+  OS << "#ifdef TBLGEN_REGISTERBANKINFO_CPP\n"
+     << "#undef TBLGEN_REGISTERBANKINFO_CPP\n"
+     << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n";
+
+  // Declare the global instance variables.
+  OS << "RegisterBank NoRegisterBank;\n";
+  for (const auto &Bank : Banks)
+    OS << "RegisterBank " << Bank.getInstanceVarName() << ";\n";
+  OS << "\n";
+
+  // Declare the map of ID's to global instance variables.
+  OS << "RegisterBank *RegBanks[] = {\n";
+  for (const auto &Bank : Banks)
+    OS << "  &" << Bank.getInstanceVarName() << ",\n";
+  OS << "};\n"
+     << "} // end namespace " << TargetName << "\n\n";
+
+  OS << "void " << TargetName << "RegisterBankInfo::initGeneratedInfo(const "
+                                 "TargetRegisterInfo &TRI) {\n";
+  for (const auto &Bank : Banks) {
+    Twine QualifiedBank = TargetName + "::" + Bank.getInstanceVarName().str();
+    Twine QualifiedBankID = TargetName + "::" + Bank.getEnumeratorName().str();
+    OS << "  createRegisterBank(" << QualifiedBankID << ", \"" << Bank.getName()
+       << "\");\n";
+
+    for (const CodeGenRegisterClass *RC :
+         Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+      Twine QualifiedRegClassID =
+          TargetName + "::" + RC->getName() + "RegClassID";
+      OS << "  addRegBankCoverage(" << QualifiedBankID << ", "
+         << QualifiedRegClassID << ", TRI);\n";
+    }
+
+    OS << "#ifndef NDEBUG\n"
+       << "  {\n"
+       << "    const RegisterBank &RB = getRegBank(" << QualifiedBankID
+       << ");\n"
+       << "    assert(&" << QualifiedBank
+       << " == &RB && \"The order in RegBanks is messed up\");\n";
+
+    for (const auto &Pair : Bank.register_classes()) {
+      const CodeGenRegisterClass *RC = Pair.first;
+      const StringRef Kind = Pair.second;
+      // Assert that the class was added by addRegBankCoverage.
+      OS << "    assert(RB.covers(*TRI.getRegClass(" << RC->getQualifiedName()
+         << "RegClassID)) && \"" << Kind << " not added?\");\n";
+    }
+
+    Twine PartialMappingEnumerationName = TargetName + "::PartialMappingIdx";
+    // PartialMappingIdx is sorted with smallest sizes first. In addition to
+    // this FirstX and LastX are aliases of the first and last sizes in the
+    // list.
+    if (!Bank.hasPartialMappings()) {
+      OS << "    // No asserts on " << PartialMappingEnumerationName.str()
+         << " required because there are no valid sizes\n";
+    } else {
+      OS << "    assert(" << PartialMappingEnumerationName.str()
+         << "::" << Bank.getName() << Bank.getRCWithSmallestRegsSize()->SpillSize
+         << " == " << PartialMappingEnumerationName << "::First"
+         << Bank.getName() << " && "
+         << "\"" << Bank.getName() << Bank.getRCWithSmallestRegsSize()->SpillSize
+         << " not last in the " << Bank.getName() << " list\");\n";
+      OS << "    assert(" << PartialMappingEnumerationName.str()
+         << "::" << Bank.getName() << Bank.getRCWithLargestRegsSize()->SpillSize
+         << " == " << PartialMappingEnumerationName.str() << "::Last"
+         << Bank.getName() << " && "
+         << "\"" << Bank.getName() << Bank.getRCWithLargestRegsSize()->SpillSize
+         << " not last in the " << Bank.getName() << " list\");\n";
+      OS << "    assert(" << PartialMappingEnumerationName.str() << "::First"
+         << Bank.getName() << " <= " << PartialMappingEnumerationName.str()
+         << "::Last" << Bank.getName() << " && \"" << Bank.getName()
+         << " list is backward\");\n";
+
+      emitPartialMappingSortedAssertion(
+          OS, Bank.partial_mappings().begin(), Bank.partial_mappings().end(),
+          PartialMappingEnumerationName.str(), Bank.getName());
+
+      OS << "    assert(RB.getSize() == "
+         << Bank.getRCWithLargestRegsSize()->SpillSize << " && \""
+         << Bank.getName() << " should hold up to "
+         << Bank.getRCWithLargestRegsSize()->SpillSize << "-bits via "
+         << Bank.getRCWithLargestRegsSize()->getName() << "\");\n";
+    }
+    OS << "  }\n"
+       << "#endif // NDEBUG\n";
+  }
+  OS << "}\n";
+  OS << "} // end namespace llvm\n"
+     << "#endif // TBLGEN_REGISTERBANKINFO_CPP\n\n";
+}
+
+void RegisterBankEmitter::run(raw_ostream &OS) {
+  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
+  if (Targets.size() != 1)
+    PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
+  StringRef TargetName = Targets[0]->getName();
+
+  std::vector<RegisterBank> Banks;
+  for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
+    RegisterBank Bank(V);
+
+    visitSelfAndSubclassesAndClassesWithSubRegs(
+        RegisterClassHierarchy, Bank,
+        [&OS, &Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
+          Bank.addRegisterClass(RC, Kind);
+        });
+
+    Bank.finalizePartialMappings();
+    Banks.push_back(Bank);
+  }
+
+  OS << "// This file is generated. Do not edit.\n\n";
+  emitHeader(OS, TargetName, Banks);
+  emitRegisterBankInfoPrivateMembers(OS);
+  emitRegisterBankInfoImplementation(OS, TargetName, Banks);
+}
+
+namespace llvm {
+
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS) {
+  RegisterBankEmitter(RK).run(OS);
+}
+
+} // end namespace llvm

utils/TableGen/TableGen.cpp

enum ActionType {
   GenIntrinsic,
   GenTgtIntrinsic,
   PrintEnums,
   PrintSets,
   GenOptParserDefs,
   GenCTags,
   GenAttributes,
   GenSearchableTables,
+  GenRegisterBank,
 };
 
 namespace {
   cl::opt<ActionType>
   Action(cl::desc("Action to perform:"),
          cl::values(clEnumValN(PrintRecords, "print-records",
                                "Print all records to stdout (default)"),
                     clEnumValN(GenEmitter, "gen-emitter",
Action(cl::desc("Action to perform:"),
                                "Print expanded sets for testing DAG exprs"),
                     clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
                                "Generate option definitions"),
                     clEnumValN(GenCTags, "gen-ctags",
                                "Generate ctags-compatible index"),
                     clEnumValN(GenAttributes, "gen-attrs",
                                "Generate attributes"),
                     clEnumValN(GenSearchableTables, "gen-searchable-tables",
-                               "Generate generic binary-searchable table")));
+                               "Generate generic binary-searchable table"),
+                    clEnumValN(GenRegisterBank, "gen-register-bank",
+                               "Generate registers bank descriptions")));
 
   cl::opt<std::string>
   Class("class", cl::desc("Print Enum list for this class"),
           cl::value_desc("class name"));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
   case PrintRecords:
case GenCTags:
     EmitCTags(Records, OS);
     break;
   case GenAttributes:
     EmitAttributes(Records, OS);
     break;
   case GenSearchableTables:
     EmitSearchableTables(Records, OS);
     break;
+  case GenRegisterBank:
+    EmitRegisterBank(Records, OS);
+    break;
   }
 
   return false;
 }
 }
 
 int main(int argc, char **argv) {
   sys::PrintStackTraceOnErrorSignal(argv[0]);

utils/TableGen/TableGenBackends.h

 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS);
 void EmitMapTable(RecordKeeper &RK, raw_ostream &OS);
 void EmitOptParser(RecordKeeper &RK, raw_ostream &OS);
 void EmitCTags(RecordKeeper &RK, raw_ostream &OS);
 void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);
 void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS);
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
 
 } // End llvm namespace
 
 #endif