[globalisel] Initialize RegisterBanks with static data. Part 1 of 2.

[dsanders]

Summary

This patch is the first step in refactoring the RegisterBank to a static
table. This patch marks addRegBankCoverage() as unreachable and requires
GlobalISel implementations to rewrite this call into setRegBankMaxSize()
and setRegBankCoverage() calls. addRegBankCoverage() emits all the information
you need to do this rewrite just before calling llvm_unreachable().

The next patch will drop addRegBankCoverage() and move the data to a
static table.

[rovka]

I like the direction where this is going.
LGTM, but feel free to wait for more feedback from the others before committing this series.

[dsanders]

Thanks. I'll update this patch to cover ARM too (since the addRegBankCoverage change will break it) and get an LGTM for that too before committing

[qcolombet]

Hi Daniel,

Unless you can find a more elegant way for the intermediate step, I would push the change from BitSet to uint32_t* as part of the TableGen.
That being said, I think we could use intermediate steps:

1. Provide methods that perform the current add coverage logic, while producing the result in a dynamically allocated uint32_t
2. Gradually switch the dynamic array to static ones
3. Generate the static array with TableGen

Step #2 and #3 could be merged.

Cheers,
-Quentin

include/llvm/CodeGen/GlobalISel/RegisterBank.h

38 ↗

(On Diff #81579)

What's the use for this indirection?

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

426

What does CoveredClasses represent?

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

95

Why not directly use uint32_t *?
In particular, if we have target with more than 64 classes the API falls apart.

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

183

I think I would rather have the change in representation be part of the TableGen change, because the intermediate step is painful to read and write IMO.

223

Indeed, I don't want to check if this is correct :S

[dsanders]

Rebase and include ARM support (this change would otherwise break the recently-added ARM GlobalISel).

[dsanders]

In D27807#627299, @qcolombet wrote:

Hi Daniel,

Unless you can find a more elegant way for the intermediate step, I would push the change from BitSet to uint32_t* as part of the TableGen.

(I assume you mean BitVector rather than BitSet)

The problem with this is that BitVector needs to know its size in advance and this information is obtained from the TRI which doesn't exist at initialization-time.

That being said, I think we could use intermediate steps:

1. Provide methods that perform the current add coverage logic, while producing the result in a dynamically allocated uint32_t
2. Gradually switch the dynamic array to static ones
3. Generate the static array with TableGen

Step #2 and #3 could be merged.

Cheers,
-Quentin

That was my first approach but I was asked to create the static tables in advance and follow it with an NFC tablegen patch.

include/llvm/CodeGen/GlobalISel/RegisterBank.h

38 ↗

(On Diff #81579)

Tablegen is going to generate a big table of static register bank data and DataTy represents an element of that table. The elements appear in this patch (see GPRData) and the <BankName>Data members are merged into a single table in D27808.

Eventually, RegisterBank::Data will just be a reference to that static table. I was going to do it in the tablegen patch but there's no technical reason I can't make that change in this patch if you prefer.

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

426

It's the classes that addRegBankCoverage() used to add to the register bank.

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

95

I wasn't expecting to hit this before the tablegen patch landed and there was no longer a need for an API. However, the ARM target now has GlobalISel and has just under 100 classes so I hit this yesterday while rebasing. It's uint32_t* now.

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

183

I think I'm getting mutually exclusive comments. On the one hand I'm being asked to refactor up front so that the tablegen patch is NFC but on the other hand I'm being asked to defer that refactoring to the tablegen patch.

I agree that this is ugly but it's not needed for long and there are ways to avoid maintaining it manually. If you call addRegBankCoverage() then it will dump the classes before aborting and it's a simple transformation to convert the class list to this expression. I'm happy to maintain the patch series until they're all ready and commit them in quick succession if that helps.

[dsanders]

@rovka: I had to rework setRegBankCoverage() to account for the number of register classes in ARM (~100). Are you still ok with the latest version?

[rovka]

Hi,

Still LGTM, thanks!
For the record, until you can generate everything with TableGen, it's fine by me to handle only a subset of the ARM register classes (i.e. those that we have asserts for in ARMRegisterBankInfo). I can manually add the others as I run into them. I guess now you've already done all the work, but if it ever gets in your way later on feel free to get rid of the clutter.

[qcolombet]

The problem with this is that BitVector needs to know its size in advance and this information is obtained from the TRI which doesn't exist at initialization-time.

IIRC, we get this information statically when we do the generation of TargetRegisterInfo. I suspect we would need to refactor that code to reuse it here, but in the end, everything should be static and this finishInit should not be here.

That was my first approach but I was asked to create the static tables in advance and follow it with an NFC tablegen patch.

I believe the NFC approach is not incompatible with a change of representation in the same patch.

[dsanders]

Unless you can find a more elegant way for the intermediate step, I would push the change from BitSet to uint32_t* as part of the TableGen.

! In D27807#628051, @qcolombet wrote:
The problem with this is that BitVector needs to know its size in advance and this information is obtained from the TRI which doesn't exist at initialization-time.

IIRC, we get this information statically when we do the generation of TargetRegisterInfo. I suspect we would need to refactor that code to reuse it here, but in the end, everything should be static and this finishInit should not be here.

Yes, the information is available to tablegen but we don't have our tablegen pass until later in the patch series so we can't make use of that just yet. At the moment, the number of classes is only available to the backend after <Target>Subtarget has been constructed which is after the point that the table is initialized.

Would you be ok with this patch if I eliminate the finishInit() function in D27338 and make sure they are committed close together so we're not in this halfway state for long?

That being said, I think we could use intermediate steps:

1. Provide methods that perform the current add coverage logic, while producing the result in a dynamically allocated uint32_t
2. Gradually switch the dynamic array to static ones
3. Generate the static array with TableGen

Step #2 and #3 could be merged.

Cheers, -Quentin

That was my first approach but I was asked to create the static tables in advance and follow it with an NFC tablegen patch.

I believe the NFC approach is not incompatible with a change of representation in the same patch.

Sorry, I've been confusing here by mis-using 'NFC'. I meant that the plan was to re-factor into the desired implementation and then have a tablegen patch emit the same implementation.

For reference, the plan Ahmed suggested on D27338 was:

• introduce an intermediate class, 'AArch64GenRegisterBankInfo'
• make the RegBanks array a member
• replace initGeneratedInfo with the ctor
• remove the AlreadyInit logic
• consolidate the now-redundant GET_REGBANK_*IFACE* into a single GET_REGBANK_IMPLEMENTATION to avoid having everything in the header

My current patch series isn't completely in line with this at the moment (in particular AlreadyInit hasn't been removed yet) but this is the general direction I've been aiming for.

If we do switch to your plan, how would you construct the BitVectors for ARM. ARM has ~100 classes so I'd add BitVector(unsigned Size, uint32_t *Bits) but that brings us back to converting the BitVectors to uint32_t* before we tablegen the table.

[dsanders]

Updated to account for comments on later patches in the series.

RegisterBank::DataTy has been removed in favour of passing each value to
setRegBankData() and setRegBankCoverage(). RegisterBank::DataTy would have been
removed in D27809 in order to move to a similar initialization style as
TargetRegisterClass so it makes sense to not add it.

D27809 also requested that the finishInit() call that was added be removed.
This call was needed to use the TRI in the initialization of a BitVector but is
not needed by the end of the patch series. I've therefore hardcoded the number
of register classes as 200 and this will be changed in D27338 to be the number
of register classes defined for the target. This shouldn't be a problem since
D27338 already needs to be commited shortly after this patch to minimize the
maintenance burden of the register class tables.

Added the missing printing code to addRegBankCoverage().

This hasn't been rebased to trunk yet.

[qcolombet]

Hi Daniel,

LGTM with a couple of nitpicks.

No need for another room of review.

Cheers,
-Quentin

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

428

Could we merge these two methods?

Also, add a comment explaining the format of CoveredClasses and the effect on RegBank with ID. E.g., \post getRegBank(\p ID).getSize() == Size, etc.

lib/CodeGen/GlobalISel/RegisterBank.cpp

27

Maybe keep the assert but with >=?

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

187

Shouldn't we just delete this API instead?

[dsanders]

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

428

Sure. The next patch merges them at the moment but I can move that bit to this patch

lib/CodeGen/GlobalISel/RegisterBank.cpp

27

Ok

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

187

That's done in the next patch. It's been kept in this patch so that any targets that aren't migrated by this patch yet will dump the information needed to migrate instead of just failing to link.

[qcolombet]

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

187

Let's just squash the two part of this patch.
I expect that people would look at the commit list to understand why this method disappeared. Just add that information in the commit message.

[dsanders]

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

187

Ok. Other targets won't be able to apply a few s///'s to the dump to create the tables like I did but I suppose we can always point them at this version of the patch if we need to.

[dsanders]

Refresh before commit.

I regenerated the tables from the current trunk to be sure they were correct
and the ARM ones have changed upstream during the review.

[dsanders]

Squashed with D27808 in rL291768

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

protected:
   /// does not necessarily mean that \p ID covers the set of registers
   /// of RCId's superclasses.
   /// This method does *not* add the superreg classes as well for consistents.
   /// The expected use is to add the coverage top-down with respect to the
   /// register hierarchy.
   ///
   /// \todo TableGen should just generate the BitSet vector for us.
   void addRegBankCoverage(unsigned ID, unsigned RCId,
                           const TargetRegisterInfo &TRI);
+  void setRegBankData(unsigned ID, unsigned Size);
+  void setRegBankCoverage(unsigned ID, const uint32_t *CoveredClasses);
 
   /// Get the register bank identified by \p ID.
   RegisterBank &getRegBank(unsigned ID) {
     assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
     return *RegBanks[ID];
   }
 
   /// Try to get the mapping of \p MI.

lib/CodeGen/GlobalISel/RegisterBank.cpp

 using namespace llvm;
 
 const unsigned RegisterBank::InvalidID = UINT_MAX;
 
 RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {}
 
 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
   assert(isValid() && "Invalid register bank");
-  assert(ContainedRegClasses.size() == TRI.getNumRegClasses() &&
-         "TRI does not match the initialization process?");
   for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
 
     if (!covers(RC))
       continue;
     // Verify that the register bank covers all the sub classes of the
     // classes it covers.
 

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

void RegisterBankInfo::createRegisterBank(unsigned ID, const char *Name) {
   RegisterBank &RegBank = getRegBank(ID);
   assert(RegBank.getID() == RegisterBank::InvalidID &&
          "A register bank should be created only once");
   RegBank.ID = ID;
   RegBank.Name = Name;
 }
 
 void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
                                           const TargetRegisterInfo &TRI) {
   RegisterBank &RB = getRegBank(ID);
   unsigned NbOfRegClasses = TRI.getNumRegClasses();
 
   DEBUG(dbgs() << "Add coverage for: " << RB << '\n');
 
   // Check if RB is underconstruction.
   if (!RB.isValid())
     RB.ContainedRegClasses.resize(NbOfRegClasses);
for (unsigned SubRCId = 0; SubRCId < NbOfRegClasses; ++SubRCId) {
             break;
           }
         }
       }
     }
     if (!First)
       DEBUG(dbgs() << '\n');
   } while (!WorkList.empty());
+
+  RB.dump(&TRI);
+  llvm_unreachable("Please call setRegBankData() and setRegBankCoverage() instead");
+}
+
+void RegisterBankInfo::setRegBankData(unsigned ID, unsigned Size) {
+  RegisterBank &RB = getRegBank(ID);
+  RB.Size = Size;
+}
+
+void RegisterBankInfo::setRegBankCoverage(unsigned ID,
+                                          const uint32_t *CoveredClasses) {
+  RegisterBank &RB = getRegBank(ID);
+  RB.ContainedRegClasses.resize(200);
+  RB.ContainedRegClasses.setBitsInMask(CoveredClasses);
 }
 
 const RegisterBank *
 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
                              const TargetRegisterInfo &TRI) const {
   if (TargetRegisterInfo::isPhysicalRegister(Reg))
     return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg));
 

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

 #include "AArch64GenRegisterBankInfo.def"
 
 using namespace llvm;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
+const uint32_t GPRCoverageData[] = {
+    // Classes 0-31
+    (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |
+        (1u << AArch64::GPR32spRegClassID) |
+        (1u << AArch64::GPR32commonRegClassID) |
+        (1u << AArch64::GPR32sponlyRegClassID) |
+        (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |
+        (1u << AArch64::GPR64spRegClassID) |
+        (1u << AArch64::GPR64commonRegClassID) |
+        (1u << AArch64::tcGPR64RegClassID) |
+        (1u << AArch64::GPR64sponlyRegClassID),
+    // Classes 32-63
+    0,
+    // FIXME: The entries below this point can be safely removed once this is
+    // tablegenerated. It's only needed because of the hardcoded register class
+    // limit.
+    // Classes 64-96
+    0,
+    // Classes 97-128
+    0,
+    // Classes 129-160
+    0,
+    // Classes 161-192
+    0,
+    // Classes 193-224
+    0,
+};
+
+const uint32_t FPRCoverageData[] = {
+    // Classes 0-31
+    (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |
+        (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |
+        (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |
+        (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |
+        (1u << AArch64::DDDDRegClassID),
+    // Classes 32-63
+    (1u << (AArch64::QQRegClassID - 32)) |
+        (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+        (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+        (1u
+         << (AArch64::
+                 QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
+             32)) |
+        (1u << (AArch64::QQQQRegClassID - 32)) |
+        (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+        (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+        (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
+        (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
+        (1u
+         << (AArch64::
+                 QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
+             32)) |
+        (1u
+         << (AArch64::
+                 QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID -
+             32)) |
+        (1u << (AArch64::QQQRegClassID - 32)) |
+        (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+        (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+        (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
+        (1u
+         << (AArch64::
+                 QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID -
+             32)),
+    // FIXME: The entries below this point can be safely removed once this
+    // is tablegenerated. It's only needed because of the hardcoded register
+    // class limit.
+    // Classes 64-96
+    0,
+    // Classes 97-128
+    0,
+    // Classes 129-160
+    0,
+    // Classes 161-192
+    0,
+    // Classes 193-224
+    0,
+};
+
+const uint32_t CCRCoverageData[] = {
+    // Classes 0-31
+    1u << AArch64::CCRRegClassID,
+    // Classes 32-63
+    0,
+    // FIXME: The entries below this point can be safely removed once this
+    // is tablegenerated. It's only needed because of the hardcoded register
+    // class limit.
+    // Classes 64-96
+    0,
+    // Classes 97-128
+    0,
+    // Classes 129-160
+    0,
+    // Classes 161-192
+    0,
+    // Classes 193-224
+    0,
+};
+
 AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
     : RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) {
   static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (AArch64::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.
   if (AlreadyInit)
     return;
   AlreadyInit = true;
   // Initialize the GPR bank.
   createRegisterBank(AArch64::GPRRegBankID, "GPR");
   // The GPR register bank is fully defined by all the registers in
   // GR64all + its subclasses.
-  addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
+  setRegBankData(AArch64::GPRRegBankID, 64);
+  setRegBankCoverage(AArch64::GPRRegBankID, GPRCoverageData);
   const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
   (void)RBGPR;
   assert(&AArch64::GPRRegBank == &RBGPR &&
          "The order in RegBanks is messed up");
   assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
          "Subclass not added?");
   assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
 
   // Initialize the FPR bank.
   createRegisterBank(AArch64::FPRRegBankID, "FPR");
   // The FPR register bank is fully defined by all the registers in
   // GR64all + its subclasses.
-  addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
+  setRegBankData(AArch64::FPRRegBankID, 512);
+  setRegBankCoverage(AArch64::FPRRegBankID, FPRCoverageData);
+
   const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
   (void)RBFPR;
   assert(&AArch64::FPRRegBank == &RBFPR &&
          "The order in RegBanks is messed up");
   assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
          "Subclass not added?");
   assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
          "Subclass not added?");
   assert(RBFPR.getSize() == 512 &&
          "FPRs should hold up to 512-bit via QQQQ sequence");
 
   // Initialize the CCR bank.
   createRegisterBank(AArch64::CCRRegBankID, "CCR");
-  addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
+  setRegBankData(AArch64::CCRRegBankID, 32);
+  setRegBankCoverage(AArch64::CCRRegBankID, CCRCoverageData);
   const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
   (void)RBCCR;
   assert(&AArch64::CCRRegBank == &RBCCR &&
          "The order in RegBanks is messed up");
   assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
          "Class not added?");
   assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
 
   // Check that the TableGen'ed like file is in sync we our expectations.
   // First, the Idx.
   assert(AArch64::PartialMappingIdx::PMI_GPR32 ==
              AArch64::PartialMappingIdx::PMI_FirstGPR &&
          "GPR32 index not first in the GPR list");
   assert(AArch64::PartialMappingIdx::PMI_GPR64 ==
              AArch64::PartialMappingIdx::PMI_LastGPR &&
          "GPR64 index not last in the GPR list");
   assert(AArch64::PartialMappingIdx::PMI_FirstGPR <=
              AArch64::PartialMappingIdx::PMI_LastGPR &&
          "GPR list is backward");
   assert(AArch64::PartialMappingIdx::PMI_FPR32 ==
              AArch64::PartialMappingIdx::PMI_FirstFPR &&
          "FPR32 index not first in the FPR list");
   assert(AArch64::PartialMappingIdx::PMI_FPR512 ==
              AArch64::PartialMappingIdx::PMI_LastFPR &&
          "FPR512 index not last in the FPR list");
   assert(AArch64::PartialMappingIdx::PMI_FirstFPR <=
              AArch64::PartialMappingIdx::PMI_LastFPR &&
          "FPR list is backward");
   assert(AArch64::PartialMappingIdx::PMI_FPR32 + 1 ==

lib/Target/ARM/ARMRegisterBankInfo.cpp

 #error "You shouldn't build this"
 #endif
 
 // FIXME: TableGen this.
 // If it grows too much and TableGen still isn't ready to do the job, extract it
 // into an ARMGenRegisterBankInfo.def (similar to AArch64).
 namespace llvm {
 namespace ARM {
+const uint32_t GPRCoverageData[] = {
+    // Classes 0-31
+    (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
+        (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
+        (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
+        (1u << ARM::GPRnopc_and_hGPRRegClassID) |
+        (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
+        (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
+        (1u << ARM::hGPR_and_tcGPRRegClassID),
+    // Classes 32-63
+    0,
+    // Classes 64-96
+    0,
+    // FIXME: Some of the entries below this point can be safely removed once
+    // this is tablegenerated. It's only needed because of the hardcoded
+    // register class limit.
+    // Classes 97-128
+    0,
+    // Classes 129-160
+    0,
+    // Classes 161-192
+    0,
+    // Classes 193-224
+    0,
+};
+
 RegisterBank GPRRegBank;
 RegisterBank *RegBanks[] = {&GPRRegBank};
 
 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
 
 RegisterBankInfo::ValueMapping ValueMappings[] = {
     {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}};
 } // end namespace arm
 } // end namespace llvm
 
 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
     : RegisterBankInfo(ARM::RegBanks, ARM::NumRegisterBanks) {
   static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (ARM::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.
   if (AlreadyInit)
     return;
   AlreadyInit = true;
 
   // Initialize the GPR bank.
   createRegisterBank(ARM::GPRRegBankID, "GPRB");
-
-  addRegBankCoverage(ARM::GPRRegBankID, ARM::GPRRegClassID, TRI);
-  addRegBankCoverage(ARM::GPRRegBankID, ARM::GPRwithAPSRRegClassID, TRI);
+  setRegBankData(ARM::GPRRegBankID, 32);
+  setRegBankCoverage(ARM::GPRRegBankID, ARM::GPRCoverageData);
   const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
   (void)RBGPR;
   assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
          "Subclass not added?");
   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
          "Subclass not added?");
   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&