[InlineAsm] wrap Kind in enum class NFC

[nickdesaulniers]

Summary

Should add some minor type safety to the use of this information, since
there's quite a bit of metadata being laundered through an unsigned.

I'm looking to potentially add more bitfields to that unsigned, but I
find InlineAsm's big ol' bag of enum values and usage of unsigned
confusing, type-unsafe, and un-ergonomic. These can probably be better
abstracted.

I think the lack of static_cast outside of InlineAsm indicates the prior
code smell fixed here.

[qcolombet]

Nice clean-up!

llvm/include/llvm/IR/InlineAsm.h

public:
   static bool classof(const Value *V) {
     return V->getValueID() == Value::InlineAsmVal;
   }
 
   // These are helper methods for dealing with flags in the INLINEASM SDNode
   // in the backend.
   //
   // The encoding of the flag word is currently:
-  //   Bits 2-0 - A Kind_* value indicating the kind of the operand.
+  //   Bits 2-0 - A Kind::* value indicating the kind of the operand.
   //   Bits 15-3 - The number of SDNode operands associated with this inline
   //               assembly operand.
   //   If bit 31 is set:
   //     Bit 30-16 - The operand number that this operand must match.
-  //                 When bits 2-0 are Kind_Mem, the Constraint_* value must be
+  //                 When bits 2-0 are Kind::Mem, the Constraint_* value must be
   //                 obtained from the flags for this operand number.
-  //   Else if bits 2-0 are Kind_Mem:
+  //   Else if bits 2-0 are Kind::Mem:
   //     Bit 30-16 - A Constraint_* value indicating the original constraint
   //                 code.
   //   Else:
   //     Bit 30-16 - The register class ID to use for the operand.
 
   enum : uint32_t {
     // Fixed operands on an INLINEASM SDNode.
     Op_InputChain = 0,
     Op_AsmString = 1,
     Op_MDNode = 2,
-    Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
+    Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
     Op_FirstOperand = 4,
 
     // Fixed operands on an INLINEASM MachineInstr.
     MIOp_AsmString = 0,
-    MIOp_ExtraInfo = 1,    // HasSideEffects, IsAlignStack, AsmDialect.
+    MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
     MIOp_FirstOperand = 2,
 
     // Interpretation of the MIOp_ExtraInfo bit field.
     Extra_HasSideEffects = 1,
     Extra_IsAlignStack = 2,
     Extra_AsmDialect = 4,
     Extra_MayLoad = 8,
     Extra_MayStore = 16,
     Extra_IsConvergent = 32,
 
-    // Inline asm operands map to multiple SDNode / MachineInstr operands.
-    // The first operand is an immediate describing the asm operand, the low
-    // bits is the kind:
-    Kind_RegUse = 1,             // Input register, "r".
-    Kind_RegDef = 2,             // Output register, "=r".
-    Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
-    Kind_Clobber = 4,            // Clobbered register, "~r".
-    Kind_Imm = 5,                // Immediate.
-    Kind_Mem = 6,                // Memory operand, "m", or an address, "p".
-    Kind_Func = 7,               // Address operand of function call
-
     // Memory constraint codes.
     // These could be tablegenerated but there's little need to do that since
     // there's plenty of space in the encoding to support the union of all
     // constraint codes for all targets.
     // Addresses are included here as they need to be treated the same by the
     // backend, the only difference is that they are not used to actaully
     // access memory by the instruction.
     Constraint_Unknown = 0,
enum : uint32_t {
     Constraint_ZT,
 
     Constraints_Max = Constraint_ZT,
     Constraints_ShiftAmount = 16,
 
     Flag_MatchingOperand = 0x80000000
   };
 
-  static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
+  // Inline asm operands map to multiple SDNode / MachineInstr operands.
+  // The first operand is an immediate describing the asm operand, the low
+  // bits is the kind:
+  enum class Kind {
+    RegUse = 1,             // Input register, "r".
+    RegDef = 2,             // Output register, "=r".
+    RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
+    Clobber = 4,            // Clobbered register, "~r".
+    Imm = 5,                // Immediate.
+    Mem = 6,                // Memory operand, "m", or an address, "p".
+    Func = 7,               // Address operand of function call
+  };
+
+  static unsigned getFlagWord(Kind Kind, unsigned NumOps) {
     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
-    assert(Kind >= Kind_RegUse && Kind <= Kind_Func && "Invalid Kind");
-    return Kind | (NumOps << 3);
+    return static_cast<unsigned>(Kind) | (NumOps << 3);
   }
 
-  static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
-  static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
-  static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
-  static bool isFuncKind(unsigned Flag) { return getKind(Flag) == Kind_Func; }
+  static bool isRegDefKind(unsigned Flag) {
+    return getKind(Flag) == Kind::RegDef;
+  }
+  static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind::Imm; }
+  static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind::Mem; }
+  static bool isFuncKind(unsigned Flag) { return getKind(Flag) == Kind::Func; }
   static bool isRegDefEarlyClobberKind(unsigned Flag) {
-    return getKind(Flag) == Kind_RegDefEarlyClobber;
+    return getKind(Flag) == Kind::RegDefEarlyClobber;
   }
   static bool isClobberKind(unsigned Flag) {
-    return getKind(Flag) == Kind_Clobber;
+    return getKind(Flag) == Kind::Clobber;
   }
 
   /// getFlagWordForMatchingOp - Augment an existing flag word returned by
   /// getFlagWord with information indicating that this input operand is tied
   /// to a previous output operand.
   static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
                                            unsigned MatchedOperandNo) {
     assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
     return InputFlag | (Constraint << Constraints_ShiftAmount);
   }
 
   static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
     assert(isMemKind(InputFlag));
     return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
   }
 
-  static unsigned getKind(unsigned Flags) {
-    return Flags & 7;
-  }
+  static Kind getKind(unsigned Flags) { return static_cast<Kind>(Flags & 7); }
 
   static unsigned getMemoryConstraintID(unsigned Flag) {
     assert((isMemKind(Flag) || isFuncKind(Flag)) &&
            "Not expected mem or function flang!");
     return (Flag >> Constraints_ShiftAmount) & 0x7fff;
   }
 
   /// getNumOperandRegisters - Extract the number of registers field from the
static std::vector<StringRef> getExtraInfoNames(unsigned ExtraInfo) {
     if (Dialect == InlineAsm::AD_ATT)
       Result.push_back("attdialect");
     if (Dialect == InlineAsm::AD_Intel)
       Result.push_back("inteldialect");
 
     return Result;
   }
 
-  static StringRef getKindName(unsigned Kind) {
+  static StringRef getKindName(Kind Kind) {
     switch (Kind) {
-    case InlineAsm::Kind_RegUse:
+    case Kind::RegUse:
       return "reguse";
-    case InlineAsm::Kind_RegDef:
+    case Kind::RegDef:
       return "regdef";
-    case InlineAsm::Kind_RegDefEarlyClobber:
+    case Kind::RegDefEarlyClobber:
       return "regdef-ec";
-    case InlineAsm::Kind_Clobber:
+    case Kind::Clobber:
       return "clobber";
-    case InlineAsm::Kind_Imm:
+    case Kind::Imm:
       return "imm";
-    case InlineAsm::Kind_Mem:
-    case InlineAsm::Kind_Func:
+    case Kind::Mem:
+    case Kind::Func:
       return "mem";
-    default:
-      llvm_unreachable("Unknown operand kind");
     }
+    llvm_unreachable("Unknown operand kind");
   }
 
   static StringRef getMemConstraintName(unsigned Constraint) {
     switch (Constraint) {
     case InlineAsm::Constraint_es:
       return "es";
     case InlineAsm::Constraint_i:
       return "i";

llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

void AsmPrinter::emitInlineAsm(const MachineInstr *MI) const {
   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
   // Start with the first operand descriptor, and iterate over them.
   for (unsigned I = InlineAsm::MIOp_FirstOperand, NumOps = MI->getNumOperands();
        I < NumOps; ++I) {
     const MachineOperand &MO = MI->getOperand(I);
     if (!MO.isImm())
       continue;
     unsigned Flags = MO.getImm();
-    if (InlineAsm::getKind(Flags) == InlineAsm::Kind_Clobber) {
+    if (InlineAsm::getKind(Flags) == InlineAsm::Kind::Clobber) {
       Register Reg = MI->getOperand(I + 1).getReg();
       if (!TRI->isAsmClobberable(*MF, Reg))
         RestrRegs.push_back(Reg);
     }
     // Skip to one before the next operand descriptor, if it exists.
     I += InlineAsm::getNumOperandRegisters(Flags);
   }
 

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

case InlineAsm::isOutput:
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
         unsigned ConstraintID =
             TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM instruction to know about this
         // output.
-        unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
+        unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
         OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
         Inst.addImm(OpFlags);
         ArrayRef<Register> SourceRegs =
             GetOrCreateVRegs(*OpInfo.CallOperandVal);
         assert(
             SourceRegs.size() == 1 &&
             "Expected the memory output to fit into a single virtual register");
         Inst.addReg(SourceRegs[0]);
case InlineAsm::isOutput:
           LLVM_DEBUG(dbgs()
                      << "Couldn't allocate output register for constraint\n");
           return false;
         }
 
         // Add information to the INLINEASM instruction to know that this
         // register is set.
         unsigned Flag = InlineAsm::getFlagWord(
-            OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
-                                  : InlineAsm::Kind_RegDef,
+            OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
+                                  : InlineAsm::Kind::RegDef,
             OpInfo.Regs.size());
         if (OpInfo.Regs.front().isVirtual()) {
           // Put the register class of the virtual registers in the flag word.
           // That way, later passes can recompute register class constraints for
           // inline assembly as well as normal instructions. Don't do this for
           // tied operands that can use the regclass information from the def.
           const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
           Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
case InlineAsm::isLabel: {
         // When Def is vreg: copy input to new vreg with same reg class as Def.
         if (Def.isVirtual()) {
           In = MRI->createVirtualRegister(MRI->getRegClass(Def));
           if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder))
             return false;
         }
 
         // Add Flag and input register operand (In) to Inst. Tie In to Def.
-        unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
+        unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, 1);
         unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
         Inst.addImm(Flag);
         Inst.addReg(In);
         Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1);
         break;
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Other &&
case InlineAsm::isLabel: {
           return false;
         }
 
         assert(Ops.size() > 0 &&
                "Expected constraint to be lowered to at least one operand");
 
         // Add information to the INLINEASM node to know about this input.
         unsigned OpFlags =
-            InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
+            InlineAsm::getFlagWord(InlineAsm::Kind::Imm, Ops.size());
         Inst.addImm(OpFlags);
         Inst.add(Ops);
         break;
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
 
         if (!OpInfo.isIndirect) {
           LLVM_DEBUG(dbgs()
                      << "Cannot indirectify memory input operands yet\n");
           return false;
         }
 
         assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
 
         unsigned ConstraintID =
             TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
-        unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
+        unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
         OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
         Inst.addImm(OpFlags);
         ArrayRef<Register> SourceRegs =
             GetOrCreateVRegs(*OpInfo.CallOperandVal);
         assert(
             SourceRegs.size() == 1 &&
             "Expected the memory input to fit into a single virtual register");
         Inst.addReg(SourceRegs[0]);
case InlineAsm::isLabel: {
              "source registers");
 
       if (NumRegs > 1) {
         LLVM_DEBUG(dbgs() << "Input operands with multiple input registers are "
                              "not supported yet\n");
         return false;
       }
 
-      unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs);
+      unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, NumRegs);
       if (OpInfo.Regs.front().isVirtual()) {
         // Put the register class of the virtual registers in the flag word.
         const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
         Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
       }
       Inst.addImm(Flag);
       if (!buildAnyextOrCopy(OpInfo.Regs[0], SourceRegs[0], MIRBuilder))
         return false;
       Inst.addReg(OpInfo.Regs[0]);
       break;
     }
 
     case InlineAsm::isClobber: {
 
       unsigned NumRegs = OpInfo.Regs.size();
       if (NumRegs > 0) {
         unsigned Flag =
-            InlineAsm::getFlagWord(InlineAsm::Kind_Clobber, NumRegs);
+            InlineAsm::getFlagWord(InlineAsm::Kind::Clobber, NumRegs);
         Inst.addImm(Flag);
 
         for (Register Reg : OpInfo.Regs) {
           Inst.addReg(Reg, RegState::Define | RegState::EarlyClobber |
                                getImplRegState(Reg.isPhysical()));
         }
       }
       break;

llvm/lib/CodeGen/MachineInstr.cpp

MachineInstr::getRegClassConstraint(unsigned OpIdx,
 
   // Inline asm stores register class constraints in the flag word.
   int FlagIdx = findInlineAsmFlagIdx(OpIdx);
   if (FlagIdx < 0)
     return nullptr;
 
   unsigned Flag = getOperand(FlagIdx).getImm();
   unsigned RCID;
-  if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
-       InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
-       InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
+  if ((InlineAsm::getKind(Flag) == InlineAsm::Kind::RegUse ||
+       InlineAsm::getKind(Flag) == InlineAsm::Kind::RegDef ||
+       InlineAsm::getKind(Flag) == InlineAsm::Kind::RegDefEarlyClobber) &&
       InlineAsm::hasRegClassConstraint(Flag, RCID))
     return TRI->getRegClass(RCID);
 
   // Assume that all registers in a memory operand are pointers.
-  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
+  if (InlineAsm::getKind(Flag) == InlineAsm::Kind::Mem)
     return TRI->getPointerRegClass(MF);
 
   return nullptr;
 }
 
 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
     Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
     const TargetRegisterInfo *TRI, bool ExploreBundle) const {

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
       const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 
       GroupIdx.push_back(MIB->getNumOperands());
       MIB.addImm(Flags);
       ++i;  // Skip the ID value.
 
       switch (InlineAsm::getKind(Flags)) {
-      default: llvm_unreachable("Bad flags!");
-        case InlineAsm::Kind_RegDef:
+      case InlineAsm::Kind::RegDef:
         for (unsigned j = 0; j != NumVals; ++j, ++i) {
           Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
           // FIXME: Add dead flags for physical and virtual registers defined.
           // For now, mark physical register defs as implicit to help fast
           // regalloc. This makes inline asm look a lot like calls.
           MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical()));
         }
         break;
-      case InlineAsm::Kind_RegDefEarlyClobber:
-      case InlineAsm::Kind_Clobber:
+      case InlineAsm::Kind::RegDefEarlyClobber:
+      case InlineAsm::Kind::Clobber:
         for (unsigned j = 0; j != NumVals; ++j, ++i) {
           Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
           MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
                               getImplRegState(Reg.isPhysical()));
           ECRegs.push_back(Reg);
         }
         break;
-      case InlineAsm::Kind_RegUse:  // Use of register.
-      case InlineAsm::Kind_Imm:  // Immediate.
-      case InlineAsm::Kind_Mem:  // Non-function addressing mode.
+      case InlineAsm::Kind::RegUse: // Use of register.
+      case InlineAsm::Kind::Imm:    // Immediate.
+      case InlineAsm::Kind::Mem:    // Non-function addressing mode.
         // The addressing mode has been selected, just add all of the
         // operands to the machine instruction.
         for (unsigned j = 0; j != NumVals; ++j, ++i)
           AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
                      /*IsDebug=*/false, IsClone, IsCloned);
 
         // Manually set isTied bits.
-        if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
+        if (InlineAsm::getKind(Flags) == InlineAsm::Kind::RegUse) {
           unsigned DefGroup = 0;
           if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
             unsigned DefIdx = GroupIdx[DefGroup] + 1;
             unsigned UseIdx = GroupIdx.back() + 1;
             for (unsigned j = 0; j != NumVals; ++j)
               MIB->tieOperands(DefIdx + j, UseIdx + j);
           }
         }
         break;
-      case InlineAsm::Kind_Func: // Function addressing mode.
+      case InlineAsm::Kind::Func: // Function addressing mode.
         for (unsigned j = 0; j != NumVals; ++j, ++i) {
           SDValue Op = Node->getOperand(i);
           AddOperand(MIB, Op, 0, nullptr, VRBaseMap,
                      /*IsDebug=*/false, IsClone, IsCloned);
 
           // Adjust Target Flags for function reference.
           if (auto *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
             unsigned NewFlags =

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

struct RegsForValue {
   /// diagnostic messages on error.
   void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl,
                      SDValue &Chain, SDValue *Glue, const Value *V = nullptr,
                      ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
 
   /// Add this value to the specified inlineasm node operand list. This adds the
   /// code marker, matching input operand index (if applicable), and includes
   /// the number of values added into it.
-  void AddInlineAsmOperands(unsigned Code, bool HasMatching,
+  void AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
                             unsigned MatchingIdx, const SDLoc &dl,
                             SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
 
   /// Check if the total RegCount is greater than one.
   bool occupiesMultipleRegs() const {
     return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
   }
 
   /// Return a list of registers and their sizes.
   SmallVector<std::pair<unsigned, TypeSize>, 4> getRegsAndSizes() const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (NumRegs == 1 || Glue)
     // c3     = TokenFactor c1, c2
     // ...
     //        = op c3, ..., f2
     Chain = Chains[NumRegs-1];
   else
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
 }
 
-void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
+void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
                                         unsigned MatchingIdx, const SDLoc &dl,
                                         SelectionDAG &DAG,
                                         std::vector<SDValue> &Ops) const {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
   unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
   if (HasMatching)
     Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
   else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
     // Put the register class of the virtual registers in the flag word.  That
     // way, later passes can recompute register class constraints for inline
     // assembly as well as normal instructions.
     // Don't do this for tied operands that can use the regclass information
     // from the def.
     const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
     const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
     Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
   }
 
   SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
   Ops.push_back(Res);
 
-  if (Code == InlineAsm::Kind_Clobber) {
+  if (Code == InlineAsm::Kind::Clobber) {
     // Clobbers should always have a 1:1 mapping with registers, and may
     // reference registers that have illegal (e.g. vector) types. Hence, we
     // shouldn't try to apply any sort of splitting logic to them.
     assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
            "No 1:1 mapping from clobbers to regs?");
     Register SP = TLI.getStackPointerRegisterToSaveRestore();
     (void)SP;
     for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
     case InlineAsm::isOutput:
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
         unsigned ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM node to know about this output.
-        unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
+        unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
         OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
         AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
                                                         MVT::i32));
         AsmNodeOperands.push_back(OpInfo.CallOperand);
       } else {
         // Otherwise, this outputs to a register (directly for C_Register /
         // C_RegisterClass, and a target-defined fashion for
         // C_Immediate/C_Other). Find a register that we can use.
         if (OpInfo.AssignedRegs.Regs.empty()) {
           emitInlineAsmError(
               Call, "couldn't allocate output register for constraint '" +
                         Twine(OpInfo.ConstraintCode) + "'");
           return;
         }
 
         if (DetectWriteToReservedRegister())
           return;
 
         // Add information to the INLINEASM node to know that this register is
         // set.
         OpInfo.AssignedRegs.AddInlineAsmOperands(
-            OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
-                                  : InlineAsm::Kind_RegDef,
+            OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
+                                  : InlineAsm::Kind::RegDef,
             false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
       }
       break;
 
     case InlineAsm::isInput:
     case InlineAsm::isLabel: {
       SDValue InOperandVal = OpInfo.CallOperand;
 
case InlineAsm::isLabel: {
           for (unsigned i = 0; i != NumRegs; ++i)
             Regs.push_back(MRI.createVirtualRegister(RC));
 
           RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
 
           SDLoc dl = getCurSDLoc();
           // Use the produced MatchedRegs object to
           MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, &Call);
-          MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
-                                           true, OpInfo.getMatchedOperand(), dl,
-                                           DAG, AsmNodeOperands);
+          MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, true,
+                                           OpInfo.getMatchedOperand(), dl, DAG,
+                                           AsmNodeOperands);
           break;
         }
 
         assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
         assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
                "Unexpected number of operands");
         // Add information to the INLINEASM node to know about this input.
         // See InlineAsm.h isUseOperandTiedToDef.
case InlineAsm::isLabel: {
           emitInlineAsmError(Call,
                              "invalid operand for inline asm constraint '" +
                                  Twine(OpInfo.ConstraintCode) + "'");
           return;
         }
 
         // Add information to the INLINEASM node to know about this input.
         unsigned ResOpType =
-          InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
+            InlineAsm::getFlagWord(InlineAsm::Kind::Imm, Ops.size());
         AsmNodeOperands.push_back(DAG.getTargetConstant(
             ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
         llvm::append_range(AsmNodeOperands, Ops);
         break;
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
         assert((OpInfo.isIndirect ||
                 OpInfo.ConstraintType != TargetLowering::C_Memory) &&
                "Operand must be indirect to be a mem!");
         assert(InOperandVal.getValueType() ==
                    TLI.getPointerTy(DAG.getDataLayout()) &&
                "Memory operands expect pointer values");
 
         unsigned ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM node to know about this input.
-        unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
+        unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
         ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
         AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
                                                         getCurSDLoc(),
                                                         MVT::i32));
         AsmNodeOperands.push_back(InOperandVal);
         break;
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Address) {
         unsigned ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
-        unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
+        unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
 
         SDValue AsmOp = InOperandVal;
         if (isFunction(InOperandVal)) {
           auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
-          ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Func, 1);
+          ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Func, 1);
           AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(),
                                              InOperandVal.getValueType(),
                                              GA->getOffset());
         }
 
         // Add information to the INLINEASM node to know about this input.
         ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
 
case InlineAsm::isLabel: {
       if (DetectWriteToReservedRegister())
         return;
 
       SDLoc dl = getCurSDLoc();
 
       OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue,
                                         &Call);
 
-      OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
-                                               dl, DAG, AsmNodeOperands);
+      OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, false,
+                                               0, dl, DAG, AsmNodeOperands);
       break;
     }
     case InlineAsm::isClobber:
       // Add the clobbered value to the operand list, so that the register
       // allocator is aware that the physreg got clobbered.
       if (!OpInfo.AssignedRegs.Regs.empty())
-        OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
+        OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::Clobber,
                                                  false, 0, getCurSDLoc(), DAG,
                                                  AsmNodeOperands);
       break;
     }
   }
 
   // Finish up input operands.  Set the input chain and add the flag last.
   AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

if (!InlineAsm::isMemKind(Flags) && !InlineAsm::isFuncKind(Flags)) {
       unsigned ConstraintID = InlineAsm::getMemoryConstraintID(Flags);
       if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
         report_fatal_error("Could not match memory address.  Inline asm"
                            " failure!");
 
       // Add this to the output node.
       unsigned NewFlags =
           InlineAsm::isMemKind(Flags)
-              ? InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size())
-              : InlineAsm::getFlagWord(InlineAsm::Kind_Func, SelOps.size());
+              ? InlineAsm::getFlagWord(InlineAsm::Kind::Mem, SelOps.size())
+              : InlineAsm::getFlagWord(InlineAsm::Kind::Func, SelOps.size());
       NewFlags = InlineAsm::getFlagWordForMem(NewFlags, ConstraintID);
       Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
       llvm::append_range(Ops, SelOps);
       i += 2;
     }
   }
 
   // Add the glue input back if present.

llvm/lib/CodeGen/TargetInstrInfo.cpp

std::string TargetInstrInfo::createMIROperandComment(
 
   int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
   if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
     return "";
 
   assert(Op.isImm() && "Expected flag operand to be an immediate");
   // Pretty print the inline asm operand descriptor.
   unsigned Flag = Op.getImm();
-  unsigned Kind = InlineAsm::getKind(Flag);
+  InlineAsm::Kind Kind = InlineAsm::getKind(Flag);
   OS << InlineAsm::getKindName(Kind);
 
   unsigned RCID = 0;
   if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
       InlineAsm::hasRegClassConstraint(Flag, RCID)) {
     if (TRI) {
       OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
     } else

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

if (Mask != -1) {
     return true;
   }
 
   return false;
 }
 
 bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
   std::vector<SDValue> AsmNodeOperands;
-  unsigned Flag, Kind;
+  unsigned Flag;
+  InlineAsm::Kind Kind;
   bool Changed = false;
   unsigned NumOps = N->getNumOperands();
 
   // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
   // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
   // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
   // respectively. Since there is no constraint to explicitly specify a
   // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
       Flag = C->getZExtValue();
       Kind = InlineAsm::getKind(Flag);
     }
     else
       continue;
 
     // Immediate operands to inline asm in the SelectionDAG are modeled with
-    // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
+    // two operands. The first is a constant of value InlineAsm::Kind::Imm, and
     // the second is a constant with the value of the immediate. If we get here
-    // and we have a Kind_Imm, skip the next operand, and continue.
-    if (Kind == InlineAsm::Kind_Imm) {
+    // and we have a Kind::Imm, skip the next operand, and continue.
+    if (Kind == InlineAsm::Kind::Imm) {
       SDValue op = N->getOperand(++i);
       AsmNodeOperands.push_back(op);
       continue;
     }
 
     unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
     if (NumRegs)
       OpChanged.push_back(false);
 
     unsigned DefIdx = 0;
     bool IsTiedToChangedOp = false;
     // If it's a use that is tied with a previous def, it has no
     // reg class constraint.
     if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
       IsTiedToChangedOp = OpChanged[DefIdx];
 
     // Memory operands to inline asm in the SelectionDAG are modeled with two
-    // operands: a constant of value InlineAsm::Kind_Mem followed by the input
-    // operand. If we get here and we have a Kind_Mem, skip the next operand (so
-    // it doesn't get misinterpreted), and continue. We do this here because
+    // operands: a constant of value InlineAsm::Kind::Mem followed by the input
+    // operand. If we get here and we have a Kind::Mem, skip the next operand
+    // (so it doesn't get misinterpreted), and continue. We do this here because
     // it's important to update the OpChanged array correctly before moving on.
-    if (Kind == InlineAsm::Kind_Mem) {
+    if (Kind == InlineAsm::Kind::Mem) {
       SDValue op = N->getOperand(++i);
       AsmNodeOperands.push_back(op);
       continue;
     }
 
-    if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
-        && Kind != InlineAsm::Kind_RegDefEarlyClobber)
+    if (Kind != InlineAsm::Kind::RegUse && Kind != InlineAsm::Kind::RegDef &&
+        Kind != InlineAsm::Kind::RegDefEarlyClobber)
       continue;
 
     unsigned RC;
     bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
     if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
         || NumRegs != 2)
       continue;
 
     assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
     SDValue V0 = N->getOperand(i+1);
     SDValue V1 = N->getOperand(i+2);
     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();
     Register Reg1 = cast<RegisterSDNode>(V1)->getReg();
     SDValue PairedReg;
     MachineRegisterInfo &MRI = MF->getRegInfo();
 
-    if (Kind == InlineAsm::Kind_RegDef ||
-        Kind == InlineAsm::Kind_RegDefEarlyClobber) {
+    if (Kind == InlineAsm::Kind::RegDef ||
+        Kind == InlineAsm::Kind::RegDefEarlyClobber) {
       // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
       // the original GPRs.
 
       Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
       PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
       SDValue Chain = SDValue(N,0);
 
       SDNode *GU = N->getGluedUser();
       SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
                                                Chain.getValue(1));
 
       // Extract values from a GPRPair reg and copy to the original GPR reg.
       SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
                                                     RegCopy);
       SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
                                                     RegCopy);
       SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
                                         RegCopy.getValue(1));
       SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
 
       // Update the original glue user.
       std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
       Ops.push_back(T1.getValue(1));
       CurDAG->UpdateNodeOperands(GU, Ops);
-    }
-    else {
-      // For Kind  == InlineAsm::Kind_RegUse, we first copy two GPRs into a
+    } else {
+      // For Kind  == InlineAsm::Kind::RegUse, we first copy two GPRs into a
       // GPRPair and then pass the GPRPair to the inline asm.
       SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
 
       // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
       SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
                                           Chain.getValue(1));
       SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
                                           T0.getValue(1));

llvm/lib/Target/AVR/AVRISelLowering.cpp

for (unsigned I = 0; I < N->getNumOperands(); I++) {
     if (Operand.getValueType() == MVT::Glue) {
       // The glue operand always needs to be at the end, so we need to treat it
       // specially.
       Glue = Operand;
     } else {
       Ops.push_back(Operand);
     }
   }
-  unsigned Flags = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
+  unsigned Flags = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, 1);
   Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
   Ops.push_back(ZeroReg);
   if (Glue) {
     Ops.push_back(Glue);
   }
 
   // Replace the current INLINEASM node with a new one that has the zero
   // register as implicit parameter.

llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp

if (IsSelected)
     return;
 
   // Select the default instruction.
   SelectCode(N);
 }
 
 bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
   std::vector<SDValue> AsmNodeOperands;
-  unsigned Flag, Kind;
+  unsigned Flag;
+  InlineAsm::Kind Kind;
   bool Changed = false;
   unsigned NumOps = N->getNumOperands();
 
   // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
   // However, some instructions (e.g. mula.s32) require GPR pair.
   // Since there is no constraint to explicitly specify a
   // reg pair, we use GPRPair reg class for "%r" for 64-bit data.
 
for (unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e;
 
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
       Flag = C->getZExtValue();
       Kind = InlineAsm::getKind(Flag);
     } else
       continue;
 
     // Immediate operands to inline asm in the SelectionDAG are modeled with
-    // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
+    // two operands. The first is a constant of value InlineAsm::Kind::Imm, and
     // the second is a constant with the value of the immediate. If we get here
-    // and we have a Kind_Imm, skip the next operand, and continue.
-    if (Kind == InlineAsm::Kind_Imm) {
+    // and we have a Kind::Imm, skip the next operand, and continue.
+    if (Kind == InlineAsm::Kind::Imm) {
       SDValue op = N->getOperand(++i);
       AsmNodeOperands.push_back(op);
       continue;
     }
 
     unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
     if (NumRegs)
       OpChanged.push_back(false);
 
     unsigned DefIdx = 0;
     bool IsTiedToChangedOp = false;
     // If it's a use that is tied with a previous def, it has no
     // reg class constraint.
     if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
       IsTiedToChangedOp = OpChanged[DefIdx];
 
     // Memory operands to inline asm in the SelectionDAG are modeled with two
-    // operands: a constant of value InlineAsm::Kind_Mem followed by the input
-    // operand. If we get here and we have a Kind_Mem, skip the next operand (so
-    // it doesn't get misinterpreted), and continue. We do this here because
+    // operands: a constant of value InlineAsm::Kind::Mem followed by the input
+    // operand. If we get here and we have a Kind::Mem, skip the next operand
+    // (so it doesn't get misinterpreted), and continue. We do this here because
     // it's important to update the OpChanged array correctly before moving on.
-    if (Kind == InlineAsm::Kind_Mem) {
+    if (Kind == InlineAsm::Kind::Mem) {
       SDValue op = N->getOperand(++i);
       AsmNodeOperands.push_back(op);
       continue;
     }
 
-    if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef &&
-        Kind != InlineAsm::Kind_RegDefEarlyClobber)
+    if (Kind != InlineAsm::Kind::RegUse && Kind != InlineAsm::Kind::RegDef &&
+        Kind != InlineAsm::Kind::RegDefEarlyClobber)
       continue;
 
     unsigned RC;
     bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
     if ((!IsTiedToChangedOp && (!HasRC || RC != CSKY::GPRRegClassID)) ||
         NumRegs != 2)
       continue;
 
     assert((i + 2 < NumOps) && "Invalid number of operands in inline asm");
     SDValue V0 = N->getOperand(i + 1);
     SDValue V1 = N->getOperand(i + 2);
     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
     unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
     SDValue PairedReg;
     MachineRegisterInfo &MRI = MF->getRegInfo();
 
-    if (Kind == InlineAsm::Kind_RegDef ||
-        Kind == InlineAsm::Kind_RegDefEarlyClobber) {
+    if (Kind == InlineAsm::Kind::RegDef ||
+        Kind == InlineAsm::Kind::RegDefEarlyClobber) {
       // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
       // the original GPRs.
 
       Register GPVR = MRI.createVirtualRegister(&CSKY::GPRPairRegClass);
       PairedReg = CurDAG->getRegister(GPVR, MVT::i64);
       SDValue Chain = SDValue(N, 0);
 
       SDNode *GU = N->getGluedUser();
if (Kind == InlineAsm::Kind::RegDef ||
           CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1));
       SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
 
       // Update the original glue user.
       std::vector<SDValue> Ops(GU->op_begin(), GU->op_end() - 1);
       Ops.push_back(T1.getValue(1));
       CurDAG->UpdateNodeOperands(GU, Ops);
     } else {
-      // For Kind  == InlineAsm::Kind_RegUse, we first copy two GPRs into a
+      // For Kind  == InlineAsm::Kind::RegUse, we first copy two GPRs into a
       // GPRPair and then pass the GPRPair to the inline asm.
       SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
 
       // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
       SDValue T0 =
           CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1));
       SDValue T1 =
           CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1));

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
   for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
     unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
     unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
     ++i;  // Skip the ID value.
 
     switch (InlineAsm::getKind(Flags)) {
       default:
         llvm_unreachable("Bad flags!");
-      case InlineAsm::Kind_RegUse:
-      case InlineAsm::Kind_Imm:
-      case InlineAsm::Kind_Mem:
+      case InlineAsm::Kind::RegUse:
+      case InlineAsm::Kind::Imm:
+      case InlineAsm::Kind::Mem:
         i += NumVals;
         break;
-      case InlineAsm::Kind_Clobber:
-      case InlineAsm::Kind_RegDef:
-      case InlineAsm::Kind_RegDefEarlyClobber: {
+      case InlineAsm::Kind::Clobber:
+      case InlineAsm::Kind::RegDef:
+      case InlineAsm::Kind::RegDefEarlyClobber: {
         for (; NumVals; --NumVals, ++i) {
           Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
           if (Reg != LR)
             continue;
           HMFI.setHasClobberLR(true);
           return Op;
         }
         break;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
   for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
     unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
     unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
     ++i; // Skip the ID value.
 
     switch (InlineAsm::getKind(Flags)) {
     default:
       llvm_unreachable("Bad flags!");
-    case InlineAsm::Kind_RegUse:
-    case InlineAsm::Kind_Imm:
-    case InlineAsm::Kind_Mem:
+    case InlineAsm::Kind::RegUse:
+    case InlineAsm::Kind::Imm:
+    case InlineAsm::Kind::Mem:
       i += NumVals;
       break;
-    case InlineAsm::Kind_Clobber:
-    case InlineAsm::Kind_RegDef:
-    case InlineAsm::Kind_RegDefEarlyClobber: {
+    case InlineAsm::Kind::Clobber:
+    case InlineAsm::Kind::RegDef:
+    case InlineAsm::Kind::RegDefEarlyClobber: {
       for (; NumVals; --NumVals, ++i) {
         Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
         if (Reg != PPC::LR && Reg != PPC::LR8)
           continue;
         MFI.setLRStoreRequired();
         return Op;
       }
       break;

llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

 // such hacking-up is necessary; a rethink of how inline asm operands
 // are handled may be in order to make doing this more sane.
 //
 // TODO: fix inline asm support so I can simply tell it that 'i64'
 // inputs to asm need to be allocated to the IntPair register type,
 // and have that work. Then, delete this function.
 bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
   std::vector<SDValue> AsmNodeOperands;
-  unsigned Flag, Kind;
+  unsigned Flag;
+  InlineAsm::Kind Kind;
   bool Changed = false;
   unsigned NumOps = N->getNumOperands();
 
   // Normally, i64 data is bounded to two arbitrary GPRs for "%r"
   // constraint.  However, some instructions (e.g. ldd/std) require
   // (even/even+1) GPRs.
 
   // So, here, we check for this case, and mutate the inlineasm to use
for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
       Flag = C->getZExtValue();
       Kind = InlineAsm::getKind(Flag);
     }
     else
       continue;
 
     // Immediate operands to inline asm in the SelectionDAG are modeled with
-    // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
+    // two operands. The first is a constant of value InlineAsm::Kind::Imm, and
     // the second is a constant with the value of the immediate. If we get here
-    // and we have a Kind_Imm, skip the next operand, and continue.
-    if (Kind == InlineAsm::Kind_Imm) {
+    // and we have a Kind::Imm, skip the next operand, and continue.
+    if (Kind == InlineAsm::Kind::Imm) {
       SDValue op = N->getOperand(++i);
       AsmNodeOperands.push_back(op);
       continue;
     }
 
     unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
     if (NumRegs)
       OpChanged.push_back(false);
 
     unsigned DefIdx = 0;
     bool IsTiedToChangedOp = false;
     // If it's a use that is tied with a previous def, it has no
     // reg class constraint.
     if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
       IsTiedToChangedOp = OpChanged[DefIdx];
 
-    if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
-        && Kind != InlineAsm::Kind_RegDefEarlyClobber)
+    if (Kind != InlineAsm::Kind::RegUse && Kind != InlineAsm::Kind::RegDef &&
+        Kind != InlineAsm::Kind::RegDefEarlyClobber)
       continue;
 
     unsigned RC;
     bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
     if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
         || NumRegs != 2)
       continue;
 
     assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
     SDValue V0 = N->getOperand(i+1);
     SDValue V1 = N->getOperand(i+2);
     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();
     Register Reg1 = cast<RegisterSDNode>(V1)->getReg();
     SDValue PairedReg;
     MachineRegisterInfo &MRI = MF->getRegInfo();
 
-    if (Kind == InlineAsm::Kind_RegDef ||
-        Kind == InlineAsm::Kind_RegDefEarlyClobber) {
+    if (Kind == InlineAsm::Kind::RegDef ||
+        Kind == InlineAsm::Kind::RegDefEarlyClobber) {
       // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
       // the original GPRs.
 
       Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
       PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
       SDValue Chain = SDValue(N,0);
 
       SDNode *GU = N->getGluedUser();
       SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,
                                                Chain.getValue(1));
 
       // Extract values from a GPRPair reg and copy to the original GPR reg.
       SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32,
                                                     RegCopy);
       SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
                                                     RegCopy);
       SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
                                         RegCopy.getValue(1));
       SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
 
       // Update the original glue user.
       std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
       Ops.push_back(T1.getValue(1));
       CurDAG->UpdateNodeOperands(GU, Ops);
-    }
-    else {
-      // For Kind  == InlineAsm::Kind_RegUse, we first copy two GPRs into a
+    } else {
+      // For Kind  == InlineAsm::Kind::RegUse, we first copy two GPRs into a
       // GPRPair and then pass the GPRPair to the inline asm.
       SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
 
       // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
       SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
                                           Chain.getValue(1));
       SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
                                           T0.getValue(1));

llvm/lib/Target/X86/X86FloatingPoint.cpp

for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands();
       // If the flag has a register class constraint, this must be an operand
       // with constraint "f". Record its index and continue.
       if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
         FRegIdx.insert(i + 1);
         continue;
       }
 
       switch (InlineAsm::getKind(Flags)) {
-      case InlineAsm::Kind_RegUse:
+      case InlineAsm::Kind::RegUse:
         STUses |= (1u << STReg);
         break;
-      case InlineAsm::Kind_RegDef:
-      case InlineAsm::Kind_RegDefEarlyClobber:
+      case InlineAsm::Kind::RegDef:
+      case InlineAsm::Kind::RegDefEarlyClobber:
         STDefs |= (1u << STReg);
         break;
-      case InlineAsm::Kind_Clobber:
+      case InlineAsm::Kind::Clobber:
         STClobbers |= (1u << STReg);
         break;
       default:
         break;
       }
     }
 
     if (STUses && !isMask_32(STUses))