[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics

[michaelmaitland]

Summary

D150312 added a TODO:

TODO: consider renaming the field StartAtCycle and Cycles to
AcquireAtCycle and ReleaseAtCycle respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that StartAtCycle was
singular but Cycles was plural. This renaming fixes this inconsistency.

[fpetrogalli]

Thank you for doing this @michaelmaitland.

Patch looks great. Just one minor thing. I believe there is a typo all across the patch: it should be Acquire, not Aquire.

Francesco

llvm/include/llvm/CodeGen/MachineScheduler.h

660

llvm/include/llvm/Target/TargetSchedule.td

257–264

This is very useful, thank you.

llvm/test/TableGen/AcquireAtCycle.td

1

File name has typo too.

[michaelmaitland]

It is spelled Acquire, not Aquire... (:embarrased:)

[michaelmaitland]

I am failing build and will look into it. I built all targets locally and had no problem, but perhaps I missed something.

[michaelmaitland]

Rebase.

[michaelmaitland]

SystemZ Cycles -> ReleaseAtCycle

[wangpc]

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

[michaelmaitland]

In D158568#4623906, @wangpc wrote:

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

Working on improving the SiFive7 to use it. Will add you as reviewer once posted.

[fpetrogalli]

In D158568#4623906, @wangpc wrote:

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

You can watch the talk that describes what StartAtCycle (which became AcquireAtCycle) is for: https://www.youtube.com/watch?v=XWBVLcdzmFg

[wangpc]

In D158568#4636688, @fpetrogalli wrote:

In D158568#4623906, @wangpc wrote:

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

You can watch the talk that describes what StartAtCycle (which became AcquireAtCycle) is for: https://www.youtube.com/watch?v=XWBVLcdzmFg

Oh thanks! That's really helpful! I understand it now, thanks for your admirable works! :-)

llvm/include/llvm/CodeGen/MachineScheduler.h

public:
   /// Checks whether intervals intersect.
   static bool intersects(IntervalTy A, IntervalTy B);
 
   /// These function return the interval used by a resource in bottom and top
   /// scheduling.
   ///
   /// Consider an instruction that uses resources X0, X1 and X2 as follows:
   ///
-  /// X0 X1 X1 X2    +--------+------------+------+
-  ///                |Resource|StartAtCycle|Cycles|
-  ///                +--------+------------+------+
-  ///                |   X0   |     0      |  1   |
-  ///                +--------+------------+------+
-  ///                |   X1   |     1      |  3   |
-  ///                +--------+------------+------+
-  ///                |   X2   |     3      |  4   |
-  ///                +--------+------------+------+
+  /// X0 X1 X1 X2    +--------+-------------+--------------+
+  ///                |Resource|AcquireAtCycle|ReleaseAtCycle|
+  ///                +--------+-------------+--------------+
+  ///                |   X0   |     0       |       1      |
+  ///                +--------+-------------+--------------+
+  ///                |   X1   |     1       |       3      |
+  ///                +--------+-------------+--------------+
+  ///                |   X2   |     3       |       4      |
+  ///                +--------+-------------+--------------+
   ///
   /// If we can schedule the instruction at cycle C, we need to
   /// compute the interval of the resource as follows:
   ///
   /// # TOP DOWN SCHEDULING
   ///
   /// Cycles scheduling flows to the _right_, in the same direction
   /// of time.
   ///
   ///       C      1      2      3      4      5  ...
   /// ------|------|------|------|------|------|----->
   ///       X0     X1     X1     X2   ---> direction of time
   /// X0    [C, C+1)
   /// X1           [C+1,      C+3)
   /// X2                         [C+3, C+4)
   ///
   /// Therefore, the formula to compute the interval for a resource
   /// of an instruction that can be scheduled at cycle C in top-down
   /// scheduling is:
   ///
-  ///       [C+StartAtCycle, C+Cycles)
+  ///       [C+AcquireAtCycle, C+ReleaseAtCycle)
   ///
   ///
   /// # BOTTOM UP SCHEDULING
   ///
   /// Cycles scheduling flows to the _left_, in opposite direction
   /// of time.
   ///
   /// In bottom up scheduling, the scheduling happens in opposite
   /// direction to the execution of the cycles of the
   /// instruction. When the instruction is scheduled at cycle `C`,
   /// the resources are allocated in the past relative to `C`:
   ///
   ///       2      1      C     -1     -2     -3     -4     -5  ...
   /// <-----|------|------|------|------|------|------|------|---
   ///                     X0     X1     X1     X2   ---> direction of time
   /// X0           (C+1, C]
   /// X1                  (C,        C-2]
   /// X2                              (C-2, C-3]
   ///
   /// Therefore, the formula to compute the interval for a resource
   /// of an instruction that can be scheduled at cycle C in bottom-up
   /// scheduling is:
   ///
-  ///       [C-Cycle+1, C-StartAtCycle+1)
+  ///       [C-ReleaseAtCycle+1, C-AcquireAtCycle+1)
   ///
   ///
   /// NOTE: In both cases, the number of cycles booked by a
-  /// resources is the value (Cycle - StartAtCycles).
-  static IntervalTy getResourceIntervalBottom(unsigned C, unsigned StartAtCycle,
-                                              unsigned Cycle) {
-    return std::make_pair<long, long>((long)C - (long)Cycle + 1L,
-                                      (long)C - (long)StartAtCycle + 1L);
-  }
-  static IntervalTy getResourceIntervalTop(unsigned C, unsigned StartAtCycle,
-                                           unsigned Cycle) {
-    return std::make_pair<long, long>((long)C + (long)StartAtCycle,
-                                      (long)C + (long)Cycle);
+  /// resources is the value (ReleaseAtCycle - AcquireAtCycle).
+  static IntervalTy getResourceIntervalBottom(unsigned C, unsigned AcquireAtCycle,
+                                              unsigned ReleaseAtCycle) {
+    return std::make_pair<long, long>((long)C - (long)ReleaseAtCycle + 1L,
+                                      (long)C - (long)AcquireAtCycle + 1L);
+  }
+  static IntervalTy getResourceIntervalTop(unsigned C, unsigned AcquireAtCycle,
+                                           unsigned ReleaseAtCycle) {
+    return std::make_pair<long, long>((long)C + (long)AcquireAtCycle,
+                                      (long)C + (long)ReleaseAtCycle);
   }
 
 private:
   /// Finds the first cycle in which a resource can be allocated.
   ///
   /// The function uses the \param IntervalBuider [*] to build a
   /// resource interval [a, b[ out of the input parameters \param
-  /// CurrCycle, \param StartAtCycle and \param Cycle.
+  /// CurrCycle, \param AcquireAtCycle and \param ReleaseAtCycle.
   ///
   /// The function then loops through the intervals in the ResourceSegments
   /// and shifts the interval [a, b[ and the ReturnCycle to the
   /// right until there is no intersection between the intervals of
   /// the \ref ResourceSegments instance and the new shifted [a, b[. When
   /// this condition is met, the ReturnCycle  (which
   /// correspond to the cycle in which the resource can be
   /// allocated) is returned.
   ///
   ///               c = CurrCycle in input
   ///               c   1   2   3   4   5   6   7   8   9   10 ... ---> (time
   ///               flow)
   ///  ResourceSegments...  [---)   [-------)           [-----------)
-  ///               c   [1     3[  -> StartAtCycle=1, Cycles=3
+  ///               c   [1     3[  -> AcquireAtCycle=1, ReleaseAtCycle=3
   ///                 ++c   [1     3)
   ///                     ++c   [1     3)
   ///                         ++c   [1     3)
   ///                             ++c   [1     3)
   ///                                 ++c   [1     3)    ---> returns c
   ///                                 incremented by 5 (c+5)
   ///
   ///
private:
   ///
   /// Even though bottom-up scheduling moves against the flow of
   /// time, the algorithm used to find the first free slot in between
   /// intervals is the same as for top-down scheduling.
   ///
   /// [*] See \ref `getResourceIntervalTop` and
   /// \ref `getResourceIntervalBottom` to see how such resource intervals
   /// are built.
-  unsigned
-  getFirstAvailableAt(unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
-                      std::function<IntervalTy(unsigned, unsigned, unsigned)>
-                          IntervalBuilder) const;
+  unsigned getFirstAvailableAt(
+      unsigned CurrCycle, unsigned AcquireAtCycle, unsigned ReleaseAtCycle,
+      std::function<IntervalTy(unsigned, unsigned, unsigned)> IntervalBuilder)
+      const;
 
 public:
   /// getFirstAvailableAtFromBottom and getFirstAvailableAtFromTop
   /// should be merged in a single function in which a function that
   /// creates the `NewInterval` is passed as a parameter.
   unsigned getFirstAvailableAtFromBottom(unsigned CurrCycle,
-                                         unsigned StartAtCycle,
-                                         unsigned Cycle) const {
-    return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
+                                         unsigned AcquireAtCycle,
+                                         unsigned ReleaseAtCycle) const {
+    return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
                                getResourceIntervalBottom);
   }
-  unsigned getFirstAvailableAtFromTop(unsigned CurrCycle, unsigned StartAtCycle,
-                                      unsigned Cycle) const {
-    return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
+  unsigned getFirstAvailableAtFromTop(unsigned CurrCycle,
+                                      unsigned AcquireAtCycle,
+                                      unsigned ReleaseAtCycle) const {
+    return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
                                getResourceIntervalTop);
   }
 
 private:
   std::list<IntervalTy> _Intervals;
   /// Merge all adjacent intervals in the collection. For all pairs
   /// of adjacient intervals, it performs [a, b) + [b, c) -> [a, c).
   ///
public:
   // Is the scheduled region resource limited vs. latency limited.
   bool isResourceLimited() const { return IsResourceLimited; }
 
   /// Get the difference between the given SUnit's ready time and the current
   /// cycle.
   unsigned getLatencyStallCycles(SUnit *SU);
 
   unsigned getNextResourceCycleByInstance(unsigned InstanceIndex,
-                                          unsigned Cycles,
-                                          unsigned StartAtCycle);
+                                          unsigned ReleaseAtCycle,
+                                          unsigned AcquireAtCycle);
 
   std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
                                                      unsigned PIdx,
-                                                     unsigned Cycles,
-                                                     unsigned StartAtCycle);
+                                                     unsigned ReleaseAtCycle,
+                                                     unsigned AcquireAtCycle);
 
   bool isUnbufferedGroup(unsigned PIdx) const {
     return SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin &&
            !SchedModel->getProcResource(PIdx)->BufferSize;
   }
 
   bool checkHazard(SUnit *SU);
 

llvm/include/llvm/CodeGen/MachineTraceMetrics.h

public:
   /// Get the fixed resource information about MBB. Compute it on demand.
   const FixedBlockInfo *getResources(const MachineBasicBlock*);
 
   /// Get the scaled number of cycles used per processor resource in MBB.
   /// This is an array with SchedModel.getNumProcResourceKinds() entries.
   /// The getResources() function above must have been called first.
   ///
   /// These numbers have already been scaled by SchedModel.getResourceFactor().
-  ArrayRef<unsigned> getProcResourceCycles(unsigned MBBNum) const;
+  ArrayRef<unsigned> getProcReleaseAtCycles(unsigned MBBNum) const;
 
   /// A virtual register or regunit required by a basic block or its trace
   /// successors.
   struct LiveInReg {
     /// The virtual register required, or a register unit.
     Register Reg;
 
     /// For virtual registers: Minimum height of the defining instruction.

 
 private:
   // One entry per basic block, indexed by block number.
   SmallVector<FixedBlockInfo, 4> BlockInfo;
 
   // Cycles consumed on each processor resource per block.
   // The number of processor resource kinds is constant for a given subtarget,
   // but it is not known at compile time. The number of cycles consumed by
-  // block B on processor resource R is at ProcResourceCycles[B*Kinds + R]
+  // block B on processor resource R is at ProcReleaseAtCycles[B*Kinds + R]
   // where Kinds = SchedModel.getNumProcResourceKinds().
-  SmallVector<unsigned, 0> ProcResourceCycles;
+  SmallVector<unsigned, 0> ProcReleaseAtCycles;
 
   // One ensemble per strategy.
   Ensemble
       *Ensembles[static_cast<size_t>(MachineTraceStrategy::TS_NumStrategies)];
 
   // Convert scaled resource usage to a cycle count that can be compared with
   // latencies.
   unsigned getCycles(unsigned Scaled) {

llvm/include/llvm/MC/MCSchedule.h

struct MCProcResourceDesc {
   bool operator==(const MCProcResourceDesc &Other) const {
     return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
       && BufferSize == Other.BufferSize;
   }
 };
 
 /// Identify one of the processor resource kinds consumed by a
 /// particular scheduling class for the specified number of cycles.
-/// TODO: consider renaming the field `StartAtCycle` and `Cycles` to
-/// `AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
-/// fact that resource allocation is now represented as an interval,
-/// relatively to the issue cycle of the instruction.
 struct MCWriteProcResEntry {
   uint16_t ProcResourceIdx;
   /// Cycle at which the resource will be released by an instruction,
   /// relatively to the cycle in which the instruction is issued
   /// (assuming no stalls inbetween).
-  uint16_t Cycles;
-  /// Cycle at which the resource will be grabbed by an instruction,
+  uint16_t ReleaseAtCycle;
+  /// Cycle at which the resource will be aquired by an instruction,
   /// relatively to the cycle in which the instruction is issued
   /// (assuming no stalls inbetween).
-  uint16_t StartAtCycle;
+  uint16_t AcquireAtCycle;
 
   bool operator==(const MCWriteProcResEntry &Other) const {
-    return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles &&
-           StartAtCycle == Other.StartAtCycle;
+    return ProcResourceIdx == Other.ProcResourceIdx &&
+           ReleaseAtCycle == Other.ReleaseAtCycle &&
+           AcquireAtCycle == Other.AcquireAtCycle;
   }
 };
 
 /// Specify the latency in cpu cycles for a particular scheduling class and def
 /// index. -1 indicates an invalid latency. Heuristics would typically consider
 /// an instruction with invalid latency to have infinite latency.  Also identify
 /// the WriteResources of this def. When the operand expands to a sequence of
 /// writes, this ID is the last write in the sequence.

 ///
 /// The abstract pipeline is built around the notion of an "issue point". This
 /// is merely a reference point for counting machine cycles. The physical
 /// machine will have pipeline stages that delay execution. The scheduler does
 /// not model those delays because they are irrelevant as long as they are
 /// consistent. Inaccuracies arise when instructions have different execution
 /// delays relative to each other, in addition to their intrinsic latency. Those
 /// special cases can be handled by TableGen constructs such as, ReadAdvance,
-/// which reduces latency when reading data, and ResourceCycles, which consumes
+/// which reduces latency when reading data, and ReleaseAtCycles, which consumes
 /// a processor resource when writing data for a number of abstract
 /// cycles.
 ///
 /// TODO: One tool currently missing is the ability to add a delay to
-/// ResourceCycles. That would be easy to add and would likely cover all cases
+/// ReleaseAtCycles. That would be easy to add and would likely cover all cases
 /// currently handled by the legacy itinerary tables.
 ///
 /// A note on out-of-order execution and, more generally, instruction
 /// buffers. Part of the CPU pipeline is always in-order. The issue point, which
 /// is the point of reference for counting cycles, only makes sense as an
 /// in-order part of the pipeline. Other parts of the pipeline are sometimes
 /// falling behind and sometimes catching up. It's only interesting to model
 /// those other, decoupled parts of the pipeline if they may be predictably

llvm/include/llvm/MCA/HWEventListener.h

public:
   // The instruction this event was generated for.
   const InstRef &IR;
 };
 
 // ResourceRef::first is the index of the associated Resource.
 // ResourceRef::second is a bitmask of the referenced sub-unit of the resource.
 using ResourceRef = std::pair<uint64_t, uint64_t>;
 
-using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
+using ResourceUse = std::pair<ResourceRef, ReleaseAtCycles>;
 
 class HWInstructionIssuedEvent : public HWInstructionEvent {
 public:
   HWInstructionIssuedEvent(const InstRef &IR, ArrayRef<ResourceUse> UR)
       : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
 
   ArrayRef<ResourceUse> UsedResources;
 };

llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h

public:
   // resource unit or a reserved processor resource group.
   uint64_t checkAvailability(const InstrDesc &Desc) const;
 
   uint64_t getProcResUnitMask() const { return ProcResUnitMask; }
   uint64_t getAvailableProcResUnits() const { return AvailableProcResUnits; }
 
   void issueInstruction(
       const InstrDesc &Desc,
-      SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
+      SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
 
   void cycleEvent(SmallVectorImpl<ResourceRef> &ResourcesFreed);
 
 #ifndef NDEBUG
   void dump() const {
     for (const std::unique_ptr<ResourceState> &Resource : Resources)
       Resource->dump();
   }
 #endif
 };
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_HARDWAREUNITS_RESOURCEMANAGER_H

llvm/include/llvm/MCA/HardwareUnits/Scheduler.h

class Scheduler : public HardwareUnit {
   /// Verify the given selection strategy and set the Strategy member
   /// accordingly.  If no strategy is provided, the DefaultSchedulerStrategy is
   /// used.
   void initializeStrategy(std::unique_ptr<SchedulerStrategy> S);
 
   /// Issue an instruction without updating the ready queue.
   void issueInstructionImpl(
       InstRef &IR,
-      SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
+      SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
 
   // Identify instructions that have finished executing, and remove them from
   // the IssuedSet. References to executed instructions are added to input
   // vector 'Executed'.
   void updateIssuedSet(SmallVectorImpl<InstRef> &Executed);
 
   // Try to promote instructions from the PendingSet to the ReadySet.
   // Add promoted instructions to the 'Ready' vector in input.
public:
   /// dependencies.
   bool dispatch(InstRef &IR);
 
   /// Issue an instruction and populates a vector of used pipeline resources,
   /// and a vector of instructions that transitioned to the ready state as a
   /// result of this event.
   void issueInstruction(
       InstRef &IR,
-      SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Used,
+      SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Used,
       SmallVectorImpl<InstRef> &Pending,
       SmallVectorImpl<InstRef> &Ready);
 
   /// Returns true if IR has to be issued immediately, or if IR is a zero
   /// latency instruction.
   bool mustIssueImmediately(const InstRef &IR) const;
 
   /// This routine notifies the Scheduler that a new cycle just started.

llvm/include/llvm/MCA/Support.h

 template <typename T> char InstructionError<T>::ID;
 
 /// This class represents the number of cycles per resource (fractions of
 /// cycles).  That quantity is managed here as a ratio, and accessed via the
 /// double cast-operator below.  The two quantities, number of cycles and
 /// number of resources, are kept separate.  This is used by the
 /// ResourcePressureView to calculate the average resource cycles
 /// per instruction/iteration.
-class ResourceCycles {
+class ReleaseAtCycles {
   unsigned Numerator, Denominator;
 
 public:
-  ResourceCycles() : Numerator(0), Denominator(1) {}
-  ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
+  ReleaseAtCycles() : Numerator(0), Denominator(1) {}
+  ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1)
       : Numerator(Cycles), Denominator(ResourceUnits) {}
 
   operator double() const {
     assert(Denominator && "Invalid denominator (must be non-zero).");
     return (Denominator == 1) ? Numerator : (double)Numerator / Denominator;
   }
 
   unsigned getNumerator() const { return Numerator; }
   unsigned getDenominator() const { return Denominator; }
 
   // Add the components of RHS to this instance.  Instead of calculating
   // the final value here, we keep track of the numerator and denominator
   // separately, to reduce floating point error.
-  ResourceCycles &operator+=(const ResourceCycles &RHS);
+  ReleaseAtCycles &operator+=(const ReleaseAtCycles &RHS);
 };
 
 /// Populates vector Masks with processor resource masks.
 ///
 /// The number of bits set in a mask depends on the processor resource type.
 /// Each processor resource mask has at least one bit set. For groups, the
 /// number of bits set in the mask is equal to the cardinality of the group plus
 /// one. Excluding the most significant bit, the remaining bits in the mask

 inline unsigned getResourceStateIndex(uint64_t Mask) {
   assert(Mask && "Processor Resource Mask cannot be zero!");
   return llvm::Log2_64(Mask);
 }
 
 /// Compute the reciprocal block throughput from a set of processor resource
 /// cycles. The reciprocal block throughput is computed as the MAX between:
 ///  - NumMicroOps / DispatchWidth
-///  - ProcResourceCycles / #ProcResourceUnits  (for every consumed resource).
+///  - ProcReleaseAtCycles / #ProcResourceUnits  (for every consumed resource).
 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
                                unsigned NumMicroOps,
                                ArrayRef<unsigned> ProcResourceUsage);
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_SUPPORT_H

llvm/include/llvm/Target/TargetSchedule.td

 //
 // ProcResourceUnits normally model a few buffered resources within an
 // out-of-order engine. Buffered resources may be held for multiple
 // clock cycles, but the scheduler does not pin them to a particular
 // clock cycle relative to instruction dispatch. Setting BufferSize=0
 // changes this to an in-order issue/dispatch resource. In this case,
 // the scheduler counts down from the cycle that the instruction
 // issues in-order, forcing a stall whenever a subsequent instruction
-// requires the same resource until the number of ResourceCycles
+// requires the same resource until the number of ReleaseAtCycles
 // specified in WriteRes expire. Setting BufferSize=1 changes this to
 // an in-order latency resource. In this case, the scheduler models
 // producer/consumer stalls between instructions that use the
 // resource.
 //
 // Examples (all assume an out-of-order engine):
 //
 // Use BufferSize = -1 for "issue ports" fed by a unified reservation
class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
   SchedMachineModel SchedModel = ?;
 }
 
 // Define values common to WriteRes and SchedWriteRes.
 //
 // SchedModel ties these resources to a processor.
 class ProcWriteResources<list<ProcResourceKind> resources> {
   list<ProcResourceKind> ProcResources = resources;
-  list<int> ResourceCycles = [];
-  list<int> StartAtCycles = [];
+  /// Cycle at which the resource will be released by an instruction,
+  /// relatively to the cycle in which the instruction is issued
+  /// (assuming no stalls inbetween).
+  list<int> ReleaseAtCycles = [];
+  /// Cycle at which the resource will be aquired by an instruction,
+  /// relatively to the cycle in which the instruction is issued
+  /// (assuming no stalls inbetween).
+  list<int> AcquireAtCycles = [];
   int Latency = 1;
   int NumMicroOps = 1;
   bit BeginGroup = false;
   bit EndGroup = false;
   // Allow a processor to mark some scheduling classes as unsupported
   // for stronger verification.
   bit Unsupported = false;
   // Allow a processor to mark some scheduling classes as single-issue.

 // resources.
 //
 // If a target already has itinerary classes, SchedWriteResources can
 // be used instead to define subtarget specific SchedWrites and map
 // them to processor resources in one place. Then ItinRW can map
 // itinerary classes to the subtarget's SchedWrites.
 //
 // ProcResources indicates the set of resources consumed by the write.
-// Optionally, ResourceCycles indicates the number of cycles the
-// resource is consumed. Each ResourceCycles item is paired with the
-// ProcResource item at the same position in its list. ResourceCycles
+// Optionally, ReleaseAtCycles indicates the number of cycles the
+// resource is consumed. Each ReleaseAtCycles item is paired with the
+// ProcResource item at the same position in its list. ReleaseAtCycles
 // can be `[]`: in that case, all resources are consumed for a single
 // cycle, regardless of latency, which models a fully pipelined processing
-// unit. A value of 0 for ResourceCycles means that the resource must
+// unit. A value of 0 for ReleaseAtCycles means that the resource must
 // be available but is not consumed, which is only relevant for
 // unbuffered resources.
 //
 // By default, each SchedWrite takes one micro-op, which is counted
 // against the processor's IssueWidth limit. If an instruction can
 // write multiple registers with a single micro-op, the subtarget
 // should define one of the writes to be zero micro-ops. If a
 // subtarget requires multiple micro-ops to write a single result, it

llvm/lib/CodeGen/MachinePipeliner.cpp

if (STI && STI->getSchedModel().hasInstrSchedModel()) {
       if (!SCDesc->isValid())
         // No valid Schedule Class Desc for schedClass, should be
         // Pseudo/PostRAPseudo
         return min;
 
       for (const MCWriteProcResEntry &PRE :
            make_range(STI->getWriteProcResBegin(SCDesc),
                       STI->getWriteProcResEnd(SCDesc))) {
-        if (!PRE.Cycles)
+        if (!PRE.ReleaseAtCycle)
           continue;
         const MCProcResourceDesc *ProcResource =
             STI->getSchedModel().getProcResource(PRE.ProcResourceIdx);
         unsigned NumUnits = ProcResource->NumUnits;
         if (NumUnits < min) {
           min = NumUnits;
           F = PRE.ProcResourceIdx;
         }
if (STI && STI->getSchedModel().hasInstrSchedModel()) {
       if (!SCDesc->isValid())
         // No valid Schedule Class Desc for schedClass, should be
         // Pseudo/PostRAPseudo
         return;
 
       for (const MCWriteProcResEntry &PRE :
            make_range(STI->getWriteProcResBegin(SCDesc),
                       STI->getWriteProcResEnd(SCDesc))) {
-        if (!PRE.Cycles)
+        if (!PRE.ReleaseAtCycle)
           continue;
         Resources[PRE.ProcResourceIdx]++;
       }
       return;
     }
     llvm_unreachable("Should have non-empty InstrItins or hasInstrSchedModel!");
   }
 
void ResourceManager::reserveResources(SUnit &SU, int Cycle) {
   });
 }
 
 void ResourceManager::reserveResources(const MCSchedClassDesc *SCDesc,
                                        int Cycle) {
   assert(!UseDFA);
   for (const MCWriteProcResEntry &PRE : make_range(
            STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
-    for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
+    for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
       ++MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
 
   for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
     ++NumScheduledMops[positiveModulo(C, InitiationInterval)];
 }
 
 void ResourceManager::unreserveResources(const MCSchedClassDesc *SCDesc,
                                          int Cycle) {
   assert(!UseDFA);
   for (const MCWriteProcResEntry &PRE : make_range(
            STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
-    for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
+    for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
       --MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
 
   for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
     --NumScheduledMops[positiveModulo(C, InitiationInterval)];
 }
 
 bool ResourceManager::isOverbooked() const {
   assert(!UseDFA);
for (SUnit &SU : DAG->SUnits) {
     NumMops += SCDesc->NumMicroOps;
     for (const MCWriteProcResEntry &PRE :
          make_range(STI->getWriteProcResBegin(SCDesc),
                     STI->getWriteProcResEnd(SCDesc))) {
       LLVM_DEBUG({
         if (SwpDebugResource) {
           const MCProcResourceDesc *Desc =
               SM.getProcResource(PRE.ProcResourceIdx);
-          dbgs() << Desc->Name << ": " << PRE.Cycles << ", ";
+          dbgs() << Desc->Name << ": " << PRE.ReleaseAtCycle << ", ";
         }
       });
-      ResourceCount[PRE.ProcResourceIdx] += PRE.Cycles;
+      ResourceCount[PRE.ProcResourceIdx] += PRE.ReleaseAtCycle;
     }
     LLVM_DEBUG(if (SwpDebugResource) dbgs() << "\n");
   }
 
   int Result = (NumMops + IssueWidth - 1) / IssueWidth;
   LLVM_DEBUG({
     if (SwpDebugResource)
       dbgs() << "#Mops: " << NumMops << ", "

llvm/lib/CodeGen/MachineScheduler.cpp

LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceTopDown() const {
   for (MachineInstr &MI : *this) {
     SUnit *SU = getSUnit(&MI);
     if (!SU)
       continue;
     const MCSchedClassDesc *SC = getSchedClass(SU);
     for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC),
                                        PE = SchedModel.getWriteProcResEnd(SC);
          PI != PE; ++PI) {
-      if (SU->TopReadyCycle + PI->Cycles - 1 > LastCycle)
-        LastCycle = SU->TopReadyCycle + PI->Cycles - 1;
+      if (SU->TopReadyCycle + PI->ReleaseAtCycle - 1 > LastCycle)
+        LastCycle = SU->TopReadyCycle + PI->ReleaseAtCycle - 1;
     }
   }
   // Print the header with the cycles
   dbgs() << llvm::left_justify("Cycle", HeaderColWidth);
   for (unsigned C = FirstCycle; C <= LastCycle; ++C)
     dbgs() << llvm::left_justify("| " + std::to_string(C), ColWidth);
   dbgs() << "|\n";
 
for (MachineInstr &MI : *this) {
     SmallVector<MCWriteProcResEntry, 4> ResourcesIt(
         make_range(SchedModel.getWriteProcResBegin(SC),
                    SchedModel.getWriteProcResEnd(SC)));
 
     if (MISchedSortResourcesInTrace)
       llvm::stable_sort(ResourcesIt,
                         [](const MCWriteProcResEntry &LHS,
                            const MCWriteProcResEntry &RHS) -> bool {
-                          return LHS.StartAtCycle < RHS.StartAtCycle ||
-                                 (LHS.StartAtCycle == RHS.StartAtCycle &&
-                                  LHS.Cycles < RHS.Cycles);
+                          return LHS.AcquireAtCycle < RHS.AcquireAtCycle ||
+                                 (LHS.AcquireAtCycle == RHS.AcquireAtCycle &&
+                                  LHS.ReleaseAtCycle < RHS.ReleaseAtCycle);
                         });
     for (const MCWriteProcResEntry &PI : ResourcesIt) {
       C = FirstCycle;
       const std::string ResName =
           SchedModel.getResourceName(PI.ProcResourceIdx);
       dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth);
-      for (; C < SU->TopReadyCycle + PI.StartAtCycle; ++C) {
+      for (; C < SU->TopReadyCycle + PI.AcquireAtCycle; ++C) {
         dbgs() << llvm::left_justify("|", ColWidth);
       }
-      for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, ++C)
+      for (unsigned I = 0, E = PI.ReleaseAtCycle - PI.AcquireAtCycle; I != E;
+           ++I, ++C)
         dbgs() << llvm::left_justify("| x", ColWidth);
       while (C++ <= LastCycle)
         dbgs() << llvm::left_justify("|", ColWidth);
       // Place end char
       dbgs() << "| \n";
     }
   }
 }
LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceBottomUp() const {
   for (MachineInstr &MI : *this) {
     SUnit *SU = getSUnit(&MI);
     if (!SU)
       continue;
     const MCSchedClassDesc *SC = getSchedClass(SU);
     for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC),
                                        PE = SchedModel.getWriteProcResEnd(SC);
          PI != PE; ++PI) {
-      if ((int)SU->BotReadyCycle - PI->Cycles + 1 < LastCycle)
-        LastCycle = (int)SU->BotReadyCycle - PI->Cycles + 1;
+      if ((int)SU->BotReadyCycle - PI->ReleaseAtCycle + 1 < LastCycle)
+        LastCycle = (int)SU->BotReadyCycle - PI->ReleaseAtCycle + 1;
     }
   }
   // Print the header with the cycles
   dbgs() << llvm::left_justify("Cycle", HeaderColWidth);
   for (int C = FirstCycle; C >= LastCycle; --C)
     dbgs() << llvm::left_justify("| " + std::to_string(C), ColWidth);
   dbgs() << "|\n";
 
for (MachineInstr &MI : *this) {
     SmallVector<MCWriteProcResEntry, 4> ResourcesIt(
         make_range(SchedModel.getWriteProcResBegin(SC),
                    SchedModel.getWriteProcResEnd(SC)));
 
     if (MISchedSortResourcesInTrace)
       llvm::stable_sort(ResourcesIt,
                         [](const MCWriteProcResEntry &LHS,
                            const MCWriteProcResEntry &RHS) -> bool {
-                          return LHS.StartAtCycle < RHS.StartAtCycle ||
-                                 (LHS.StartAtCycle == RHS.StartAtCycle &&
-                                  LHS.Cycles < RHS.Cycles);
+                          return LHS.AcquireAtCycle < RHS.AcquireAtCycle ||
+                                 (LHS.AcquireAtCycle == RHS.AcquireAtCycle &&
+                                  LHS.ReleaseAtCycle < RHS.ReleaseAtCycle);
                         });
     for (const MCWriteProcResEntry &PI : ResourcesIt) {
       C = FirstCycle;
       const std::string ResName =
           SchedModel.getResourceName(PI.ProcResourceIdx);
       dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth);
-      for (; C > ((int)SU->BotReadyCycle - (int)PI.StartAtCycle); --C) {
+      for (; C > ((int)SU->BotReadyCycle - (int)PI.AcquireAtCycle); --C) {
         dbgs() << llvm::left_justify("|", ColWidth);
       }
-      for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, --C)
+      for (unsigned I = 0, E = PI.ReleaseAtCycle - PI.AcquireAtCycle; I != E;
+           ++I, --C)
         dbgs() << llvm::left_justify("| x", ColWidth);
       while (C-- >= LastCycle)
         dbgs() << llvm::left_justify("|", ColWidth);
       // Place end char
       dbgs() << "| \n";
     }
   }
 }
for (SUnit &SU : DAG->SUnits) {
     const MCSchedClassDesc *SC = DAG->getSchedClass(&SU);
     RemIssueCount += SchedModel->getNumMicroOps(SU.getInstr(), SC)
       * SchedModel->getMicroOpFactor();
     for (TargetSchedModel::ProcResIter
            PI = SchedModel->getWriteProcResBegin(SC),
            PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
       unsigned PIdx = PI->ProcResourceIdx;
       unsigned Factor = SchedModel->getResourceFactor(PIdx);
-      assert(PI->Cycles >= PI->StartAtCycle);
-      RemainingCounts[PIdx] += (Factor * (PI->Cycles - PI->StartAtCycle));
+      assert(PI->ReleaseAtCycle >= PI->AcquireAtCycle);
+      RemainingCounts[PIdx] +=
+          (Factor * (PI->ReleaseAtCycle - PI->AcquireAtCycle));
     }
   }
 }
 
 void SchedBoundary::
 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
   reset();
   DAG = dag;
unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
   if (ReadyCycle > CurrCycle)
     return ReadyCycle - CurrCycle;
   return 0;
 }
 
 /// Compute the next cycle at which the given processor resource unit
 /// can be scheduled.
 unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
-                                                       unsigned Cycles,
-                                                       unsigned StartAtCycle) {
+                                                       unsigned ReleaseAtCycle,
+                                                       unsigned AcquireAtCycle) {
   if (SchedModel && SchedModel->enableIntervals()) {
     if (isTop())
       return ReservedResourceSegments[InstanceIdx].getFirstAvailableAtFromTop(
-          CurrCycle, StartAtCycle, Cycles);
+          CurrCycle, AcquireAtCycle, ReleaseAtCycle);
 
     return ReservedResourceSegments[InstanceIdx].getFirstAvailableAtFromBottom(
-        CurrCycle, StartAtCycle, Cycles);
+        CurrCycle, AcquireAtCycle, ReleaseAtCycle);
   }
 
   unsigned NextUnreserved = ReservedCycles[InstanceIdx];
   // If this resource has never been used, always return cycle zero.
   if (NextUnreserved == InvalidCycle)
     return CurrCycle;
   // For bottom-up scheduling add the cycles needed for the current operation.
   if (!isTop())
-    NextUnreserved = std::max(CurrCycle, NextUnreserved + Cycles);
+    NextUnreserved = std::max(CurrCycle, NextUnreserved + ReleaseAtCycle);
   return NextUnreserved;
 }
 
 /// Compute the next cycle at which the given processor resource can be
 /// scheduled.  Returns the next cycle and the index of the processor resource
 /// instance in the reserved cycles vector.
 std::pair<unsigned, unsigned>
 SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
-                                    unsigned Cycles, unsigned StartAtCycle) {
+                                    unsigned ReleaseAtCycle,
+                                    unsigned AcquireAtCycle) {
   if (MischedDetailResourceBooking) {
     LLVM_DEBUG(dbgs() << "  Resource booking (@" << CurrCycle << "c): \n");
     LLVM_DEBUG(dumpReservedCycles());
     LLVM_DEBUG(dbgs() << "  getNextResourceCycle (@" << CurrCycle << "c): \n");
   }
   unsigned MinNextUnreserved = InvalidCycle;
   unsigned InstanceIdx = 0;
   unsigned StartIndex = ReservedCyclesIndex[PIdx];
if (isUnbufferedGroup(PIdx)) {
     // group with buffered subunits will appear to schedule
     // strangely. In the first case, the additional cycles for the
     // group will be ignored.  In the second, the group will be
     // ignored entirely.
     for (const MCWriteProcResEntry &PE :
          make_range(SchedModel->getWriteProcResBegin(SC),
                     SchedModel->getWriteProcResEnd(SC)))
       if (ResourceGroupSubUnitMasks[PIdx][PE.ProcResourceIdx])
-        return std::make_pair(
-            getNextResourceCycleByInstance(StartIndex, Cycles, StartAtCycle),
+        return std::make_pair(getNextResourceCycleByInstance(
+                                  StartIndex, ReleaseAtCycle, AcquireAtCycle),
                               StartIndex);
 
     auto SubUnits = SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin;
     for (unsigned I = 0, End = NumberOfInstances; I < End; ++I) {
       unsigned NextUnreserved, NextInstanceIdx;
       std::tie(NextUnreserved, NextInstanceIdx) =
-          getNextResourceCycle(SC, SubUnits[I], Cycles, StartAtCycle);
+          getNextResourceCycle(SC, SubUnits[I], ReleaseAtCycle, AcquireAtCycle);
       if (MinNextUnreserved > NextUnreserved) {
         InstanceIdx = NextInstanceIdx;
         MinNextUnreserved = NextUnreserved;
       }
     }
     return std::make_pair(MinNextUnreserved, InstanceIdx);
   }
 
   for (unsigned I = StartIndex, End = StartIndex + NumberOfInstances; I < End;
        ++I) {
     unsigned NextUnreserved =
-        getNextResourceCycleByInstance(I, Cycles, StartAtCycle);
+        getNextResourceCycleByInstance(I, ReleaseAtCycle, AcquireAtCycle);
     if (MischedDetailResourceBooking)
       LLVM_DEBUG(dbgs() << "    Instance " << I - StartIndex << " available @"
                         << NextUnreserved << "c\n");
     if (MinNextUnreserved > NextUnreserved) {
       InstanceIdx = I;
       MinNextUnreserved = NextUnreserved;
     }
   }
bool SchedBoundary::checkHazard(SUnit *SU) {
   }
 
   if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
     const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
     for (const MCWriteProcResEntry &PE :
           make_range(SchedModel->getWriteProcResBegin(SC),
                      SchedModel->getWriteProcResEnd(SC))) {
       unsigned ResIdx = PE.ProcResourceIdx;
-      unsigned Cycles = PE.Cycles;
-      unsigned StartAtCycle = PE.StartAtCycle;
+      unsigned ReleaseAtCycle = PE.ReleaseAtCycle;
+      unsigned AcquireAtCycle = PE.AcquireAtCycle;
       unsigned NRCycle, InstanceIdx;
       std::tie(NRCycle, InstanceIdx) =
-          getNextResourceCycle(SC, ResIdx, Cycles, StartAtCycle);
+          getNextResourceCycle(SC, ResIdx, ReleaseAtCycle, AcquireAtCycle);
       if (NRCycle > CurrCycle) {
 #if LLVM_ENABLE_ABI_BREAKING_CHECKS
-        MaxObservedStall = std::max(Cycles, MaxObservedStall);
+        MaxObservedStall = std::max(ReleaseAtCycle, MaxObservedStall);
 #endif
         LLVM_DEBUG(dbgs() << "  SU(" << SU->NodeNum << ") "
                           << SchedModel->getResourceName(ResIdx)
                           << '[' << InstanceIdx - ReservedCyclesIndex[ResIdx]  << ']'
                           << "=" << NRCycle << "c\n");
         return true;
       }
     }

 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
   ExecutedResCounts[PIdx] += Count;
   if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
     MaxExecutedResCount = ExecutedResCounts[PIdx];
 }
 
 /// Add the given processor resource to this scheduled zone.
 ///
-/// \param Cycles indicates the number of consecutive (non-pipelined) cycles
-/// during which this resource is consumed.
+/// \param ReleaseAtCycle indicates the number of consecutive (non-pipelined)
+/// cycles during which this resource is released.
+///
+/// \param AcquireAtCycle indicates the number of consecutive (non-pipelined)
+/// cycles at which the resource is aquired after issue (assuming no stalls).
 ///
 /// \return the next cycle at which the instruction may execute without
 /// oversubscribing resources.
 unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx,
-                                      unsigned Cycles, unsigned NextCycle,
-                                      unsigned StartAtCycle) {
+                                      unsigned ReleaseAtCycle,
+                                      unsigned NextCycle,
+                                      unsigned AcquireAtCycle) {
   unsigned Factor = SchedModel->getResourceFactor(PIdx);
-  unsigned Count = Factor * (Cycles - StartAtCycle);
+  unsigned Count = Factor * (ReleaseAtCycle- AcquireAtCycle);
   LLVM_DEBUG(dbgs() << "  " << SchedModel->getResourceName(PIdx) << " +"
-                    << Cycles << "x" << Factor << "u\n");
+                    << ReleaseAtCycle << "x" << Factor << "u\n");
 
   // Update Executed resources counts.
   incExecutedResources(PIdx, Count);
   assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
   Rem->RemainingCounts[PIdx] -= Count;
 
   // Check if this resource exceeds the current critical resource. If so, it
   // becomes the critical resource.
   if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
     ZoneCritResIdx = PIdx;
     LLVM_DEBUG(dbgs() << "  *** Critical resource "
                       << SchedModel->getResourceName(PIdx) << ": "
                       << getResourceCount(PIdx) / SchedModel->getLatencyFactor()
                       << "c\n");
   }
   // For reserved resources, record the highest cycle using the resource.
   unsigned NextAvailable, InstanceIdx;
   std::tie(NextAvailable, InstanceIdx) =
-      getNextResourceCycle(SC, PIdx, Cycles, StartAtCycle);
+      getNextResourceCycle(SC, PIdx, ReleaseAtCycle, AcquireAtCycle);
   if (NextAvailable > CurrCycle) {
     LLVM_DEBUG(dbgs() << "  Resource conflict: "
                       << SchedModel->getResourceName(PIdx)
                       << '[' << InstanceIdx - ReservedCyclesIndex[PIdx]  << ']'
                       << " reserved until @" << NextAvailable << "\n");
   }
   return NextAvailable;
 }
if (ZoneCritResIdx) {
         LLVM_DEBUG(dbgs() << "  *** Critical resource NumMicroOps: "
                           << ScaledMOps / SchedModel->getLatencyFactor()
                           << "c\n");
       }
     }
     for (TargetSchedModel::ProcResIter
            PI = SchedModel->getWriteProcResBegin(SC),
            PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
-      unsigned RCycle = countResource(SC, PI->ProcResourceIdx, PI->Cycles,
-                                      NextCycle, PI->StartAtCycle);
+      unsigned RCycle =
+          countResource(SC, PI->ProcResourceIdx, PI->ReleaseAtCycle, NextCycle,
+                        PI->AcquireAtCycle);
       if (RCycle > NextCycle)
         NextCycle = RCycle;
     }
     if (SU->hasReservedResource) {
       // For reserved resources, record the highest cycle using the resource.
       // For top-down scheduling, this is the cycle in which we schedule this
       // instruction plus the number of cycles the operations reserves the
       // resource. For bottom-up is it simply the instruction's cycle.
       for (TargetSchedModel::ProcResIter
              PI = SchedModel->getWriteProcResBegin(SC),
              PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
         unsigned PIdx = PI->ProcResourceIdx;
         if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
 
           if (SchedModel && SchedModel->enableIntervals()) {
             unsigned ReservedUntil, InstanceIdx;
-            std::tie(ReservedUntil, InstanceIdx) =
-                getNextResourceCycle(SC, PIdx, PI->Cycles, PI->StartAtCycle);
+            std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(
+                SC, PIdx, PI->ReleaseAtCycle, PI->AcquireAtCycle);
             if (isTop()) {
               ReservedResourceSegments[InstanceIdx].add(
                   ResourceSegments::getResourceIntervalTop(
-                      NextCycle, PI->StartAtCycle, PI->Cycles),
+                      NextCycle, PI->AcquireAtCycle, PI->ReleaseAtCycle),
                   MIResourceCutOff);
             } else {
               ReservedResourceSegments[InstanceIdx].add(
                   ResourceSegments::getResourceIntervalBottom(
-                      NextCycle, PI->StartAtCycle, PI->Cycles),
+                      NextCycle, PI->AcquireAtCycle, PI->ReleaseAtCycle),
                   MIResourceCutOff);
             }
           } else {
 
             unsigned ReservedUntil, InstanceIdx;
-            std::tie(ReservedUntil, InstanceIdx) =
-                getNextResourceCycle(SC, PIdx, PI->Cycles, PI->StartAtCycle);
+            std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(
+                SC, PIdx, PI->ReleaseAtCycle, PI->AcquireAtCycle);
             if (isTop()) {
               ReservedCycles[InstanceIdx] =
-                  std::max(ReservedUntil, NextCycle + PI->Cycles);
+                  std::max(ReservedUntil, NextCycle + PI->ReleaseAtCycle);
             } else
               ReservedCycles[InstanceIdx] = NextCycle;
           }
         }
       }
     }
   }
   // Update ExpectedLatency and DependentLatency.
initResourceDelta(const ScheduleDAGMI *DAG,
   if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
     return;
 
   const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
   for (TargetSchedModel::ProcResIter
          PI = SchedModel->getWriteProcResBegin(SC),
          PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
     if (PI->ProcResourceIdx == Policy.ReduceResIdx)
-      ResDelta.CritResources += PI->Cycles;
+      ResDelta.CritResources += PI->ReleaseAtCycle;
     if (PI->ProcResourceIdx == Policy.DemandResIdx)
-      ResDelta.DemandedResources += PI->Cycles;
+      ResDelta.DemandedResources += PI->ReleaseAtCycle;
   }
 }
 
 /// Compute remaining latency. We need this both to determine whether the
 /// overall schedule has become latency-limited and whether the instructions
 /// outside this zone are resource or latency limited.
 ///
 /// The "dependent" latency is updated incrementally during scheduling as the

 /// for any pairs of intervals), therefore we can sort the totality of
 /// the intervals by looking only at the left boundary.
 static bool sortIntervals(const ResourceSegments::IntervalTy &A,
                           const ResourceSegments::IntervalTy &B) {
   return A.first < B.first;
 }
 
 unsigned ResourceSegments::getFirstAvailableAt(
-    unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
+    unsigned CurrCycle, unsigned AcquireAtCycle, unsigned Cycle,
     std::function<ResourceSegments::IntervalTy(unsigned, unsigned, unsigned)>
         IntervalBuilder) const {
   assert(std::is_sorted(std::begin(_Intervals), std::end(_Intervals),
                         sortIntervals) &&
          "Cannot execute on an un-sorted set of intervals.");
   unsigned RetCycle = CurrCycle;
   ResourceSegments::IntervalTy NewInterval =
-      IntervalBuilder(RetCycle, StartAtCycle, Cycle);
+      IntervalBuilder(RetCycle, AcquireAtCycle, Cycle);
   for (auto &Interval : _Intervals) {
     if (!intersects(NewInterval, Interval))
       continue;
 
     // Move the interval right next to the top of the one it
     // intersects.
     assert(Interval.second > NewInterval.first &&
            "Invalid intervals configuration.");
     RetCycle += (unsigned)Interval.second - (unsigned)NewInterval.first;
-    NewInterval = IntervalBuilder(RetCycle, StartAtCycle, Cycle);
+    NewInterval = IntervalBuilder(RetCycle, AcquireAtCycle, Cycle);
   }
   return RetCycle;
 }
 
 void ResourceSegments::add(ResourceSegments::IntervalTy A,
                            const unsigned CutOff) {
   assert(A.first < A.second && "Cannot add empty resource usage");
   assert(CutOff > 0 && "0-size interval history has no use.");

llvm/lib/CodeGen/MachineTraceMetrics.cpp

bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) {
   MF = &Func;
   const TargetSubtargetInfo &ST = MF->getSubtarget();
   TII = ST.getInstrInfo();
   TRI = ST.getRegisterInfo();
   MRI = &MF->getRegInfo();
   Loops = &getAnalysis<MachineLoopInfo>();
   SchedModel.init(&ST);
   BlockInfo.resize(MF->getNumBlockIDs());
-  ProcResourceCycles.resize(MF->getNumBlockIDs() *
+  ProcReleaseAtCycles.resize(MF->getNumBlockIDs() *
                             SchedModel.getNumProcResourceKinds());
   return false;
 }
 
 void MachineTraceMetrics::releaseMemory() {
   MF = nullptr;
   BlockInfo.clear();
   for (Ensemble *&E : Ensembles) {
for (const auto &MI : *MBB) {
     const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
     if (!SC->isValid())
       continue;
 
     for (TargetSchedModel::ProcResIter
          PI = SchedModel.getWriteProcResBegin(SC),
          PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
       assert(PI->ProcResourceIdx < PRKinds && "Bad processor resource kind");
-      PRCycles[PI->ProcResourceIdx] += PI->Cycles;
+      PRCycles[PI->ProcResourceIdx] += PI->ReleaseAtCycle;
     }
   }
   FBI->InstrCount = InstrCount;
 
   // Scale the resource cycles so they are comparable.
   unsigned PROffset = MBB->getNumber() * PRKinds;
   for (unsigned K = 0; K != PRKinds; ++K)
-    ProcResourceCycles[PROffset + K] =
+    ProcReleaseAtCycles[PROffset + K] =
       PRCycles[K] * SchedModel.getResourceFactor(K);
 
   return FBI;
 }
 
 ArrayRef<unsigned>
-MachineTraceMetrics::getProcResourceCycles(unsigned MBBNum) const {
+MachineTraceMetrics::getProcReleaseAtCycles(unsigned MBBNum) const {
   assert(BlockInfo[MBBNum].hasResources() &&
-         "getResources() must be called before getProcResourceCycles()");
+         "getResources() must be called before getProcReleaseAtCycles()");
   unsigned PRKinds = SchedModel.getNumProcResourceKinds();
-  assert((MBBNum+1) * PRKinds <= ProcResourceCycles.size());
-  return ArrayRef(ProcResourceCycles.data() + MBBNum * PRKinds, PRKinds);
+  assert((MBBNum+1) * PRKinds <= ProcReleaseAtCycles.size());
+  return ArrayRef(ProcReleaseAtCycles.data() + MBBNum * PRKinds, PRKinds);
 }
 
 //===----------------------------------------------------------------------===//
 //                         Ensemble utility functions
 //===----------------------------------------------------------------------===//
 
 MachineTraceMetrics::Ensemble::Ensemble(MachineTraceMetrics *ct)
   : MTM(*ct) {
computeDepthResources(const MachineBasicBlock *MBB) {
   TraceBlockInfo *PredTBI = &BlockInfo[PredNum];
   assert(PredTBI->hasValidDepth() && "Trace above has not been computed yet");
   const FixedBlockInfo *PredFBI = MTM.getResources(TBI->Pred);
   TBI->InstrDepth = PredTBI->InstrDepth + PredFBI->InstrCount;
   TBI->Head = PredTBI->Head;
 
   // Compute per-resource depths.
   ArrayRef<unsigned> PredPRDepths = getProcResourceDepths(PredNum);
-  ArrayRef<unsigned> PredPRCycles = MTM.getProcResourceCycles(PredNum);
+  ArrayRef<unsigned> PredPRCycles = MTM.getProcReleaseAtCycles(PredNum);
   for (unsigned K = 0; K != PRKinds; ++K)
     ProcResourceDepths[PROffset + K] = PredPRDepths[K] + PredPRCycles[K];
 }
 
 // Update resource-related information in the TraceBlockInfo for MBB.
 // Only update resources related to the trace below MBB.
 void MachineTraceMetrics::Ensemble::
 computeHeightResources(const MachineBasicBlock *MBB) {
   TraceBlockInfo *TBI = &BlockInfo[MBB->getNumber()];
   unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds();
   unsigned PROffset = MBB->getNumber() * PRKinds;
 
   // Compute resources for the current block.
   TBI->InstrHeight = MTM.getResources(MBB)->InstrCount;
-  ArrayRef<unsigned> PRCycles = MTM.getProcResourceCycles(MBB->getNumber());
+  ArrayRef<unsigned> PRCycles = MTM.getProcReleaseAtCycles(MBB->getNumber());
 
   // The trace tail is done.
   if (!TBI->Succ) {
     TBI->Tail = MBB->getNumber();
     llvm::copy(PRCycles, ProcResourceHeights.begin() + PROffset);
     return;
   }
 

 
 /// When bottom is set include instructions in current block in estimate.
 unsigned MachineTraceMetrics::Trace::getResourceDepth(bool Bottom) const {
   // Find the limiting processor resource.
   // Numbers have been pre-scaled to be comparable.
   unsigned PRMax = 0;
   ArrayRef<unsigned> PRDepths = TE.getProcResourceDepths(getBlockNum());
   if (Bottom) {
-    ArrayRef<unsigned> PRCycles = TE.MTM.getProcResourceCycles(getBlockNum());
+    ArrayRef<unsigned> PRCycles = TE.MTM.getProcReleaseAtCycles(getBlockNum());
     for (unsigned K = 0; K != PRDepths.size(); ++K)
       PRMax = std::max(PRMax, PRDepths[K] + PRCycles[K]);
   } else {
     for (unsigned PRD : PRDepths)
       PRMax = std::max(PRMax, PRD);
   }
   // Convert to cycle count.
   PRMax = TE.MTM.getCycles(PRMax);
for (const MCSchedClassDesc *SC : Instrs) {
       if (!SC->isValid())
         continue;
       for (TargetSchedModel::ProcResIter
                PI = TE.MTM.SchedModel.getWriteProcResBegin(SC),
                PE = TE.MTM.SchedModel.getWriteProcResEnd(SC);
            PI != PE; ++PI) {
         if (PI->ProcResourceIdx != ResourceIdx)
           continue;
-        Cycles +=
-            (PI->Cycles * TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
+        Cycles += (PI->ReleaseAtCycle *
+                   TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
       }
     }
     return Cycles;
   };
 
   for (unsigned K = 0; K != PRDepths.size(); ++K) {
     unsigned PRCycles = PRDepths[K] + PRHeights[K];
     for (const MachineBasicBlock *MBB : Extrablocks)
-      PRCycles += TE.MTM.getProcResourceCycles(MBB->getNumber())[K];
+      PRCycles += TE.MTM.getProcReleaseAtCycles(MBB->getNumber())[K];
     PRCycles += extraCycles(ExtraInstrs, K);
     PRCycles -= extraCycles(RemoveInstrs, K);
     PRMax = std::max(PRMax, PRCycles);
   }
   // Convert to cycle count.
   PRMax = TE.MTM.getCycles(PRMax);
 
   // Instrs: #instructions in current trace outside current block.

llvm/lib/MC/MCSchedule.cpp

 double
 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
                                       const MCSchedClassDesc &SCDesc) {
   std::optional<double> Throughput;
   const MCSchedModel &SM = STI.getSchedModel();
   const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
   const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
   for (; I != E; ++I) {
-    if (!I->Cycles)
+    if (!I->ReleaseAtCycle)
       continue;
     unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
-    double Temp = NumUnits * 1.0 / I->Cycles;
+    double Temp = NumUnits * 1.0 / I->ReleaseAtCycle;
     Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
   }
   if (Throughput)
     return 1.0 / *Throughput;
 
   // If no throughput value was calculated, assume that we can execute at the
   // maximum issue width scaled by number of micro-ops for the schedule class.
   return ((double)SCDesc.NumMicroOps) / SM.IssueWidth;

llvm/lib/MCA/HardwareUnits/ResourceManager.cpp

for (const std::pair<uint64_t, ResourceUsage> &E : Desc.Resources) {
     }
   }
 
   return BusyResourceMask;
 }
 
 void ResourceManager::issueInstruction(
     const InstrDesc &Desc,
-    SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes) {
+    SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes) {
   for (const std::pair<uint64_t, ResourceUsage> &R : Desc.Resources) {
     const CycleSegment &CS = R.second.CS;
     if (!CS.size()) {
       releaseResource(R.first);
       continue;
     }
 
     assert(CS.begin() == 0 && "Invalid {Start, End} cycles!");
     if (!R.second.isReserved()) {
       ResourceRef Pipe = selectPipe(R.first);
       use(Pipe);
       BusyResources[Pipe] += CS.size();
-      Pipes.emplace_back(std::pair<ResourceRef, ResourceCycles>(
-          Pipe, ResourceCycles(CS.size())));
+      Pipes.emplace_back(std::pair<ResourceRef, ReleaseAtCycles>(
+          Pipe, ReleaseAtCycles(CS.size())));
     } else {
       assert((llvm::popcount(R.first) > 1) && "Expected a group!");
       // Mark this group as reserved.
       assert(R.second.isReserved());
       reserveResource(R.first);
       BusyResources[ResourceRef(R.first, R.first)] += CS.size();
     }
   }

llvm/lib/MCA/HardwareUnits/Scheduler.cpp

case LSUnit::LSU_AVAILABLE:
     return Scheduler::SC_AVAILABLE;
   }
 
   llvm_unreachable("Don't know how to process this LSU state result!");
 }
 
 void Scheduler::issueInstructionImpl(
     InstRef &IR,
-    SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources) {
+    SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources) {
   Instruction *IS = IR.getInstruction();
   const InstrDesc &D = IS->getDesc();
 
   // Issue the instruction and collect all the consumed resources
   // into a vector. That vector is then used to notify the listener.
   Resources->issueInstruction(D, UsedResources);
 
   // Notify the instruction that it started executing.
if (IS->isExecuting())
     IssuedSet.emplace_back(IR);
   else if (IS->isExecuted())
     LSU.onInstructionExecuted(IR);
 }
 
 // Release the buffered resources and issue the instruction.
 void Scheduler::issueInstruction(
     InstRef &IR,
-    SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources,
+    SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources,
     SmallVectorImpl<InstRef> &PendingInstructions,
     SmallVectorImpl<InstRef> &ReadyInstructions) {
   const Instruction &Inst = *IR.getInstruction();
   bool HasDependentUsers = Inst.hasDependentUsers();
   HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR);
 
   Resources->releaseBuffers(Inst.getUsedBuffers());
   issueInstructionImpl(IR, UsedResources);

llvm/lib/MCA/InstrBuilder.cpp

static void initializeUsedResources(InstrDesc &ID,
   unsigned NumProcResources = SM.getNumProcResourceKinds();
   APInt Buffers(NumProcResources, 0);
 
   bool AllInOrderResources = true;
   bool AnyDispatchHazards = false;
   for (unsigned I = 0, E = SCDesc.NumWriteProcResEntries; I < E; ++I) {
     const MCWriteProcResEntry *PRE = STI.getWriteProcResBegin(&SCDesc) + I;
     const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx);
-    if (!PRE->Cycles) {
+    if (!PRE->ReleaseAtCycle) {
 #ifndef NDEBUG
       WithColor::warning()
           << "Ignoring invalid write of zero cycles on processor resource "
           << PR.Name << "\n";
       WithColor::note() << "found in scheduling class " << SCDesc.Name
                         << " (write index #" << I << ")\n";
 #endif
       continue;
     }
 
     uint64_t Mask = ProcResourceMasks[PRE->ProcResourceIdx];
     if (PR.BufferSize < 0) {
       AllInOrderResources = false;
     } else {
       Buffers.setBit(getResourceStateIndex(Mask));
       AnyDispatchHazards |= (PR.BufferSize == 0);
       AllInOrderResources &= (PR.BufferSize <= 1);
     }
 
-    CycleSegment RCy(0, PRE->Cycles, false);
+    CycleSegment RCy(0, PRE->ReleaseAtCycle, false);
     Worklist.emplace_back(ResourcePlusCycles(Mask, ResourceUsage(RCy)));
     if (PR.SuperIdx) {
       uint64_t Super = ProcResourceMasks[PR.SuperIdx];
-      SuperResources[Super] += PRE->Cycles;
+      SuperResources[Super] += PRE->ReleaseAtCycle;
     }
   }
 
   ID.MustIssueImmediately = AllInOrderResources && AnyDispatchHazards;
 
   // Sort elements by mask popcount, so that we prioritize resource units over
   // resource groups, and smaller groups over larger groups.
   sort(Worklist, [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) {
for (unsigned J = I + 1; J < E; ++J) {
       }
     }
   }
 
   // A SchedWrite may specify a number of cycles in which a resource group
   // is reserved. For example (on target x86; cpu Haswell):
   //
   //  SchedWriteRes<[HWPort0, HWPort1, HWPort01]> {
-  //    let ResourceCycles = [2, 2, 3];
+  //    let ReleaseAtCycles = [2, 2, 3];
   //  }
   //
   // This means:
   // Resource units HWPort0 and HWPort1 are both used for 2cy.
   // Resource group HWPort01 is the union of HWPort0 and HWPort1.
   // Since this write touches both HWPort0 and HWPort1 for 2cy, HWPort01
   // will not be usable for 2 entire cycles from instruction issue.
   //

llvm/lib/MCA/Stages/ExecuteStage.cpp

#ifndef NDEBUG
   HWS.instructionCheck(IR);
 #endif
 
   if (IR.getInstruction()->isEliminated())
     return handleInstructionEliminated(IR);
 
   // Reserve a slot in each buffered resource. Also, mark units with
   // BufferSize=0 as reserved. Resources with a buffer size of zero will only
-  // be released after MCIS is issued, and all the ResourceCycles for those
+  // be released after MCIS is issued, and all the ReleaseAtCycles for those
   // units have been consumed.
   bool IsReadyInstruction = HWS.dispatch(IR);
   const Instruction &Inst = *IR.getInstruction();
   unsigned NumMicroOps = Inst.getNumMicroOps();
   NumDispatchedOpcodes += NumMicroOps;
   notifyReservedOrReleasedBuffers(IR, /* Reserved */ true);
 
   if (!IsReadyInstruction) {

llvm/lib/MCA/Stages/InstructionTables.cpp

for (const std::pair<uint64_t, ResourceUsage> &Resource :
     unsigned Index = std::distance(Masks.begin(), find(Masks, Resource.first));
     const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index);
     unsigned NumUnits = ProcResource.NumUnits;
     if (!ProcResource.SubUnitsIdxBegin) {
       // The number of cycles consumed by each unit.
       for (unsigned I = 0, E = NumUnits; I < E; ++I) {
         ResourceRef ResourceUnit = std::make_pair(Index, 1U << I);
         UsedResources.emplace_back(
-            std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits)));
+            std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits)));
       }
       continue;
     }
 
     // This is a group. Obtain the set of resources contained in this
     // group. Some of these resources may implement multiple units.
     // Uniformly distribute Cycles across all of the units.
     for (unsigned I1 = 0; I1 < NumUnits; ++I1) {
       unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1];
       const MCProcResourceDesc &SubUnit = *SM.getProcResource(SubUnitIdx);
       // Compute the number of cycles consumed by each resource unit.
       for (unsigned I2 = 0, E2 = SubUnit.NumUnits; I2 < E2; ++I2) {
         ResourceRef ResourceUnit = std::make_pair(SubUnitIdx, 1U << I2);
         UsedResources.emplace_back(std::make_pair(
-            ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits)));
+            ResourceUnit,
+            ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits)));
       }
     }
   }
 
   // Send a fake instruction issued event to all the views.
   HWInstructionIssuedEvent Event(IR, UsedResources);
   notifyEvent<HWInstructionIssuedEvent>(Event);
   return ErrorSuccess();
 }
 
 } // namespace mca
 } // namespace llvm

llvm/lib/MCA/Support.cpp

 #include "llvm/MC/MCSchedule.h"
 #include <numeric>
 
 namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
-ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) {
+ReleaseAtCycles &ReleaseAtCycles::operator+=(const ReleaseAtCycles &RHS) {
   if (Denominator == RHS.Denominator)
     Numerator += RHS.Numerator;
   else {
     // Create a common denominator for LHS and RHS by calculating the least
     // common multiple from the GCD.
     unsigned GCD = std::gcd(Denominator, RHS.Denominator);
     unsigned LCM = (Denominator * RHS.Denominator) / GCD;
     unsigned LHSNumerator = Numerator * (LCM / Denominator);
double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
   // throughput. That is because the DispatchWidth is an upper bound on the
   // number of opcodes that can be part of a single dispatch group.
   double Max = static_cast<double>(NumMicroOps) / DispatchWidth;
 
   // The block throughput is also limited by the amount of hardware parallelism.
   // The number of available resource units affects the resource pressure
   // distribution, as well as how many blocks can be executed every cycle.
   for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
-    unsigned ResourceCycles = ProcResourceUsage[I];
-    if (!ResourceCycles)
+    unsigned ReleaseAtCycles = ProcResourceUsage[I];
+    if (!ReleaseAtCycles)
       continue;
 
     const MCProcResourceDesc &MCDesc = *SM.getProcResource(I);
-    double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits;
+    double Throughput = static_cast<double>(ReleaseAtCycles) / MCDesc.NumUnits;
     Max = std::max(Max, Throughput);
   }
 
   // The block reciprocal throughput is computed as the MAX of:
   //  - (NumMicroOps / DispatchWidth)
-  //  - (NumUnits / ResourceCycles)   for every consumed processor resource.
+  //  - (NumUnits / ReleaseAtCycles)   for every consumed processor resource.
   return Max;
 }
 
 } // namespace mca
 } // namespace llvm

llvm/lib/Target/AArch64/AArch64SchedA510.td

 def : WriteRes<WriteI, [CortexA510UnitALU]> { let Latency = 1; }      // ALU
 def : WriteRes<WriteISReg, [CortexA510UnitALU]> { let Latency = 2; }  // ALU of Shifted-Reg
 def : WriteRes<WriteIEReg, [CortexA510UnitALU]> { let Latency = 2; }  // ALU of Extended-Reg
 def : WriteRes<WriteExtr, [CortexA510UnitALU]> { let Latency = 2; }   // EXTR from a reg pair
 def : WriteRes<WriteIS, [CortexA510UnitALU]> { let Latency = 2; }     // Shift/Scale
 
 // MAC
 def : WriteRes<WriteIM32, [CortexA510UnitMAC]> { let Latency = 3; }   // 32-bit Multiply
-def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ResourceCycles = [2];}   // 64-bit Multiply
+def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ReleaseAtCycles = [2];}   // 64-bit Multiply
 
 // Div
 def : WriteRes<WriteID32, [CortexA510UnitDiv]> {
-  let Latency = 8; let ResourceCycles = [8];
+  let Latency = 8; let ReleaseAtCycles = [8];
 }
 def : WriteRes<WriteID64, [CortexA510UnitDiv]> {
-  let Latency = 16; let ResourceCycles = [16];
+  let Latency = 16; let ReleaseAtCycles = [16];
 }
 
 //===----------------------------------------------------------------------===//
 // Define customized scheduler read/write types specific to the Cortex A510
 
 //===----------------------------------------------------------------------===//
 class CortexA510Write<int n, ProcResourceKind res> : SchedWriteRes<[res]> {
   let Latency = n;
 }
 
 class CortexA510MCWrite<int n, int m, ProcResourceKind res> : SchedWriteRes<[res]> {
   let Latency = n;
-  let ResourceCycles = [m];
+  let ReleaseAtCycles = [m];
   let BeginGroup = 1;
 }
 
 class CortexA510MC_RC0Write<int n, ProcResourceKind res> : SchedWriteRes<[res]> {
   let Latency = n;
   let BeginGroup = 1;
 }
 

 // Load
 def : WriteRes<WriteLD, [CortexA510UnitLd]> { let Latency = 2; }
 def : WriteRes<WriteLDIdx, [CortexA510UnitLd]> { let Latency = 2; }
 def : WriteRes<WriteLDHi, [CortexA510UnitLd]> { let Latency = 2; }
 
 def CortexA510WriteVLD1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
 def CortexA510WriteVLD1SI : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; let SingleIssue = 1; }
 def CortexA510WriteVLD2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 4;
-                                                  let ResourceCycles = [2]; }
+                                                  let ReleaseAtCycles = [2]; }
 def CortexA510WriteVLD3 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 def CortexA510WriteVLD4 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
-                                                  let ResourceCycles = [4]; }
+                                                  let ReleaseAtCycles = [4]; }
 def CortexA510WriteVLD6 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 def CortexA510WriteVLD8 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
-                                                  let ResourceCycles = [4]; }
+                                                  let ReleaseAtCycles = [4]; }
 
 def CortexA510WriteLDP1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
 def CortexA510WriteLDP2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
 def CortexA510WriteLDP4 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
 
 // Pre/Post Indexing - Performed as part of address generation
 def : WriteRes<WriteAdr, []> { let Latency = 0; }
 
 // Store
 let RetireOOO = 1 in {
 def : WriteRes<WriteST, [CortexA510UnitLdSt]> { let Latency = 1; }
 def : WriteRes<WriteSTP, [CortexA510UnitLdSt]> { let Latency = 1; }
 def : WriteRes<WriteSTIdx, [CortexA510UnitLdSt]> { let Latency = 1; }
 }
 def : WriteRes<WriteSTX, [CortexA510UnitLdSt]> { let Latency = 3; }
 
 // Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
 def : WriteRes<WriteVST, [CortexA510UnitLdSt]> { let Latency = 5;
-                                          let ResourceCycles = [2];}
+                                          let ReleaseAtCycles = [2];}
 def CortexA510WriteVST1 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 4; }
 def CortexA510WriteVST2 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
-                                                  let ResourceCycles = [2]; }
+                                                  let ReleaseAtCycles = [2]; }
 def CortexA510WriteVST3 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 def CortexA510WriteVST4 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
-                                                  let ResourceCycles = [4]; }
+                                                  let ReleaseAtCycles = [4]; }
 
 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
 
 // Branch
 def : WriteRes<WriteBr, [CortexA510UnitB]>;
 def : WriteRes<WriteBrReg, [CortexA510UnitB]>;
 def : WriteRes<WriteSys, [CortexA510UnitB]>;
 def : WriteRes<WriteBarrier, [CortexA510UnitB]>;
 def : WriteRes<WriteHint, [CortexA510UnitB]>;
 
 // FP ALU
 //   As WriteF result is produced in F5 and it can be mostly forwarded
 //   to consumer at F1, the effectively Latency is set as 4.
 def : WriteRes<WriteF, [CortexA510UnitVALU]> { let Latency = 4; }
 def : WriteRes<WriteFCmp, [CortexA510UnitVALU]> { let Latency = 3; }
 def : WriteRes<WriteFCvt, [CortexA510UnitVALU]> { let Latency = 4; }
 def : WriteRes<WriteFCopy, [CortexA510UnitVALU]> { let Latency = 3; }
 def : WriteRes<WriteFImm, [CortexA510UnitVALU]> { let Latency = 3; }
 
 class CortexA510VSt<int n> : SchedWriteRes<[CortexA510UnitLdSt]> {
   let RetireOOO = 1;
-  let ResourceCycles = [n];
+  let ReleaseAtCycles = [n];
 }
 
 def CortexA510VSt0      : SchedWriteRes<[CortexA510UnitLdSt]> {
   let RetireOOO = 1;
 }
 
 def : SchedAlias<WriteVd, CortexA510Write<4, CortexA510UnitVALU>>;
 def : SchedAlias<WriteVq, CortexA510Write<4, CortexA510UnitVALU>>;
 
 // FP ALU specific new schedwrite definitions
 def CortexA510WriteFPALU_F3 : SchedWriteRes<[CortexA510UnitVALU]> { let Latency = 3;}
 def CortexA510WriteFPALU_F4 : SchedWriteRes<[CortexA510UnitVALU]> { let Latency = 4;}
 
 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
 def : WriteRes<WriteFMul, [CortexA510UnitVMAC]> { let Latency = 4; }
 
 let RetireOOO = 1 in {
 def : WriteRes<WriteFDiv, [CortexA510UnitVMC]> { let Latency = 22;
-                                            let ResourceCycles = [29]; }
+                                            let ReleaseAtCycles = [29]; }
 def CortexA510WriteVMAC : SchedWriteRes<[CortexA510UnitVMAC]> { let Latency = 4; }
 def CortexA510WriteFDivHP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 8;
-                                                     let ResourceCycles = [5]; }
+                                                     let ReleaseAtCycles = [5]; }
 def CortexA510WriteFDivSP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 13;
-                                                     let ResourceCycles = [10]; }
+                                                     let ReleaseAtCycles = [10]; }
 def CortexA510WriteFDivDP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 22;
-                                                     let ResourceCycles = [19]; }
+                                                     let ReleaseAtCycles = [19]; }
 def CortexA510WriteFSqrtHP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 8;
-                                                      let ResourceCycles = [5]; }
+                                                      let ReleaseAtCycles = [5]; }
 def CortexA510WriteFSqrtSP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 12;
-                                                      let ResourceCycles = [9]; }
+                                                      let ReleaseAtCycles = [9]; }
 def CortexA510WriteFSqrtDP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 22;
-                                                      let ResourceCycles = [19]; }
+                                                      let ReleaseAtCycles = [19]; }
 }
 //===----------------------------------------------------------------------===//
 // Subtarget-specific SchedRead types.
 
 def : ReadAdvance<ReadVLD, 0>;
 def : ReadAdvance<ReadExtrHi, 0>;
 def : ReadAdvance<ReadAdrBase, 0>;
 def : ReadAdvance<ReadST, 1>;

llvm/lib/Target/AArch64/AArch64SchedA53.td

 def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
 def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
 
 // Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
 //               below, choosing the median of 3 which makes the latency 6.
 //               May model this more carefully in the future. The remaining
 //               A53WriteVLD# types represent the 1-5 cycle issues explicitly.
 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
-                                          let ResourceCycles = [3]; }
+                                          let ReleaseAtCycles = [3]; }
 def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
 def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
-                                                  let ResourceCycles = [2]; }
+                                                  let ReleaseAtCycles = [2]; }
 def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
-                                                  let ResourceCycles = [4]; }
+                                                  let ReleaseAtCycles = [4]; }
 def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
-                                                  let ResourceCycles = [5]; }
+                                                  let ReleaseAtCycles = [5]; }
 
 // Pre/Post Indexing - Performed as part of address generation which is already
 //                     accounted for in the WriteST* latencies below
 def : WriteRes<WriteAdr, []> { let Latency = 0; }
 
 // Store
 def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
 def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
 def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
 def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
 
 // Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
 def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
-                                          let ResourceCycles = [2];}
+                                          let ReleaseAtCycles = [2];}
 def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
 def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
-                                                  let ResourceCycles = [2]; }
+                                                  let ReleaseAtCycles = [2]; }
 def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 
 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
 
 // Branch
 def : WriteRes<WriteBr, [A53UnitB]>;
 def : WriteRes<WriteBrReg, [A53UnitB]>;
 def : WriteRes<WriteSys, [A53UnitB]>;
 def : WriteRes<WriteBarrier, [A53UnitB]>;
 def : WriteRes<WriteHint, [A53UnitB]>;
 
 // FP ALU
 def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteVd, [A53UnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteVq, [A53UnitFPALU]> { let Latency = 6; }
 
 // FP Mul, Div, Sqrt
 def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
 def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
-                                            let ResourceCycles = [29]; }
+                                            let ReleaseAtCycles = [29]; }
 def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
 def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
-                                                     let ResourceCycles = [14]; }
+                                                     let ReleaseAtCycles = [14]; }
 def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
-                                                     let ResourceCycles = [29]; }
+                                                     let ReleaseAtCycles = [29]; }
 def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
-                                                      let ResourceCycles = [13]; }
+                                                      let ReleaseAtCycles = [13]; }
 def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
-                                                      let ResourceCycles = [28]; }
+                                                      let ReleaseAtCycles = [28]; }
 
 //===----------------------------------------------------------------------===//
 // Subtarget-specific SchedRead types.
 
 // No forwarding for these reads.
 def : ReadAdvance<ReadExtrHi, 0>;
 def : ReadAdvance<ReadAdrBase, 0>;
 def : ReadAdvance<ReadST, 0>;

llvm/lib/Target/AArch64/AArch64SchedA55.td

 def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; }     // Shift/Scale
 
 // MAC
 def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; }   // 32-bit Multiply
 def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; }   // 64-bit Multiply
 
 // Div
 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
-  let Latency = 8; let ResourceCycles = [8];
+  let Latency = 8; let ReleaseAtCycles = [8];
 }
 def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
-  let Latency = 8; let ResourceCycles = [8];
+  let Latency = 8; let ReleaseAtCycles = [8];
 }
 
 // Load
 def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }
 def : WriteRes<WriteLDIdx, [CortexA55UnitLd]> { let Latency = 4; }
 def : WriteRes<WriteLDHi, [CortexA55UnitLd]> { let Latency = 5; }
 
 // Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
 //               below, choosing the median of 3 which makes the latency 6.
 // An extra cycle is needed to get the swizzling right.
 def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
-                                           let ResourceCycles = [3]; }
+                                           let ReleaseAtCycles = [3]; }
 def CortexA55WriteVLD1 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; }
 def CortexA55WriteVLD1SI : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; let SingleIssue = 1; }
 def CortexA55WriteVLD2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5;
-                                                  let ResourceCycles = [2]; }
+                                                  let ReleaseAtCycles = [2]; }
 def CortexA55WriteVLD3 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 6;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 def CortexA55WriteVLD4 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 7;
-                                                  let ResourceCycles = [4]; }
+                                                  let ReleaseAtCycles = [4]; }
 def CortexA55WriteVLD5 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 8;
-                                                  let ResourceCycles = [5]; }
+                                                  let ReleaseAtCycles = [5]; }
 def CortexA55WriteVLD6 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 9;
-                                                  let ResourceCycles = [6]; }
+                                                  let ReleaseAtCycles = [6]; }
 def CortexA55WriteVLD7 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 10;
-                                                  let ResourceCycles = [7]; }
+                                                  let ReleaseAtCycles = [7]; }
 def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11;
-                                                  let ResourceCycles = [8]; }
+                                                  let ReleaseAtCycles = [8]; }
 
 def CortexA55WriteLDP1 : SchedWriteRes<[]> { let Latency = 4; }
 def CortexA55WriteLDP2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5; }
 def CortexA55WriteLDP4 : SchedWriteRes<[CortexA55UnitLd, CortexA55UnitLd, CortexA55UnitLd, CortexA55UnitLd, CortexA55UnitLd]> { let Latency = 6; }
 
 // Pre/Post Indexing - Performed as part of address generation
 def : WriteRes<WriteAdr, []> { let Latency = 0; }
 
 // Store
 let RetireOOO = 1 in {
 def : WriteRes<WriteST, [CortexA55UnitSt]> { let Latency = 1; }
 def : WriteRes<WriteSTP, [CortexA55UnitSt]> { let Latency = 1; }
 def : WriteRes<WriteSTIdx, [CortexA55UnitSt]> { let Latency = 1; }
 }
 def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }
 
 // Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
 def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;
-                                          let ResourceCycles = [2];}
+                                          let ReleaseAtCycles = [2];}
 def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; }
 def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
-                                                  let ResourceCycles = [2]; }
+                                                  let ReleaseAtCycles = [2]; }
 def CortexA55WriteVST3 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 6;
-                                                  let ResourceCycles = [3]; }
+                                                  let ReleaseAtCycles = [3]; }
 def CortexA55WriteVST4 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
-                                                  let ResourceCycles = [4]; }
+                                                  let ReleaseAtCycles = [4]; }
 
 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
 
 // Branch
 def : WriteRes<WriteBr, [CortexA55UnitB]>;
 def : WriteRes<WriteBrReg, [CortexA55UnitB]>;
 def : WriteRes<WriteSys, [CortexA55UnitB]>;
 def : WriteRes<WriteBarrier, [CortexA55UnitB]>;

 def CortexA55WriteFPALU_F4 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 4;}
 def CortexA55WriteFPALU_F5 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 5;}
 
 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
 def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }
 
 let RetireOOO = 1 in {
 def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;
-                                            let ResourceCycles = [29]; }
+                                            let ReleaseAtCycles = [29]; }
 def CortexA55WriteFMAC : SchedWriteRes<[CortexA55UnitFPMAC]> { let Latency = 4; }
 def CortexA55WriteFDivHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
-                                                     let ResourceCycles = [5]; }
+                                                     let ReleaseAtCycles = [5]; }
 def CortexA55WriteFDivSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 13;
-                                                     let ResourceCycles = [10]; }
+                                                     let ReleaseAtCycles = [10]; }
 def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
-                                                     let ResourceCycles = [19]; }
+                                                     let ReleaseAtCycles = [19]; }
 def CortexA55WriteFSqrtHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
-                                                      let ResourceCycles = [5]; }
+                                                      let ReleaseAtCycles = [5]; }
 def CortexA55WriteFSqrtSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 12;
-                                                      let ResourceCycles = [9]; }
+                                                      let ReleaseAtCycles = [9]; }
 def CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
-                                                      let ResourceCycles = [19]; }
+                                                      let ReleaseAtCycles = [19]; }
 }
 //===----------------------------------------------------------------------===//
 // Subtarget-specific SchedRead types.
 
 def : ReadAdvance<ReadVLD, 0>;
 def : ReadAdvance<ReadExtrHi, 1>;
 def : ReadAdvance<ReadAdrBase, 1>;
 def : ReadAdvance<ReadST, 1>;

llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td

 def A57Write_5cyc_1L  : SchedWriteRes<[A57UnitL]> { let Latency = 5;  }
 def A57Write_5cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 5;  }
 def A57Write_5cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 5;  }
 def A57Write_5cyc_1V_FP_Forward  : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
 def A57Write_5cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
 def A57Write_5cyc_1W_Mul_Forward  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
-                                                    let ResourceCycles = [17]; }
+                                                    let ReleaseAtCycles = [17]; }
 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
-                                                    let ResourceCycles = [19]; }
+                                                    let ReleaseAtCycles = [19]; }
 def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
 def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;  }
 def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
 def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;  }
 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
-                                                    let ResourceCycles = [32]; }
+                                                    let ReleaseAtCycles = [32]; }
 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
-                                                    let ResourceCycles = [35]; }
+                                                    let ReleaseAtCycles = [35]; }
 def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
 def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }
 def A57Write_3cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 3;  }
 def A57Write_3cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 3;  }
 def A57Write_4cyc_1L  : SchedWriteRes<[A57UnitL]> { let Latency = 4;  }
 def A57Write_4cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
 def A57Write_4cyc_1X_NonMul_Forward  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
 def A57Write_9cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
 def A57Write_6cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 6;  }
 def A57Write_6cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 6;  }
 
 
 //===----------------------------------------------------------------------===//
 // Define Generic 2 micro-op types
 
 def A57Write_64cyc_2W    : SchedWriteRes<[A57UnitW, A57UnitW]> {
   let Latency     = 64;
   let NumMicroOps = 2;
-  let ResourceCycles = [32, 32];
+  let ReleaseAtCycles = [32, 32];
 }
 def A57Write_6cyc_1I_1L  : SchedWriteRes<[A57UnitI,
                                           A57UnitL]> {
   let Latency     = 6;
   let NumMicroOps = 2;
 }
 def A57Write_7cyc_1V_1X  : SchedWriteRes<[A57UnitV,
                                           A57UnitX]> {

 }
 def A57Write_2cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
   let Latency     = 2;
   let NumMicroOps = 2;
 }
 def A57Write_34cyc_2W    : SchedWriteRes<[A57UnitW, A57UnitW]> {
   let Latency     = 34;
   let NumMicroOps = 2;
-  let ResourceCycles = [17, 17];
+  let ReleaseAtCycles = [17, 17];
 }
 def A57Write_3cyc_1I_1M  : SchedWriteRes<[A57UnitI,
                                           A57UnitM]> {
   let Latency     = 3;
   let NumMicroOps = 2;
 }
 def A57Write_3cyc_1I_1S  : SchedWriteRes<[A57UnitI,
                                           A57UnitS]> {

llvm/lib/Target/AArch64/AArch64SchedA64FX.td

 
 //---
 // 3.4 Divide and Multiply Instructions
 //---
 
 // Divide, W-form
 def : WriteRes<WriteID32,    [A64FXGI4]> {
   let Latency = 39;
-  let ResourceCycles = [39];
+  let ReleaseAtCycles = [39];
 }
 
 // Divide, X-form
 def : WriteRes<WriteID64,    [A64FXGI4]> {
   let Latency = 23;
-  let ResourceCycles = [23];
+  let ReleaseAtCycles = [23];
 }
 
 // Multiply accumulate, W-form
 def : WriteRes<WriteIM32,    [A64FXGI2456]> {
   let Latency = 5;
 }
 
 // Multiply accumulate, X-form

 // 3.8 FP Data Processing Instructions
 //---
 
 // FP absolute value
 // FP min/max
 // FP negate
 def : WriteRes<WriteF,       [A64FXGI03]> {
   let Latency = 4;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // FP arithmetic
 
 def : InstRW<[A64FXWrite_4Cyc_GI03], (instrs FADDDrr, FADDHrr)>;
 def : InstRW<[A64FXWrite_4Cyc_GI03], (instrs FSUBDrr, FSUBHrr)>;
 
 // FP compare
 def : WriteRes<WriteFCmp,    [A64FXGI03]> {
   let Latency = 4;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // FP Div, Sqrt
 def : WriteRes<WriteFDiv, [A64FXGI0]> {
   let Latency = 43;
 }
 
 def A64FXXWriteFDiv : SchedWriteRes<[A64FXGI0]> {

 // 3.9 FP Miscellaneous Instructions
 //---
 
 // FP convert, from vec to vec reg
 // FP convert, from gen to vec reg
 // FP convert, from vec to gen reg
 def : WriteRes<WriteFCvt, [A64FXGI03]> {
   let Latency = 9;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // FP move, immed
 // FP move, register
 def : WriteRes<WriteFImm, [A64FXGI0]> {
   let Latency = 4;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // FP transfer, from gen to vec reg
 // FP transfer, from vec to gen reg
 def : WriteRes<WriteFCopy, [A64FXGI0]> {
   let Latency = 4;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 def : InstRW<[A64FXWrite_FMOV_GV], (instrs FMOVXDHighr)>;
 def : InstRW<[A64FXWrite_FMOV_VG14], (instrs FMOVDXHighr)>;
 
 //---
 // 3.12 ASIMD Integer Instructions
 //---

 
 def A64FXWrite_None : SchedWriteRes<[]> {
 }
 def : InstRW<[A64FXWrite_None], (instregex "^SETFFR", "^MOVPRFX")>;
 
 def A64FXWrite_FMAIndexed : SchedWriteRes<[A64FXGI03]> {
   let Latency = 15;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[A64FXWrite_FMAIndexed], (instregex "^F(MLA|MLS|MUL)_ZZZI")>;
 
 def A64FXWrite_ADR_LSL_Z : SchedWriteRes<[A64FXGI0]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[A64FXWrite_ADR_LSL_Z], (instregex "^ADR_LSL_Z")>;
 
 def A64FXWrite_ASRD : SchedWriteRes<[A64FXGI0, A64FXGI01]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
 def : InstRW<[A64FXWrite_ASRD], (instregex "^ASRD_Z")>;
 
 def A64FXWrite_Reduction4CycB : SchedWriteRes<[A64FXGI03]> {
   let Latency = 46;
   let NumMicroOps = 10;
-  let ResourceCycles = [10];
+  let ReleaseAtCycles = [10];
 }
 def : InstRW<[A64FXWrite_Reduction4CycB],
       (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
 
 def A64FXWrite_Reduction4CycH : SchedWriteRes<[A64FXGI03]> {
   let Latency = 42;
   let NumMicroOps = 9;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 def : InstRW<[A64FXWrite_Reduction4CycH],
       (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
 
 def A64FXWrite_Reduction4CycS : SchedWriteRes<[A64FXGI03]> {
   let Latency = 38;
   let NumMicroOps = 8;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def : InstRW<[A64FXWrite_Reduction4CycS],
       (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
 
 def A64FXWrite_Reduction4CycD : SchedWriteRes<[A64FXGI03]> {
   let Latency = 34;
   let NumMicroOps = 7;
-  let ResourceCycles = [7];
+  let ReleaseAtCycles = [7];
 }
 def : InstRW<[A64FXWrite_Reduction4CycD],
       (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
 
 def A64FXWrite_CLAST_R : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 29;
 }
 def : InstRW<[A64FXWrite_CLAST_R], (instregex "^CLAST[AB]_R")>;

 
 def A64FXWrite_CPYScalar : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
   let Latency = 8;
 }
 def : InstRW<[A64FXWrite_CPYScalar], (instregex "^CPY_ZPmR")>;
 
 def A64FXWrite_CTERM : SchedWriteRes<[A64FXGI24]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[A64FXWrite_CTERM], (instregex "^CTERM")>;
 
 def A64FXWrite_INCPScalar : SchedWriteRes<[A64FXGI1, A64FXGI2, A64FXGI4]> {
   let Latency = 7;
   let NumMicroOps = 2;
 }
 def : InstRW<[A64FXWrite_INCPScalar], (instregex "^DECP_X", "^INCP_X")>;
 
 def A64FXWrite_INCPVector : SchedWriteRes<[A64FXGI0, A64FXGI1]> {
   let Latency = 12;
 }
 def : InstRW<[A64FXWrite_INCPVector], (instregex "^DECP_Z", "^INCP_Z")>;
 
 def A64FXWrite_FADDVH : SchedWriteRes<[A64FXGI03]> {
   let Latency = 75;
   let NumMicroOps = 11;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 def : InstRW<[A64FXWrite_FADDVH], (instrs FADDV_VPZ_H)>;
 
 def A64FXWrite_FADDVS : SchedWriteRes<[A64FXGI03]> {
   let Latency = 60;
   let NumMicroOps = 9;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 def : InstRW<[A64FXWrite_FADDVS], (instrs FADDV_VPZ_S)>;
 
 def A64FXWrite_FADDVD : SchedWriteRes<[A64FXGI03]> {
   let Latency = 45;
   let NumMicroOps = 7;
-  let ResourceCycles = [7];
+  let ReleaseAtCycles = [7];
 }
 def : InstRW<[A64FXWrite_FADDVD], (instrs FADDV_VPZ_D)>;
 
 def A64FXWrite_FADDAH : SchedWriteRes<[A64FXGI03]> {
   let Latency = 468;
   let NumMicroOps = 63;
-  let ResourceCycles = [63];
+  let ReleaseAtCycles = [63];
 }
 def : InstRW<[A64FXWrite_FADDAH], (instrs FADDA_VPZ_H)>;
 
 def A64FXWrite_FADDAS : SchedWriteRes<[A64FXGI03]> {
   let Latency = 228;
   let NumMicroOps = 31;
-  let ResourceCycles = [31];
+  let ReleaseAtCycles = [31];
 }
 def : InstRW<[A64FXWrite_FADDAS], (instrs FADDA_VPZ_S)>;
 
 def A64FXWrite_FADDAD : SchedWriteRes<[A64FXGI03]> {
   let Latency = 108;
   let NumMicroOps = 15;
-  let ResourceCycles = [15];
+  let ReleaseAtCycles = [15];
 }
 def : InstRW<[A64FXWrite_FADDAD], (instrs FADDA_VPZ_D)>;
 
 def A64FXWrite_FCADDZ : SchedWriteRes<[A64FXGI0, A64FXGI3]> {
   let Latency = 15;
   let NumMicroOps = 2;
 }
 def : InstRW<[A64FXWrite_FCADDZ], (instregex "^FCADD_Z")>;
 
 def A64FXWrite_FCMLAZ : SchedWriteRes<[A64FXGI03]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : InstRW<[A64FXWrite_FCMLAZ], (instregex "^FCMLA_Z")>;
 
 def A64FXWrite_FDIVH : SchedWriteRes<[A64FXGI0]> {
   let Latency = 134;
-  let ResourceCycles = [134];
+  let ReleaseAtCycles = [134];
 }
 def : InstRW<[A64FXWrite_FDIVH], (instregex "^F(DIVR?|SQRT)_Z.*_H")>;
 
 def A64FXWrite_FDIVS : SchedWriteRes<[A64FXGI0]> {
   let Latency = 98;
-  let ResourceCycles = [98];
+  let ReleaseAtCycles = [98];
 }
 def : InstRW<[A64FXWrite_FDIVS], (instregex "^F(DIVR?|SQRT)_Z.*_S")>;
 
 def A64FXWrite_FDIVD : SchedWriteRes<[A64FXGI0]> {
   let Latency = 154;
-  let ResourceCycles = [154];
+  let ReleaseAtCycles = [154];
 }
 def : InstRW<[A64FXWrite_FDIVD], (instregex "^F(DIVR?|SQRT)_Z.*_D")>;
 
 def A64FXWrite_FMAXVH : SchedWriteRes<[A64FXGI03]> {
   let Latency = 54;
   let NumMicroOps = 11;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 def : InstRW<[A64FXWrite_FMAXVH], (instregex "^F(MAX|MIN)(NM)?V_VPZ_H")>;
 
 def A64FXWrite_FMAXVS : SchedWriteRes<[A64FXGI03]> {
   let Latency = 44;
   let NumMicroOps = 9;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 def : InstRW<[A64FXWrite_FMAXVS], (instregex "^F(MAX|MIN)(NM)?V_VPZ_S")>;
 
 def A64FXWrite_FMAXVD : SchedWriteRes<[A64FXGI03]> {
   let Latency = 34;
   let NumMicroOps = 7;
-  let ResourceCycles = [7];
+  let ReleaseAtCycles = [7];
 }
 def : InstRW<[A64FXWrite_FMAXVH], (instregex "^F(MAX|MIN)(NM)?V_VPZ_D")>;
 
 def A64FXWrite_INDEX_RI_BH : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
   let Latency = 17;
   let NumMicroOps = 2;
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
 }
 def : InstRW<[A64FXWrite_INDEX_RI_BH], (instregex "^INDEX_(RI|IR)_[BH]")>;
 
 def A64FXWrite_INDEX_RI_SD : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
   let Latency = 13;
   let NumMicroOps = 1;
 }
 def : InstRW<[A64FXWrite_INDEX_RI_SD], (instregex "^INDEX_(RI|IR)_[SD]")>;
 
 def A64FXWrite_INDEX_II_BH : SchedWriteRes<[A64FXGI0]> {
   let Latency = 13;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[A64FXWrite_INDEX_II_BH], (instregex "^INDEX_II_[BH]")>;
 
 def A64FXWrite_INDEX_RR_BH : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI3]> {
   let Latency = 17;
   let NumMicroOps = 3;
-  let ResourceCycles = [2, 2, 1];
+  let ReleaseAtCycles = [2, 2, 1];
 }
 def : InstRW<[A64FXWrite_INDEX_RR_BH], (instregex "^INDEX_RR_[BH]")>;
 
 def A64FXWrite_INDEX_RR_SD : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
   let Latency = 17;
   let NumMicroOps = 2;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
 }
 def : InstRW<[A64FXWrite_INDEX_RR_SD], (instregex "^INDEX_RR_[SD]")>;
 
 def A64FXWrite_INSR_ZR : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
   let Latency = 10;
 }
 def : InstRW<[A64FXWrite_INSR_ZR], (instregex "^INSR_ZR")>;
 
 def A64FXWrite_LAST_R : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 25;
 }
 def : InstRW<[A64FXWrite_CLAST_R], (instregex "^LAST[AB]_R")>;
 
 def A64FXWrite_GLD_S_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
   let Latency = 19;
-  let ResourceCycles = [2, 4, 4];
+  let ReleaseAtCycles = [2, 4, 4];
 }
 def : InstRW<[A64FXWrite_GLD_S_ZI],
       (instregex "^GLD(FF)?1W_IMM", "^GLD(FF)?1S?[BHW]_S_IMM")>;
 
 def A64FXWrite_GLD_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
   let Latency = 16;
-  let ResourceCycles = [1, 2, 2];
+  let ReleaseAtCycles = [1, 2, 2];
 }
 def : InstRW<[A64FXWrite_GLD_D_ZI],
       (instregex "^GLD(FF)?1D_IMM", "^GLD(FF)?1S?[BHW]_D_IMM")>;
 
 def A64FXWrite_GLD_S_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
   let Latency = 23;
-  let ResourceCycles = [2, 1, 4, 4];
+  let ReleaseAtCycles = [2, 1, 4, 4];
 }
 def : InstRW<[A64FXWrite_GLD_S_RZ],
       (instregex "^GLD(FF)?1W_[^DI]", "^GLD(FF)?1S?[BHW]_S_[^I]")>;
 
 def A64FXWrite_GLD_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
   let Latency = 20;
-  let ResourceCycles = [1, 1, 2, 2];
+  let ReleaseAtCycles = [1, 1, 2, 2];
 }
 def : InstRW<[A64FXWrite_GLD_D_RZ],
       (instregex "^GLD(FF)?1D_[^I]", "^GLD(FF)?1D$", "^GLD(FF)?1S?[BHW]_D_[^I]",
                  "^GLD(FF)?1S?[BHW]_D$")>;
 
 def A64FXWrite_LD2_BH : SchedWriteRes<[A64FXGI56]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
 
 def A64FXWrite_LD2_WD_IMM : SchedWriteRes<[A64FXGI56]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[A64FXWrite_LD2_WD_IMM], (instregex "^LD2[WD]_IMM")>;
 
 def A64FXWrite_LD2_WD : SchedWriteRes<[A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : InstRW<[A64FXWrite_LD2_WD], (instregex "^LD2[WD]$")>;
 
 def A64FXWrite_LD3_BH : SchedWriteRes<[A64FXGI56]> {
   let Latency = 15;
   let NumMicroOps = 4;
-  let ResourceCycles = [13];
+  let ReleaseAtCycles = [13];
 }
 def : InstRW<[A64FXWrite_LD3_BH], (instregex "^LD3[BH]")>;
 
 def A64FXWrite_LD3_WD_IMM : SchedWriteRes<[A64FXGI56]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : InstRW<[A64FXWrite_LD3_WD_IMM], (instregex "^LD3[WD]_IMM")>;
 
 def A64FXWrite_LD3_WD : SchedWriteRes<[A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def : InstRW<[A64FXWrite_LD3_WD], (instregex "^LD3[WD]$")>;
 
 def A64FXWrite_LD4_BH : SchedWriteRes<[A64FXGI56]> {
   let Latency = 15;
   let NumMicroOps = 5;
-  let ResourceCycles = [17];
+  let ReleaseAtCycles = [17];
 }
 def : InstRW<[A64FXWrite_LD4_BH], (instregex "^LD4[BH]")>;
 
 def A64FXWrite_LD4_WD_IMM : SchedWriteRes<[A64FXGI56]> {
   let Latency = 11;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def : InstRW<[A64FXWrite_LD4_WD_IMM], (instregex "^LD4[WD]_IMM")>;
 
 def A64FXWrite_LD4_WD : SchedWriteRes<[A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 5;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
 }
 def : InstRW<[A64FXWrite_LD4_WD], (instregex "^LD4[WD]$")>;
 
 def A64FXWrite_PRF : SchedWriteRes<[A64FXGI56]> {
 }
 def : InstRW<[A64FXWrite_PRF], (instregex "^PRF._PR")>;
 
 def A64FXWrite_PRF_W_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI56]> {
-  let ResourceCycles = [2, 1, 4];
+  let ReleaseAtCycles = [2, 1, 4];
 }
 def : InstRW<[A64FXWrite_PRF_W_RZ], (instregex "^PRF._S_[^P]")>;
 
 def A64FXWrite_PRF_W_ZI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
-  let ResourceCycles = [2, 4];
+  let ReleaseAtCycles = [2, 4];
 }
 def : InstRW<[A64FXWrite_PRF_W_ZI], (instregex "^PRF._S_PZI")>;
 
 def A64FXWrite_PRF_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI56]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
 }
 def : InstRW<[A64FXWrite_PRF_D_RZ], (instregex "^PRF._D_[^P]")>;
 
 def A64FXWrite_PRF_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[A64FXWrite_PRF_D_ZI], (instregex "^PRF._D_PZI")>;
 
 def A64FXWrite_SDIV_S : SchedWriteRes<[A64FXGI0]> {
   let Latency = 114;
-  let ResourceCycles = [114];
+  let ReleaseAtCycles = [114];
 }
 def : InstRW<[A64FXWrite_SDIV_S], (instregex "^[SU]DIVR?.*_S")>;
 
 def A64FXWrite_SDIV_D : SchedWriteRes<[A64FXGI0]> {
   let Latency = 178;
-  let ResourceCycles = [178];
+  let ReleaseAtCycles = [178];
 }
 def : InstRW<[A64FXWrite_SDIV_D], (instregex "^[SU]DIVR?.*_D")>;
 
 def A64FXWrite_SDOT_I : SchedWriteRes<[A64FXGI0, A64FXGI3]> {
   let Latency = 15;
   let NumMicroOps = 2;
 }
 def : InstRW<[A64FXWrite_SDOT_I], (instregex "^[SU]DOT_ZZZI")>;
 
 def A64FXWrite_SQINC_Scalar : SchedWriteRes<[A64FXGI24]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[A64FXWrite_SQINC_Scalar], (instregex "^[SU]Q(INC|DEC)[BHWD]_[WX]")>;
 
 def A64FXWrite_SQINCP_X : SchedWriteRes<[A64FXGI24, A64FXGI3]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
 }
 def : InstRW<[A64FXWrite_SQINCP_X], (instregex "^[SU]Q(INC|DEC)P_[WX]")>;
 
 def A64FXWrite_SQINCP_Z : SchedWriteRes<[A64FXGI24, A64FXGI3]> {
   let Latency = 12;
 }
 def : InstRW<[A64FXWrite_SQINCP_Z], (instregex "^[SU]Q(INC|DEC)P_Z")>;
 
 def A64FXWrite_ST1 : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 11;
 }
 def : InstRW<[A64FXWrite_ST1], (instregex "^ST(NT)?1[BHWD]")>;
 
 def A64FXWrite_SST1_W_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
   let Latency = 20;
   let NumMicroOps = 8;
-  let ResourceCycles = [8, 8, 8, 8];
+  let ReleaseAtCycles = [8, 8, 8, 8];
 }
 def : InstRW<[A64FXWrite_SST1_W_RZ],
       (instregex "^SST1[BH]_S(_[^I]|$)", "^SST1W(_[^ID]|$)")>;
 
 def A64FXWrite_SST1_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
   let Latency = 20;
   let NumMicroOps = 4;
-  let ResourceCycles = [4, 4, 4, 4];
+  let ReleaseAtCycles = [4, 4, 4, 4];
 }
 def : InstRW<[A64FXWrite_SST1_D_RZ],
       (instregex "^SST1[BHW]_D(_[^I]|$)", "^SST1D(_[^I]|$)")>;
 
 def A64FXWrite_SST1_W_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
   let Latency = 16;
   let NumMicroOps = 8;
-  let ResourceCycles = [12, 8, 8];
+  let ReleaseAtCycles = [12, 8, 8];
 }
 def : InstRW<[A64FXWrite_SST1_W_ZI],
       (instregex "^SST1[BH]_S_I", "^SST1W_I")>;
 
 def A64FXWrite_SST1_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [4, 4, 4];
+  let ReleaseAtCycles = [4, 4, 4];
 }
 def : InstRW<[A64FXWrite_SST1_D_ZI],
       (instregex "^SST1[BHW]_D_I", "^SST1D_I")>;
 
 def A64FXWrite_ST2_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [8, 9];
+  let ReleaseAtCycles = [8, 9];
 }
 def : InstRW<[A64FXWrite_ST2_BH], (instregex "^ST2[BH]")>;
 
 def A64FXWrite_ST2_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
 }
 def : InstRW<[A64FXWrite_ST2_WD_RI], (instregex "^ST2[WD]$")>;
 
 def A64FXWrite_ST2_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [2, 3];
+  let ReleaseAtCycles = [2, 3];
 }
 def : InstRW<[A64FXWrite_ST2_WD_RR], (instregex "^ST2[WD]_I")>;
 
 def A64FXWrite_ST3_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 15;
   let NumMicroOps = 4;
-  let ResourceCycles = [12, 13];
+  let ReleaseAtCycles = [12, 13];
 }
 def : InstRW<[A64FXWrite_ST3_BH], (instregex "^ST3[BH]")>;
 
 def A64FXWrite_ST3_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3, 3];
+  let ReleaseAtCycles = [3, 3];
 }
 def : InstRW<[A64FXWrite_ST3_WD_RI], (instregex "^ST3[WD]$")>;
 
 def A64FXWrite_ST3_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 4;
-  let ResourceCycles = [3, 4];
+  let ReleaseAtCycles = [3, 4];
 }
 def : InstRW<[A64FXWrite_ST3_WD_RR], (instregex "^ST3[WD]_I")>;
 
 def A64FXWrite_ST4_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 15;
   let NumMicroOps = 5;
-  let ResourceCycles = [16, 17];
+  let ReleaseAtCycles = [16, 17];
 }
 def : InstRW<[A64FXWrite_ST4_BH], (instregex "^ST4[BH]")>;
 
 def A64FXWrite_ST4_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 11;
   let NumMicroOps = 4;
-  let ResourceCycles = [4, 4];
+  let ReleaseAtCycles = [4, 4];
 }
 def : InstRW<[A64FXWrite_ST4_WD_RI], (instregex "^ST4[WD]$")>;
 
 def A64FXWrite_ST4_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
   let Latency = 12;
   let NumMicroOps = 5;
-  let ResourceCycles = [4, 5];
+  let ReleaseAtCycles = [4, 5];
 }
 def : InstRW<[A64FXWrite_ST4_WD_RR], (instregex "^ST4[WD]_I")>;
 
 def A64FXWrite_STR_P : SchedWriteRes<[A64FXGI3, A64FXGI5]> {
   let Latency = 11;
 }
 def : InstRW<[A64FXWrite_STR_P], (instrs STR_PXI)>;
 

llvm/lib/Target/AArch64/AArch64SchedCyclone.td

 def : WriteRes<WriteI, [CyUnitI]>;
 
 // ADD with shifted register operand is a single micro-op that
 // consumes a shift pipeline for two cycles.
 // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
 // EXAMPLE: ADDrs Xn, Xm LSL #imm
 def : WriteRes<WriteISReg, [CyUnitIS]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // ADD with extended register operand is the same as shifted reg operand.
 // ADD(S)re,SUB(S)re
 // EXAMPLE: ADDXre Xn, Xm, UXTB #1
 def : WriteRes<WriteIEReg, [CyUnitIS]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // Variable shift and bitfield operations.
 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
 def : WriteRes<WriteIS, [CyUnitIS]>;
 
 // EXTR Shifts a pair of registers and requires two micro-ops.
 // The second micro-op is delayed, as modeled by ReadExtrHi.

 // 7.8.7. Divide
 //---
 
 // 32-bit divide takes 7-13 cycles. 10 cycles covers a 20-bit quotient.
 // The ID pipe is consumed for 2 cycles: issue and writeback.
 // SDIVW,UDIVW
 def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
   let Latency = 10;
-  let ResourceCycles = [2, 10];
+  let ReleaseAtCycles = [2, 10];
 }
 // 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient.
 // The ID pipe is consumed for 2 cycles: issue and writeback.
 // SDIVX,UDIVX
 def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> {
   let Latency = 13;
-  let ResourceCycles = [2, 13];
+  let ReleaseAtCycles = [2, 13];
 }
 
 //---
 // 7.8.8,7.8.10. Load/Store, single element
 //---
 
 // Integer loads take 4 cycles and use one LS unit for one cycle.
 def : WriteRes<WriteLD, [CyUnitLS]> {

 // 7.9.6 Divide and Square Root
 //---
 
 // FDIV,FSQRT
 // TODO: Add 64-bit variant with 19 cycle latency.
 // TODO: Specialize FSQRT for longer latency.
 def : WriteRes<WriteFDiv, [CyUnitVD, CyUnitFloatDiv]> {
   let Latency = 17;
-  let ResourceCycles = [2, 17];
+  let ReleaseAtCycles = [2, 17];
 }
 
 def : InstRW<[CyWriteV4], (instregex "FRECPEv","FRECPXv","URECPEv","URSQRTEv")>;
 
 def WriteFRSQRTE : SchedWriteRes<[CyUnitVM]> { let Latency = 4; }
 def : InstRW<[WriteFRSQRTE], (instregex "FRSQRTEv")>;
 
 def WriteFRECPS : SchedWriteRes<[CyUnitVM]> { let Latency = 8; }

llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

 
 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
                                     let NumMicroOps = 1; }
 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
                                     let NumMicroOps = 0; }
 
 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
-                                             let ResourceCycles = [2]; }
+                                             let ReleaseAtCycles = [2]; }
 def M3WriteAB : SchedWriteRes<[M3UnitALU,
                                M3UnitC]>   { let Latency = 1;
                                              let NumMicroOps = 2; }
 def M3WriteAC : SchedWriteRes<[M3UnitALU,
                                M3UnitALU,
                                M3UnitC]>   { let Latency = 2;
                                              let NumMicroOps = 3; }
 def M3WriteAD : SchedWriteRes<[M3UnitALU,

 def : SchedAlias<WriteIS,    M3WriteA1>;
 
 // Move instructions.
 def : SchedAlias<WriteImm, M3WriteA1>;
 
 // Divide and multiply instructions.
 def : WriteRes<WriteID32, [M3UnitC,
                            M3UnitD]>  { let Latency = 12;
-                                        let ResourceCycles = [1, 12]; }
+                                        let ReleaseAtCycles = [1, 12]; }
 def : WriteRes<WriteID64, [M3UnitC,
                            M3UnitD]>  { let Latency = 21;
-                                        let ResourceCycles = [1, 21]; }
+                                        let ReleaseAtCycles = [1, 21]; }
 def : WriteRes<WriteIM32, [M3UnitC]>  { let Latency = 3; }
 def : WriteRes<WriteIM64, [M3UnitC]>  { let Latency = 4;
-                                        let ResourceCycles = [2]; }
+                                        let ReleaseAtCycles = [2]; }
 
 // Miscellaneous instructions.
 def : SchedAlias<WriteExtr, M3WriteAY>;
 
 // Addressing modes.
 def : SchedAlias<WriteAdr,    M3WriteZ1>;
 def : SchedAlias<ReadAdrBase, M3ReadAdrBase>;
 
 // Load instructions.
 def : SchedAlias<WriteLD, M3WriteL4>;
 def : WriteRes<WriteLDHi, []> { let Latency = 4;
                                 let NumMicroOps = 0; }
 def : SchedAlias<WriteLDIdx, M3WriteLB>;
 
 // Store instructions.
 def : SchedAlias<WriteST,    M3WriteS1>;
 def : SchedAlias<WriteSTP,   M3WriteS1>;
 def : SchedAlias<WriteSTX,   M3WriteS1>;
 def : SchedAlias<WriteSTIdx, M3WriteSB>;
 
 // FP data instructions.
 def : WriteRes<WriteF,    [M3UnitFADD]>  { let Latency = 2; }
 def : WriteRes<WriteFCmp, [M3UnitNMSC]>  { let Latency = 2; }
 def : WriteRes<WriteFDiv, [M3UnitFDIV]>  { let Latency = 12;
-                                           let ResourceCycles = [12]; }
+                                           let ReleaseAtCycles = [12]; }
 def : WriteRes<WriteFMul, [M3UnitFMAC]>  { let Latency = 4; }
 
 // FP miscellaneous instructions.
 def : WriteRes<WriteFCvt,  [M3UnitFCVT]> { let Latency = 3; }
 def : WriteRes<WriteFImm,  [M3UnitNALU]> { let Latency = 1; }
 def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; }
 
 // FP load instructions.
def M3WriteNEONH   : SchedWriteRes<[M3UnitNALU,
                                     M3UnitS]>     { let Latency = 5;
                                                     let NumMicroOps = 2; }
 def M3WriteNEONI   : SchedWriteRes<[M3UnitNSHF,
                                     M3UnitS]>     { let Latency = 5;
                                                     let NumMicroOps = 2; }
 def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV0,
                                     M3UnitFDIV1]>  { let Latency = 7;
                                                      let NumMicroOps = 2;
-                                                     let ResourceCycles = [8, 8]; }
+                                                     let ReleaseAtCycles = [8, 8]; }
 def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV0,
                                     M3UnitFDIV1]>  { let Latency = 12;
                                                      let NumMicroOps = 2;
-                                                     let ResourceCycles = [13, 13]; }
+                                                     let ReleaseAtCycles = [13, 13]; }
 def M3WriteNEONX   : SchedWriteRes<[M3UnitFSQR,
                                     M3UnitFSQR]>  { let Latency = 18;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [19, 19]; }
+                                                    let ReleaseAtCycles = [19, 19]; }
 def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
                                     M3UnitFSQR]>  { let Latency = 25;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [26, 26]; }
+                                                    let ReleaseAtCycles = [26, 26]; }
 def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
                                     M3UnitNMSC]>  { let Latency = 5;
                                                     let NumMicroOps = 2; }
 def M3WriteFADD2   : SchedWriteRes<[M3UnitFADD]>  { let Latency = 2; }
 def M3WriteFCVT2   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 2; }
 def M3WriteFCVT3   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 3; }
 def M3WriteFCVT3A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
 def M3WriteFCVT4A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
 def M3WriteFCVT4   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 4; }
 def M3WriteFDIV10  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 7;
-                                                    let ResourceCycles = [8]; }
+                                                    let ReleaseAtCycles = [8]; }
 def M3WriteFDIV12  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 12;
-                                                    let ResourceCycles = [13]; }
+                                                    let ReleaseAtCycles = [13]; }
 def M3WriteFMAC3   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 3; }
 def M3WriteFMAC4   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 4; }
 def M3WriteFMAC5   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 5; }
 def M3WriteFSQR17  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 18;
-                                                    let ResourceCycles = [19]; }
+                                                    let ReleaseAtCycles = [19]; }
 def M3WriteFSQR25  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 25;
-                                                    let ResourceCycles = [26]; }
+                                                    let ReleaseAtCycles = [26]; }
 def M3WriteNALU1   : SchedWriteRes<[M3UnitNALU]>  { let Latency = 1; }
 def M3WriteNCRY1A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
 def M3WriteNCRY3A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
 def M3WriteNCRY5A  : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 5; }
 def M3WriteNMSC1   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 1; }
 def M3WriteNMSC2   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 2; }
 def M3WriteNMSC3   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 3; }
 def M3WriteNMUL3   : SchedWriteRes<[M3UnitNMUL]>  { let Latency = 3; }

 def M3WriteVLDC    : SchedWriteRes<[M3UnitL,
                                     M3UnitL,
                                     M3UnitL,
                                     M3UnitL]>     { let Latency = 6;
                                                     let NumMicroOps = 4; }
 def M3WriteVLDD    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU]>  { let Latency = 7;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [2, 1]; }
+                                                    let ReleaseAtCycles = [2, 1]; }
 def M3WriteVLDE    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU]>  { let Latency = 6;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [2, 1]; }
+                                                    let ReleaseAtCycles = [2, 1]; }
 def M3WriteVLDF    : SchedWriteRes<[M3UnitL,
                                     M3UnitL]>     { let Latency = 10;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [5, 5]; }
+                                                    let ReleaseAtCycles = [5, 5]; }
 def M3WriteVLDG    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU]>  { let Latency = 7;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [2, 1, 1]; }
+                                                    let ReleaseAtCycles = [2, 1, 1]; }
 def M3WriteVLDH    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU]>  { let Latency = 6;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [2, 1, 1]; }
+                                                    let ReleaseAtCycles = [2, 1, 1]; }
 def M3WriteVLDI    : SchedWriteRes<[M3UnitL,
                                     M3UnitL,
                                     M3UnitL]>     { let Latency = 12;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [6, 6, 6]; }
+                                                    let ReleaseAtCycles = [6, 6, 6]; }
 def M3WriteVLDJ    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU,
                                     M3UnitNALU]>  { let Latency = 7;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [2, 1, 1, 1]; }
+                                                    let ReleaseAtCycles = [2, 1, 1, 1]; }
 def M3WriteVLDK    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU,
                                     M3UnitNALU,
                                     M3UnitNALU]>  { let Latency = 9;
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [4, 1, 1, 1, 1]; }
+                                                    let ReleaseAtCycles = [4, 1, 1, 1, 1]; }
 def M3WriteVLDL    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU,
                                     M3UnitL,
                                     M3UnitNALU]>  { let Latency = 6;
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [6, 1, 1, 6, 1]; }
+                                                    let ReleaseAtCycles = [6, 1, 1, 6, 1]; }
 def M3WriteVLDM    : SchedWriteRes<[M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU,
                                     M3UnitL,
                                     M3UnitNALU,
                                     M3UnitNALU]>  { let Latency = 7;
                                                     let NumMicroOps = 6;
-                                                    let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
+                                                    let ReleaseAtCycles = [6, 1, 1, 6, 1, 1]; }
 def M3WriteVLDN    : SchedWriteRes<[M3UnitL,
                                     M3UnitL,
                                     M3UnitL,
                                     M3UnitL]>     { let Latency = 14;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [6, 6, 6, 6]; }
+                                                    let ReleaseAtCycles = [6, 6, 6, 6]; }
 def M3WriteVSTA    : WriteSequence<[WriteVST], 2>;
 def M3WriteVSTB    : WriteSequence<[WriteVST], 3>;
 def M3WriteVSTC    : WriteSequence<[WriteVST], 4>;
 def M3WriteVSTD    : SchedWriteRes<[M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST]>   { let Latency = 7;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [1, 3, 1, 3]; }
+                                                    let ReleaseAtCycles = [1, 3, 1, 3]; }
 def M3WriteVSTE    : SchedWriteRes<[M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST]>   { let Latency = 8;
                                                     let NumMicroOps = 6;
-                                                    let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
+                                                    let ReleaseAtCycles = [1, 3, 1, 3, 1, 3]; }
 def M3WriteVSTF    : SchedWriteRes<[M3UnitNALU,
                                     M3UnitFST,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST]>   { let Latency = 15;
                                                     let NumMicroOps = 7;
-                                                    let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
+                                                    let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3]; }
 def M3WriteVSTG    : SchedWriteRes<[M3UnitNALU,
                                     M3UnitFST,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST]>   { let Latency = 16;
                                                     let NumMicroOps = 9;
-                                                    let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
+                                                    let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 def M3WriteVSTH    : SchedWriteRes<[M3UnitNALU,
                                     M3UnitFST,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST]>   { let Latency = 14;
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [1, 3, 3, 1, 3]; }
+                                                    let ReleaseAtCycles = [1, 3, 3, 1, 3]; }
 def M3WriteVSTI    : SchedWriteRes<[M3UnitNALU,
                                     M3UnitFST,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST,
                                     M3UnitS,
                                     M3UnitFST]>   { let Latency = 17;
                                                     let NumMicroOps = 9;
-                                                    let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
+                                                    let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 
 // Special cases.
 def M3WriteAES     : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 1; }
 def M3WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>,
                                         SchedVar<NoSchedPred,  [M3WriteZ0]>]>;
 def M3WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>,
                                         SchedVar<NoSchedPred,       [M3WriteNALU1]>]>;
 

llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
                                     let NumMicroOps = 0; }
 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
                                     let NumMicroOps = 0; }
 
 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
-                                             let ResourceCycles = [2]; }
+                                             let ReleaseAtCycles = [2]; }
 def M4WriteAB : SchedWriteRes<[M4UnitALU,
                                M4UnitC]>   { let Latency = 2;
                                              let NumMicroOps = 2; }
 def M4WriteAC : SchedWriteRes<[M4UnitALU,
                                M4UnitALU,
                                M4UnitC]>   { let Latency = 3;
                                              let NumMicroOps = 3; }
 def M4WriteAD : SchedWriteRes<[M4UnitALU,

 
 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
                                    SchedVar<NoSchedPred,            [M4WriteAB]>]>;
 
 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
-                                           let ResourceCycles = [2]; }
+                                           let ReleaseAtCycles = [2]; }
 
 def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
-                                            let ResourceCycles = [12]; }
+                                            let ReleaseAtCycles = [12]; }
 def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
-                                            let ResourceCycles = [21]; }
+                                            let ReleaseAtCycles = [21]; }
 
 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
 
 def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; }
 def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; }
 def M4WriteLA : SchedWriteRes<[M4UnitL,
                                M4UnitL]> { let Latency = 5;
                                            let NumMicroOps = 1; }

 def M4WriteNEONQ   : SchedWriteRes<[M4UnitNMSC,
                                     M4UnitC]>     { let Latency = 3;
                                                     let NumMicroOps = 1; }
 def M4WriteNEONR   : SchedWriteRes<[M4UnitFCVT0,
                                     M4UnitS0]>    { let Latency = 4;
                                                     let NumMicroOps = 1; }
 def M4WriteNEONV   : SchedWriteRes<[M4UnitFDIV,
                                     M4UnitFDIV]>  { let Latency = 7;
-                                                    let ResourceCycles = [6, 6]; }
+                                                    let ReleaseAtCycles = [6, 6]; }
 def M4WriteNEONVH  : SchedWriteRes<[M4UnitFDIVH,
                                     M4UnitFDIVH]> { let Latency = 7;
-                                                    let ResourceCycles = [6, 6]; }
+                                                    let ReleaseAtCycles = [6, 6]; }
 def M4WriteNEONW   : SchedWriteRes<[M4UnitFDIV,
                                     M4UnitFDIV]>  { let Latency = 12;
-                                                    let ResourceCycles = [9, 9]; }
+                                                    let ReleaseAtCycles = [9, 9]; }
 def M4WriteNEONX   : SchedWriteRes<[M4UnitFSQR,
                                     M4UnitFSQR]>  { let Latency = 8;
-                                                    let ResourceCycles = [7, 7]; }
+                                                    let ReleaseAtCycles = [7, 7]; }
 def M4WriteNEONXH  : SchedWriteRes<[M4UnitFSQRH,
                                     M4UnitFSQRH]> { let Latency = 7;
-                                                    let ResourceCycles = [6, 6]; }
+                                                    let ReleaseAtCycles = [6, 6]; }
 def M4WriteNEONY   : SchedWriteRes<[M4UnitFSQR,
                                     M4UnitFSQR]>  { let Latency = 12;
-                                                    let ResourceCycles = [9, 9]; }
+                                                    let ReleaseAtCycles = [9, 9]; }
 def M4WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
                                         SchedVar<NoSchedPred,     [M4WriteNEONN]>]>;
 
 def M4WriteFADD2   : SchedWriteRes<[M4UnitFADD]>  { let Latency = 2; }
 def M4WriteFADD2H  : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; }
 
 def M4WriteFCVT2   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 2; }
 def M4WriteFCVT2A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; }
 def M4WriteFCVT2H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; }
 def M4WriteFCVT3   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 3; }
 def M4WriteFCVT3A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; }
 def M4WriteFCVT3H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; }
 def M4WriteFCVT4   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 4; }
 def M4WriteFCVT4A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
 def M4WriteFCVT6A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
 
 def M4WriteFDIV7   : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 7;
-                                                    let ResourceCycles = [6]; }
+                                                    let ReleaseAtCycles = [6]; }
 def M4WriteFDIV7H  : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
-                                                    let ResourceCycles = [6]; }
+                                                    let ReleaseAtCycles = [6]; }
 def M4WriteFDIV12  : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 12;
-                                                    let ResourceCycles = [9]; }
+                                                    let ReleaseAtCycles = [9]; }
 
 def M4WriteFMAC2H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
 def M4WriteFMAC3H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
 def M4WriteFMAC3   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 3; }
 def M4WriteFMAC4   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 4; }
 def M4WriteFMAC4H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
 def M4WriteFMAC5   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 5; }
 
 def M4WriteFSQR7H  : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
-                                                    let ResourceCycles = [6]; }
+                                                    let ReleaseAtCycles = [6]; }
 def M4WriteFSQR8   : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 8;
-                                                    let ResourceCycles = [7]; }
+                                                    let ReleaseAtCycles = [7]; }
 def M4WriteFSQR12  : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 12;
-                                                    let ResourceCycles = [9]; }
+                                                    let ReleaseAtCycles = [9]; }
 
 def M4WriteNALU1   : SchedWriteRes<[M4UnitNALU]>  { let Latency = 1; }
 def M4WriteNALU1H  : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
 
 def M4WriteNCRY1   : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 1; }
 def M4WriteNCRY1A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; }
 def M4WriteNCRY3A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; }
 def M4WriteNCRY5A  : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 5; }
 
 def M4WriteNHAD1   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 1; }
 def M4WriteNHAD3   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 3; }
 
 def M4WriteNMSC1   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 1; }
 def M4WriteNMSC2   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 2; }
 def M4WriteNMSC3   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 3; }
 
 def M4WriteNMUL3   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 
 def M4WriteNSHF1   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1; }
 def M4WriteNSHF1H  : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
 def M4WriteNSHF3   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3; }
 def M4WriteNSHFA   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1;
-                                                    let ResourceCycles = [2]; }
+                                                    let ReleaseAtCycles = [2]; }
 def M4WriteNSHFB   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 2;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [2]; }
+                                                    let ReleaseAtCycles = [2]; }
 def M4WriteNSHFC   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [4]; }
+                                                    let ReleaseAtCycles = [4]; }
 def M4WriteNSHFD   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 4;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [4]; }
+                                                    let ReleaseAtCycles = [4]; }
 
 def M4WriteNSHT1   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 1; }
 def M4WriteNSHT2   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 2; }
 def M4WriteNSHT3   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 3; }
 def M4WriteNSHT4A  : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; }
 
 def M4WriteVLDA    : SchedWriteRes<[M4UnitL,
                                     M4UnitL]>     { let Latency = 5;
                                                     let NumMicroOps = 2; }
 def M4WriteVLDB    : SchedWriteRes<[M4UnitL,
                                     M4UnitL,
                                     M4UnitL]>     { let Latency = 6;
                                                     let NumMicroOps = 3; }
 def M4WriteVLDC    : SchedWriteRes<[M4UnitL,
                                     M4UnitL,
                                     M4UnitL,
                                     M4UnitL]>     { let Latency = 6;
                                                     let NumMicroOps = 4; }
 def M4WriteVLDD    : SchedWriteRes<[M4UnitL,
                                     M4UnitNSHF]>  { let Latency = 6;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [2, 1]; }
+                                                    let ReleaseAtCycles = [2, 1]; }
 def M4WriteVLDF    : SchedWriteRes<[M4UnitL,
                                     M4UnitL]>     { let Latency = 10;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [3, 3]; }
+                                                    let ReleaseAtCycles = [3, 3]; }
 def M4WriteVLDG    : SchedWriteRes<[M4UnitL,
                                     M4UnitNSHF,
                                     M4UnitNSHF]>  { let Latency = 6;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [2, 1, 1]; }
+                                                    let ReleaseAtCycles = [2, 1, 1]; }
 def M4WriteVLDI    : SchedWriteRes<[M4UnitL,
                                     M4UnitL,
                                     M4UnitL]>     { let Latency = 12;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [3, 3, 3]; }
+                                                    let ReleaseAtCycles = [3, 3, 3]; }
 def M4WriteVLDJ    : SchedWriteRes<[M4UnitL,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitNSHF]>  { let Latency = 7;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [3, 1, 1, 1]; }
+                                                    let ReleaseAtCycles = [3, 1, 1, 1]; }
 def M4WriteVLDK    : SchedWriteRes<[M4UnitL,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitNSHF]>  { let Latency = 7;
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [3, 1, 1, 1, 1]; }
+                                                    let ReleaseAtCycles = [3, 1, 1, 1, 1]; }
 def M4WriteVLDL    : SchedWriteRes<[M4UnitL,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitL,
                                     M4UnitNSHF]>  { let Latency = 7;
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [3, 1, 1, 6, 1]; }
+                                                    let ReleaseAtCycles = [3, 1, 1, 6, 1]; }
 def M4WriteVLDM    : SchedWriteRes<[M4UnitL,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitL,
                                     M4UnitNSHF,
                                     M4UnitNSHF]>  { let Latency = 7;
                                                     let NumMicroOps = 6;
-                                                    let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
+                                                    let ReleaseAtCycles = [3, 1, 1, 3, 1, 1]; }
 def M4WriteVLDN    : SchedWriteRes<[M4UnitL,
                                     M4UnitL,
                                     M4UnitL,
                                     M4UnitL]>     { let Latency = 14;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [3, 3, 3, 3]; }
+                                                    let ReleaseAtCycles = [3, 3, 3, 3]; }
 
 def M4WriteVST1    : SchedWriteRes<[M4UnitS,
                                     M4UnitFST]>  { let Latency = 1;
                                                    let NumMicroOps = 1; }
 def M4WriteVSTA    : WriteSequence<[WriteVST], 2>;
 def M4WriteVSTB    : WriteSequence<[WriteVST], 3>;
 def M4WriteVSTC    : WriteSequence<[WriteVST], 4>;
 def M4WriteVSTD    : SchedWriteRes<[M4UnitS,
                                     M4UnitFST]>   { let Latency = 2; }
 def M4WriteVSTE    : SchedWriteRes<[M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 2;
                                                     let NumMicroOps = 2; }
 def M4WriteVSTF    : SchedWriteRes<[M4UnitNSHF,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 4;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [1, 2, 1, 2, 1]; }
+                                                    let ReleaseAtCycles = [1, 2, 1, 2, 1]; }
 def M4WriteVSTG    : SchedWriteRes<[M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 5;
                                                     let NumMicroOps = 6;
-                                                    let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
+                                                    let ReleaseAtCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
 def M4WriteVSTI    : SchedWriteRes<[M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 8;
                                                     let NumMicroOps = 5;
-                                                    let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
+                                                    let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 def M4WriteVSTJ    : SchedWriteRes<[M4UnitA,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 1;
                                                     let NumMicroOps = 2; }
 def M4WriteVSTK    : SchedWriteRes<[M4UnitA,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 3;
                                                     let NumMicroOps = 2; }
 def M4WriteVSTL    : SchedWriteRes<[M4UnitNSHF,
                                     M4UnitNSHF,
                                     M4UnitS,
                                     M4UnitFST,
                                     M4UnitS,
                                     M4UnitFST]>   { let Latency = 4;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
+                                                    let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
 def M4WriteVSTY    : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>,
                                         SchedVar<NoSchedPred,         [WriteVST]>]>;
 
 // Special cases.
 def M4WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
                                         SchedVar<NoSchedPred,  [M4WriteZ0]>]>;
 def M4WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>,
                                         SchedVar<NoSchedPred,       [M4WriteNALU1]>]>;

llvm/lib/Target/AArch64/AArch64SchedExynosM5.td

 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
                                     let NumMicroOps = 0; }
 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
                                     let NumMicroOps = 0; }
 
 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
-                                             let ResourceCycles = [2]; }
+                                             let ReleaseAtCycles = [2]; }
 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
-                                             let ResourceCycles = [2]; }
+                                             let ReleaseAtCycles = [2]; }
 def M5WriteAB  : SchedWriteRes<[M5UnitAX,
                                 M5UnitC,
                                 M5UnitE]>  { let Latency = 2;
                                              let NumMicroOps = 2; }
 def M5WriteAC  : SchedWriteRes<[M5UnitAX,
                                 M5UnitAX,
                                 M5UnitC]>  { let Latency = 3;
                                              let NumMicroOps = 3; }

 
 def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
 def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
                                    SchedVar<NoSchedPred,            [M5WriteAB]>]>;
 
 def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
 def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
-                                           let ResourceCycles = [2]; }
+                                           let ReleaseAtCycles = [2]; }
 
 def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
-                                            let ResourceCycles = [10]; }
+                                            let ReleaseAtCycles = [10]; }
 def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
-                                            let ResourceCycles = [16]; }
+                                            let ReleaseAtCycles = [16]; }
 
 def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
 
 def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; }
 def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; }
 def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; }
 def M5WriteLA : SchedWriteRes<[M5UnitL,
                                M5UnitL]> { let Latency = 6;
def M5WriteLE : SchedWriteRes<[M5UnitAX,
                                M5UnitL]> { let Latency = 7;
                                            let NumMicroOps = 2; }
 def M5WriteLFW : SchedWriteRes<[M5UnitAW,
                                 M5UnitAW,
                                 M5UnitAW,
                                 M5UnitAW,
                                 M5UnitL]>  { let Latency = 15;
                                              let NumMicroOps = 6;
-                                             let ResourceCycles = [1, 1, 1, 1, 15]; }
+                                             let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
 def M5WriteLFX : SchedWriteRes<[M5UnitAX,
                                 M5UnitAX,
                                 M5UnitAX,
                                 M5UnitAX,
                                 M5UnitL]>  { let Latency = 15;
                                              let NumMicroOps = 6;
-                                             let ResourceCycles = [1, 1, 1, 1, 15]; }
+                                             let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
 def M5WriteLGW : SchedWriteRes<[M5UnitAW,
                                 M5UnitL]>  { let Latency = 13;
                                              let NumMicroOps = 1;
-                                             let ResourceCycles = [1, 13]; }
+                                             let ReleaseAtCycles = [1, 13]; }
 def M5WriteLGX : SchedWriteRes<[M5UnitAX,
                                 M5UnitL]>  { let Latency = 13;
                                              let NumMicroOps = 1;
-                                             let ResourceCycles = [1, 13]; }
+                                             let ReleaseAtCycles = [1, 13]; }
 def M5WriteLH : SchedWriteRes<[]>        { let Latency = 6;
                                            let NumMicroOps = 0; }
 def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
                                    SchedVar<NoSchedPred,         [M5WriteL4]>]>;
 def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>,
                                    SchedVar<NoSchedPred,         [M5WriteL6]>]>;
 
 def M5WriteS1  : SchedWriteRes<[M5UnitS]>  { let Latency = 1; }
def M5WriteNEONI   : SchedWriteRes<[M5UnitS0,
                                                     let NumMicroOps = 2; }
 def M5WriteNEONK   : SchedWriteRes<[M5UnitNSHF,
                                     M5UnitFCVT0,
                                     M5UnitS0]>    { let Latency = 5;
                                                     let NumMicroOps = 2; }
 def M5WriteNEONN   : SchedWriteRes<[M5UnitNMSC,
                                     M5UnitNMSC]>  { let Latency = 5;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [7, 7]; }
+                                                    let ReleaseAtCycles = [7, 7]; }
 def M5WriteNEONO   : SchedWriteRes<[M5UnitNMSC,
                                     M5UnitNMSC,
                                     M5UnitNMSC]>  { let Latency = 8;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [10, 10, 10]; }
+                                                    let ReleaseAtCycles = [10, 10, 10]; }
 def M5WriteNEONP   : SchedWriteRes<[M5UnitNSHF,
                                     M5UnitS0,
                                     M5UnitFCVT]>  { let Latency = 7;
                                                     let NumMicroOps = 2; }
 def M5WriteNEONQ   : SchedWriteRes<[M5UnitNMSC,
                                     M5UnitC]>     { let Latency = 3;
                                                     let NumMicroOps = 1; }
 def M5WriteNEONU   : SchedWriteRes<[M5UnitFSQR,
                                     M5UnitFSQR]>  { let Latency = 7;
-                                                    let ResourceCycles = [4, 4]; }
+                                                    let ReleaseAtCycles = [4, 4]; }
 def M5WriteNEONV   : SchedWriteRes<[M5UnitFDIV,
                                     M5UnitFDIV]>  { let Latency = 7;
-                                                    let ResourceCycles = [6, 6]; }
+                                                    let ReleaseAtCycles = [6, 6]; }
 def M5WriteNEONW   : SchedWriteRes<[M5UnitFDIV,
                                     M5UnitFDIV]>  { let Latency = 12;
-                                                    let ResourceCycles = [9, 9]; }
+                                                    let ReleaseAtCycles = [9, 9]; }
 def M5WriteNEONX   : SchedWriteRes<[M5UnitFSQR,
                                     M5UnitFSQR]>  { let Latency = 8;
-                                                    let ResourceCycles = [5, 5]; }
+                                                    let ReleaseAtCycles = [5, 5]; }
 def M5WriteNEONY   : SchedWriteRes<[M5UnitFSQR,
                                     M5UnitFSQR]>  { let Latency = 12;
-                                                    let ResourceCycles = [9, 9]; }
+                                                    let ReleaseAtCycles = [9, 9]; }
 def M5WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
                                         SchedVar<NoSchedPred,     [M5WriteNEONN]>]>;
 
 def M5WriteFADD2   : SchedWriteRes<[M5UnitFADD]>  { let Latency = 2; }
 
 def M5WriteFCVT2   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 2; }
 def M5WriteFCVT2A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; }
 def M5WriteFCVT3   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 3; }
 def M5WriteFCVT3A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; }
 def M5WriteFCVTA   : SchedWriteRes<[M5UnitFCVT0,
                                     M5UnitS0]>    { let Latency = 3;
                                                     let NumMicroOps = 1; }
 def M5WriteFCVTB   : SchedWriteRes<[M5UnitFCVT,
                                     M5UnitS0]>    { let Latency = 4;
                                                     let NumMicroOps = 1; }
 def M5WriteFCVTC   : SchedWriteRes<[M5UnitFCVT,
                                     M5UnitS0]>    { let Latency = 6;
                                                     let NumMicroOps = 1; }
 
 def M5WriteFDIV5   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 5;
-                                                    let ResourceCycles = [2]; }
+                                                    let ReleaseAtCycles = [2]; }
 def M5WriteFDIV7   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 7;
-                                                    let ResourceCycles = [4]; }
+                                                    let ReleaseAtCycles = [4]; }
 def M5WriteFDIV12  : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 12;
-                                                    let ResourceCycles = [9]; }
+                                                    let ReleaseAtCycles = [9]; }
 
 def M5WriteFMAC3   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 3; }
 def M5WriteFMAC4   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 4; }
 def M5WriteFMAC5   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 5; }
 
 def M5WriteFSQR5   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 5;
-                                                    let ResourceCycles = [2]; }
+                                                    let ReleaseAtCycles = [2]; }
 def M5WriteFSQR7   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 7;
-                                                    let ResourceCycles = [4]; }
+                                                    let ReleaseAtCycles = [4]; }
 def M5WriteFSQR8   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 8;
-                                                    let ResourceCycles = [5]; }
+                                                    let ReleaseAtCycles = [5]; }
 def M5WriteFSQR12  : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 12;
-                                                    let ResourceCycles = [9]; }
+                                                    let ReleaseAtCycles = [9]; }
 
 def M5WriteNALU1   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 1; }
 def M5WriteNALU2   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 2; }
 
 def M5WriteNDOT2   : SchedWriteRes<[M5UnitNDOT]>  { let Latency = 2; }
 
 def M5WriteNCRY2   : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 2; }
 def M5WriteNCRY1A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; }

 def M5WriteVLDC    : SchedWriteRes<[M5UnitL,
                                     M5UnitL,
                                     M5UnitL,
                                     M5UnitL]>     { let Latency = 7;
                                                     let NumMicroOps = 4; }
 def M5WriteVLDD    : SchedWriteRes<[M5UnitL,
                                     M5UnitNSHF]>  { let Latency = 7;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [2, 1]; }
+                                                    let ReleaseAtCycles = [2, 1]; }
 def M5WriteVLDF    : SchedWriteRes<[M5UnitL,
                                     M5UnitL]>     { let Latency = 11;
                                                     let NumMicroOps = 2;
-                                                    let ResourceCycles = [6, 5]; }
+                                                    let ReleaseAtCycles = [6, 5]; }
 def M5WriteVLDG    : SchedWriteRes<[M5UnitL,
                                     M5UnitNSHF,
                                     M5UnitNSHF]>  { let Latency = 7;
                                                     let NumMicroOps = 3;
-                                                    let ResourceCycles = [2, 1, 1]; }
+                                                    let ReleaseAtCycles = [2, 1, 1]; }
 def M5WriteVLDI    : SchedWriteRes<[M5UnitL,
                                     M5UnitL,
                                     M5UnitL]>     { let Latency = 13;
                                                     let NumMicroOps = 3; }
 def M5WriteVLDJ    : SchedWriteRes<[M5UnitL,
                                     M5UnitNSHF,
                                     M5UnitNSHF,
                                     M5UnitNSHF]>  { let Latency = 8;
def M5WriteVLDM    : SchedWriteRes<[M5UnitL,
                                     M5UnitNSHF,
                                     M5UnitNSHF]>  { let Latency = 8;
                                                     let NumMicroOps = 6; }
 def M5WriteVLDN    : SchedWriteRes<[M5UnitL,
                                     M5UnitL,
                                     M5UnitL,
                                     M5UnitL]>     { let Latency = 15;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [2, 2, 2, 2]; }
+                                                    let ReleaseAtCycles = [2, 2, 2, 2]; }
 
 def M5WriteVST1    : SchedWriteRes<[M5UnitS,
                                     M5UnitFST]> { let Latency = 1;
                                                   let NumMicroOps = 1; }
 def M5WriteVSTA    : SchedWriteRes<[M5UnitS,
                                     M5UnitFST,
                                     M5UnitS,
                                     M5UnitFST]> { let Latency = 2;
def M5WriteVSTI    : SchedWriteRes<[M5UnitNSHF,
                                     M5UnitFST,
                                     M5UnitS,
                                     M5UnitFST,
                                     M5UnitS,
                                     M5UnitFST,
                                     M5UnitS,
                                     M5UnitFST]> { let Latency = 8;
                                                   let NumMicroOps = 5;
-                                                  let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
+                                                  let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 def M5WriteVSTJ    : SchedWriteRes<[M5UnitA,
                                     M5UnitS0,
                                     M5UnitFST]> { let Latency = 1;
                                                   let NumMicroOps = 1; }
 def M5WriteVSTK    : SchedWriteRes<[M5UnitAX,
                                     M5UnitS,
                                     M5UnitFST]> { let Latency = 3;
                                                   let NumMicroOps = 2; }
 def M5WriteVSTL    : SchedWriteRes<[M5UnitNSHF,
                                     M5UnitNSHF,
                                     M5UnitS,
                                     M5UnitFST,
                                     M5UnitS,
                                     M5UnitFST]> { let Latency = 4;
                                                     let NumMicroOps = 4;
-                                                    let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
+                                                    let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
 def M5WriteVSTY   : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
                                        SchedVar<NoSchedPred,         [WriteVST]>]>;
 
 // Special cases.
 def M5WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>,
                                         SchedVar<NoSchedPred,  [M5WriteZ0]>]>;
 def M5WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>,
                                         SchedVar<NoSchedPred,       [M5WriteNALU1]>]>;

llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td

 def FalkorWr_1Z_1XY_0cyc : SchedWriteRes<[FalkorUnitZ, FalkorUnitXY]> {
   let Latency = 0;
   let NumMicroOps = 2;
 }
 
 def FalkorWr_1X_1Z_8cyc  : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [2, 8];
+  let ReleaseAtCycles = [2, 8];
 }
 
 def FalkorWr_1X_1Z_11cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [2, 11];
+  let ReleaseAtCycles = [2, 11];
 }
 
 def FalkorWr_1LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitZ]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
 
 def FalkorWr_1LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD]> {

llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td

 //===----------------------------------------------------------------------===//
 // Define generic 1 micro-op types
 
 def N1Write_1c_1B     : SchedWriteRes<[N1UnitB]>  { let Latency = 1; }
 def N1Write_1c_1I     : SchedWriteRes<[N1UnitI]>  { let Latency = 1; }
 def N1Write_2c_1M     : SchedWriteRes<[N1UnitM]>  { let Latency = 2; }
 def N1Write_3c_1M     : SchedWriteRes<[N1UnitM]>  { let Latency = 3; }
 def N1Write_4c3_1M    : SchedWriteRes<[N1UnitM]>  { let Latency = 4;
-                                                    let ResourceCycles = [3]; }
+                                                    let ReleaseAtCycles = [3]; }
 def N1Write_5c3_1M    : SchedWriteRes<[N1UnitM]>  { let Latency = 5;
-                                                    let ResourceCycles = [3]; }
+                                                    let ReleaseAtCycles = [3]; }
 def N1Write_12c5_1M   : SchedWriteRes<[N1UnitM]>  { let Latency = 12;
-                                                    let ResourceCycles = [5]; }
+                                                    let ReleaseAtCycles = [5]; }
 def N1Write_20c5_1M   : SchedWriteRes<[N1UnitM]>  { let Latency = 20;
-                                                    let ResourceCycles = [5]; }
+                                                    let ReleaseAtCycles = [5]; }
 def N1Write_4c_1L     : SchedWriteRes<[N1UnitL]>  { let Latency = 4; }
 def N1Write_5c_1L     : SchedWriteRes<[N1UnitL]>  { let Latency = 5; }
 def N1Write_7c_1L     : SchedWriteRes<[N1UnitL]>  { let Latency = 7; }
 def N1Write_2c_1V     : SchedWriteRes<[N1UnitV]>  { let Latency = 2; }
 def N1Write_3c_1V     : SchedWriteRes<[N1UnitV]>  { let Latency = 3; }
 def N1Write_4c_1V     : SchedWriteRes<[N1UnitV]>  { let Latency = 4; }
 def N1Write_5c_1V     : SchedWriteRes<[N1UnitV]>  { let Latency = 5; }
 def N1Write_2c_1V0    : SchedWriteRes<[N1UnitV0]> { let Latency = 2; }
 def N1Write_3c_1V0    : SchedWriteRes<[N1UnitV0]> { let Latency = 3; }
 def N1Write_4c_1V0    : SchedWriteRes<[N1UnitV0]> { let Latency = 4; }
 def N1Write_7c7_1V0   : SchedWriteRes<[N1UnitV0]> { let Latency = 7;
-                                                    let ResourceCycles = [7]; }
+                                                    let ReleaseAtCycles = [7]; }
 def N1Write_10c7_1V0  : SchedWriteRes<[N1UnitV0]> { let Latency = 10;
-                                                    let ResourceCycles = [7]; }
+                                                    let ReleaseAtCycles = [7]; }
 def N1Write_13c10_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 13;
-                                                    let ResourceCycles = [10]; }
+                                                    let ReleaseAtCycles = [10]; }
 def N1Write_15c7_1V0  : SchedWriteRes<[N1UnitV0]> { let Latency = 15;
-                                                    let ResourceCycles = [7]; }
+                                                    let ReleaseAtCycles = [7]; }
 def N1Write_17c7_1V0  : SchedWriteRes<[N1UnitV0]> { let Latency = 17;
-                                                    let ResourceCycles = [7]; }
+                                                    let ReleaseAtCycles = [7]; }
 def N1Write_2c_1V1    : SchedWriteRes<[N1UnitV1]> { let Latency = 2; }
 def N1Write_3c_1V1    : SchedWriteRes<[N1UnitV1]> { let Latency = 3; }
 def N1Write_4c_1V1    : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }
 
 //===----------------------------------------------------------------------===//
 // Define generic 2 micro-op types
 
 let Latency = 1, NumMicroOps = 2 in

llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

 def N2Write_1cyc_1B   : SchedWriteRes<[N2UnitB]>   { let Latency = 1; }
 def N2Write_1cyc_1I   : SchedWriteRes<[N2UnitI]>   { let Latency = 1; }
 def N2Write_1cyc_1M   : SchedWriteRes<[N2UnitM]>   { let Latency = 1; }
 def N2Write_1cyc_1M0  : SchedWriteRes<[N2UnitM0]>  { let Latency = 1; }
 def N2Write_1cyc_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 1; }
 def N2Write_2cyc_1M   : SchedWriteRes<[N2UnitM]>   { let Latency = 2; }
 def N2Write_3cyc_1M   : SchedWriteRes<[N2UnitM]>   { let Latency = 3; }
 def N2Write_2cyc_1M0  : SchedWriteRes<[N2UnitM0]>  { let Latency = 2;
-                                                     let ResourceCycles = [2]; }
+                                                     let ReleaseAtCycles = [2]; }
 def N2Write_3cyc_1M0  : SchedWriteRes<[N2UnitM0]>  { let Latency = 3;
-                                                     let ResourceCycles = [3]; }
+                                                     let ReleaseAtCycles = [3]; }
 def N2Write_5cyc_1M0  : SchedWriteRes<[N2UnitM0]>  { let Latency = 5;
-                                                     let ResourceCycles = [5]; }
+                                                     let ReleaseAtCycles = [5]; }
 def N2Write_12cyc_1M0 : SchedWriteRes<[N2UnitM0]>  { let Latency = 12;
-                                                     let ResourceCycles = [12]; }
+                                                     let ReleaseAtCycles = [12]; }
 def N2Write_20cyc_1M0 : SchedWriteRes<[N2UnitM0]>  { let Latency = 20;
-                                                     let ResourceCycles = [20]; }
+                                                     let ReleaseAtCycles = [20]; }
 def N2Write_4cyc_1L   : SchedWriteRes<[N2UnitL]>   { let Latency = 4; }
 def N2Write_6cyc_1L   : SchedWriteRes<[N2UnitL]>   { let Latency = 6; }
 def N2Write_2cyc_1V   : SchedWriteRes<[N2UnitV]>   { let Latency = 2; }
 def N2Write_3cyc_1V   : SchedWriteRes<[N2UnitV]>   { let Latency = 3; }
 def N2Write_4cyc_1V   : SchedWriteRes<[N2UnitV]>   { let Latency = 4; }
 def N2Write_5cyc_1V   : SchedWriteRes<[N2UnitV]>   { let Latency = 5; }
 def N2Write_12cyc_1V  : SchedWriteRes<[N2UnitV]>   { let Latency = 12; }
 def N2Write_2cyc_1V0  : SchedWriteRes<[N2UnitV0]>  { let Latency = 2; }
 def N2Write_3cyc_1V0  : SchedWriteRes<[N2UnitV0]>  { let Latency = 3; }
 def N2Write_4cyc_1V0  : SchedWriteRes<[N2UnitV0]>  { let Latency = 4; }
 def N2Write_7cyc_1V0  : SchedWriteRes<[N2UnitV0]>  { let Latency = 7;
-                                                     let ResourceCycles = [7]; }
+                                                     let ReleaseAtCycles = [7]; }
 def N2Write_9cyc_1V0  : SchedWriteRes<[N2UnitV0]>  { let Latency = 9; }
 def N2Write_10cyc_1V0 : SchedWriteRes<[N2UnitV0]>  { let Latency = 10; }
 def N2Write_12cyc_1V0 : SchedWriteRes<[N2UnitV0]>  { let Latency = 12; }
 def N2Write_13cyc_1V0 : SchedWriteRes<[N2UnitV0]>  { let Latency = 13; }
 def N2Write_15cyc_1V0 : SchedWriteRes<[N2UnitV0]>  { let Latency = 15; }
 def N2Write_16cyc_1V0 : SchedWriteRes<[N2UnitV0]>  { let Latency = 16; }
 def N2Write_20cyc_1V0 : SchedWriteRes<[N2UnitV0]>  { let Latency = 20; }
 def N2Write_2cyc_1V1  : SchedWriteRes<[N2UnitV1]>  { let Latency = 2; }

 def N2Write_4cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
   let Latency     = 4;
   let NumMicroOps = 2;
 }
 
 def N2Write_10cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [5, 5];
+  let ReleaseAtCycles = [5, 5];
 }
 
 def N2Write_13cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
   let Latency = 13;
   let NumMicroOps = 2;
-  let ResourceCycles = [6, 7];
+  let ReleaseAtCycles = [6, 7];
 }
 
 def N2Write_15cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
   let Latency = 15;
   let NumMicroOps = 2;
-  let ResourceCycles = [7, 8];
+  let ReleaseAtCycles = [7, 8];
 }
 
 def N2Write_16cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
   let Latency = 16;
   let NumMicroOps = 2;
-  let ResourceCycles = [8, 8];
+  let ReleaseAtCycles = [8, 8];
 }
 
 def N2Write_4cyc_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {
   let Latency     = 4;
   let NumMicroOps = 2;
 }
 
 def N2Write_6cyc_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {

llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

 def V1Write_2c_1M      : SchedWriteRes<[V1UnitM]>   { let Latency = 2; }
 def V1Write_3c_1M      : SchedWriteRes<[V1UnitM]>   { let Latency = 3; }
 def V1Write_4c_1M      : SchedWriteRes<[V1UnitM]>   { let Latency = 4; }
 def V1Write_1c_1M0     : SchedWriteRes<[V1UnitM0]>  { let Latency = 1; }
 def V1Write_2c_1M0     : SchedWriteRes<[V1UnitM0]>  { let Latency = 2; }
 def V1Write_3c_1M0     : SchedWriteRes<[V1UnitM0]>  { let Latency = 3; }
 def V1Write_5c_1M0     : SchedWriteRes<[V1UnitM0]>  { let Latency = 5; }
 def V1Write_12c5_1M0   : SchedWriteRes<[V1UnitM0]>  { let Latency = 12;
-                                                      let ResourceCycles = [5]; }
+                                                      let ReleaseAtCycles = [5]; }
 def V1Write_20c5_1M0   : SchedWriteRes<[V1UnitM0]>  { let Latency = 20;
-                                                      let ResourceCycles = [5]; }
+                                                      let ReleaseAtCycles = [5]; }
 def V1Write_2c_1V      : SchedWriteRes<[V1UnitV]>   { let Latency = 2; }
 def V1Write_3c_1V      : SchedWriteRes<[V1UnitV]>   { let Latency = 3; }
 def V1Write_4c_1V      : SchedWriteRes<[V1UnitV]>   { let Latency = 4; }
 def V1Write_5c_1V      : SchedWriteRes<[V1UnitV]>   { let Latency = 5; }
 def V1Write_2c_1V0     : SchedWriteRes<[V1UnitV0]>  { let Latency = 2; }
 def V1Write_3c_1V0     : SchedWriteRes<[V1UnitV0]>  { let Latency = 3; }
 def V1Write_4c_1V0     : SchedWriteRes<[V1UnitV0]>  { let Latency = 4; }
 def V1Write_6c_1V0     : SchedWriteRes<[V1UnitV0]>  { let Latency = 6; }
 def V1Write_10c7_1V0   : SchedWriteRes<[V1UnitV0]>  { let Latency = 10;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_12c7_1V0   : SchedWriteRes<[V1UnitV0]>  { let Latency = 12;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_13c10_1V0  : SchedWriteRes<[V1UnitV0]>  { let Latency = 13;
-                                                      let ResourceCycles = [10]; }
+                                                      let ReleaseAtCycles = [10]; }
 def V1Write_15c7_1V0   : SchedWriteRes<[V1UnitV0]>  { let Latency = 15;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_16c7_1V0   : SchedWriteRes<[V1UnitV0]>  { let Latency = 16;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_20c7_1V0   : SchedWriteRes<[V1UnitV0]>  { let Latency = 20;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_2c_1V01    : SchedWriteRes<[V1UnitV01]> { let Latency = 2; }
 def V1Write_3c_1V01    : SchedWriteRes<[V1UnitV01]> { let Latency = 3; }
 def V1Write_4c_1V01    : SchedWriteRes<[V1UnitV01]> { let Latency = 4; }
 def V1Write_5c_1V01    : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }
 def V1Write_3c_1V02    : SchedWriteRes<[V1UnitV02]> { let Latency = 3; }
 def V1Write_4c_1V02    : SchedWriteRes<[V1UnitV02]> { let Latency = 4; }
 def V1Write_7c7_1V02   : SchedWriteRes<[V1UnitV02]> { let Latency = 7;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_10c7_1V02  : SchedWriteRes<[V1UnitV02]> { let Latency = 10;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_13c5_1V02  : SchedWriteRes<[V1UnitV02]> { let Latency = 13;
-                                                      let ResourceCycles = [5]; }
+                                                      let ReleaseAtCycles = [5]; }
 def V1Write_13c11_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;
-                                                      let ResourceCycles = [11]; }
+                                                      let ReleaseAtCycles = [11]; }
 def V1Write_15c7_1V02  : SchedWriteRes<[V1UnitV02]> { let Latency = 15;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_16c7_1V02  : SchedWriteRes<[V1UnitV02]> { let Latency = 16;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V1Write_2c_1V1     : SchedWriteRes<[V1UnitV1]>  { let Latency = 2; }
 def V1Write_3c_1V1     : SchedWriteRes<[V1UnitV1]>  { let Latency = 3; }
 def V1Write_4c_1V1     : SchedWriteRes<[V1UnitV1]>  { let Latency = 4; }
 def V1Write_2c_1V13    : SchedWriteRes<[V1UnitV13]> { let Latency = 2; }
 def V1Write_4c_1V13    : SchedWriteRes<[V1UnitV13]> { let Latency = 4; }
 
 //===----------------------------------------------------------------------===//
 // Define generic 2 micro-op types

llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

 def V2Write_1cyc_1M0   : SchedWriteRes<[V2UnitM0]>  { let Latency = 1; }
 def V2Write_1cyc_1L01  : SchedWriteRes<[V2UnitL01]> { let Latency = 1; }
 def V2Write_2cyc_1M    : SchedWriteRes<[V2UnitM]>   { let Latency = 2; }
 def V2Write_3cyc_1M    : SchedWriteRes<[V2UnitM]>   { let Latency = 3; }
 def V2Write_2cyc_1M0   : SchedWriteRes<[V2UnitM0]>  { let Latency = 2; }
 def V2Write_3cyc_1M0   : SchedWriteRes<[V2UnitM0]>  { let Latency = 3; }
 def V2Write_5cyc_1M0   : SchedWriteRes<[V2UnitM0]>  { let Latency = 5; }
 def V2Write_12cyc_1M0  : SchedWriteRes<[V2UnitM0]>  { let Latency = 12;
-                                                      let ResourceCycles = [12]; }
+                                                      let ReleaseAtCycles = [12]; }
 def V2Write_20cyc_1M0  : SchedWriteRes<[V2UnitM0]>  { let Latency = 20;
-                                                      let ResourceCycles = [20]; }
+                                                      let ReleaseAtCycles = [20]; }
 def V2Write_4cyc_1L    : SchedWriteRes<[V2UnitL]>   { let Latency = 4; }
 def V2Write_6cyc_1L    : SchedWriteRes<[V2UnitL]>   { let Latency = 6; }
 def V2Write_2cyc_1V    : SchedWriteRes<[V2UnitV]>   { let Latency = 2; }
 def V2Write_2cyc_1V0   : SchedWriteRes<[V2UnitV0]>  { let Latency = 2; }
 def V2Write_2cyc_1V01  : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }
 def V2Write_2cyc_1V23  : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }
 def V2Write_3cyc_1V    : SchedWriteRes<[V2UnitV]>   { let Latency = 3; }
 def V2Write_3cyc_1V01  : SchedWriteRes<[V2UnitV01]> { let Latency = 3;
-                                                      let ResourceCycles = [2]; }
+                                                      let ReleaseAtCycles = [2]; }
 def V2Write_3cyc_1V23  : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }
 def V2Write_4cyc_1V    : SchedWriteRes<[V2UnitV]>   { let Latency = 4; }
 def V2Write_5cyc_1V    : SchedWriteRes<[V2UnitV]>   { let Latency = 5; }
 def V2Write_6cyc_1V    : SchedWriteRes<[V2UnitV]>   { let Latency = 6; }
 def V2Write_12cyc_1V   : SchedWriteRes<[V2UnitV]>   { let Latency = 12; }
 def V2Write_3cyc_1V0   : SchedWriteRes<[V2UnitV0]>  { let Latency = 3; }
 def V2Write_3cyc_1V02  : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }
 def V2Write_4cyc_1V0   : SchedWriteRes<[V2UnitV0]>  { let Latency = 4; }
 def V2Write_4cyc_1V02  : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }
 def V2Write_7cyc_1V0   : SchedWriteRes<[V2UnitV0]>  { let Latency = 7;
-                                                      let ResourceCycles = [7]; }
+                                                      let ReleaseAtCycles = [7]; }
 def V2Write_7cyc_1V02  : SchedWriteRes<[V2UnitV02]> { let Latency = 7;
-                                                      let ResourceCycles = [2]; }
+                                                      let ReleaseAtCycles = [2]; }
 def V2Write_9cyc_1V0   : SchedWriteRes<[V2UnitV0]>  { let Latency = 9; }
 def V2Write_9cyc_1V02  : SchedWriteRes<[V2UnitV02]> { let Latency = 9;
-                                                      let ResourceCycles = [2]; }
+                                                      let ReleaseAtCycles = [2]; }
 def V2Write_10cyc_1V0  : SchedWriteRes<[V2UnitV0]>  { let Latency = 10; }
 def V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;
-                                                      let ResourceCycles = [2]; }
+                                                      let ReleaseAtCycles = [2]; }
 def V2Write_12cyc_1V0  : SchedWriteRes<[V2UnitV0]>  { let Latency = 12;
-                                                      let ResourceCycles = [11]; }
+                                                      let ReleaseAtCycles = [11]; }
 def V2Write_13cyc_1V0  : SchedWriteRes<[V2UnitV0]>  { let Latency = 13; }
 def V2Write_15cyc_1V0  : SchedWriteRes<[V2UnitV0]>  { let Latency = 15; }
 def V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;
-                                                      let ResourceCycles = [8]; }
+                                                      let ReleaseAtCycles = [8]; }
 def V2Write_16cyc_1V0  : SchedWriteRes<[V2UnitV0]>  { let Latency = 16; }
 def V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;
-                                                      let ResourceCycles = [8]; }
+                                                      let ReleaseAtCycles = [8]; }
 def V2Write_20cyc_1V0  : SchedWriteRes<[V2UnitV0]>  { let Latency = 20;
-                                                      let ResourceCycles = [20]; }
+                                                      let ReleaseAtCycles = [20]; }
 def V2Write_2cyc_1V1   : SchedWriteRes<[V2UnitV1]>  { let Latency = 2; }
 def V2Write_2cyc_1V13  : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }
 def V2Write_3cyc_1V1   : SchedWriteRes<[V2UnitV1]>  { let Latency = 3; }
 def V2Write_4cyc_1V1   : SchedWriteRes<[V2UnitV1]>  { let Latency = 4; }
 def V2Write_4cyc_1V13  : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }
 def V2Write_6cyc_1V1   : SchedWriteRes<[V2UnitV1]>  { let Latency = 6; }
 def V2Write_10cyc_1V1  : SchedWriteRes<[V2UnitV1]>  { let Latency = 10; }
 def V2Write_6cyc_1L01  : SchedWriteRes<[V2UnitL01]> { let Latency = 6; }

 def V2Wr_ZBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; }
 def V2Rd_ZBFMMA : SchedReadAdvance<2, [V2Wr_ZBFMMA]>;
 def V2Wr_ZBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; }
 def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>;
 
 //===----------------------------------------------------------------------===//
 // Define types with long resource cycles (rc)
 
-def V2Write_6cyc_1V1_5rc    : SchedWriteRes<[V2UnitV1]>  { let Latency =  6; let ResourceCycles = [ 5]; }
-def V2Write_7cyc_1V02_7rc   : SchedWriteRes<[V2UnitV02]> { let Latency =  7; let ResourceCycles = [ 7]; }
-def V2Write_10cyc_1V02_5rc  : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 5]; }
-def V2Write_10cyc_1V02_9rc  : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 9]; }
-def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [10]; }
-def V2Write_10cyc_1V0_9rc   : SchedWriteRes<[V2UnitV0]>  { let Latency = 10; let ResourceCycles = [ 9]; }
-def V2Write_10cyc_1V1_9rc   : SchedWriteRes<[V2UnitV1]>  { let Latency = 10; let ResourceCycles = [ 9]; }
-def V2Write_13cyc_1V0_12rc  : SchedWriteRes<[V2UnitV0]>  { let Latency = 13; let ResourceCycles = [12]; }
-def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [12]; }
-def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [13]; }
-def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ResourceCycles = [14]; }
-def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ResourceCycles = [15]; }
-def V2Write_16cyc_1V0_14rc  : SchedWriteRes<[V2UnitV0]>  { let Latency = 16; let ResourceCycles = [14]; }
+def V2Write_6cyc_1V1_5rc    : SchedWriteRes<[V2UnitV1]>  { let Latency =  6; let ReleaseAtCycles = [ 5]; }
+def V2Write_7cyc_1V02_7rc   : SchedWriteRes<[V2UnitV02]> { let Latency =  7; let ReleaseAtCycles = [ 7]; }
+def V2Write_10cyc_1V02_5rc  : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }
+def V2Write_10cyc_1V02_9rc  : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
+def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }
+def V2Write_10cyc_1V0_9rc   : SchedWriteRes<[V2UnitV0]>  { let Latency = 10; let ReleaseAtCycles = [ 9]; }
+def V2Write_10cyc_1V1_9rc   : SchedWriteRes<[V2UnitV1]>  { let Latency = 10; let ReleaseAtCycles = [ 9]; }
+def V2Write_13cyc_1V0_12rc  : SchedWriteRes<[V2UnitV0]>  { let Latency = 13; let ReleaseAtCycles = [12]; }
+def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }
+def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }
+def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }
+def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }
+def V2Write_16cyc_1V0_14rc  : SchedWriteRes<[V2UnitV0]>  { let Latency = 16; let ReleaseAtCycles = [14]; }
 
 // Miscellaneous
 // -----------------------------------------------------------------------------
 
 def : InstRW<[WriteI], (instrs COPY)>;
 
 // §3.3 Branch instructions
 // -----------------------------------------------------------------------------

llvm/lib/Target/AArch64/AArch64SchedTSV110.td

 def : WriteRes<WriteI,     [TSV110UnitALUAB]> { let Latency = 1; }
 def : WriteRes<WriteISReg, [TSV110UnitMDU]>   { let Latency = 2; } 
 def : WriteRes<WriteIEReg, [TSV110UnitMDU]>   { let Latency = 2; } 
 def : WriteRes<WriteExtr,  [TSV110UnitALUAB]> { let Latency = 1; }
 def : WriteRes<WriteIS,    [TSV110UnitALUAB]> { let Latency = 1; }
 
 // Integer Mul/MAC/Div
 def : WriteRes<WriteID32,  [TSV110UnitMDU]> { let Latency = 12;
-                                              let ResourceCycles = [12]; } 
+                                              let ReleaseAtCycles = [12]; } 
 def : WriteRes<WriteID64,  [TSV110UnitMDU]> { let Latency = 20;
-                                              let ResourceCycles = [20]; }
+                                              let ReleaseAtCycles = [20]; }
 def : WriteRes<WriteIM32,  [TSV110UnitMDU]> { let Latency = 3; }
 def : WriteRes<WriteIM64,  [TSV110UnitMDU]> { let Latency = 4; }
 
 // Load
 def : WriteRes<WriteLD,    [TSV110UnitLd]>  { let Latency = 4; }
 def : WriteRes<WriteLDIdx, [TSV110UnitLd]>  { let Latency = 4; }
 def : WriteRes<WriteLDHi,  []> { let Latency = 4; }
 

 def : WriteRes<WriteF,     [TSV110UnitF]> { let Latency = 2; }
 def : WriteRes<WriteFCmp,  [TSV110UnitF]> { let Latency = 3; }
 def : WriteRes<WriteFCvt,  [TSV110UnitF]> { let Latency = 3; } 
 def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
 def : WriteRes<WriteFImm,  [TSV110UnitF]> { let Latency = 2; } 
 def : WriteRes<WriteFMul,  [TSV110UnitF]> { let Latency = 5; }
 
 // FP Div, Sqrt
-def : WriteRes<WriteFDiv,  [TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
+def : WriteRes<WriteFDiv,  [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
 
 def : WriteRes<WriteVd,    [TSV110UnitF]>     { let Latency = 4; }
 def : WriteRes<WriteVq,    [TSV110UnitF]>     { let Latency = 4; }
 def : WriteRes<WriteVST,   [TSV110UnitF]>     { let Latency = 1; }
 
 // Branch
 def : WriteRes<WriteBr,    [TSV110UnitAB]> { let Latency = 1; }
 def : WriteRes<WriteBrReg, [TSV110UnitAB]> { let Latency = 1; }

 //===----------------------------------------------------------------------===//
 // Define Generic 1 micro-op types
 
 def TSV110Wr_1cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 1; }
 def TSV110Wr_1cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 1; }
 def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
 def TSV110Wr_1cyc_1LdSt  : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; }
 
-def TSV110Wr_2cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 2; let ResourceCycles = [2]; }
+def TSV110Wr_2cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 2; let ReleaseAtCycles = [2]; }
 def TSV110Wr_2cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 2; }
 def TSV110Wr_2cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 2; }
 def TSV110Wr_2cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 2; }
 def TSV110Wr_2cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 2; }
 
 def TSV110Wr_3cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 3; }
 def TSV110Wr_3cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 3; }
 def TSV110Wr_3cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 3; }

 def TSV110Wr_5cyc_1LdSt  : SchedWriteRes<[TSV110UnitLd]>    { let Latency = 5; }
 
 def TSV110Wr_6cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 6; }
 
 def TSV110Wr_7cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 7; }
 
 def TSV110Wr_8cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 8; }
 
-def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 11; let ResourceCycles = [11]; }
+def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 11; let ReleaseAtCycles = [11]; }
 
-def TSV110Wr_12cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 12; let ResourceCycles = [12]; }
+def TSV110Wr_12cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 12; let ReleaseAtCycles = [12]; }
 
-def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 17; let ResourceCycles = [17]; }
+def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 17; let ReleaseAtCycles = [17]; }
 
-def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 18; let ResourceCycles = [18]; }
+def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 18; let ReleaseAtCycles = [18]; }
 
-def TSV110Wr_20cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 20; let ResourceCycles = [20]; }
+def TSV110Wr_20cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 20; let ReleaseAtCycles = [20]; }
 
-def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 24; let ResourceCycles = [24]; }
+def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 24; let ReleaseAtCycles = [24]; }
 
-def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 31; let ResourceCycles = [31]; }
+def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 31; let ReleaseAtCycles = [31]; }
 
-def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 36; let ResourceCycles = [36]; }
+def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 36; let ReleaseAtCycles = [36]; }
 
-def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 38; let ResourceCycles = [38]; }
+def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 38; let ReleaseAtCycles = [38]; }
 
-def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 64; let ResourceCycles = [64]; }
+def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 64; let ReleaseAtCycles = [64]; }
 
 //===----------------------------------------------------------------------===//
 // Define Generic 2 micro-op types
 
 def TSV110Wr_1cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd0St,
                                                 TSV110UnitALUAB]> {
   let Latency = 1;
   let NumMicroOps = 2;

llvm/lib/Target/AArch64/AArch64SchedThunderX.td

 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
 
 // MAC
 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
   let Latency = 4;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
   let Latency = 4;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 // Div
 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
   let Latency = 12;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
 }
 
 def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
   let Latency = 14;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 
 // Load
 def : WriteRes<WriteLD, [THXT8XUnitLdSt]> { let Latency = 3; }
 def : WriteRes<WriteLDIdx, [THXT8XUnitLdSt]> { let Latency = 3; }
 def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; }
 
 // Vector Load
 def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
   let Latency = 8;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 
 def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 6;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 11;
-  let ResourceCycles = [7];
+  let ReleaseAtCycles = [7];
 }
 
 def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 12;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 
 def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 13;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 
 def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 13;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 
 // Pre/Post Indexing
 def : WriteRes<WriteAdr, []> { let Latency = 0; }
 
 // Store
 def : WriteRes<WriteST, [THXT8XUnitLdSt]> { let Latency = 1; }
 def : WriteRes<WriteSTP, [THXT8XUnitLdSt]> { let Latency = 1; }
 def : WriteRes<WriteSTIdx, [THXT8XUnitLdSt]> { let Latency = 1; }
 def : WriteRes<WriteSTX, [THXT8XUnitLdSt]> { let Latency = 1; }
 
 // Vector Store
 def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
 def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>;
 
 def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 10;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 
 def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> {
   let Latency = 11;
-  let ResourceCycles = [10];
+  let ReleaseAtCycles = [10];
 }
 
 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
 
 // Branch
 def : WriteRes<WriteBr, [THXT8XUnitBr]>;
 def THXT8XWriteBR : SchedWriteRes<[THXT8XUnitBr]>;
 def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;

 def : WriteRes<WriteFImm, [THXT8XUnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteVd, [THXT8XUnitFPALU]> { let Latency = 6; }
 def : WriteRes<WriteVq, [THXT8XUnitFPALU]> { let Latency = 6; }
 
 // FP Mul, Div, Sqrt
 def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; }
 def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> {
   let Latency = 22;
-  let ResourceCycles = [19];
+  let ReleaseAtCycles = [19];
 }
 
 def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; }
 
 def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
   let Latency = 12;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 
 def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
   let Latency = 22;
-  let ResourceCycles = [19];
+  let ReleaseAtCycles = [19];
 }
 
 def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
   let Latency = 17;
-  let ResourceCycles = [14];
+  let ReleaseAtCycles = [14];
 }
 
 def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
   let Latency = 31;
-  let ResourceCycles = [28];
+  let ReleaseAtCycles = [28];
 }
 
 //===----------------------------------------------------------------------===//
 // Subtarget-specific SchedRead types.
 
 // No forwarding for these reads.
 def : ReadAdvance<ReadExtrHi, 1>;
 def : ReadAdvance<ReadAdrBase, 2>;

llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td

 def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
   let Latency = 4;
   let NumMicroOps = 2;
 }
 
 // 23 cycles on I1.
 def THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
   let Latency = 23;
-  let ResourceCycles = [13, 23];
+  let ReleaseAtCycles = [13, 23];
   let NumMicroOps = 4;
 }
 
 // 39 cycles on I1.
 def THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
   let Latency = 39;
-  let ResourceCycles = [13, 39];
+  let ReleaseAtCycles = [13, 39];
   let NumMicroOps = 4;
 }
 
 // 1 cycle on I0, I1, or I2.
 def THX2T99Write_1Cyc_I012 : SchedWriteRes<[THX2T99I012]> {
   let Latency = 1;
   let NumMicroOps = 2;
 }
def THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
   let Latency = 10;
   let NumMicroOps = 3;
 }
 
 // 16 cycles on F0 or F1.
 def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
   let Latency = 16;
   let NumMicroOps = 3;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 
 // 23 cycles on F0 or F1.
 def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
   let Latency = 23;
   let NumMicroOps = 3;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 
 // 1 cycles on LS0 or LS1.
 def THX2T99Write_1Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> {
   let Latency = 0;
 }
 
 // 1 cycles on LS0 or LS1 and I0, I1, or I2.

 
 
 // ALU, basic
 // Conditional compare
 // Conditional select
 // Address generation
 def : WriteRes<WriteI,       [THX2T99I012]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[WriteI],
             (instregex "ADD?(W|X)r(i|r|s|x)",   "ADDS?(W|X)r(i|r|s|x)(64)?",
                        "AND?(W|X)r(i|r|s|x)",   "ANDS?(W|X)r(i|r|s|x)",
                        "ADC(W|X)r",
                        "BIC?(W|X)r(i|r|s|x)",   "BICS?(W|X)r(i|r|s|x)",
                        "EON?(W|X)r(i|r|s|x)",   "ORN?(W|X)r(i|r|s|x)",
                        "ORR?(W|X)r(i|r|s|x)",   "SUB?(W|X)r(i|r|s|x)",
                        "SUBS?(W|X)r(i|r|s|x)",  "SBC(W|X)r",
                        "SBCS(W|X)r",            "CCMN(W|X)(i|r)",
                        "CCMP(W|X)(i|r)",        "CSEL(W|X)r",
                        "CSINC(W|X)r",           "CSINV(W|X)r",
                        "CSNEG(W|X)r")>;
 
 def : InstRW<[WriteI], (instrs COPY)>;
 
 // ALU, extend and/or shift
 def : WriteRes<WriteISReg,   [THX2T99I012]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[WriteISReg],
             (instregex "ADD?(W|X)r(i|r|s|x)",   "ADDS?(W|X)r(i|r|s|x)(64)?",
                        "AND?(W|X)r(i|r|s|x)",   "ANDS?(W|X)r(i|r|s|x)",
                        "ADC(W|X)r",
                        "BIC?(W|X)r(i|r|s|x)",   "BICS?(W|X)r(i|r|s|x)",
                        "EON?(W|X)r(i|r|s|x)",   "ORN?(W|X)r(i|r|s|x)",
                        "ORR?(W|X)r(i|r|s|x)",   "SUB?(W|X)r(i|r|s|x)",
                        "SUBS?(W|X)r(i|r|s|x)",  "SBC(W|X)r",
                        "SBCS(W|X)r",            "CCMN(W|X)(i|r)",
                        "CCMP(W|X)(i|r)",        "CSEL(W|X)r",
                        "CSINC(W|X)r",           "CSINV(W|X)r",
                        "CSNEG(W|X)r")>;
 
 def : WriteRes<WriteIEReg,   [THX2T99I012]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[WriteIEReg],
             (instregex "ADD?(W|X)r(i|r|s|x)",   "ADDS?(W|X)r(i|r|s|x)(64)?",
                        "AND?(W|X)r(i|r|s|x)",   "ANDS?(W|X)r(i|r|s|x)",
                        "ADC(W|X)r",
                        "BIC?(W|X)r(i|r|s|x)",   "BICS?(W|X)r(i|r|s|x)",

 //---
 // 3.4 Divide and Multiply Instructions
 //---
 
 // Divide, W-form
 // Latency range of 13-23/13-39.
 def : WriteRes<WriteID32,    [THX2T99I1]> {
   let Latency = 39;
-  let ResourceCycles = [39];
+  let ReleaseAtCycles = [39];
   let NumMicroOps = 4;
 }
 
 // Divide, X-form
 def : WriteRes<WriteID64,    [THX2T99I1]> {
   let Latency = 23;
-  let ResourceCycles = [23];
+  let ReleaseAtCycles = [23];
   let NumMicroOps = 4;
 }
 
 // Multiply accumulate, W-form
 def : WriteRes<WriteIM32,    [THX2T99I012]> {
   let Latency = 5;
   let NumMicroOps = 3;
 }

 def : WriteRes<WriteFCmp,    [THX2T99F01]> {
   let Latency = 5;
   let NumMicroOps = 2;
 }
 
 // FP Mul, Div, Sqrt
 def : WriteRes<WriteFDiv, [THX2T99F01]> {
   let Latency = 22;
-  let ResourceCycles = [19];
+  let ReleaseAtCycles = [19];
 }
 
 def THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> {
   let Latency = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 
 def THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> {
   let Latency = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 
 def THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> {
   let Latency = 23;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 4;
 }
 
 def THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> {
   let Latency = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 
 def THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> {
   let Latency = 23;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 4;
 }
 
 // FP divide, S-form
 // FP square root, S-form
 def : InstRW<[THX2T99XWriteFDivSP], (instrs FDIVSrr)>;
 def : InstRW<[THX2T99XWriteFSqrtSP], (instrs FSQRTSr)>;
 def : InstRW<[THX2T99XWriteFDivSP], (instregex "^FDIVv.*32$")>;
 def : InstRW<[THX2T99XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
 def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>;
 
 // FP divide, D-form
 // FP square root, D-form
 def : InstRW<[THX2T99XWriteFDivDP], (instrs FDIVDrr)>;
 def : InstRW<[THX2T99XWriteFSqrtDP], (instrs FSQRTDr)>;
 def : InstRW<[THX2T99XWriteFDivDP], (instregex "^FDIVv.*64$")>;
 def : InstRW<[THX2T99XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
 def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
 
 // FP multiply
 // FP multiply accumulate
 def : WriteRes<WriteFMul, [THX2T99F01]> {
   let Latency = 6;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 3;
 }
 
 def THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> {
   let Latency = 6;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 3;
 }
 
 def THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> {
   let Latency = 6;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 3;
 }
 
 def : InstRW<[THX2T99XWriteFMul], (instregex "^FMUL", "^FNMUL")>;
 def : InstRW<[THX2T99XWriteFMulAcc],
             (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
 
 // FP round to integral

 // ASIMD shift by immed, complex
 // ASIMD shift by register, basic, D-form
 // ASIMD shift by register, basic, Q-form
 // ASIMD shift by register, complex, D-form
 // ASIMD shift by register, complex, Q-form
 def : WriteRes<WriteVd, [THX2T99F01]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def : WriteRes<WriteVq, [THX2T99F01]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 
 // ASIMD arith, reduce, 4H/4S
 // ASIMD arith, reduce, 8B/8H
 // ASIMD arith, reduce, 16B
 
 // ASIMD logical (MVN (alias for NOT), ORN, ORR)
 def : InstRW<[THX2T99Write_5Cyc_F01],

llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td

 def THX3T110Write_7Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 
 // 23 cycles on I1.
 def THX3T110Write_23Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
   let Latency = 23;
-  let ResourceCycles = [13, 23];
+  let ReleaseAtCycles = [13, 23];
   let NumMicroOps = 4;
 }
 
 // 39 cycles on I1.
 def THX3T110Write_39Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
   let Latency = 39;
-  let ResourceCycles = [13, 39];
+  let ReleaseAtCycles = [13, 39];
   let NumMicroOps = 4;
 }
 
 // 1 cycle on I2/I3
 def THX3T110Write_1Cyc_I23 : SchedWriteRes<[THX3T110I23]> {
   let Latency = 1;
   let NumMicroOps = 2;
 }
def THX3T110Write_10Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 10;
   let NumMicroOps = 3;
 }
 
 // 16 cycles on F0/F1/F2/F3.
 def THX3T110Write_16Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 16;
   let NumMicroOps = 3;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 
 // 23 cycles on F0/F1/F2/F3.
 def THX3T110Write_23Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 23;
   let NumMicroOps = 3;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 
 // 1 cycle on LS0/LS1.
 def THX3T110Write_1Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 1;
   let NumMicroOps = 1;
 }
 
 // 2 cycles on LS0/LS1.
 def THX3T110Write_2Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 
 // 4 cycles on LS0/LS1.
 def THX3T110Write_4Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // 5 cycles on LS0/LS1.
 def THX3T110Write_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 5;
   let NumMicroOps = 3;
 }
 
 // 6 cycles on LS0/LS1.
 def THX3T110Write_6Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 6;
   let NumMicroOps = 3;
 }
 
 // 4 + 5 cycles on LS0/LS1.
 // First resource is available after 4 cycles.
 // Second resource is available after 5 cycles.
 // Load vector pair, immed offset, Q-form [LDP/LDNP].
 def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [4, 5];
+  let ReleaseAtCycles = [4, 5];
 }
 
 // 4 + 8 cycles on LS0/LS1.
 // First resource is available after 4 cycles.
 // Second resource is available after 8 cycles.
 // Load vector pair, immed offset, S/D-form [LDP/LDNP].
 def THX3T110Write_4_8Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [4, 8];
+  let ReleaseAtCycles = [4, 8];
 }
 
 // 11 cycles on LS0/LS1 and I1.
 def THX3T110Write_11Cyc_LS01_I1 :
   SchedWriteRes<[THX3T110LS, THX3T110I1]> {
   let Latency = 11;
   let NumMicroOps = 4;
 }
def THX3T110Write_23Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {
   let NumMicroOps = 4;
 }
 
 // 3 cycles on F2/F3 and 4 cycles on F0/F1/F2/F3.
 def THX3T110Write_3_4Cyc_F23_F0123 :
   SchedWriteRes<[THX3T110FP23, THX3T110FP0123]> {
   let Latency = 3;
   let NumMicroOps = 2;
-  let ResourceCycles = [3, 4];
+  let ReleaseAtCycles = [3, 4];
 }
 
 
 // Define commonly used read types.
 
 // No forwarding is provided for these types.
 def : ReadAdvance<ReadI,       0>;
 def : ReadAdvance<ReadISReg,   0>;

 
 
 // ALU, basic
 // Conditional compare
 // Conditional select
 // Address generation
 def : WriteRes<WriteI,       [THX3T110I0123]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[WriteI],
             (instregex "ADD?(W|X)r(i|r|s|x)",   "ADDS?(W|X)r(i|r|s|x)(64)?",
                        "AND?(W|X)r(i|r|s|x)",   "ANDS?(W|X)r(i|r|s|x)",
                        "ADC(W|X)r",
                        "BIC?(W|X)r(i|r|s|x)",   "BICS?(W|X)r(i|r|s|x)",
                        "EON?(W|X)r(i|r|s|x)",   "ORN?(W|X)r(i|r|s|x)",
                        "ORR?(W|X)r(i|r|s|x)",   "SUB?(W|X)r(i|r|s|x)",
                        "SUBS?(W|X)r(i|r|s|x)",  "SBC(W|X)r",
                        "SBCS(W|X)r",            "CCMN(W|X)(i|r)",
                        "CCMP(W|X)(i|r)",        "CSEL(W|X)r",
                        "CSINC(W|X)r",           "CSINV(W|X)r",
                        "CSNEG(W|X)r")>;
 
 def : InstRW<[WriteI], (instrs COPY)>;
 
 // ALU, extend and/or shift
 def : WriteRes<WriteISReg,   [THX3T110I0123]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[WriteISReg],
             (instregex "ADD?(W|X)r(i|r|s|x)",   "ADDS?(W|X)r(i|r|s|x)(64)?",
                        "AND?(W|X)r(i|r|s|x)",   "ANDS?(W|X)r(i|r|s|x)",
                        "ADC(W|X)r",
                        "BIC?(W|X)r(i|r|s|x)",   "BICS?(W|X)r(i|r|s|x)",
                        "EON?(W|X)r(i|r|s|x)",   "ORN?(W|X)r(i|r|s|x)",
                        "ORR?(W|X)r(i|r|s|x)",   "SUB?(W|X)r(i|r|s|x)",
                        "SUBS?(W|X)r(i|r|s|x)",  "SBC(W|X)r",
                        "SBCS(W|X)r",            "CCMN(W|X)(i|r)",
                        "CCMP(W|X)(i|r)",        "CSEL(W|X)r",
                        "CSINC(W|X)r",           "CSINV(W|X)r",
                        "CSNEG(W|X)r")>;
 
 def : WriteRes<WriteIEReg,   [THX3T110I0123]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[WriteIEReg],
             (instregex "ADD?(W|X)r(i|r|s|x)",   "ADDS?(W|X)r(i|r|s|x)(64)?",
                        "AND?(W|X)r(i|r|s|x)",   "ANDS?(W|X)r(i|r|s|x)",
                        "ADC(W|X)r",
                        "BIC?(W|X)r(i|r|s|x)",   "BICS?(W|X)r(i|r|s|x)",

 //---
 // 3.4 Divide and Multiply Instructions
 //---
 
 // Divide, W-form
 // Latency range of 13-23/13-39.
 def : WriteRes<WriteID32,    [THX3T110I1]> {
   let Latency = 39;
-  let ResourceCycles = [39];
+  let ReleaseAtCycles = [39];
   let NumMicroOps = 4;
 }
 
 // Divide, X-form
 def : WriteRes<WriteID64,    [THX3T110I1]> {
   let Latency = 23;
-  let ResourceCycles = [23];
+  let ReleaseAtCycles = [23];
   let NumMicroOps = 4;
 }
 
 // Multiply accumulate, W-form
 def : WriteRes<WriteIM32,    [THX3T110I0123]> {
   let Latency = 5;
   let NumMicroOps = 3;
 }

 def : WriteRes<WriteFCmp,    [THX3T110FP0123]> {
   let Latency = 5;
   let NumMicroOps = 2;
 }
 
 // FP Mul, Div, Sqrt
 def : WriteRes<WriteFDiv, [THX3T110FP0123]> {
   let Latency = 22;
-  let ResourceCycles = [19];
+  let ReleaseAtCycles = [19];
 }
 
 def THX3T110XWriteFDiv : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 
 def THX3T110XWriteFDivSP : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 
 def THX3T110XWriteFDivDP : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 23;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 4;
 }
 
 def THX3T110XWriteFSqrtSP : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 
 def THX3T110XWriteFSqrtDP : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 23;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 4;
 }
 
 // FP divide, S-form
 // FP square root, S-form
 def : InstRW<[THX3T110XWriteFDivSP], (instrs FDIVSrr)>;
 def : InstRW<[THX3T110XWriteFSqrtSP], (instrs FSQRTSr)>;
 def : InstRW<[THX3T110XWriteFDivSP], (instregex "^FDIVv.*32$")>;
 def : InstRW<[THX3T110XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
 def : InstRW<[THX3T110Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>;
 
 // FP divide, D-form
 // FP square root, D-form
 def : InstRW<[THX3T110XWriteFDivDP], (instrs FDIVDrr)>;
 def : InstRW<[THX3T110XWriteFSqrtDP], (instrs FSQRTDr)>;
 def : InstRW<[THX3T110XWriteFDivDP], (instregex "^FDIVv.*64$")>;
 def : InstRW<[THX3T110XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
 def : InstRW<[THX3T110Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
 
 // FP multiply
 // FP multiply accumulate
 def : WriteRes<WriteFMul, [THX3T110FP0123]> {
   let Latency = 6;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 3;
 }
 
 def THX3T110XWriteFMul : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 6;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 3;
 }
 
 def THX3T110XWriteFMulAcc : SchedWriteRes<[THX3T110FP0123]> {
   let Latency = 6;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 3;
 }
 
 def : InstRW<[THX3T110XWriteFMul], (instregex "^FMUL", "^FNMUL")>;
 def : InstRW<[THX3T110XWriteFMulAcc],
             (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
 
 // FP round to integral

 // ASIMD shift by immed, complex
 // ASIMD shift by register, basic, D-form
 // ASIMD shift by register, basic, Q-form
 // ASIMD shift by register, complex, D-form
 // ASIMD shift by register, complex, Q-form
 def : WriteRes<WriteVd, [THX3T110FP0123]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def : WriteRes<WriteVq, [THX3T110FP0123]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 
 // ASIMD arith, reduce, 4H/4S
 // ASIMD arith, reduce, 8B/8H
 // ASIMD arith, reduce, 16B
 
 // ASIMD logical (MVN (alias for NOT), ORN, ORR)
 def : InstRW<[THX3T110Write_5Cyc_F0123],

llvm/lib/Target/AMDGPU/SISchedule.td

multiclass SICommonWriteRes {
   def : HWVALUWriteRes<Write32Bit,         1>;
   def : HWVALUWriteRes<WriteFloatCvt,      4>;
   def : HWVALUWriteRes<WriteTrans32,       4>;
   def : HWVALUWriteRes<WriteQuarterRate32, 4>;
 
   def : HWVALUWriteRes<Write4PassDGEMM,    4>;
   def : HWVALUWriteRes<Write8PassDGEMM,   16>;
 
-  let ResourceCycles = [2] in
+  let ReleaseAtCycles = [2] in
   def : HWWriteRes<Write2PassMAI,  [HWXDL], 2>;
-  let ResourceCycles = [4] in
+  let ReleaseAtCycles = [4] in
   def : HWWriteRes<Write4PassMAI,  [HWXDL], 4>;
-  let ResourceCycles = [8] in
+  let ReleaseAtCycles = [8] in
   def : HWWriteRes<Write8PassMAI,  [HWXDL], 8>;
-  let ResourceCycles = [16] in
+  let ReleaseAtCycles = [16] in
   def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;
   } // End RetireOOO = 1
 
   def : ReadAdvance<MIVGPRRead, -2>;
 
   // Technically mfma reads can be from 0 to 4 cycles but that does not make
   // sense to model because its register setup is huge. In particular if we
   // properly model read advance as -2 for a vgpr read it will result in a

llvm/lib/Target/ARM/ARMSchedule.td

 //  def P01 : ProcResource<3>; // ALU unit (3 of it).
 //  ...
 //  // Resource usages.
 //  def : WriteRes<WriteALUsr, [P01, P01]> {
 //    Latency = 4; // Latency of 4.
 //    NumMicroOps = 2; // Dispatch 2 micro-ops.
 //    // The two instances of resource P01 are occupied for one cycle. It is one
 //    // cycle because these resources happen to be pipelined.
-//    ResourceCycles = [1, 1];
+//    ReleaseAtCycles = [1, 1];
 //  }
 //  def : ReadAdvance<ReadAdvanceALUsr, 3>;
 
 //===----------------------------------------------------------------------===//
 // Sched definitions for integer pipeline instructions
 //
 // Basic ALU operation.
 def WriteALU : SchedWrite;

 def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
 
 class IsRegPCPred<int n> : MCSchedPredicate<CheckRegOperand<n, PC>>;
 
 class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
                      list<int> rcl, SchedWriteRes wr> :
   SchedWriteRes<!listconcat(wr.ProcResources, resl)> {
   let Latency = !add(wr.Latency, lat);
-  let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
+  let ReleaseAtCycles = !listconcat(wr.ReleaseAtCycles, rcl);
   let NumMicroOps = !add(wr.NumMicroOps, uops);
   SchedWriteRes BaseWr = wr;
 }
 
 class CheckBranchForm<int n, BranchWriteRes br> :
   SchedWriteVariant<[
     SchedVar<IsRegPCPred<n>, [br]>,
     SchedVar<NoSchedPred,    [br.BaseWr]>

llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td

 //===----------------------------------------------------------------------===//
 // Define Generic 1 micro-op types
 
 def A57Write_5cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 5;  }
 def A57Write_5cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 5;  }
 def A57Write_5cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
-                                                    let ResourceCycles = [17]; }
+                                                    let ReleaseAtCycles = [17]; }
 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
-                                                    let ResourceCycles = [18]; }
+                                                    let ReleaseAtCycles = [18]; }
 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
-                                                    let ResourceCycles = [19]; }
+                                                    let ReleaseAtCycles = [19]; }
 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
-                                                    let ResourceCycles = [20]; }
+                                                    let ReleaseAtCycles = [20]; }
 def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
 def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;
-                                                    let ResourceCycles = [1]; }
+                                                    let ReleaseAtCycles = [1]; }
 def A57Write_2cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 2;
-                                                    let ResourceCycles = [1]; }
+                                                    let ReleaseAtCycles = [1]; }
 def A57Write_3cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 3;  }
 def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
 def A57Write_2cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 2;  }
 def A57Write_3cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 3;  }
 def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;
-                                                    let ResourceCycles = [1]; }
+                                                    let ReleaseAtCycles = [1]; }
 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
-                                                    let ResourceCycles = [32]; }
+                                                    let ReleaseAtCycles = [32]; }
 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
-                                                    let ResourceCycles = [32]; }
+                                                    let ReleaseAtCycles = [32]; }
 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
-                                                    let ResourceCycles = [35]; }
+                                                    let ReleaseAtCycles = [35]; }
 def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
 def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }
 def A57Write_3cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 3;  }
 def A57Write_3cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 3;  }
 
 // A57Write_3cyc_1L - A57Write_20cyc_1L
 foreach Lat = 3-20 in {
   def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {

 
 
 //===----------------------------------------------------------------------===//
 // Define Generic 2 micro-op types
 
 def A57Write_64cyc_2X    : SchedWriteRes<[A57UnitX, A57UnitX]> {
   let Latency     = 64;
   let NumMicroOps = 2;
-  let ResourceCycles = [32, 32];
+  let ReleaseAtCycles = [32, 32];
 }
 def A57Write_6cyc_1I_1L  : SchedWriteRes<[A57UnitI,
                                           A57UnitL]> {
   let Latency     = 6;
   let NumMicroOps = 2;
 }
 def A57Write_6cyc_1V_1X  : SchedWriteRes<[A57UnitV,
                                           A57UnitX]> {

 }
 def A57Write_2cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
   let Latency     = 2;
   let NumMicroOps = 2;
 }
 def A57Write_36cyc_2X    : SchedWriteRes<[A57UnitX, A57UnitX]> {
   let Latency     = 36;
   let NumMicroOps = 2;
-  let ResourceCycles = [18, 18];
+  let ReleaseAtCycles = [18, 18];
 }
 def A57Write_3cyc_1I_1M  : SchedWriteRes<[A57UnitI,
                                           A57UnitM]> {
   let Latency     = 3;
   let NumMicroOps = 2;
 }
 def A57Write_4cyc_1I_1M  : SchedWriteRes<[A57UnitI,
                                           A57UnitM]> {

llvm/lib/Target/ARM/ARMScheduleA9.td

 def : WriteRes<WriteVST1, []>;
 def : WriteRes<WriteVST2, []>;
 def : WriteRes<WriteVST3, []>;
 def : WriteRes<WriteVST4, []>;
 
 // Reserve A9UnitFP for 2 consecutive cycles.
 def A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
   let Latency = 4;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
 }
 def A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
   let Latency = 7;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
 }
 def A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
   let Latency = 9;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
 }
 
 // Branches don't have a def operand but still consume resources.
 def A9WriteB : SchedWriteRes<[A9UnitB]>;
 
 // Address generation.
 def A9WriteAdr : SchedWriteRes<[A9UnitAGU]> { let NumMicroOps = 0; }
 

llvm/lib/Target/ARM/ARMScheduleM55.td

 // But a sequence of VLDR;VLDRB;VADD;VSTR because the loads cannot overlap,
 // looks like:
 //          1     2     3     4     5    6
 // LD/ST  : VLDR  VLDR  VLDRB VLDRB VSTR VSTR
 // INTEGER:                   VADD  VADD
 //
 // For this schedule, we currently model latencies and pipelines well for each
 // instruction. MVE instruction take two beats, modelled using
-// ResourceCycles=[2].
+// ReleaseAtCycles=[2].
 //
 //
 // Dual Issue
 //
 // Cortex-M55 can dual issue two 16-bit T1 instructions providing one is one of
 // NOPs, ITs, Brs, ADDri/SUBri, UXTB/H, SXTB/H and MOVri's. NOPs and IT's are
 // not relevant (they will not appear when scheduling), Brs are only at the end
 // of the block. The others are more useful, and where the problems arise.

 def : ReadAdvance<ReadALUsr, 0>;
 def : ReadAdvance<ReadMUL, 0>;
 def : ReadAdvance<ReadMAC, 0>;
 
 //=============//
 // MVE and VFP //
 //=============//
 
-// The Writes that take ResourceCycles=[2] are MVE instruction, the others VFP.
+// The Writes that take ReleaseAtCycles=[2] are MVE instruction, the others VFP.
 
 let SingleIssue = 1, Latency = 1 in {
   def M55WriteLSE2 : SchedWriteRes<[M55UnitLoadStore]>;
   def M55WriteIntE2 : SchedWriteRes<[M55UnitVecALU]>;
   def M55WriteFloatE2 : SchedWriteRes<[M55UnitVecFPALU]>;
   def M55WriteSysE2 : SchedWriteRes<[M55UnitVecSys]>;
 
-  def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
-  def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
-  def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
-  def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ResourceCycles=[2]; }
+  def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
+  def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
+  def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
+  def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ReleaseAtCycles=[2]; }
 }
 
 let SingleIssue = 1, Latency = 2 in {
   def M55WriteLSE3 : SchedWriteRes<[M55UnitLoadStore]>;
   def M55WriteIntE3 : SchedWriteRes<[M55UnitVecALU]>;
   def M55WriteFloatE3 : SchedWriteRes<[M55UnitVecFPALU]>;
 
-  def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
-  def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
-  def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
+  def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
+  def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
+  def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
 }
 
 let SingleIssue = 1, Latency = 3 in {
-  def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
+  def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
 
   // Same as M55Write2IntE3/M55Write2FloatE3 above, but longer latency and no forwarding into stores
-  def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
-  def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
+  def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
+  def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
 }
 let SingleIssue = 1, Latency = 4 in {
-  def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
+  def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
   def M55WriteFloatE3Plus2 : SchedWriteRes<[M55UnitVecFPALU]>;
 }
 let SingleIssue = 1, Latency = 9 in {
   def M55WriteFloatE3Plus7 : SchedWriteRes<[M55UnitVecFPALU]>;
 }
 let SingleIssue = 1, Latency = 15 in {
   def M55WriteFloatE3Plus13 : SchedWriteRes<[M55UnitVecFPALU]>;
 }

llvm/lib/Target/ARM/ARMScheduleR52.td

 def : WriteRes<WriteCMP, [R52UnitALU]> { let Latency = 0; }
 def : WriteRes<WriteCMPsi, [R52UnitALU]> { let Latency = 0; }
 def : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; }
 
 // Multiply - aliased to sub-target specific later
 
 // Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2)
 def : WriteRes<WriteDIV, [R52UnitDiv]> {
-  let Latency = 8; let ResourceCycles = [8]; // non-pipelined
+  let Latency = 8; let ReleaseAtCycles = [8]; // non-pipelined
 }
 
 // Branches  - LR written in Late EX2
 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
 def : WriteRes<WriteBrL, [R52UnitB]> { let Latency = 0; }
 def : WriteRes<WriteBrTbl, [R52UnitALU]> { let Latency = 0; }
 
 // Misc

 
 def : WriteRes<WriteFPMAC64, [R52UnitFPMUL, R52UnitFPMUL,
                               R52UnitFPALU, R52UnitFPALU]> {
   let Latency = 11;
 }
 
 def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
   let Latency = 7;          // FP div takes fixed #cycles
-  let ResourceCycles = [7]; // is not pipelined
+  let ReleaseAtCycles = [7]; // is not pipelined
 }
 
 def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
   let Latency = 17;
-  let ResourceCycles = [17];
+  let ReleaseAtCycles = [17];
 }
 
 def : WriteRes<WriteFPSQRT32, [R52UnitDiv]> { let Latency = 7; }
 def : WriteRes<WriteFPSQRT64, [R52UnitDiv]> { let Latency = 17; }
 
 // Overriden via InstRW for this processor.
 def : WriteRes<WriteVST1, []>;
 def : WriteRes<WriteVST2, []>;

 
 
 // Cortex-R52 specific SchedWrites for use with InstRW
 def R52WriteMAC        : SchedWriteRes<[R52UnitMAC]> { let Latency = 4; }
 def R52WriteMACHi      : SchedWriteRes<[R52UnitMAC]> {
   let Latency = 4; let NumMicroOps = 0;
 }
 def R52WriteDIV        : SchedWriteRes<[R52UnitDiv]> {
-  let Latency = 8; let ResourceCycles = [8]; // not pipelined
+  let Latency = 8; let ReleaseAtCycles = [8]; // not pipelined
 }
 def R52WriteLd         : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
 def R52WriteST         : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
 def R52WriteAdr        : SchedWriteRes<[]> { let Latency = 0; }
 def R52WriteCC         : SchedWriteRes<[]> { let Latency = 0; }
 def R52WriteALU_EX1    : SchedWriteRes<[R52UnitALU]> { let Latency = 2; }
 def R52WriteALU_EX2    : SchedWriteRes<[R52UnitALU]> { let Latency = 3; }
 def R52WriteALU_WRI    : SchedWriteRes<[R52UnitALU]> { let Latency = 4; }
foreach Lat = 1-32 in {
   def R52WriteLM#Lat#Cy : SchedWriteRes<[]> {
     let Latency = Lat;
   }
 }
 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
   def R52ReserveLd#Num#Cy : SchedWriteRes<[R52UnitLd]> {
     let Latency = 0;
     let NumMicroOps = Num;
-    let ResourceCycles = [Num];
+    let ReleaseAtCycles = [Num];
   }
 }
 def R52WriteVLDM : SchedWriteVariant<[
   // 1 D reg
   SchedVar<R52LMAddrPred1,  [R52WriteLM5Cy,
                               R52ReserveLd5Cy]>,
   SchedVar<R52LMAddrPred2,  [R52WriteLM5Cy,
                               R52ReserveLd5Cy]>,
SchedVar<NoSchedPred,      [R52WriteLM5Cy, R52WriteLM6Cy,
                               R52WriteLM11Cy, R52WriteLM12Cy,
                               R52ReserveLd5Cy]>
 ]> { let Variadic=1;}
 
 // variable stores. Cannot dual-issue
 def R52WriteSTM5  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def R52WriteSTM6  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def R52WriteSTM7  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 7;
   let NumMicroOps = 6;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def R52WriteSTM8  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 8;
   let NumMicroOps = 8;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def R52WriteSTM9  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 9;
   let NumMicroOps = 10;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
 }
 def R52WriteSTM10 : SchedWriteRes<[R52UnitLd]> {
   let Latency = 10;
   let NumMicroOps = 12;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
 }
 def R52WriteSTM11 : SchedWriteRes<[R52UnitLd]> {
   let Latency = 11;
   let NumMicroOps = 14;
-  let ResourceCycles = [7];
+  let ReleaseAtCycles = [7];
 }
 def R52WriteSTM12 : SchedWriteRes<[R52UnitLd]> {
   let Latency = 12;
   let NumMicroOps = 16;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def R52WriteSTM13 : SchedWriteRes<[R52UnitLd]> {
   let Latency = 13;
   let NumMicroOps = 18;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 def R52WriteSTM14 : SchedWriteRes<[R52UnitLd]> {
   let Latency = 14;
   let NumMicroOps = 20;
-  let ResourceCycles = [10];
+  let ReleaseAtCycles = [10];
 }
 def R52WriteSTM15 : SchedWriteRes<[R52UnitLd]> {
   let Latency = 15;
   let NumMicroOps = 22;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 
 def R52WriteSTM : SchedWriteVariant<[
   SchedVar<R52LMAddrPred1, [R52WriteSTM5]>,
   SchedVar<R52LMAddrPred2, [R52WriteSTM5]>,
   SchedVar<R52LMAddrPred3, [R52WriteSTM6]>,
   SchedVar<R52LMAddrPred4, [R52WriteSTM6]>,
   SchedVar<R52LMAddrPred5, [R52WriteSTM7]>,

 ]>;
 
 // Vector Load/Stores. Can issue only in slot-0. Can dual-issue with
 // another instruction in slot-1, but only in the last issue.
 def : WriteRes<WriteVLD1, [R52UnitLd]> { let Latency = 5;}
 def : WriteRes<WriteVLD2, [R52UnitLd]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let SingleIssue = 1;
 }
 def : WriteRes<WriteVLD3, [R52UnitLd]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let SingleIssue = 1;
 }
 def : WriteRes<WriteVLD4, [R52UnitLd]> {
   let Latency = 8;
   let NumMicroOps = 7;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let SingleIssue = 1;
 }
 def R52WriteVST1Mem  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def R52WriteVST2Mem  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def R52WriteVST3Mem  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def R52WriteVST4Mem  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 8;
   let NumMicroOps = 7;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def R52WriteVST5Mem  : SchedWriteRes<[R52UnitLd]> {
   let Latency = 9;
   let NumMicroOps = 9;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
 }
 
 
 def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v8i8|v4i16|v2i32)")>;
 def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v16i8|v8i16|v4i32)")>;
 def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABAL(u|s)(v8i16|v4i32|v2i64)")>;
 
 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v8i8|v4i16|v2i32)")>;

llvm/lib/Target/ARM/ARMScheduleSwift.td

let SchedModel = SwiftModel in {
   def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01,
                                                       SwiftUnitP01]> {
     let Latency = 3;
     let NumMicroOps = 2;
   }
   def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> {
     let Latency = 3;
     let NumMicroOps = 3;
-    let ResourceCycles = [3];
+    let ReleaseAtCycles = [3];
   }
   // Plain load without writeback.
   def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
     let Latency = 3;
   }
   def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> {
     let Latency = 4;
   }
def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
         "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT",
         "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT")>;
   def : InstRW< [SwiftPredP0P01FourFiveCycle],
         (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX")>;
 
   def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
     let Latency = 5;
     let NumMicroOps = 3;
-    let ResourceCycles = [2, 1];
+    let ReleaseAtCycles = [2, 1];
   }
   def SwiftWrite1Cycle : SchedWriteRes<[]> {
     let Latency = 1;
     let NumMicroOps = 0;
   }
   def SwiftWrite5Cycle : SchedWriteRes<[]> {
     let Latency = 5;
     let NumMicroOps = 0;
   }
   def SwiftWrite6Cycle : SchedWriteRes<[]> {
     let Latency = 6;
     let NumMicroOps = 0;
   }
 
   // 4.2.14 Integer Multiply, Long
   def : InstRW< [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle],
         (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
 
   def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
     let Latency = 7;
     let NumMicroOps = 5;
-    let ResourceCycles = [2, 3];
+    let ReleaseAtCycles = [2, 3];
   }
 
   // Aliasing sub-target specific WriteRes to generic ones
   def : SchedAlias<WriteMUL16, SwiftWriteP0FourCycle>;
   def : SchedAlias<WriteMUL32, SwiftWriteP0FourCycle>;
   def : SchedAlias<WriteMUL64Lo, SwiftP0P0P01FiveCycle>;
   def : SchedAlias<WriteMUL64Hi, SwiftWrite5Cycle>;
   def : SchedAlias<WriteMAC16, SwiftPredP0P01FourFiveCycle>;
def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU,
         "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
         "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT",
         "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX",
         "t2UMAAL")>;
 
   def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
     let NumMicroOps = 1;
     let Latency = 14;
-    let ResourceCycles = [1, 14];
+    let ReleaseAtCycles = [1, 14];
   }
   // 4.2.18 Integer Divide
   def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround.
   def : InstRW <[SwiftDiv],
         (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
 
   // 4.2.19 Integer Load Single Element
   // 4.2.20 Integer Load Signextended
let SchedModel = SwiftModel in {
   def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle,
                                SwiftWriteP01OneCycle]>],
         (instregex "VGETLNs")>;
 
   // 4.2.38 Advanced SIMD and VFP, Move FPSCR
   // Serializing instructions.
   def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
     let Latency = 15;
-    let ResourceCycles = [15];
+    let ReleaseAtCycles = [15];
   }
   def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
     let Latency = 15;
-    let ResourceCycles = [15];
+    let ReleaseAtCycles = [15];
   }
   def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
     let Latency = 15;
-    let ResourceCycles = [15];
+    let ReleaseAtCycles = [15];
   }
   def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
         (instregex "VMRS")>;
   def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
         (instregex "VMSR")>;
   // Not serializing.
   def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
 
   // 4.2.39 Advanced SIMD and VFP, Load Single Element
   def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>;
 
   // 4.2.40 Advanced SIMD and VFP, Store Single Element
   def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>;
 
   // 4.2.41 Advanced SIMD and VFP, Load Multiple
   // 4.2.42 Advanced SIMD and VFP, Store Multiple
 
   // Resource requirement for permuting, just reserves the resources.
   foreach Num = 1-28 in {
     def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
       let Latency = 0;
       let NumMicroOps = Num;
-      let ResourceCycles = [Num];
+      let ReleaseAtCycles = [Num];
     }
   }
 
   // Pre RA pseudos - load/store to a Q register as a D register pair.
   def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>;
 
   // Post RA not modelled accurately. We assume that register use of width 64
   // bit maps to a D register, 128 maps to a Q register. Not all different kinds
let SchedModel = SwiftModel in {
   def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>;
 
   def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM],
         (instregex "VSTM[SD](IA|DB)_UPD")>;
 
   // 4.2.43 Advanced SIMD, Element or Structure Load and Store
   def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
       let Latency = 4;
-      let ResourceCycles = [2];
+      let ReleaseAtCycles = [2];
   }
   def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
       let Latency = 4;
-      let ResourceCycles = [3];
+      let ReleaseAtCycles = [3];
   }
   foreach Num = 1-2 in {
     def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
       let Latency = 0;
       let NumMicroOps = Num;
-      let ResourceCycles = [Num];
+      let ReleaseAtCycles = [Num];
     }
   }
   // VLDx
   // Multiple structures.
   // Single element structure loads.
   // We assume aligned.
   // Single/two register.
   def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>;
let SchedModel = SwiftModel in {
   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2],
         (instregex "VST4LN(d|q)(8|16|32)_UPD",
                    "VST4LN(d|q)(8|16|32)Pseudo_UPD")>;
 
   // 4.2.44 VFP, Divide and Square Root
   def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
     let NumMicroOps = 1;
     let Latency = 17;
-    let ResourceCycles = [1, 15];
+    let ReleaseAtCycles = [1, 15];
   }
   def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
     let NumMicroOps = 1;
     let Latency = 32;
-    let ResourceCycles = [1, 30];
+    let ReleaseAtCycles = [1, 30];
   }
   def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
   def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
 
   // ===---------------------------------------------------------------------===//
   // Floating-point. Map target defined SchedReadWrite to processor specific ones
   //
   def : SchedAlias<WriteFPCVT, SwiftWriteP1FourCycle>;

   def : WriteRes<WriteVST2, []>;
   def : WriteRes<WriteVST3, []>;
   def : WriteRes<WriteVST4, []>;
 
   // Not specified.
   def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
   // Preload.
   def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
-    let ResourceCycles = [0];
+    let ReleaseAtCycles = [0];
   }
 
 }

llvm/lib/Target/Mips/MipsScheduleGeneric.td

 
 def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> {
   let Latency = 5;
 }
 
 def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
   // Estimated worst case
   let Latency = 33;
-  let ResourceCycles = [33];
+  let ReleaseAtCycles = [33];
 }
 def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
   // Estimated worst case
   let Latency = 31;
-  let ResourceCycles = [31];
+  let ReleaseAtCycles = [31];
 }
 
 // mul
 def : InstRW<[GenericWriteMDUtoGPR], (instrs MUL)>;
 
 // mult, multu
 def : InstRW<[GenericWriteMul], (instrs MULT, MULTu)>;
 

 def GenericWriteFPUMoveFP : SchedWriteRes<[GenericIssueFPUMove]> {
   let Latency = 4;
 }
 def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> {
   let Latency = 2;
 }
 def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 17;
-  let ResourceCycles = [ 14 ];
+  let ReleaseAtCycles = [ 14 ];
 }
 def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 32;
-  let ResourceCycles = [ 29 ];
+  let ReleaseAtCycles = [ 29 ];
 }
 def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 13;
-  let ResourceCycles = [ 10 ];
+  let ReleaseAtCycles = [ 10 ];
 }
 def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 25;
-  let ResourceCycles = [ 21 ];
+  let ReleaseAtCycles = [ 21 ];
 }
 def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 17;
-  let ResourceCycles = [ 14 ];
+  let ReleaseAtCycles = [ 14 ];
 }
 def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 32;
-  let ResourceCycles = [ 29 ];
+  let ReleaseAtCycles = [ 29 ];
 }
 def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 17;
-  let ResourceCycles = [ 14 ];
+  let ReleaseAtCycles = [ 14 ];
 }
 def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
   let Latency = 29;
-  let ResourceCycles = [ 29 ];
+  let ReleaseAtCycles = [ 29 ];
 }
 
 // Floating point compare and branch
 // ---------------------------------
 //
 // c.<cc>.[ds], bc1[tf], bc1[tf]l
 def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_D32, FCMP_D64, FCMP_S32, BC1F,
                                     BC1T, BC1FL, BC1TL)>;

 def GenericWriteMSAOther3 : SchedWriteRes<[GenericIssueFPUS]> {
 let Latency = 3;
 }
 def GenericWriteMSALongInt : SchedWriteRes<[GenericIssueFPUS]> {
 let Latency = 5;
 }
 def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> {
   let Latency = 33;
-  let ResourceCycles = [ 33 ];
+  let ReleaseAtCycles = [ 33 ];
 }
 
 // FPUS is also used in moves from floating point and MSA registers to general
 // purpose registers.
 def GenericWriteMoveFPUSToOtherUnits : SchedWriteRes<[GenericIssueFPUS]> {
   let Latency = 0;
 }
 

llvm/lib/Target/Mips/MipsScheduleP5600.td

def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
   let Latency = 4;
 }
 
 def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>;
 
 def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
   // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
   //        not during 0, 1, and 2.
-  let ResourceCycles = [ 1, 3 ];
+  let ReleaseAtCycles = [ 1, 3 ];
 }
 
 def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
   let Latency = 2;
 }
 
 def P5600WriteStoreFromOtherUnits : SchedWriteRes<[P5600IssueLDST]>;
 def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {

 def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
 def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
 def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
   let Latency = 2;
 }
 def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
   // Estimated worst case
   let Latency = 34;
-  let ResourceCycles = [1, 34];
+  let ReleaseAtCycles = [1, 34];
 }
 def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
   // Estimated worst case
   let Latency = 34;
-  let ResourceCycles = [1, 34];
+  let ReleaseAtCycles = [1, 34];
 }
 def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
 def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
 def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
   let Latency = 5;
 }
 
 // clo, clz, di, ei, mfhi, mflo

 def P5600FPUDivSqrt : ProcResource<2>;
 
 def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>;
 def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; }
 def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; }
 def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 23 / 27
   let Latency = 23; // Using common case
-  let ResourceCycles = [ 1, 23 ];
+  let ReleaseAtCycles = [ 1, 23 ];
 }
 def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 23 / 27
   let Latency = 23; // Using common case
-  let ResourceCycles = [ 1, 23 ];
+  let ReleaseAtCycles = [ 1, 23 ];
 }
 def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 31 / 35
   let Latency = 31; // Using common case
-  let ResourceCycles = [ 1, 31 ];
+  let ReleaseAtCycles = [ 1, 31 ];
 }
 def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 19 / 23
   let Latency = 19; // Using common case
-  let ResourceCycles = [ 1, 19 ];
+  let ReleaseAtCycles = [ 1, 19 ];
 }
 def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 27 / 31
   let Latency = 27; // Using common case
-  let ResourceCycles = [ 1, 27 ];
+  let ReleaseAtCycles = [ 1, 27 ];
 }
 def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 27 / 27
   let Latency = 27; // Using common case
-  let ResourceCycles = [ 1, 27 ];
+  let ReleaseAtCycles = [ 1, 27 ];
 }
 def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 27 / 31
   let Latency = 27; // Using common case
-  let ResourceCycles = [ 1, 27 ];
+  let ReleaseAtCycles = [ 1, 27 ];
 }
 def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 27 / 31
   let Latency = 27; // Using common case
-  let ResourceCycles = [ 1, 27 ];
+  let ReleaseAtCycles = [ 1, 27 ];
 }
 def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
   // Best/Common/Worst case = 7 / 35 / 39
   let Latency = 35; // Using common case
-  let ResourceCycles = [ 1, 35 ];
+  let ReleaseAtCycles = [ 1, 35 ];
 }
 def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
 def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }
 def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>;
 def P5600WriteMSAOther3 : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 3; }
 def P5600WriteMSALongInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 5; }
 
 // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd],

llvm/lib/Target/PowerPC/PPCScheduleP10.td

let SchedModel = P10Model in {
 
   // A BF pipeline may take from 7 to 36 cycles to complete.
   // Some BF operations may keep the pipeline busy for up to 10 cycles.
   def P10W_BF_7C : SchedWriteRes<[P10_BF]> {
     let Latency = 7;
   }
 
   def P10W_BF_22C : SchedWriteRes<[P10_BF]> {
-    let ResourceCycles = [ 5 ];
+    let ReleaseAtCycles = [ 5 ];
     let Latency = 22;
   }
 
   def P10W_BF_24C : SchedWriteRes<[P10_BF]> {
-    let ResourceCycles = [ 8 ];
+    let ReleaseAtCycles = [ 8 ];
     let Latency = 24;
   }
 
   def P10W_BF_26C : SchedWriteRes<[P10_BF]> {
-    let ResourceCycles = [ 5 ];
+    let ReleaseAtCycles = [ 5 ];
     let Latency = 26;
   }
 
   def P10W_BF_27C : SchedWriteRes<[P10_BF]> {
-    let ResourceCycles = [ 7 ];
+    let ReleaseAtCycles = [ 7 ];
     let Latency = 27;
   }
 
   def P10W_BF_36C : SchedWriteRes<[P10_BF]> {
-    let ResourceCycles = [ 10 ];
+    let ReleaseAtCycles = [ 10 ];
     let Latency = 36;
   }
 
   // A BR pipeline may take 2 cycles to complete.
   def P10W_BR_2C : SchedWriteRes<[P10_BR]> {
     let Latency = 2;
   }
 
   // A CY pipeline may take 7 cycles to complete.
   def P10W_CY_7C : SchedWriteRes<[P10_CY]> {
     let Latency = 7;
   }
 
   // A DF pipeline may take from 13 to 174 cycles to complete.
   // Some DF operations may keep the pipeline busy for up to 67 cycles.
   def P10W_DF_13C : SchedWriteRes<[P10_DF]> {
     let Latency = 13;
   }
 
   def P10W_DF_24C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 16 ];
+    let ReleaseAtCycles = [ 16 ];
     let Latency = 24;
   }
 
   def P10W_DF_25C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 17 ];
+    let ReleaseAtCycles = [ 17 ];
     let Latency = 25;
   }
 
   def P10W_DF_26C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 18 ];
+    let ReleaseAtCycles = [ 18 ];
     let Latency = 26;
   }
 
   def P10W_DF_32C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 22 ];
+    let ReleaseAtCycles = [ 22 ];
     let Latency = 32;
   }
 
   def P10W_DF_33C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 25 ];
+    let ReleaseAtCycles = [ 25 ];
     let Latency = 33;
   }
 
   def P10W_DF_34C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 25 ];
+    let ReleaseAtCycles = [ 25 ];
     let Latency = 34;
   }
 
   def P10W_DF_38C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 30 ];
+    let ReleaseAtCycles = [ 30 ];
     let Latency = 38;
   }
 
   def P10W_DF_40C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 17 ];
+    let ReleaseAtCycles = [ 17 ];
     let Latency = 40;
   }
 
   def P10W_DF_43C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 34 ];
+    let ReleaseAtCycles = [ 34 ];
     let Latency = 43;
   }
 
   def P10W_DF_59C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 49 ];
+    let ReleaseAtCycles = [ 49 ];
     let Latency = 59;
   }
 
   def P10W_DF_61C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 12 ];
+    let ReleaseAtCycles = [ 12 ];
     let Latency = 61;
   }
 
   def P10W_DF_68C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 15 ];
+    let ReleaseAtCycles = [ 15 ];
     let Latency = 68;
   }
 
   def P10W_DF_77C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 67 ];
+    let ReleaseAtCycles = [ 67 ];
     let Latency = 77;
   }
 
   def P10W_DF_87C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 12 ];
+    let ReleaseAtCycles = [ 12 ];
     let Latency = 87;
   }
 
   def P10W_DF_100C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 32 ];
+    let ReleaseAtCycles = [ 32 ];
     let Latency = 100;
   }
 
   def P10W_DF_174C : SchedWriteRes<[P10_DF]> {
-    let ResourceCycles = [ 33 ];
+    let ReleaseAtCycles = [ 33 ];
     let Latency = 174;
   }
 
   // A DV pipeline may take from 20 to 83 cycles to complete.
   // Some DV operations may keep the pipeline busy for up to 33 cycles.
   def P10W_DV_20C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 10 ];
+    let ReleaseAtCycles = [ 10 ];
     let Latency = 20;
   }
 
   def P10W_DV_25C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 10 ];
+    let ReleaseAtCycles = [ 10 ];
     let Latency = 25;
   }
 
   def P10W_DV_27C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 10 ];
+    let ReleaseAtCycles = [ 10 ];
     let Latency = 27;
   }
 
   def P10W_DV_41C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 10 ];
+    let ReleaseAtCycles = [ 10 ];
     let Latency = 41;
   }
 
   def P10W_DV_43C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 21 ];
+    let ReleaseAtCycles = [ 21 ];
     let Latency = 43;
   }
 
   def P10W_DV_47C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 21 ];
+    let ReleaseAtCycles = [ 21 ];
     let Latency = 47;
   }
 
   def P10W_DV_54C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 33 ];
+    let ReleaseAtCycles = [ 33 ];
     let Latency = 54;
   }
 
   def P10W_DV_60C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 33 ];
+    let ReleaseAtCycles = [ 33 ];
     let Latency = 60;
   }
 
   def P10W_DV_75C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 21 ];
+    let ReleaseAtCycles = [ 21 ];
     let Latency = 75;
   }
 
   def P10W_DV_83C : SchedWriteRes<[P10_DV]> {
-    let ResourceCycles = [ 33 ];
+    let ReleaseAtCycles = [ 33 ];
     let Latency = 83;
   }
 
   // A DX pipeline may take 5 cycles to complete.
   def P10W_DX_5C : SchedWriteRes<[P10_DX]> {
     let Latency = 5;
   }
 

llvm/lib/Target/PowerPC/PPCScheduleP9.td

def P9_DIV_5C : SchedWriteRes<[DIV]> {
     let Latency = 5;
   }
 
   def P9_DIV_12C : SchedWriteRes<[DIV]> {
     let Latency = 12;
   }
 
   def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 16;
   }
 
   def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 24;
   }
 
   def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 40;
   }
 
   // DP Unit
   // A DP unit may take from 2 to 36 cycles to complete.
   // Some DP operations keep the unit busy for up to 10 cycles.
   def P9_DP_5C : SchedWriteRes<[DP]> {
     let Latency = 5;
   }
 
   def P9_DP_7C : SchedWriteRes<[DP]> {
     let Latency = 7;
   }
 
   def P9_DPE_7C : SchedWriteRes<[DPE]> {
     let Latency = 7;
   }
 
   def P9_DPO_7C : SchedWriteRes<[DPO]> {
     let Latency = 7;
   }
 
   def P9_DP_22C_5 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [5];
+    let ReleaseAtCycles = [5];
     let Latency = 22;
   }
 
   def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 24;
   }
 
   def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 24;
   }
 
   def P9_DP_26C_5 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [5];
+    let ReleaseAtCycles = [5];
     let Latency = 22;
   }
 
   def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [10];
+    let ReleaseAtCycles = [10];
     let Latency = 27;
   }
 
   def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [10];
+    let ReleaseAtCycles = [10];
     let Latency = 27;
   }
 
   def P9_DP_33C_8 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 33;
   }
 
   def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 33;
   }
 
   def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
-    let ResourceCycles = [8];
+    let ReleaseAtCycles = [8];
     let Latency = 33;
   }
 
   def P9_DP_36C_10 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [10];
+    let ReleaseAtCycles = [10];
     let Latency = 36;
   }
 
   def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [10];
+    let ReleaseAtCycles = [10];
     let Latency = 36;
   }
 
   def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
-    let ResourceCycles = [10];
+    let ReleaseAtCycles = [10];
     let Latency = 36;
   }
 
   // PM Unit
   // Three cycle permute operations.
   def P9_PM_3C : SchedWriteRes<[PM]> {
     let Latency = 3;
   }
let SchedModel = P9Model in {
   // Can take from 12 cycles to 76 cycles to obtain a result.
   // The unit may be busy for up to 62 cycles.
   def P9_DFU_12C : SchedWriteRes<[DFU]> {
     let Latency = 12;
   }
 
   def P9_DFU_23C : SchedWriteRes<[DFU]> {
     let Latency = 23;
-    let ResourceCycles = [11];
+    let ReleaseAtCycles = [11];
   }
 
   def P9_DFU_24C : SchedWriteRes<[DFU]> {
     let Latency = 24;
-    let ResourceCycles = [12];
+    let ReleaseAtCycles = [12];
   }
 
   def P9_DFU_37C : SchedWriteRes<[DFU]> {
     let Latency = 37;
-    let ResourceCycles = [25];
+    let ReleaseAtCycles = [25];
   }
 
   def P9_DFU_58C : SchedWriteRes<[DFU]> {
     let Latency = 58;
-    let ResourceCycles = [44];
+    let ReleaseAtCycles = [44];
   }
 
   def P9_DFU_76C : SchedWriteRes<[DFU]> {
     let Latency = 76;
-    let ResourceCycles = [62];
+    let ReleaseAtCycles = [62];
   }
 
   // 2 or 5 cycle latencies for the branch unit.
   def P9_BR_2C : SchedWriteRes<[BR]> {
     let Latency = 2;
   }
 
   def P9_BR_5C : SchedWriteRes<[BR]> {

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 def : WriteRes<WriteIMul, [RocketUnitIMul]>;
 def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
 }
 
 // Integer division
 // Worst case latency is used.
 def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
   let Latency = 34;
-  let ResourceCycles = [34];
+  let ReleaseAtCycles = [34];
 }
 def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
   let Latency = 33;
-  let ResourceCycles = [33];
+  let ReleaseAtCycles = [33];
 }
 
 // Memory
 def : WriteRes<WriteSTB, [RocketUnitMem]>;
 def : WriteRes<WriteSTH, [RocketUnitMem]>;
 def : WriteRes<WriteSTW, [RocketUnitMem]>;
 def : WriteRes<WriteSTD, [RocketUnitMem]>;
 def : WriteRes<WriteFST32, [RocketUnitMem]>;

 
 let Latency = 7 in {
 def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
 def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
 }
 
 // FP division
 // FP division unit on Rocket is not pipelined, so set resource cycles to latency.
-let Latency = 20, ResourceCycles = [20] in {
+let Latency = 20, ReleaseAtCycles = [20] in {
 def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
 def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
 }
 
 // FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
 def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
-                                                      let ResourceCycles = [20]; }
+                                                      let ReleaseAtCycles = [20]; }
 def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
-                                                      let ResourceCycles = [25]; }
+                                                      let ReleaseAtCycles = [25]; }
 
 // Others
 def : WriteRes<WriteCSR, []>;
 def : WriteRes<WriteNop, []>;
 
 def : InstRW<[WriteIALU], (instrs COPY)>;
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 let Latency = 3 in {
 def : WriteRes<WriteIMul, [SiFive7PipeB]>;
 def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
 }
 
 // Integer division
 def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
   let Latency = 66;
-  let ResourceCycles = [1, 65];
+  let ReleaseAtCycles = [1, 65];
 }
 def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
   let Latency = 34;
-  let ResourceCycles = [1, 33];
+  let ReleaseAtCycles = [1, 33];
 }
 
 // Bitmanip
 let Latency = 3 in {
 // Rotates are in the late-B ALU.
 def : WriteRes<WriteRotateImm, [SiFive7PipeB]>;
 def : WriteRes<WriteRotateImm32, [SiFive7PipeB]>;
 def : WriteRes<WriteRotateReg, [SiFive7PipeB]>;

 def : WriteRes<WriteFMul16, [SiFive7PipeB]>;
 def : WriteRes<WriteFMA16, [SiFive7PipeB]>;
 }
 let Latency = 3 in {
 def : WriteRes<WriteFSGNJ16, [SiFive7PipeB]>;
 def : WriteRes<WriteFMinMax16, [SiFive7PipeB]>;
 }
 
-let Latency = 14, ResourceCycles = [1, 13] in {
+let Latency = 14, ReleaseAtCycles = [1, 13] in {
 def :  WriteRes<WriteFDiv16, [SiFive7PipeB, SiFive7FDiv]>;
 def :  WriteRes<WriteFSqrt16, [SiFive7PipeB, SiFive7FDiv]>;
 }
 
 // Single precision.
 let Latency = 5 in {
 def : WriteRes<WriteFAdd32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMA32, [SiFive7PipeB]>;
 }
 let Latency = 3 in {
 def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
 }
 
 def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
-                                                         let ResourceCycles = [1, 26]; }
+                                                         let ReleaseAtCycles = [1, 26]; }
 def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
-                                                          let ResourceCycles = [1, 26]; }
+                                                          let ReleaseAtCycles = [1, 26]; }
 
 // Double precision
 let Latency = 7 in {
 def : WriteRes<WriteFAdd64, [SiFive7PipeB]>;
 def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
 def : WriteRes<WriteFMA64, [SiFive7PipeB]>;
 }
 let Latency = 3 in {
 def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
 def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
 }
 
 def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
-                                                         let ResourceCycles = [1, 55]; }
+                                                         let ReleaseAtCycles = [1, 55]; }
 def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
-                                                          let ResourceCycles = [1, 55]; }
+                                                          let ReleaseAtCycles = [1, 55]; }
 
 // Conversions
 let Latency = 3 in {
 def : WriteRes<WriteFCvtI32ToF16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI64ToF16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>;

 }
 
 // 7. Vector Loads and Stores
 // Unit-stride loads and stores can operate at the full bandwidth of the memory
 // pipe. The memory pipe is DLEN bits wide on x280.
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVLDE",    [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDFF",   [SiFive7VL], mx, IsWorstCase>;
   }
-  let Latency = 1, ResourceCycles = [Cycles] in
+  let Latency = 1, ReleaseAtCycles = [Cycles] in
   defm "" : LMULWriteResMX<"WriteVSTE",    [SiFive7VS], mx, IsWorstCase>;
 }
 
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetMaskLoadStoreCycles<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in
+  let Latency = 4, ReleaseAtCycles = [Cycles] in
   defm "" : LMULWriteResMX<"WriteVLDM",    [SiFive7VL], mx, IsWorstCase>;
-  let Latency = 1, ResourceCycles = [Cycles] in
+  let Latency = 1, ReleaseAtCycles = [Cycles] in
   defm "" : LMULWriteResMX<"WriteVSTM",    [SiFive7VS], mx, IsWorstCase>;
 }
 
 // Strided loads and stores operate at one element per cycle and should be
 // scheduled accordingly. Indexed loads and stores operate at one element per
 // cycle, and they stall the machine until all addresses have been generated,
 // so they cannot be scheduled. Indexed and strided loads and stores have LMUL
 // specific suffixes, but since SEW is already encoded in the name of the
 // resource, we do not need to use LMULSEWXXX constructors. However, we do
 // use the SEW from the name to determine the number of Cycles.
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+  let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVLDS8",  [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFive7VL], mx, IsWorstCase>;
   }
-  let Latency = 1, ResourceCycles = [Cycles] in {
+  let Latency = 1, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVSTS8",  [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFive7VS], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+  let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVLDS16",  [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFive7VL], mx, IsWorstCase>;
   }
-  let Latency = 1, ResourceCycles = [Cycles] in {
+  let Latency = 1, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVSTS16",  [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFive7VS], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+  let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVLDS32",  [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFive7VL], mx, IsWorstCase>;
   }
-  let Latency = 1, ResourceCycles = [Cycles] in {
+  let Latency = 1, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVSTS32",  [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFive7VS], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+  let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVLDS64",  [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFive7VL], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFive7VL], mx, IsWorstCase>;
   }
-  let Latency = 1, ResourceCycles = [Cycles] in {
+  let Latency = 1, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVSTS64",  [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFive7VS], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFive7VS], mx, IsWorstCase>;
   }
 }
 
 // VLD*R is LMUL aware
-let Latency = 4, ResourceCycles = [2] in
+let Latency = 4, ReleaseAtCycles = [2] in
   def : WriteRes<WriteVLD1R,  [SiFive7VL]>;
-let Latency = 4, ResourceCycles = [4] in
+let Latency = 4, ReleaseAtCycles = [4] in
   def : WriteRes<WriteVLD2R,  [SiFive7VL]>;
-let Latency = 4, ResourceCycles = [8] in
+let Latency = 4, ReleaseAtCycles = [8] in
   def : WriteRes<WriteVLD4R,  [SiFive7VL]>;
-let Latency = 4, ResourceCycles = [16] in
+let Latency = 4, ReleaseAtCycles = [16] in
   def : WriteRes<WriteVLD8R,  [SiFive7VL]>;
 // VST*R is LMUL aware
-let Latency = 1, ResourceCycles = [2] in
+let Latency = 1, ReleaseAtCycles = [2] in
   def : WriteRes<WriteVST1R,   [SiFive7VS]>;
-let Latency = 1, ResourceCycles = [4] in
+let Latency = 1, ReleaseAtCycles = [4] in
   def : WriteRes<WriteVST2R,   [SiFive7VS]>;
-let Latency = 1, ResourceCycles = [8] in
+let Latency = 1, ReleaseAtCycles = [8] in
   def : WriteRes<WriteVST4R,   [SiFive7VS]>;
-let Latency = 1, ResourceCycles = [16] in
+let Latency = 1, ReleaseAtCycles = [16] in
   def : WriteRes<WriteVST8R,   [SiFive7VS]>;
 
 // Segmented Loads and Stores
 // Unit-stride segmented loads and stores are effectively converted into strided
 // segment loads and stores. Strided segment loads and stores operate at up to
 // one segment per cycle if the segment fits within one aligned memory beat.
 // Indexed segment loads and stores operate at the same rate as strided ones,
 // but they stall the machine until all addresses have been generated.
 foreach mx = SchedMxList in {
   foreach eew = [8, 16, 32, 64] in {
     defvar Cycles = SiFive7GetCyclesSegmentedSeg2<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     // Does not chain so set latency high
-    let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+    let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
       defm "" : LMULWriteResMX<"WriteVLSEG2e" # eew,   [SiFive7VL], mx, IsWorstCase>;
       defm "" : LMULWriteResMX<"WriteVLSEGFF2e" # eew, [SiFive7VL], mx, IsWorstCase>;
     }
-    let Latency = 1, ResourceCycles = [Cycles] in
+    let Latency = 1, ReleaseAtCycles = [Cycles] in
     defm "" : LMULWriteResMX<"WriteVSSEG2e" # eew,   [SiFive7VS], mx, IsWorstCase>;
     foreach nf=3-8 in {
       defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
       // Does not chain so set latency high
-      let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+      let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
         defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew,   [SiFive7VL], mx, IsWorstCase>;
         defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
       }
-      let Latency = 1, ResourceCycles = [Cycles] in
+      let Latency = 1, ReleaseAtCycles = [Cycles] in
       defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew,   [SiFive7VS], mx, IsWorstCase>;
     }
   }
 }
 foreach mx = SchedMxList in {
   foreach nf=2-8 in {
     foreach eew = [8, 16, 32, 64] in {
       defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
       // Does not chain so set latency high
-      let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
+      let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
         defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew,  [SiFive7VL], mx, IsWorstCase>;
         defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
         defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
       }
-      let Latency = 1, ResourceCycles = [Cycles] in {
+      let Latency = 1, ReleaseAtCycles = [Cycles] in {
         defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew,  [SiFive7VS], mx, IsWorstCase>;
         defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
         defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
       }
     }
   }
 }
 
 // 11. Vector Integer Arithmetic Instructions
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVIALUV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIALUX",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIALUI",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVICALUV",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVICALUX",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVICALUI",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVShiftV",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVShiftX",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVShiftI",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMinMaxV",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMinMaxX",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMulV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMulX",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMulAddV",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMulAddX",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMergeV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMergeX",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMergeI",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMovV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMovX",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIMovI",     [SiFive7VA], mx, IsWorstCase>;
   }
   // Mask results can't chain.
-  let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
+  let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVICmpV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVICmpX",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVICmpI",     [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVExtV",      [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxList in {
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
                          !div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = Cycles, ResourceCycles = [Cycles] in {
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
       defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFive7VA], mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFive7VA], mx, sew, IsWorstCase>;
     }
   }
 }
 
 // Widening
 foreach mx = SchedMxListW in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVIWALUV",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIWALUX",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIWALUI",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIWMulV",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIWMulX",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 // Narrowing
 foreach mx = SchedMxListW in {
   defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVNShiftV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVNShiftX",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVNShiftI",   [SiFive7VA], mx, IsWorstCase>;
   }
 }
 
 // 12. Vector Fixed-Point Arithmetic Instructions
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVSALUV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSALUX",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSALUI",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVAALUV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVAALUX",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSMulV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSMulX",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 // Narrowing
 foreach mx = SchedMxListW in {
   defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVNClipV",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVNClipX",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVNClipI",  [SiFive7VA], mx, IsWorstCase>;
   }
 }
 
 // 13. Vector Floating-Point Instructions
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFALUV",      [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFALUF",      [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMulV",      [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMulF",      [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMulAddV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMulAddF",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFRecpV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFCvtIToFV",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFCvtFToIV",  [SiFive7VA], mx, IsWorstCase>;
   }
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFSgnjV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFSgnjF",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMinMaxV",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMinMaxF",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFClassV",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMergeV",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFMovV",      [SiFive7VA], mx, IsWorstCase>;
   }
   // Mask results can't chain.
-  let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
+  let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFCmpV",      [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFCmpF",      [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxListF in {
   foreach sew = SchedSEWSet<mx, isF=1>.val in {
     defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
                          !div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
-    let Latency = Cycles, ResourceCycles = [Cycles] in {
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
       defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VA], mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV",  [SiFive7VA], mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF",  [SiFive7VA], mx, sew, IsWorstCase>;
     }
   }
 }
 
 // Widening
 foreach mx = SchedMxListW in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxListFW in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFWALUV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWMulV",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWMulAddV",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWCvtFToFV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWMulAddF",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWMulF",     [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFWALUF",     [SiFive7VA], mx, IsWorstCase>;
   }
 }
 // Narrowing
 foreach mx = SchedMxListW in {
   defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxListFW in {
   defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 
 // 14. Vector Reduction Operations
 foreach mx = SchedMxList in {
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = Cycles, ResourceCycles = [Cycles] in
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in
     defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;
     defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;
   }
 }
 
 foreach mx = SchedMxListWRed in {
   foreach sew = SchedSEWSet<mx, 0, 1>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
-    let Latency = Cycles, ResourceCycles = [Cycles] in
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in
     defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;
   }
 }
 
 foreach mx = SchedMxListF in {
   foreach sew = SchedSEWSet<mx, 1>.val in {
     defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
-    let Latency = RedCycles, ResourceCycles = [RedCycles] in {
+    let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in {
       defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFive7VA],
                                      mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SiFive7VA],
                                      mx, sew, IsWorstCase>;
     }
     defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
-    let Latency = OrdRedCycles, ResourceCycles = [OrdRedCycles] in
+    let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in
     defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;
   }
 }
 
 foreach mx = SchedMxListFWRed in {
   foreach sew = SchedSEWSet<mx, 1, 1>.val in {
     defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
-    let Latency = RedCycles, ResourceCycles = [RedCycles] in
+    let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in
     defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;
     defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
-    let Latency = OrdRedCycles, ResourceCycles = [OrdRedCycles] in
+    let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in
     defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;
   }
 }
 
 // 15. Vector Mask Instructions
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesVMask<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVMALUV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVMPopV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VA], mx, IsWorstCase>;
   }
 }
 
 // 16. Vector Permutation Instructions
-let Latency = 4, ResourceCycles = [1] in {
+let Latency = 4, ReleaseAtCycles = [1] in {
   def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
   def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
   def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
   def : WriteRes<WriteVFMovFV, [SiFive7VA]>;
 }
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 8, ResourceCycles = [Cycles] in {
+  let Latency = 8, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVRGatherVX",    [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVRGatherVI",    [SiFive7VA], mx, IsWorstCase>;
   }
 }
 
 foreach mx = SchedMxList in {
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
+    let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
       defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFive7VA], mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFive7VA], mx, sew, IsWorstCase>;
     }
   }
 }
 
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = 4, ResourceCycles = [Cycles] in {
+  let Latency = 4, ReleaseAtCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVISlideX",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVISlideI",   [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVISlide1X",  [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFSlide1F",  [SiFive7VA], mx, IsWorstCase>;
   }
 }
 
 // VMov*V is LMUL Aware
-let Latency = 4, ResourceCycles = [2] in
+let Latency = 4, ReleaseAtCycles = [2] in
   def : WriteRes<WriteVMov1V,     [SiFive7VA]>;
-let Latency = 4, ResourceCycles = [4] in
+let Latency = 4, ReleaseAtCycles = [4] in
   def : WriteRes<WriteVMov2V,     [SiFive7VA]>;
-let Latency = 4, ResourceCycles = [8] in
+let Latency = 4, ReleaseAtCycles = [8] in
   def : WriteRes<WriteVMov4V,     [SiFive7VA]>;
-let Latency = 4, ResourceCycles = [16] in
+let Latency = 4, ReleaseAtCycles = [16] in
   def : WriteRes<WriteVMov8V,     [SiFive7VA]>;
 
 // Others
 def : WriteRes<WriteCSR, [SiFive7PipeB]>;
 def : WriteRes<WriteNop, []>;
 let Latency = 3 in
   def : WriteRes<WriteRdVLENB, [SiFive7PipeB]>;
 

llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

 def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
 def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
 
 // Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
 def : WriteRes<WriteIMul, [SCR1_MUL]>;
 def : WriteRes<WriteIMul32, [SCR1_MUL]>;
 
 // Integer division: latency 33, inverse throughput 33
-let Latency = 33, ResourceCycles = [33] in {
+let Latency = 33, ReleaseAtCycles = [33] in {
 def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
 def : WriteRes<WriteIDiv, [SCR1_DIV]>;
 }
 
 // Load/store instructions on SCR1 have latency 2 and inverse throughput 2
 // (SCR1_CFG_RV32IMC_MAX includes TCM)
-let Latency = 2, ResourceCycles=[2] in {
+let Latency = 2, ReleaseAtCycles=[2] in {
 // Memory
 def : WriteRes<WriteSTB, [SCR1_LSU]>;
 def : WriteRes<WriteSTH, [SCR1_LSU]>;
 def : WriteRes<WriteSTW, [SCR1_LSU]>;
 def : WriteRes<WriteSTD, [SCR1_LSU]>;
 def : WriteRes<WriteLDB, [SCR1_LSU]>;
 def : WriteRes<WriteLDH, [SCR1_LSU]>;
 def : WriteRes<WriteLDW, [SCR1_LSU]>;

llvm/lib/Target/SystemZ/SystemZScheduleZ13.td

let NumMicroOps = 0 in {
   def : WriteRes<FXb, [Z13_FXbUnit]>;
   def : WriteRes<LSU, [Z13_LSUnit]>;
   def : WriteRes<VecBF,  [Z13_VecUnit]>;
   def : WriteRes<VecDF,  [Z13_VecUnit]>;
   def : WriteRes<VecDFX, [Z13_VecUnit]>;
   def : WriteRes<VecMul,  [Z13_VecUnit]>;
   def : WriteRes<VecStr,  [Z13_VecUnit]>;
   def : WriteRes<VecXsPm, [Z13_VecUnit]>;
-  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+  foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
     def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
     def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
   }}
 
-  def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
 
   def : WriteRes<VBU,     [Z13_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z13_MCD]> { let NumMicroOps = 3;
                                  let BeginGroup  = 1;
                                  let EndGroup    = 1; }
 

llvm/lib/Target/SystemZ/SystemZScheduleZ14.td

let NumMicroOps = 0 in {
   def : WriteRes<FXb, [Z14_FXbUnit]>;
   def : WriteRes<LSU, [Z14_LSUnit]>;
   def : WriteRes<VecBF,  [Z14_VecUnit]>;
   def : WriteRes<VecDF,  [Z14_VecUnit]>;
   def : WriteRes<VecDFX, [Z14_VecUnit]>;
   def : WriteRes<VecMul,  [Z14_VecUnit]>;
   def : WriteRes<VecStr,  [Z14_VecUnit]>;
   def : WriteRes<VecXsPm, [Z14_VecUnit]>;
-  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+  foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
     def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
     def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
   }}
 
-  def : WriteRes<VecFPd,  [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<VecFPd,  [Z14_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
 
   def : WriteRes<VBU,     [Z14_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z14_MCD]> { let NumMicroOps = 3;
                                  let BeginGroup  = 1;
                                  let EndGroup    = 1; }
 

llvm/lib/Target/SystemZ/SystemZScheduleZ15.td

let NumMicroOps = 0 in {
   def : WriteRes<FXb, [Z15_FXbUnit]>;
   def : WriteRes<LSU, [Z15_LSUnit]>;
   def : WriteRes<VecBF,  [Z15_VecUnit]>;
   def : WriteRes<VecDF,  [Z15_VecUnit]>;
   def : WriteRes<VecDFX, [Z15_VecUnit]>;
   def : WriteRes<VecMul,  [Z15_VecUnit]>;
   def : WriteRes<VecStr,  [Z15_VecUnit]>;
   def : WriteRes<VecXsPm, [Z15_VecUnit]>;
-  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+  foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
     def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
     def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z15_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z15_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z15_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z15_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z15_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
   }}
 
-  def : WriteRes<VecFPd,  [Z15_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<VecFPd,  [Z15_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
 
   def : WriteRes<VBU,     [Z15_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z15_MCD]> { let NumMicroOps = 3;
                                     let BeginGroup  = 1;
                                     let EndGroup    = 1; }
 

llvm/lib/Target/SystemZ/SystemZScheduleZ16.td

let NumMicroOps = 0 in {
   def : WriteRes<FXb, [Z16_FXbUnit]>;
   def : WriteRes<LSU, [Z16_LSUnit]>;
   def : WriteRes<VecBF,  [Z16_VecUnit]>;
   def : WriteRes<VecDF,  [Z16_VecUnit]>;
   def : WriteRes<VecDFX, [Z16_VecUnit]>;
   def : WriteRes<VecMul,  [Z16_VecUnit]>;
   def : WriteRes<VecStr,  [Z16_VecUnit]>;
   def : WriteRes<VecXsPm, [Z16_VecUnit]>;
-  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+  foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
     def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z16_FXaUnit]>;
     def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z16_FXbUnit]>;
     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z16_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z16_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z16_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z16_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z16_VecUnit]>;
     def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z16_VecUnit]>;
   }}
 
-  def : WriteRes<VecFPd,   [Z16_VecFPdUnit]> { let ResourceCycles = [30]; }
-  def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ResourceCycles = [20]; }
+  def : WriteRes<VecFPd,   [Z16_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
+  def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [20]; }
 
   def : WriteRes<VBU,     [Z16_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z16_MCD]> { let NumMicroOps = 3;
                                  let BeginGroup  = 1;
                                  let EndGroup    = 1; }
 

llvm/lib/Target/SystemZ/SystemZScheduleZ196.td

 def Z196_MCD    : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
   def : WriteRes<FXU, [Z196_FXUnit]>;
   def : WriteRes<LSU, [Z196_LSUnit]>;
   def : WriteRes<FPU, [Z196_FPUnit]>;
   def : WriteRes<DFU, [Z196_DFUnit]>;
-  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
+  foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
     def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
     def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
     def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
   }}
 }
 
 def : WriteRes<MCD, [Z196_MCD]> { let NumMicroOps = 3;

llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td

 def ZEC12_MCD    : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
   def : WriteRes<FXU, [ZEC12_FXUnit]>;
   def : WriteRes<LSU, [ZEC12_LSUnit]>;
   def : WriteRes<FPU, [ZEC12_FPUnit]>;
   def : WriteRes<DFU, [ZEC12_DFUnit]>;
-  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
+  foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
     def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
     def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
     def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
   }}
 
   def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
 }

llvm/lib/Target/X86/X86SchedAlderlakeP.td

 // folded loads.
 multiclass ADLPWriteResPair<X86FoldableSchedWrite SchedRW,
                             list<ProcResourceKind> ExePorts,
                             int Lat, list<int> Res = [1], int UOps = 1,
                             int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([ADLPPort02_03_11], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 //===----------------------------------------------------------------------===//
 // The following definitons are infered by smg.
 //===----------------------------------------------------------------------===//
 

 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 def : WriteRes<WriteFSign, [ADLPPort00]>;
 defm : ADLPWriteResPair<WriteFSqrt, [ADLPPort00], 12, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFSqrt64, [ADLPPort00], 18, [1]>;
 defm : ADLPWriteResPair<WriteFSqrt64X, [ADLPPort00], 18, [1], 1, 6>;
 defm : ADLPWriteResPair<WriteFSqrt64Y, [ADLPPort00], 18, [1], 1, 7>;
 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 def : WriteRes<WriteFSqrt80, [ADLPPortInvalid, ADLPPort00]> {
-  let ResourceCycles = [7, 1];
+  let ReleaseAtCycles = [7, 1];
   let Latency = 21;
 }
 defm : ADLPWriteResPair<WriteFSqrtX, [ADLPPort00], 12, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFSqrtY, [ADLPPort00], 12, [1], 1, 8>;
 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 defm : X86WriteRes<WriteFStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
 defm : X86WriteResUnsupported<WriteFStoreNT>;
 defm : X86WriteRes<WriteFStoreNTX, [ADLPPort04_09, ADLPPort07_08], 518, [1, 1], 2>;

 def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup0], (instregex "^AA(D|N)D64mr$",
                                               "^A(X?)OR64mr$")>;
 
 def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [2, 1, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1, 1];
   let Latency = 12;
   let NumMicroOps = 6;
 }
 def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
 
 def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m((_NT)?)$",
                                               "^RET(16|32)$",
                                               "^RORX(32|64)mi$")>;
 def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
                                                                                                                                          "^AD(C|O)X(32|64)rm$")>;
 
 def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 13;
   let NumMicroOps = 5;
 }
 def : InstRW<[ADLPWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
 
 def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [2, 1, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1, 1];
   let Latency = 13;
   let NumMicroOps = 6;
 }
 def : InstRW<[ADLPWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
 
 def ADLPWriteResGroup5 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;
def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
   let Latency = 10;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup9], (instregex "^ADD_F(32|64)m$",
                                               "^ILD_F(16|32|64)m$",
                                               "^SUB(R?)_F(32|64)m$")>;
 
 def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup10], (instregex "^ADD_FI(16|32)m$",
                                                "^SUB(R?)_FI(16|32)m$")>;
 
 def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
   let Latency = 2;

 def : InstRW<[ADLPWriteResGroup13, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
 
 def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort01_05_10]> {
   let Latency = 2;
 }
 def : InstRW<[ADLPWriteResGroup14], (instregex "^ANDN(32|64)rr$")>;
 
 def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [5, 2, 1, 1];
+  let ReleaseAtCycles = [5, 2, 1, 1];
   let Latency = 10;
   let NumMicroOps = 9;
 }
 def : InstRW<[ADLPWriteResGroup15], (instrs BT64mr)>;
 
 def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort01]> {
   let Latency = 3;
 }
 def : InstRW<[ADLPWriteResGroup16], (instregex "^BT((C|R|S)?)64rr$",
                                                "^P(DEP|EXT)(32|64)rr$")>;
 
 def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [4, 2, 1, 1, 1, 1];
+  let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
   let Latency = 17;
   let NumMicroOps = 10;
 }
 def : InstRW<[ADLPWriteResGroup17], (instregex "^BT(C|R|S)64mr$")>;
 
 def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 7;
   let NumMicroOps = 5;

 
 def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup26], (instrs CLFLUSHOPT)>;
 
 def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup27], (instrs CLI)>;
 
 def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
-  let ResourceCycles = [6, 1, 3];
+  let ReleaseAtCycles = [6, 1, 3];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 10;
 }
 def : InstRW<[ADLPWriteResGroup28], (instrs CLTS)>;
 
 def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup29], (instregex "^MOV16o(16|32|64)a$")>;
 def : InstRW<[ADLPWriteResGroup29], (instrs CLWB)>;
 
 def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
-  let ResourceCycles = [5, 2];
+  let ReleaseAtCycles = [5, 2];
   let Latency = 6;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPS(B|L|Q|W)$")>;
 
 def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
+  let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
   let Latency = 32;
   let NumMicroOps = 22;
 }
 def : InstRW<[ADLPWriteResGroup31], (instrs CMPXCHG16B)>;
 
 def ADLPWriteResGroup32 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [4, 7, 2, 1, 1, 1];
+  let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
   let Latency = 25;
   let NumMicroOps = 16;
 }
 def : InstRW<[ADLPWriteResGroup32], (instrs CMPXCHG8B)>;
 
 def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [1, 2, 1, 1, 1];
+  let ReleaseAtCycles = [1, 2, 1, 1, 1];
   let Latency = 13;
   let NumMicroOps = 6;
 }
 def : InstRW<[ADLPWriteResGroup33], (instrs CMPXCHG8rm)>;
 
 def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
+  let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
   let Latency = 18;
   let NumMicroOps = 26;
 }
 def : InstRW<[ADLPWriteResGroup34], (instrs CPUID)>;
 
 def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_11]> {
   let Latency = 26;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup35], (instregex "^(V?)CVT(T?)SD2SIrm((_Int)?)$")>;
 
 def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup36], (instrs CVTSI642SSrm)>;
 def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$")>;
 def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
 
 def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 8;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup37, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
 def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
 def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;
 
 def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {

 
 def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 20;
 }
 def : InstRW<[ADLPWriteResGroup48], (instregex "^DIV_F(P?)rST0$")>;
 def : InstRW<[ADLPWriteResGroup48], (instrs DIV_FST0r)>;
 
 def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
+  let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
   let Latency = 126;
   let NumMicroOps = 57;
 }
 def : InstRW<[ADLPWriteResGroup49], (instrs ENTER)>;
 
 def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup54], (instregex "^(V?)MASKMOVDQU((64)?)$",
                                                "^ST_FP(32|64|80)m$")>;
 def : InstRW<[ADLPWriteResGroup54], (instrs FBSTPm,
                                             VMPTRSTm)>;
 
 def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup55], (instrs FDECSTP)>;
 
 def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 11;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup56], (instregex "^FICOM(P?)(16|32)m$")>;
 
 def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00_05]>;
 def : InstRW<[ADLPWriteResGroup57], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
 def : InstRW<[ADLPWriteResGroup57], (instrs FINCSTP,
                                             FNOP)>;
 
 def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup58], (instrs FLDCW16m)>;
 
 def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
-  let ResourceCycles = [2, 39, 5, 10, 8];
+  let ReleaseAtCycles = [2, 39, 5, 10, 8];
   let Latency = 62;
   let NumMicroOps = 64;
 }
 def : InstRW<[ADLPWriteResGroup59], (instrs FLDENVm)>;
 
 def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort00_01_05_06]> {
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let Latency = 4;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup60], (instrs FNCLEX)>;
 
 def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
-  let ResourceCycles = [6, 3, 6];
+  let ReleaseAtCycles = [6, 3, 6];
   let Latency = 75;
   let NumMicroOps = 15;
 }
 def : InstRW<[ADLPWriteResGroup61], (instrs FNINIT)>;
 
 def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup62], (instrs FNSTCW16m)>;
 
 def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup63], (instrs FNSTSW16r)>;
 
 def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup64], (instrs FNSTSWm)>;
 
 def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
-  let ResourceCycles = [9, 30, 21, 1, 11, 11, 16, 1];
+  let ReleaseAtCycles = [9, 30, 21, 1, 11, 11, 16, 1];
   let Latency = 106;
   let NumMicroOps = 100;
 }
 def : InstRW<[ADLPWriteResGroup65], (instrs FSTENVm)>;
 
 def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
-  let ResourceCycles = [4, 47, 1, 2, 1, 33, 2];
+  let ReleaseAtCycles = [4, 47, 1, 2, 1, 33, 2];
   let Latency = 63;
   let NumMicroOps = 90;
 }
 def : InstRW<[ADLPWriteResGroup66], (instrs FXRSTOR)>;
 
 def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
-  let ResourceCycles = [4, 45, 1, 2, 1, 31, 4];
+  let ReleaseAtCycles = [4, 45, 1, 2, 1, 31, 4];
   let Latency = 63;
   let NumMicroOps = 88;
 }
 def : InstRW<[ADLPWriteResGroup67], (instrs FXRSTOR64)>;
 
 def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
+  let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 110;
 }
 def : InstRW<[ADLPWriteResGroup68], (instregex "^FXSAVE((64)?)$")>;
 
 def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup69, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
                                                                 "^(V?)GF2P8MULBrm$")>;
 def : InstRW<[ADLPWriteResGroup69, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$")>;
 def : InstRW<[ADLPWriteResGroup69, ReadAfterVecYLd], (instrs VGF2P8MULBYrm)>;
 
 def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort00_01]> {
   let Latency = 5;
 }
 def : InstRW<[ADLPWriteResGroup70], (instregex "^(V?)GF2P8MULBrr$")>;
 def : InstRW<[ADLPWriteResGroup70], (instrs VGF2P8MULBYrr)>;
 
 def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
+  let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];
   let Latency = 35;
   let NumMicroOps = 87;
 }
 def : InstRW<[ADLPWriteResGroup71], (instrs IN16ri)>;
 
 def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
+  let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];
   let Latency = 35;
   let NumMicroOps = 87;
 }
 def : InstRW<[ADLPWriteResGroup72], (instrs IN16rr)>;
 
 def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
+  let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];
   let Latency = 35;
   let NumMicroOps = 94;
 }
 def : InstRW<[ADLPWriteResGroup73], (instrs IN32ri)>;
 
 def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
+  let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];
   let NumMicroOps = 99;
 }
 def : InstRW<[ADLPWriteResGroup74], (instrs IN32rr)>;
 
 def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
+  let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];
   let Latency = 35;
   let NumMicroOps = 87;
 }
 def : InstRW<[ADLPWriteResGroup75], (instrs IN8ri)>;
 
 def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
+  let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];
   let Latency = 35;
   let NumMicroOps = 86;
 }
 def : InstRW<[ADLPWriteResGroup76], (instrs IN8rr)>;
 
 def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort00_06]> {
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup77], (instrs INC16r_alt)>;
 
 def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 7;
 }
 def : InstRW<[ADLPWriteResGroup78], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
                                                "^VPBROADCAST(D|Q)rm$")>;
 def : InstRW<[ADLPWriteResGroup78], (instrs INC32r_alt,
                                             VBROADCASTSSrm)>;
 
 def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
+  let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];
   let Latency = 20;
   let NumMicroOps = 83;
 }
 def : InstRW<[ADLPWriteResGroup79], (instrs INSB)>;
 
 def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
+  let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
   let Latency = 20;
   let NumMicroOps = 92;
 }
 def : InstRW<[ADLPWriteResGroup80], (instrs INSL)>;
 
 def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
+  let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
   let Latency = 20;
   let NumMicroOps = 86;
 }
 def : InstRW<[ADLPWriteResGroup81], (instrs INSW)>;
 
 def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
+  let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 42;
 }
 def : InstRW<[ADLPWriteResGroup82], (instrs INVLPG)>;
 
 def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {
   let Latency = 4;
   let NumMicroOps = 3;

 def ADLPWriteResGroup86 : SchedWriteRes<[]> {
   let Latency = 0;
   let NumMicroOps = 0;
 }
 def : InstRW<[ADLPWriteResGroup86], (instregex "^JMP_(1|4)$")>;
 def : InstRW<[ADLPWriteResGroup86], (instrs VZEROUPPER)>;
 
 def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [8, 2, 14, 3, 1];
+  let ReleaseAtCycles = [8, 2, 14, 3, 1];
   let Latency = 198;
   let NumMicroOps = 81;
 }
 def : InstRW<[ADLPWriteResGroup87], (instrs LAR16rm)>;
 
 def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
   let Latency = 66;
   let NumMicroOps = 22;
 }
 def : InstRW<[ADLPWriteResGroup88], (instrs LAR16rr)>;
 
 def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
+  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
   let Latency = 71;
   let NumMicroOps = 85;
 }
 def : InstRW<[ADLPWriteResGroup89], (instrs LAR32rm)>;
 
 def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
   let Latency = 65;
   let NumMicroOps = 22;
 }
 def : InstRW<[ADLPWriteResGroup90], (instregex "^LAR(32|64)rr$")>;
 
 def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
+  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
   let Latency = 71;
   let NumMicroOps = 87;
 }
 def : InstRW<[ADLPWriteResGroup91], (instrs LAR64rm)>;
 
 def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort02_03]> {
   let Latency = 7;
 }
 def : InstRW<[ADLPWriteResGroup92], (instregex "^LD_F(32|64|80)m$")>;
 
 def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup93], (instrs LEA16r)>;
 
 def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 6;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup94], (instregex "^LODS(B|W)$",
                                                "^SCAS(B|L|Q|W)$")>;
 def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE)>;
 
 def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup95], (instrs LEAVE64)>;
 
 def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
+  let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 14;
 }
 def : InstRW<[ADLPWriteResGroup96], (instrs LGDT64m)>;
 
 def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
+  let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 14;
 }
 def : InstRW<[ADLPWriteResGroup97], (instrs LIDT64m)>;
 
 def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [5, 3, 2, 1, 1];
+  let ReleaseAtCycles = [5, 3, 2, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 12;
 }
 def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16m)>;
 
 def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [1, 4, 3, 1, 1, 1];
+  let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 11;
 }
 def : InstRW<[ADLPWriteResGroup99], (instrs LLDT16r)>;
 
 def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
+  let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 27;
 }
 def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16m)>;
 
 def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [5, 7, 1, 2, 5, 2];
+  let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 22;
 }
 def : InstRW<[ADLPWriteResGroup101], (instrs LMSW16r)>;
 
 def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup102], (instregex "^LODS(L|Q)$")>;
 
 def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [2, 4, 1];
+  let ReleaseAtCycles = [2, 4, 1];
   let Latency = 3;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup103], (instrs LOOP)>;
 
 def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [4, 6, 1];
+  let ReleaseAtCycles = [4, 6, 1];
   let Latency = 3;
   let NumMicroOps = 11;
 }
 def : InstRW<[ADLPWriteResGroup104], (instrs LOOPE)>;
 
 def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [4, 6, 1];
+  let ReleaseAtCycles = [4, 6, 1];
   let Latency = 2;
   let NumMicroOps = 11;
 }
 def : InstRW<[ADLPWriteResGroup105], (instrs LOOPNE)>;
 
 def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup106], (instrs LRET64)>;
 
 def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 5, 3, 3, 1];
+  let ReleaseAtCycles = [1, 5, 3, 3, 1];
   let Latency = 70;
   let NumMicroOps = 13;
 }
 def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rm$")>;
 
 def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 4, 4, 3, 2, 1];
+  let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];
   let Latency = 63;
   let NumMicroOps = 15;
 }
 def : InstRW<[ADLPWriteResGroup108], (instregex "^LSL(16|32|64)rr$")>;
 
 def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 24;
   let NumMicroOps = 3;

 
 def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
 
 def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup115], (instregex "^MMX_MASKMOVQ((64)?)$")>;
 
 def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 18;
   let NumMicroOps = 2;

 
 def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
 
 def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
 def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
 
 def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 4;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup121], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
 def : InstRW<[ADLPWriteResGroup121], (instrs MMX_PACKUSWBrr)>;
 def : InstRW<[ADLPWriteResGroup121, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
 
 def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
 
 def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 11;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
 
 def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup124], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
 
 def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 9;
   let NumMicroOps = 2;

 def : InstRW<[ADLPWriteResGroup131], (instrs MOVZX32rr8_NOREX)>;
 
 def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 5;
 }
 def : InstRW<[ADLPWriteResGroup132], (instrs MOV64ao32)>;
 
 def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
+  let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
   let Latency = 217;
   let NumMicroOps = 48;
 }
 def : InstRW<[ADLPWriteResGroup133], (instrs MOV64dr)>;
 
 def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup134], (instrs MOV64o32a)>;
 
 def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rc)>;
 
 def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
-  let ResourceCycles = [3, 4, 8, 4, 2, 3];
+  let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];
   let Latency = 181;
   let NumMicroOps = 24;
 }
 def : InstRW<[ADLPWriteResGroup136], (instrs MOV64rd)>;
 
 def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let NumMicroOps = 2;
 }

 
 def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 518;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup149], (instrs MOVNTImr)>;
 
 def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [4, 1, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1, 1];
   let Latency = 8;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup150], (instrs MOVSB)>;
 
 def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05]>;
 def : InstRW<[ADLPWriteResGroup151], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
                                                 "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
                                                 "^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;
 def : InstRW<[ADLPWriteResGroup151], (instrs VPBLENDDrri)>;
 
 def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [4, 1, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1, 1];
   let Latency = 7;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVS(L|Q|W)$")>;
 
 def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 6;
 }

 
 def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 4;
 }
 def : InstRW<[ADLPWriteResGroup158], (instregex "^MUL_F(P?)rST0$")>;
 def : InstRW<[ADLPWriteResGroup158], (instrs MUL_FST0r)>;
 
 def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
-  let ResourceCycles = [7, 1, 2];
+  let ReleaseAtCycles = [7, 1, 2];
   let Latency = 20;
   let NumMicroOps = 10;
 }
 def : InstRW<[ADLPWriteResGroup159], (instrs MWAITrr)>;
 
 def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
+  let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
   let Latency = 35;
   let NumMicroOps = 79;
 }
 def : InstRW<[ADLPWriteResGroup160], (instrs OUT16ir)>;
 
 def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
+  let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];
   let Latency = 35;
   let NumMicroOps = 79;
 }
 def : InstRW<[ADLPWriteResGroup161], (instrs OUT16rr)>;
 
 def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
+  let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
   let Latency = 35;
   let NumMicroOps = 85;
 }
 def : InstRW<[ADLPWriteResGroup162], (instrs OUT32ir)>;
 
 def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
+  let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];
   let Latency = 35;
   let NumMicroOps = 85;
 }
 def : InstRW<[ADLPWriteResGroup163], (instrs OUT32rr)>;
 
 def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
+  let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
   let Latency = 35;
   let NumMicroOps = 73;
 }
 def : InstRW<[ADLPWriteResGroup164], (instrs OUT8ir)>;
 
 def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
+  let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];
   let Latency = 35;
   let NumMicroOps = 73;
 }
 def : InstRW<[ADLPWriteResGroup165], (instrs OUT8rr)>;
 
 def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
+  let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 80;
 }
 def : InstRW<[ADLPWriteResGroup166], (instrs OUTSB)>;
 
 def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
+  let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 89;
 }
 def : InstRW<[ADLPWriteResGroup167], (instrs OUTSL)>;
 
 def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
+  let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 83;
 }
 def : InstRW<[ADLPWriteResGroup168], (instrs OUTSW)>;
 
 def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 10;
   let NumMicroOps = 2;

 
 def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PEXTR(D|Q)mr$")>;
 
 def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 9;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup177, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
 
 def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup178], (instregex "^(V?)PH(ADD|SUB)SWrr$",
                                                 "^VPH(ADD|SUB)SWYrr$")>;
 
 def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup179], (instregex "^POP(16|32|64)rmm$",
                                                 "^PUSH(16|32)rmm$")>;
 
 def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort02_03]> {
   let Latency = 5;
 }
 def : InstRW<[ADLPWriteResGroup180], (instregex "^POPA(16|32)$",
                                                 "^PREFETCHIT(0|1)$")>;
 def : InstRW<[ADLPWriteResGroup180], (instrs POPF32)>;
 
 def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [6, 2, 1, 1];
+  let ReleaseAtCycles = [6, 2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 10;
 }
 def : InstRW<[ADLPWriteResGroup181], (instrs POPF16)>;
 
 def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup182], (instrs POPF64)>;
 
 def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 0;
 }
 def : InstRW<[ADLPWriteResGroup183], (instregex "^PREFETCHT(0|1|2)$")>;
 def : InstRW<[ADLPWriteResGroup183], (instrs PREFETCHNTA)>;
 
 def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITE((64)?)m$")>;
 
 def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup185], (instrs PTWRITE64r)>;
 
 def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup186], (instrs PTWRITEr)>;
 
 def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 2;
 }

 def : InstRW<[ADLPWriteResGroup190], (instrs PUSHF64)>;
 
 def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup191], (instregex "^PUSH(F|G)S64$")>;
 
 def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [2, 3, 2];
+  let ReleaseAtCycles = [2, 3, 2];
   let Latency = 8;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup192], (instregex "^RC(L|R)(16|32|64)rCL$")>;
 
 def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
 
 def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [1, 5, 2];
+  let ReleaseAtCycles = [1, 5, 2];
   let Latency = 20;
   let NumMicroOps = 8;
 }
 def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instrs RCL8mCL)>;
 
 def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [2, 5, 2];
+  let ReleaseAtCycles = [2, 5, 2];
   let Latency = 7;
   let NumMicroOps = 9;
 }
 def : InstRW<[ADLPWriteResGroup195], (instrs RCL8rCL)>;
 
 def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [2, 4, 3];
+  let ReleaseAtCycles = [2, 4, 3];
   let Latency = 20;
   let NumMicroOps = 9;
 }
 def : InstRW<[ADLPWriteResGroup196, WriteRMW], (instrs RCR8mCL)>;
 
 def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [3, 4, 3];
+  let ReleaseAtCycles = [3, 4, 3];
   let Latency = 9;
   let NumMicroOps = 10;
 }
 def : InstRW<[ADLPWriteResGroup197], (instrs RCR8rCL)>;
 
 def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
-  let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
+  let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 54;
 }
 def : InstRW<[ADLPWriteResGroup198], (instrs RDMSR)>;
 
 def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort01]> {
   let Latency = AlderlakePModel.MaxLatency;
 }
 def : InstRW<[ADLPWriteResGroup199], (instrs RDPID64)>;
 
 def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup200], (instrs RDPKRUr)>;
 
 def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
-  let ResourceCycles = [9, 6, 2, 1];
+  let ReleaseAtCycles = [9, 6, 2, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 18;
 }
 def : InstRW<[ADLPWriteResGroup201], (instrs RDPMC)>;
 
 def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
   let Latency = 1386;
   let NumMicroOps = 25;
 }
 def : InstRW<[ADLPWriteResGroup202], (instrs RDRAND16r)>;
 
 def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 25;
 }
 def : InstRW<[ADLPWriteResGroup203], (instregex "^RDRAND(32|64)r$")>;
 
 def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
+  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
   let Latency = 1381;
   let NumMicroOps = 25;
 }
 def : InstRW<[ADLPWriteResGroup204], (instrs RDSEED16r)>;
 
 def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
+  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 25;
 }
 def : InstRW<[ADLPWriteResGroup205], (instregex "^RDSEED(32|64)r$")>;
 
 def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
-  let ResourceCycles = [5, 6, 3, 1];
+  let ReleaseAtCycles = [5, 6, 3, 1];
   let Latency = 18;
   let NumMicroOps = 15;
 }
 def : InstRW<[ADLPWriteResGroup206], (instrs RDTSC)>;
 
 def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
-  let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
+  let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];
   let Latency = 42;
   let NumMicroOps = 21;
 }
 def : InstRW<[ADLPWriteResGroup207], (instrs RDTSCP)>;
 
 def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup208], (instrs RET64)>;
 
 def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup209], (instregex "^RETI(16|32|64)$")>;
 
 def ADLPWriteResGroup210 : SchedWriteRes<[]>;
 def : InstRW<[ADLPWriteResGroup210], (instrs REX64_PREFIX)>;
 
 def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
 
 def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
 
 def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 13;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
                                                           "^(RO|SH)L8mCL$",
                                                           "^(RO|SA|SH)R8mCL$")>;
 
 def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 4;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup214], (instrs SAHF)>;
 
 def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06]> {
   let Latency = 13;
 }

 
 def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort00_06]> {
   let Latency = 3;
 }
 def : InstRW<[ADLPWriteResGroup217], (instregex "^S(A|H)RX(32|64)rr$",
                                                 "^SHLX(32|64)rr$")>;
 
 def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [2, 2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 2, 1, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup218], (instrs SERIALIZE)>;
 
 def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup219], (instrs SFENCE)>;
 
 def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [1, 2, 2, 2];
+  let ReleaseAtCycles = [1, 2, 2, 2];
   let Latency = 21;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup220], (instregex "^S(G|I)DT64m$")>;
 
 def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 9;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup221, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
 
 def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup222], (instrs SHA1MSG1rr)>;
 
 def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [2, 2, 1, 2, 1];
+  let ReleaseAtCycles = [2, 2, 1, 2, 1];
   let Latency = 13;
   let NumMicroOps = 8;
 }
 def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
 
 def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
-  let ResourceCycles = [2, 2, 1, 2];
+  let ReleaseAtCycles = [2, 2, 1, 2];
   let Latency = 6;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup224], (instrs SHA1MSG2rr)>;
 
 def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 4;

 
 def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort05]> {
   let Latency = 6;
 }
 def : InstRW<[ADLPWriteResGroup228], (instrs SHA1RNDS4rri,
                                              SHA256RNDS2rr)>;
 
 def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [3, 2, 1, 1, 1];
+  let ReleaseAtCycles = [3, 2, 1, 1, 1];
   let Latency = 12;
   let NumMicroOps = 8;
 }
 def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
 
 def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
-  let ResourceCycles = [3, 2, 1, 1];
+  let ReleaseAtCycles = [3, 2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 7;
 }
 def : InstRW<[ADLPWriteResGroup230], (instrs SHA256MSG1rr)>;
 
 def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup231, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
 
 def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup232], (instrs SHA256MSG2rr)>;
 
 def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 13;
   let NumMicroOps = 5;

 
 def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup238], (instrs STD)>;
 
 def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [1, 4, 1];
+  let ReleaseAtCycles = [1, 4, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 6;
 }
 def : InstRW<[ADLPWriteResGroup239], (instrs STI)>;
 
 def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 8;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup240], (instrs STOSB)>;
 
 def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 7;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup241], (instregex "^STOS(L|Q|W)$")>;
 
 def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
   let Latency = 5;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup242], (instregex "^STR(32|64)r$")>;
 
 def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 2;
 }
 def : InstRW<[ADLPWriteResGroup243], (instregex "^(TST|XAM)_F$")>;
 def : InstRW<[ADLPWriteResGroup243], (instrs UCOM_FPPr)>;
 
 def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 9;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
 def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
 
 def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01_05]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rr$")>;
 def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrr)>;
 
 def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [6, 7, 18];
+  let ReleaseAtCycles = [6, 7, 18];
   let Latency = 81;
   let NumMicroOps = 31;
 }
 def : InstRW<[ADLPWriteResGroup246], (instrs VERRm)>;
 
 def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [6, 7, 17];
+  let ReleaseAtCycles = [6, 7, 17];
   let Latency = 74;
   let NumMicroOps = 30;
 }
 def : InstRW<[ADLPWriteResGroup247], (instrs VERRr)>;
 
 def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [5, 8, 21];
+  let ReleaseAtCycles = [5, 8, 21];
   let Latency = 81;
   let NumMicroOps = 34;
 }
 def : InstRW<[ADLPWriteResGroup248], (instrs VERWm)>;
 
 def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
-  let ResourceCycles = [5, 8, 20];
+  let ReleaseAtCycles = [5, 8, 20];
   let Latency = 74;
   let NumMicroOps = 33;
 }
 def : InstRW<[ADLPWriteResGroup249], (instrs VERWr)>;
 
 def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2, 4];
+  let ReleaseAtCycles = [1, 1, 2, 4];
   let Latency = 29;
   let NumMicroOps = 8;
 }
 def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
                                                                                "^VPGATHER(D|Q)QYrm$")>;
 def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
                                                                             VPGATHERQDYrm)>;
 
 def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [1, 1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 1, 2];
   let Latency = 20;
   let NumMicroOps = 5;
 }
 def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
                                                                                "^VPGATHER(D|Q)Qrm$")>;
 def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
                                                                             VPGATHERQDrm)>;
 
 def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2, 8];
+  let ReleaseAtCycles = [1, 1, 2, 8];
   let Latency = 30;
   let NumMicroOps = 12;
 }
 def : InstRW<[ADLPWriteResGroup252, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
                                                                             VPGATHERDDYrm)>;
 
 def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2, 4];
+  let ReleaseAtCycles = [1, 1, 2, 4];
   let Latency = 28;
   let NumMicroOps = 8;
 }
 def : InstRW<[ADLPWriteResGroup253, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
                                                                             VPGATHERDDrm)>;
 
 def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup254], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
 
 def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup255, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
                                                                  "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
 
 def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup256], (instrs VLDMXCSR)>;
 
 def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
-  let ResourceCycles = [8, 1, 1, 1, 1, 1, 2, 3];
+  let ReleaseAtCycles = [8, 1, 1, 1, 1, 1, 2, 3];
   let Latency = 40;
   let NumMicroOps = 18;
 }
 def : InstRW<[ADLPWriteResGroup257], (instrs VMCLEARm)>;
 
 def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 5;
 }

 def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
 def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
 
 def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup266, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
 
 def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
-  let ResourceCycles = [1, 2, 3, 3, 1];
+  let ReleaseAtCycles = [1, 2, 3, 3, 1];
   let Latency = 16;
   let NumMicroOps = 10;
 }
 def : InstRW<[ADLPWriteResGroup267], (instrs VZEROALL)>;
 
 def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup268], (instrs WAIT)>;
 
 def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
+  let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 144;
 }
 def : InstRW<[ADLPWriteResGroup269], (instrs WRMSR)>;
 
 def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
-  let ResourceCycles = [2, 1, 4, 1];
+  let ReleaseAtCycles = [2, 1, 4, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 8;
 }
 def : InstRW<[ADLPWriteResGroup270], (instrs WRPKRUr)>;
 
 def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
 
 def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 13;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instrs XADD8rm)>;
 
 def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
-  let ResourceCycles = [4, 1];
+  let ReleaseAtCycles = [4, 1];
   let Latency = 39;
   let NumMicroOps = 5;
 }
 def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
 
 def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
-  let ResourceCycles = [5, 1];
+  let ReleaseAtCycles = [5, 1];
   let Latency = 39;
   let NumMicroOps = 6;
 }
 def : InstRW<[ADLPWriteResGroup274, WriteRMW], (instrs XCHG64rm)>;
 
 def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
-  let ResourceCycles = [4, 1];
+  let ReleaseAtCycles = [4, 1];
   let Latency = 40;
   let NumMicroOps = 5;
 }
 def : InstRW<[ADLPWriteResGroup275, WriteRMW], (instrs XCHG8rm)>;
 
 def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
-  let ResourceCycles = [2, 4, 2, 1, 2, 4];
+  let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
   let Latency = 17;
   let NumMicroOps = 15;
 }
 def : InstRW<[ADLPWriteResGroup276], (instrs XCH_F)>;
 
 def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
-  let ResourceCycles = [7, 3, 8, 5];
+  let ReleaseAtCycles = [7, 3, 8, 5];
   let Latency = 4;
   let NumMicroOps = 23;
 }
 def : InstRW<[ADLPWriteResGroup277], (instrs XGETBV)>;
 
 def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup278], (instrs XLAT)>;
 
 def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
-  let ResourceCycles = [21, 1, 1, 8];
+  let ReleaseAtCycles = [21, 1, 1, 8];
   let Latency = 37;
   let NumMicroOps = 31;
 }
 def : InstRW<[ADLPWriteResGroup279], (instregex "^XRSTOR((S|64)?)$")>;
 def : InstRW<[ADLPWriteResGroup279], (instrs XRSTORS64)>;
 
 def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
   let Latency = 42;
   let NumMicroOps = 140;
 }
 def : InstRW<[ADLPWriteResGroup280], (instrs XSAVE)>;
 
 def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
   let Latency = 41;
   let NumMicroOps = 140;
 }
 def : InstRW<[ADLPWriteResGroup281], (instrs XSAVE64)>;
 
 def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
+  let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
   let Latency = 42;
   let NumMicroOps = 151;
 }
 def : InstRW<[ADLPWriteResGroup282], (instrs XSAVEC)>;
 
 def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
+  let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
   let Latency = 42;
   let NumMicroOps = 152;
 }
 def : InstRW<[ADLPWriteResGroup283], (instrs XSAVEC64)>;
 
 def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
+  let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
   let Latency = 46;
   let NumMicroOps = 155;
 }
 def : InstRW<[ADLPWriteResGroup284], (instrs XSAVEOPT)>;
 
 def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
+  let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
   let Latency = 46;
   let NumMicroOps = 156;
 }
 def : InstRW<[ADLPWriteResGroup285], (instrs XSAVEOPT64)>;
 
 def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
+  let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
   let Latency = 42;
   let NumMicroOps = 184;
 }
 def : InstRW<[ADLPWriteResGroup286], (instrs XSAVES)>;
 
 def ADLPWriteResGroup287 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
-  let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
+  let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
   let Latency = 42;
   let NumMicroOps = 186;
 }
 def : InstRW<[ADLPWriteResGroup287], (instrs XSAVES64)>;
 
 def ADLPWriteResGroup288 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
-  let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
+  let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
   let Latency = 5;
   let NumMicroOps = 54;
 }
 def : InstRW<[ADLPWriteResGroup288], (instrs XSETBV)>;
 
 }

llvm/lib/Target/X86/X86SchedBroadwell.td

 // folded loads.
 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [1], int UOps = 1,
                           int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3/7 cycle to recompute the address.
 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
 

 defm : BWWriteResPair<WriteVarVecShift,  [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 
 // Vector insert/extract operations.
 def : WriteRes<WriteVecInsert, [BWPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 
 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 
 // String instructions.
 
 // Packed Compare Implicit Length Strings, Return Mask
 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
   let Latency = 19;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
   let Latency = 24;
   let NumMicroOps = 10;
-  let ResourceCycles = [4,3,1,1,1];
+  let ReleaseAtCycles = [4,3,1,1,1];
 }
 
 // Packed Compare Implicit Length Strings, Return Index
 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [4,3,1];
+  let ReleaseAtCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 23;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK,    [BWPort0]> { let Latency = 3; }
 def : WriteRes<WriteVecMOVMSK,  [BWPort0]> { let Latency = 3; }
 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
 def : WriteRes<WriteMMXMOVMSK,  [BWPort0]> { let Latency = 1; }
 
 // AES Instructions.
 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
   let Latency = 14;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
   let Latency = 19;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 
 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
   let Latency = 29;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,7,2];
+  let ReleaseAtCycles = [2,7,2];
 }
 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
   let Latency = 33;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,7,1,1];
+  let ReleaseAtCycles = [2,7,1,1];
 }
 
 // Carry-less multiplication instructions.
 defm : BWWriteResPair<WriteCLMul,  [BWPort0], 5>;
 // Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 
 // Catch-all for expensive system instructions.
 def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; }
 
 // Old microcoded instructions that nobody use.
 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; }
 
 // Fence instructions.

 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
 
 // Remaining instrs.
 
 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
                                            "VPSRLVQ(Y?)rr")>;
 
 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
                                            "UCOM_F(P?)r")>;
 
 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
 
 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 
 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
 
 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
 
 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
 
 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
 
 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
                                         SIDT64m,
                                         SMSW16m,
                                         STRm,
                                         SYSCALL)>;
 
 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
   let Latency = 1;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
 def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
 
 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 
 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
                                          MFENCE,
                                          WAIT,
                                          XGETBV)>;
 
 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
 
 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
 
 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 
 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup20], (instrs CWD,
                                          JCXZ, JECXZ, JRCXZ,
                                          ADC8i8, SBB8i8,
                                          ADC16i16, SBB16i16,
                                          ADC32i32, SBB32i32,
                                          ADC64i32, SBB64i32)>;
 
 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 
 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 
 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
                                          STOSB, STOSL, STOSQ, STOSW)>;
 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
 
 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr")>;
 
 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
                                          VPBROADCASTWrr)>;
 
 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr,
                                          MMX_PACKSSWBrr,
                                          MMX_PACKUSWBrr)>;
 
 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
 
 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                          RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def BWWriteResGroup36 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[BWWriteResGroup36], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def BWWriteResGroup36b : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[BWWriteResGroup36b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 
 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
 
 
 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
 
 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PS2PIrr")>;
 
 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
 
 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
                                             "IST_F(16|32)m")>;
 
 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
 
 def BWWriteResGroup46 : SchedWriteRes<[]> {
   let Latency = 0;
   let NumMicroOps = 4;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
 }
 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
 
 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 
 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
                                          VMOVDDUPrm, MOVDDUPrm,
                                          VMOVSHDUPrm, MOVSHDUPrm,
                                          VMOVSLDUPrm, MOVSLDUPrm,
                                          VPBROADCASTDrm,
                                          VPBROADCASTQrm)>;
 
 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
 
 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
 
 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
 
 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 
 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,4];
+  let ReleaseAtCycles = [1,1,4];
 }
 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
 
 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
 def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
                                          VBROADCASTI128,
                                          VBROADCASTSDYrm,
                                          VBROADCASTSSYrm,
                                          VMOVDDUPYrm,
                                          VMOVSHDUPYrm,
                                          VMOVSLDUPYrm,
                                          VPBROADCASTDYrm,
                                          VPBROADCASTQYrm)>;
 
 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup59], (instrs VPSLLVQrm, VPSRLVQrm)>;
 
 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>;
 def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
 
 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
                                             "MOVBE(16|32|64)rm")>;
 
 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
                                          VINSERTI128rm,
                                          VPBLENDDrmi)>;
 
 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
 
 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
 
 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
                                             "SHL(8|16|32|64)m(1|i)",
                                             "SHR(8|16|32|64)m(1|i)")>;
 
 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
                                             "PUSH(16|32|64)rmm")>;
 
 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,5];
+  let ReleaseAtCycles = [1,5];
 }
 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
 
 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
                                          VPSRLVQYrm)>;
 
 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
 
 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
 
 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm,
                                          MMX_PACKSSWBrm,
                                          MMX_PACKUSWBrm)>;
 
 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
                                          SCASB, SCASL, SCASQ, SCASW)>;
 
 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
 
 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>;
 
 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
                                             "ROR(8|16|32|64)m(1|i)")>;
 
 def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
                                            ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
 
 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
 
 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
 def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>;
 
 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,2,1,2];
+  let ReleaseAtCycles = [2,2,1,2];
 }
 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
 
 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
 
 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
                                          VPMOVSXBQYrm,
                                          VPMOVSXBWYrm,
                                          VPMOVSXDQYrm,
                                          VPMOVSXWDYrm,
                                          VPMOVSXWQYrm,
                                          VPMOVZXWDYrm)>;
 
 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
                                             "RCR(8|16|32|64)m(1|i)")>;
 
 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,3];
 }
 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
 
 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,2,1];
+  let ReleaseAtCycles = [1,1,1,2,1];
 }
 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
                                              "ROR(8|16|32|64)mCL",
                                              "SAR(8|16|32|64)mCL",
                                              "SHL(8|16|32|64)mCL",
                                              "SHR(8|16|32|64)mCL")>;
 
 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                              "ILD_F(16|32|64)m")>;
 
 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
   let Latency = 9;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
                                              "VPBROADCASTW(Y?)rm")>;
 
 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,3];
+  let ReleaseAtCycles = [1,1,3];
 }
 def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
 
 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
                                              "LSL(16|32|64)rm")>;
 
 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
 
 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
 
 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
   let Latency = 11;
   let NumMicroOps = 1;
-  let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
+  let ReleaseAtCycles = [1,3]; // Really 2.5 cycle throughput
 }
 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
 
 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
 def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
 
 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
   let Latency = 11;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,2,3];
+  let ReleaseAtCycles = [2,2,3];
 }
 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
                                              "RCR(16|32|64)rCL")>;
 
 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 11;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,4,1,3];
+  let ReleaseAtCycles = [1,4,1,3];
 }
 def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
 
 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 11;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,9];
+  let ReleaseAtCycles = [2,9];
 }
 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
 
 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
 
 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
   let Latency = 14;
   let NumMicroOps = 1;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
 
 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
 
 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
   let Latency = 14;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,2,1,3];
+  let ReleaseAtCycles = [2,2,1,3];
 }
 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
 
 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 14;
   let NumMicroOps = 10;
-  let ResourceCycles = [2,3,1,4];
+  let ReleaseAtCycles = [2,3,1,4];
 }
 def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
 
 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
   let Latency = 14;
   let NumMicroOps = 12;
-  let ResourceCycles = [2,1,4,5];
+  let ReleaseAtCycles = [2,1,4,5];
 }
 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
 
 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
   let Latency = 15;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
 
 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 15;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,1,1,4,1,2];
+  let ReleaseAtCycles = [1,1,1,4,1,2];
 }
 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
 
 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
   let Latency = 16;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1,5];
+  let ReleaseAtCycles = [1,1,5];
 }
 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
 
 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 16;
   let NumMicroOps = 14;
-  let ResourceCycles = [1,1,1,4,2,5];
+  let ReleaseAtCycles = [1,1,1,4,2,5];
 }
 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
 
 def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
   let Latency = 8;
   let NumMicroOps = 20;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
 
 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,5];
+  let ReleaseAtCycles = [1,1,1,5];
 }
 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
 
 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 18;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,1,1,3,1,3];
+  let ReleaseAtCycles = [2,1,1,3,1,3];
 }
 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
 
 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
   let Latency = 19;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1,8];
+  let ReleaseAtCycles = [1,1,8];
 }
 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
 
 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
   let Latency = 20;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
 
 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 20;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,1,1,1,2];
 }
 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
 
 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
   let Latency = 21;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
 
 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 21;
   let NumMicroOps = 19;
-  let ResourceCycles = [2,1,4,1,1,4,6];
+  let ReleaseAtCycles = [2,1,4,1,1,4,6];
 }
 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
 
 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
   let Latency = 22;
   let NumMicroOps = 18;
-  let ResourceCycles = [1,1,16];
+  let ReleaseAtCycles = [1,1,16];
 }
 def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
 
 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
   let Latency = 23;
   let NumMicroOps = 19;
-  let ResourceCycles = [3,1,15];
+  let ReleaseAtCycles = [3,1,15];
 }
 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
 
 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
   let Latency = 24;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
 
 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
   let Latency = 26;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
 
 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
   let Latency = 29;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
 
 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 17;
   let NumMicroOps = 7;
-  let ResourceCycles = [1,3,2,1];
+  let ReleaseAtCycles = [1,3,2,1];
 }
 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm,
                                             VGATHERQPDrm, VPGATHERQQrm)>;
 
 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 18;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,3,4,1];
+  let ReleaseAtCycles = [1,3,4,1];
 }
 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
                                             VGATHERQPDYrm, VPGATHERQQYrm)>;
 
 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 19;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,5,2,1];
+  let ReleaseAtCycles = [1,5,2,1];
 }
 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
 
 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 19;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,4,4,1];
+  let ReleaseAtCycles = [1,4,4,1];
 }
 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm,
                                             VGATHERQPSYrm, VPGATHERQDYrm)>;
 
 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 21;
   let NumMicroOps = 14;
-  let ResourceCycles = [1,4,8,1];
+  let ReleaseAtCycles = [1,4,8,1];
 }
 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
 
 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
   let Latency = 29;
   let NumMicroOps = 27;
-  let ResourceCycles = [1,5,1,1,19];
+  let ReleaseAtCycles = [1,5,1,1,19];
 }
 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
 
 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
   let Latency = 30;
   let NumMicroOps = 28;
-  let ResourceCycles = [1,6,1,1,19];
+  let ReleaseAtCycles = [1,6,1,1,19];
 }
 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
 
 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
   let Latency = 34;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,3,4,10];
+  let ReleaseAtCycles = [1,5,3,4,10];
 }
 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
                                              "IN(8|16|32)rr")>;
 
 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,2,1,4,10];
+  let ReleaseAtCycles = [1,5,2,1,4,10];
 }
 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
                                              "OUT(8|16|32)rr")>;
 
 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
   let Latency = 42;
   let NumMicroOps = 22;
-  let ResourceCycles = [2,20];
+  let ReleaseAtCycles = [2,20];
 }
 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
 
 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
   let Latency = 60;
   let NumMicroOps = 64;
-  let ResourceCycles = [2,2,8,1,10,2,39];
+  let ReleaseAtCycles = [2,2,8,1,10,2,39];
 }
 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
 
 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 63;
   let NumMicroOps = 88;
-  let ResourceCycles = [4,4,31,1,2,1,45];
+  let ReleaseAtCycles = [4,4,31,1,2,1,45];
 }
 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
 
 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
   let Latency = 63;
   let NumMicroOps = 90;
-  let ResourceCycles = [4,2,33,1,2,1,47];
+  let ReleaseAtCycles = [4,2,33,1,2,1,47];
 }
 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
 
 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
   let Latency = 75;
   let NumMicroOps = 15;
-  let ResourceCycles = [6,3,6];
+  let ReleaseAtCycles = [6,3,6];
 }
 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
 
 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 115;
   let NumMicroOps = 100;
-  let ResourceCycles = [9,9,11,8,1,11,21,30];
+  let ReleaseAtCycles = [9,9,11,8,1,11,21,30];
 }
 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
 
 def: InstRW<[WriteZero], (instrs CLC)>;
 
 
 // Instruction variants handled by the renamer. These might not need execution
 // ports in certain conditions.
def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
                                               VPSUBWYrr,
                                               VPCMPGTBYrr,
                                               VPCMPGTDYrr,
                                               VPCMPGTWYrr)>;
 
 def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [BWWritePCMPGTQ]>
 ]>;
 def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
                                                  VPCMPGTQYrr)>;
 
 
 // CMOVs that use both Z and C flag require an extra uop.
 def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
   let NumMicroOps = 2;
 }
 
 def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
   let Latency = 7;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
   let NumMicroOps = 3;
 }
 
 def BWCMOVA_CMOVBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>,
   SchedVar<NoSchedPred,                             [WriteCMOV]>
 ]>;
 
 def BWCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 // SETCCs that use both Z and C flag require an extra uop.
 def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
   let NumMicroOps = 2;
 }
 
 def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 3;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
   let NumMicroOps = 4;
 }
 
 def BWSETA_SETBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>,
   SchedVar<NoSchedPred,                         [WriteSETCC]>
 ]>;
 

llvm/lib/Target/X86/X86SchedHaswell.td

 // folded loads.
 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [1], int UOps = 1,
                           int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3/7 cycle to recompute the address.
 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
 

 defm : HWWriteResPair<WriteVarVecShift,  [HWPort0, HWPort5], 3, [2,1], 3, 6>;
 defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>;
 defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1
 
 // Vector insert/extract operations.
 def : WriteRes<WriteVecInsert, [HWPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 
 def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 
 // String instructions.
 
 // Packed Compare Implicit Length Strings, Return Mask
 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
   let Latency = 17;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
   let Latency = 19;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
   let Latency = 25;
   let NumMicroOps = 10;
-  let ResourceCycles = [4,3,1,1,1];
+  let ReleaseAtCycles = [4,3,1,1,1];
 }
 
 // Packed Compare Implicit Length Strings, Return Index
 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
   let Latency = 17;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
 def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [4,3,1];
+  let ReleaseAtCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK,    [HWPort0]> { let Latency = 3; }
 def : WriteRes<WriteVecMOVMSK,  [HWPort0]> { let Latency = 3; }
 def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; }
 def : WriteRes<WriteMMXMOVMSK,  [HWPort0]> { let Latency = 1; }
 
 // AES Instructions.
 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
   let Latency = 13;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 def : WriteRes<WriteAESIMC, [HWPort5]> {
   let Latency = 14;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
   let Latency = 20;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 
 def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
   let Latency = 29;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,7,2];
+  let ReleaseAtCycles = [2,7,2];
 }
 def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
   let Latency = 34;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,7,1,1];
+  let ReleaseAtCycles = [2,7,1,1];
 }
 
 // Carry-less multiplication instructions.
 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
   let Latency = 17;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 
 // Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 
 // Catch-all for expensive system instructions.
 def : WriteRes<WriteSystem,     [HWPort0156]> { let Latency = 100; }
 
 // Old microcoded instructions that nobody use.
 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
 
 // Fence instructions.

 }
 
 def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
   let NumMicroOps = 2;
 }
 
 def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
   let NumMicroOps = 3;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
 }
 
 // Starting with P1.
 def HWWriteP1 : SchedWriteRes<[HWPort1]>;
 
 
 def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // Notation:
 // - r: register.
 // - mm: 64 bit mmx register.
 // - x = 128 bit xmm register.
 // - (x)mm = mmx or xmm register.
 // - y = 256 bit ymm register.

 def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>;
 
 //-- Control transfer instructions --//
 
 // CALL.
 // i.
 def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
   let NumMicroOps = 4;
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
 }
 def : InstRW<[HWWriteRETI], (instregex "RETI(16|32|64)", "LRETI(16|32|64)")>;
 
 // BOUND.
 // r,m.
 def HWWriteBOUND : SchedWriteRes<[]> {
   let NumMicroOps = 15;
 }

 
 // LODSD/Q.
 def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
 
 // MOVS.
 def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 5;
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
 }
 def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
 
 // CMPS.
 def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 5;
-  let ResourceCycles = [2, 3];
+  let ReleaseAtCycles = [2, 3];
 }
 def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
 
 //-- Other --//
 
 // RDPMC.f
 def HWWriteRDPMC : SchedWriteRes<[]> {
   let NumMicroOps = 34;
 }
 def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
 
 // RDRAND.
 def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
   let NumMicroOps = 17;
-  let ResourceCycles = [1, 16];
+  let ReleaseAtCycles = [1, 16];
 }
 def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
 
 //=== Floating Point x87 Instructions ===//
 //-- Move instructions --//
 
 // FLD.
 // m80.

 
 //=== Floating Point XMM and YMM Instructions ===//
 
 // Remaining instrs.
 
 def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>;
 def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",
                                            "(V?)MOVSLDUPrm",
                                            "(V?)MOVDDUPrm",
                                            "VPBROADCAST(D|Q)rm")>;
 
 def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
                                           VBROADCASTI128,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
                                           VMOVSHDUPYrm,
                                           VMOVSLDUPYrm)>;
 def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
                                              "VPBROADCAST(D|Q)Yrm")>;
 
 def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
   let Latency = 1;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>;
 def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;
 
 def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
                                            "VPSRLVQ(Y?)rr")>;
 
 def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
                                            "UCOM_F(P?)r")>;
 
 def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>;
 
 def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
 
 def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
 
 def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
 
 def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 
 def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
 
 def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup10], (instrs SGDT64m,
                                          SIDT64m,
                                          SMSW16m,
                                          STRm,
                                          SYSCALL)>;
 
 def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;
 
 def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>;
 
 def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSrm)>;
 def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
 
 def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
                                             "(V?)PMOV(SX|ZX)BQrm",
                                             "(V?)PMOV(SX|ZX)BWrm",
                                             "(V?)PMOV(SX|ZX)DQrm",
                                             "(V?)PMOV(SX|ZX)WDrm",
                                             "(V?)PMOV(SX|ZX)WQrm")>;
 
 def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,
                                            VPMOVSXBQYrm,
                                            VPMOVSXWQYrm)>;
 
 def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>;
 def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
 
 def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
                                             "MOVBE(16|32|64)rm")>;
 
 def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm,
                                          VINSERTI128rm,
                                          VPBLENDDrmi)>;
 
 def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>;
 
 def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
 def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
 
 def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
 
 def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;
 
 def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
 
 def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;
 
 def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
                                          STOSB, STOSL, STOSQ, STOSW)>;
 def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>;
 
 def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
                                             "SHL(8|16|32|64)m(1|i)",
                                             "SHR(8|16|32|64)m(1|i)")>;
 
 def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
                                             "PUSH(16|32|64)rmm")>;
 
 def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
 
 def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
                                          MFENCE,
                                          WAIT,
                                          XGETBV)>;
 
 def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
 
 def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;
 
 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
 
 def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWrm,
                                            MMX_PACKSSWBrm,
                                            MMX_PACKUSWBrm)>;
 
 def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
                                          SCASB, SCASL, SCASQ, SCASW)>;
 
 def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
 
 def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup41], (instrs LRET64, RET32, RET64)>;
 
 def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
 
 def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
 
 def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
                                             "ROR(8|16|32|64)m(1|i)")>;
 
 def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
                                            ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
 
 def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
 
 def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
 def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>;
 
 def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr")>;
 
 def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
 
 def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                               "ILD_F(16|32|64)m")>;
 
 def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,
                                            VPMOVSXDQYrm,
                                            VPMOVSXWDYrm,
                                            VPMOVZXWDYrm)>;
 
 def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWrr,
                                          MMX_PACKSSWBrr,
                                          MMX_PACKUSWBrr)>;
 
 def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
 
 def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[HWWriteResGroup59], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                          RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def HWWriteResGroup60 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[HWWriteResGroup60], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def HWWriteResGroup60b : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[HWWriteResGroup60b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;
 
 def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
                                             "IST_F(16|32)m")>;
 
 def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
                                             "RCR(8|16|32|64)m(1|i)")>;
 
 def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 9;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,3];
 }
 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
 
 def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 9;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,2,1];
+  let ReleaseAtCycles = [1,1,1,2,1];
 }
 def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
                                             "ROR(8|16|32|64)mCL",
                                             "SAR(8|16|32|64)mCL",
                                             "SHL(8|16|32|64)mCL",
                                             "SHR(8|16|32|64)mCL")>;
 def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
 
 def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;
 
 def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPS2PIrr,
                                          MMX_CVTTPS2PIrr)>;
 
 def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;
 
 def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
   let Latency = 9;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDrm)>;
 
 def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
   let Latency = 9;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;
 
 def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
 
 def HWWriteResGroup82 : SchedWriteRes<[]> {
   let Latency = 0;
   let NumMicroOps = 4;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
 }
 def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;
 
 def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
 
 def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
                                             "LSL(16|32|64)rm")>;
 
 def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,4];
+  let ReleaseAtCycles = [1,1,4];
 }
 def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;
 
 def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 
 def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;
 
 def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>;
 def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;
 
 def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
 
 def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
 
 def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
 
 def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
 
 def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
 
 def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
 
 def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
   let Latency = 6;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,5];
+  let ReleaseAtCycles = [1,5];
 }
 def: InstRW<[HWWriteResGroup108], (instrs STD)>;
 
 def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,2,1,2];
+  let ReleaseAtCycles = [2,2,1,2];
 }
 def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;
 
 def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
 
 def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 16;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,1,1,4,1,2];
+  let ReleaseAtCycles = [1,1,1,4,1,2];
 }
 def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
 
 def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
   let Latency = 11;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,2,3];
+  let ReleaseAtCycles = [2,2,3];
 }
 def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
                                              "RCR(16|32|64)rCL")>;
 
 def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 11;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,4,1,3];
+  let ReleaseAtCycles = [1,4,1,3];
 }
 def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>;
 
 def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 11;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,9];
+  let ReleaseAtCycles = [2,9];
 }
 def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;
 
 def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 17;
   let NumMicroOps = 14;
-  let ResourceCycles = [1,1,1,4,2,5];
+  let ReleaseAtCycles = [1,1,1,4,2,5];
 }
 def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;
 
 def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 19;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,1,1,3,1,3];
+  let ReleaseAtCycles = [2,1,1,3,1,3];
 }
 def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
 
 def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 14;
   let NumMicroOps = 10;
-  let ResourceCycles = [2,3,1,4];
+  let ReleaseAtCycles = [2,3,1,4];
 }
 def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>;
 
 def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
   let Latency = 19;
   let NumMicroOps = 15;
-  let ResourceCycles = [1,14];
+  let ReleaseAtCycles = [1,14];
 }
 def: InstRW<[HWWriteResGroup143], (instrs POPF16)>;
 
 def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 21;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,1,1,1,2];
 }
 def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
 
 def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {
   let Latency = 8;
   let NumMicroOps = 20;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
 
 def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 22;
   let NumMicroOps = 19;
-  let ResourceCycles = [2,1,4,1,1,4,6];
+  let ReleaseAtCycles = [2,1,4,1,1,4,6];
 }
 def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;
 
 def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
   let Latency = 17;
   let NumMicroOps = 15;
-  let ResourceCycles = [2,1,2,4,2,4];
+  let ReleaseAtCycles = [2,1,2,4,2,4];
 }
 def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;
 
 def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,5];
+  let ReleaseAtCycles = [1,1,1,5];
 }
 def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
 
 def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
   let Latency = 23;
   let NumMicroOps = 19;
-  let ResourceCycles = [3,1,15];
+  let ReleaseAtCycles = [3,1,15];
 }
 def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
 
 def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
   let Latency = 20;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
 
 def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 27;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
 
 def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
   let Latency = 20;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,2,7];
+  let ReleaseAtCycles = [1,2,7];
 }
 def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;
 
 def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
   let Latency = 30;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
 
 def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
   let Latency = 24;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
 
 def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 31;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
 
 def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 30;
   let NumMicroOps = 27;
-  let ResourceCycles = [1,5,1,1,19];
+  let ReleaseAtCycles = [1,5,1,1,19];
 }
 def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;
 
 def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 31;
   let NumMicroOps = 28;
-  let ResourceCycles = [1,6,1,1,19];
+  let ReleaseAtCycles = [1,6,1,1,19];
 }
 def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;
 def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
 
 def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
   let Latency = 34;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
 
 def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,3,4,10];
+  let ReleaseAtCycles = [1,5,3,4,10];
 }
 def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
                                              "IN(8|16|32)rr")>;
 
 def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 36;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,2,1,4,10];
+  let ReleaseAtCycles = [1,5,2,1,4,10];
 }
 def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
                                              "OUT(8|16|32)rr")>;
 
 def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
   let Latency = 41;
   let NumMicroOps = 18;
-  let ResourceCycles = [1,1,2,3,1,1,1,8];
+  let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
 }
 def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;
 
 def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
   let Latency = 42;
   let NumMicroOps = 22;
-  let ResourceCycles = [2,20];
+  let ReleaseAtCycles = [2,20];
 }
 def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;
 
 def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
   let Latency = 61;
   let NumMicroOps = 64;
-  let ResourceCycles = [2,2,8,1,10,2,39];
+  let ReleaseAtCycles = [2,2,8,1,10,2,39];
 }
 def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;
 
 def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 64;
   let NumMicroOps = 88;
-  let ResourceCycles = [4,4,31,1,2,1,45];
+  let ReleaseAtCycles = [4,4,31,1,2,1,45];
 }
 def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;
 
 def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
   let Latency = 64;
   let NumMicroOps = 90;
-  let ResourceCycles = [4,2,33,1,2,1,47];
+  let ReleaseAtCycles = [4,2,33,1,2,1,47];
 }
 def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;
 
 def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
   let Latency = 75;
   let NumMicroOps = 15;
-  let ResourceCycles = [6,3,6];
+  let ReleaseAtCycles = [6,3,6];
 }
 def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
 
 def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 115;
   let NumMicroOps = 100;
-  let ResourceCycles = [9,9,11,8,1,11,21,30];
+  let ReleaseAtCycles = [9,9,11,8,1,11,21,30];
 }
 def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;
 
 def HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 14;
   let NumMicroOps = 12;
-  let ResourceCycles = [2,2,2,1,3,2];
+  let ReleaseAtCycles = [2,2,2,1,3,2];
 }
 def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>;
 
 def HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 17;
   let NumMicroOps = 20;
-  let ResourceCycles = [3,3,4,1,5,4];
+  let ReleaseAtCycles = [3,3,4,1,5,4];
 }
 def: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>;
 
 def HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 16;
   let NumMicroOps = 20;
-  let ResourceCycles = [3,3,4,1,5,4];
+  let ReleaseAtCycles = [3,3,4,1,5,4];
 }
 def: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>;
 
 def HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 22;
   let NumMicroOps = 34;
-  let ResourceCycles = [5,3,8,1,9,8];
+  let ReleaseAtCycles = [5,3,8,1,9,8];
 }
 def: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
 
 def HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 15;
   let NumMicroOps = 14;
-  let ResourceCycles = [3,3,2,1,3,2];
+  let ReleaseAtCycles = [3,3,2,1,3,2];
 }
 def: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>;
 
 def HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 17;
   let NumMicroOps = 22;
-  let ResourceCycles = [5,3,4,1,5,4];
+  let ReleaseAtCycles = [5,3,4,1,5,4];
 }
 def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm,
                                           VGATHERQPSYrm, VPGATHERQDYrm)>;
 
 def HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
   let Latency = 16;
   let NumMicroOps = 15;
-  let ResourceCycles = [3,3,2,1,4,2];
+  let ReleaseAtCycles = [3,3,2,1,4,2];
 }
 def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
 
 def: InstRW<[WriteZero], (instrs CLC)>;
 
 
 // Instruction variants handled by the renamer. These might not need execution
 // ports in certain conditions.
def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
                                               VPSUBWYrr,
                                               VPCMPGTBYrr,
                                               VPCMPGTDYrr,
                                               VPCMPGTWYrr)>;
 
 def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [HWWritePCMPGTQ]>
 ]>;
 def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
                                                  VPCMPGTQYrr)>;
CheckAll<[
     CheckNot<CheckRegOperand<1, EAX>>,  // First MCOperand is not register EAX
     CheckNot<CheckRegOperand<1, RAX>>   // First MCOperand is not register RAX
   ]>
 >;
 
 def HWWriteADC0 : SchedWriteRes<[HWPort06]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def HWWriteADC : SchedWriteVariant<[
   SchedVar<HWFastADC0, [HWWriteADC0]>,
   SchedVar<NoSchedPred, [WriteADC]>
 ]>;
 
 def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8,
                                       SBB16ri8, SBB32ri8, SBB64ri8)>;
 
 // CMOVs that use both Z and C flag require an extra uop.
 def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
   let NumMicroOps = 3;
 }
 
 def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
   let Latency = 8;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
   let NumMicroOps = 4;
 }
 
 def HWCMOVA_CMOVBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>,
   SchedVar<NoSchedPred,                             [WriteCMOV]>
 ]>;
 
 def HWCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 // SETCCs that use both Z and C flag require an extra uop.
 def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
   let NumMicroOps = 2;
 }
 
 def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 3;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
   let NumMicroOps = 4;
 }
 
 def HWSETA_SETBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>,
   SchedVar<NoSchedPred,                         [WriteSETCC]>
 ]>;
 

llvm/lib/Target/X86/X86SchedIceLake.td

 // folded loads.
 multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [1], int UOps = 1,
                           int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([ICXPort23], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3/7 cycle to recompute the address.
 def : WriteRes<WriteRMW, [ICXPort78,ICXPort49]>;
 

 defm : ICXWriteResPair<WriteVarVecShift,  [ICXPort01], 1, [1], 1, 6>; // Variable vector shifts.
 defm : ICXWriteResPair<WriteVarVecShiftY, [ICXPort01], 1, [1], 1, 7>;
 defm : ICXWriteResPair<WriteVarVecShiftZ, [ICXPort0], 1, [1], 1, 7>;
 
 // Vector insert/extract operations.
 def : WriteRes<WriteVecInsert, [ICXPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteVecInsertLd, [ICXPort5,ICXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 
 def : WriteRes<WriteVecExtract, [ICXPort0,ICXPort5]> {

 defm : X86WriteRes<WriteCvtPS2PHZSt, [ICXPort49,ICXPort5,ICXPort78,ICXPort05], 8, [1,1,1,1], 4>;
 
 // Strings instructions.
 
 // Packed Compare Implicit Length Strings, Return Mask
 def : WriteRes<WritePCmpIStrM, [ICXPort0]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrMLd, [ICXPort0, ICXPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [ICXPort0, ICXPort5, ICXPort015, ICXPort0156]> {
   let Latency = 19;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 def : WriteRes<WritePCmpEStrMLd, [ICXPort0, ICXPort5, ICXPort23, ICXPort015, ICXPort0156]> {
   let Latency = 25;
   let NumMicroOps = 10;
-  let ResourceCycles = [4,3,1,1,1];
+  let ReleaseAtCycles = [4,3,1,1,1];
 }
 
 // Packed Compare Implicit Length Strings, Return Index
 def : WriteRes<WritePCmpIStrI, [ICXPort0]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrILd, [ICXPort0, ICXPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
 def : WriteRes<WritePCmpEStrI, [ICXPort0,ICXPort5,ICXPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [4,3,1];
+  let ReleaseAtCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [ICXPort0, ICXPort5, ICXPort23, ICXPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK,    [ICXPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSK,  [ICXPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSKY, [ICXPort0]> { let Latency = 2; }
 def : WriteRes<WriteMMXMOVMSK,  [ICXPort0]> { let Latency = 2; }
 
 // AES instructions.
 def : WriteRes<WriteAESDecEnc, [ICXPort0]> { // Decryption, encryption.
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [ICXPort0, ICXPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 def : WriteRes<WriteAESIMC, [ICXPort0]> { // InvMixColumn.
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteAESIMCLd, [ICXPort0, ICXPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 
 def : WriteRes<WriteAESKeyGen, [ICXPort0,ICXPort5,ICXPort015]> { // Key Generation.
   let Latency = 20;
   let NumMicroOps = 11;
-  let ResourceCycles = [3,6,2];
+  let ReleaseAtCycles = [3,6,2];
 }
 def : WriteRes<WriteAESKeyGenLd, [ICXPort0,ICXPort5,ICXPort23,ICXPort015]> {
   let Latency = 25;
   let NumMicroOps = 11;
-  let ResourceCycles = [3,6,1,1];
+  let ReleaseAtCycles = [3,6,1,1];
 }
 
 // Carry-less multiplication instructions.
 def : WriteRes<WriteCLMul, [ICXPort5]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteCLMulLd, [ICXPort5, ICXPort23]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 // Catch-all for expensive system instructions.
 def : WriteRes<WriteSystem,     [ICXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 
 // AVX2.
 defm : ICXWriteResPair<WriteFShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 defm : ICXWriteResPair<WriteFVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 defm : ICXWriteResPair<WriteShuffle256, [ICXPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 defm : ICXWriteResPair<WriteVPMOV256, [ICXPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
 defm : ICXWriteResPair<WriteVarShuffle256, [ICXPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 
 // Old microcoded instructions that nobody use.
 def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 
 // Fence instructions.
 def : WriteRes<WriteFence,  [ICXPort78, ICXPort49]>;
 
 // Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [ICXPort49,ICXPort5,ICXPort78]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [ICXPort49,ICXPort5,ICXPort78]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 
 // Nop, not very useful expect it provides a model for nops!
 def : WriteRes<WriteNop, []>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Horizontal add/sub  instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : ICXWriteResPair<WriteFHAdd,  [ICXPort5,ICXPort015], 6, [2,1], 3, 6>;
 defm : ICXWriteResPair<WriteFHAddY, [ICXPort5,ICXPort015], 6, [2,1], 3, 7>;
 defm : ICXWriteResPair<WritePHAdd,  [ICXPort5,ICXPort05],  3, [2,1], 3, 5>;
 defm : ICXWriteResPair<WritePHAddX, [ICXPort5,ICXPort015], 3, [2,1], 3, 6>;
 defm : ICXWriteResPair<WritePHAddY, [ICXPort5,ICXPort015], 3, [2,1], 3, 7>;
 
 // Remaining instrs.
 
 def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
                                             "KANDN(B|D|Q|W)rr",
                                             "KMOV(B|D|Q|W)kk",
                                             "KNOT(B|D|Q|W)rr",
                                             "KOR(B|D|Q|W)rr",
                                             "KXNOR(B|D|Q|W)rr",
                                             "KXOR(B|D|Q|W)rr",
def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
                                             "VPMOVB2M(Z|Z128|Z256)rr",
                                             "VPMOVD2M(Z|Z128|Z256)rr",
                                             "VPMOVQ2M(Z|Z128|Z256)rr",
                                             "VPMOVW2M(Z|Z128|Z256)rr")>;
 
 def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r",
                                             "KMOV(B|D|Q|W)kr",
                                             "UCOM_F(P?)r",
                                             "VPBROADCAST(D|Q)rr",
                                             "(V?)INSERTPS(Z?)rr",
                                             "(V?)MOV(HL|LH)PS(Z?)rr",
                                             "(V?)MOVDDUP(Y|Z128|Z256)?rr",
                                             "(V?)PALIGNR(Y|Z128|Z256)?rri",
                                             "(V?)PERMIL(PD|PS)(Y|Z128|Z256)?ri",
                                             "(V?)PERMIL(PD|PS)(Y|Z128|Z256)?rr",
                                             "(V?)UNPCK(L|H)(PD|PS)(Y|Z128|Z256)?rr")>;
 
 def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 
 def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>;
 
 def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 
 def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 
 def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
                                             "VBLENDMPS(Z128|Z256)rr",
                                             "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
                                             "(V?)PADD(B|D|Q|W)rr",
                                             "(V?)MOV(SD|SS)(Z?)rr",
                                             "VPBLENDD(Y?)rri",
                                             "VPBLENDMB(Z128|Z256)rr",
                                             "VPBLENDMD(Z128|Z256)rr",
                                             "VPBLENDMQ(Z128|Z256)rr",
                                             "VPBLENDMW(Z128|Z256)rr",
                                             "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
                                             "VPTERNLOGD(Z|Z128|Z256)rri",
                                             "VPTERNLOGQ(Z|Z128|Z256)rri")>;
 
 def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup10], (instrs SGDT64m,
                                           SIDT64m,
                                           SMSW16m,
                                           STRm,
                                           SYSCALL)>;
 
 def ICXWriteResGroup11 : SchedWriteRes<[ICXPort49,ICXPort78]> {
   let Latency = 1;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
                                              "ST_FP(32|64|80)m")>;
 
 def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 
 def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP,
                                           MMX_MOVDQ2Qrr)>;
 
 def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[ICXWriteResGroup17], (instrs LFENCE,
                                           WAIT,
                                           XGETBV)>;
 
 def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>;
 
 def ICXWriteResGroup21 : SchedWriteRes<[ICXPort49,ICXPort78]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>;
 
 def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup23], (instrs CWD,
                                           JCXZ, JECXZ, JRCXZ,
                                           ADC8i8, SBB8i8,
                                           ADC16i16, SBB16i16,
                                           ADC32i32, SBB32i32,
                                           ADC64i32, SBB64i32)>;
 
 def ICXWriteResGroup25 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort78]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>;
 
 def ICXWriteResGroup27 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 
 def ICXWriteResGroup28 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
                                           STOSB, STOSL, STOSQ, STOSW)>;
 def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 
 def ICXWriteResGroup29 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort15]> {
   let Latency = 2;
   let NumMicroOps = 5;
-  let ResourceCycles = [2,2,1];
+  let ReleaseAtCycles = [2,2,1];
 }
 def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
 
 def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
                                              "KORTEST(B|D|Q|W)rr",
                                              "KTEST(B|D|Q|W)rr")>;
 
 def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr",
                                              "PEXT(32|64)rr")>;
 
 def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
                                              "VALIGND(Z|Z128|Z256)rri",
                                              "VALIGNQ(Z|Z128|Z256)rri",
                                              "VPBROADCAST(B|W)rr",
                                              "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z128|Z256)?rr",
                                              "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;
 
 def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
                                              "KSHIFTL(B|D|Q|W)ri",
                                              "KSHIFTR(B|D|Q|W)ri",
                                              "KUNPCK(BW|DQ|WD)rr",
                                              "VCMPPD(Z|Z128|Z256)rri",
                                              "VCMPPS(Z|Z128|Z256)rri",
                                              "VCMP(SD|SS)Zrr",
                                              "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
                                              "VFPCLASS(SD|SS)Zrr",
                                              "VPCMPB(Z|Z128|Z256)rri",
                                              "VPCMPD(Z|Z128|Z256)rri",
                                              "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
                                              "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
                                              "VPCMPQ(Z|Z128|Z256)rri",
                                              "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
                                              "VPCMPW(Z|Z128|Z256)rri",
                                              "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
 
 def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>;
 
 def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 
 def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
 
 def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr,
                                           MMX_PACKSSWBrr,
                                           MMX_PACKUSWBrr)>;
 
 def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>;
 
 def ICXWriteResGroup43 : SchedWriteRes<[ICXPort49,ICXPort78]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>;
 
 def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                           RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def ICXWriteResGroup44b : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,3,2];
+  let ReleaseAtCycles = [2,3,2];
 }
 def: InstRW<[ICXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def ICXWriteResGroup44c : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,3,2];
+  let ReleaseAtCycles = [2,3,2];
 }
 def: InstRW<[ICXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>;
 
 def ICXWriteResGroup47 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort78,ICXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 
 def ICXWriteResGroup48 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>;
 
 def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 
 def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
                                              "VCVTPD2UQQ(Z128|Z256)rr",
                                              "VCVTPS2DQ(Y|Z128|Z256)rr",
                                              "(V?)CVTPS2DQrr",
                                              "VCVTPS2UDQ(Z128|Z256)rr",
                                              "VCVTTPD2QQ(Z128|Z256)rr",
                                              "VCVTTPD2UQQ(Z128|Z256)rr",
                                              "VCVTTPS2DQ(Z128|Z256)rr",
                                              "(V?)CVTTPS2DQrr",
                                              "VCVTTPS2UDQ(Z128|Z256)rr")>;
 
 def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup50z], (instrs VCVTPD2QQZrr,
                                            VCVTPD2UQQZrr,
                                            VCVTPS2DQZrr,
                                            VCVTPS2UDQZrr,
                                            VCVTTPD2QQZrr,
                                            VCVTTPD2UQQZrr,
                                            VCVTTPS2DQZrr,
                                            VCVTTPS2UDQZrr)>;
 
 def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
                                              "VEXPANDPS(Z|Z128|Z256)rr",
                                              "VPEXPANDD(Z|Z128|Z256)rr",
                                              "VPEXPANDQ(Z|Z128|Z256)rr",
                                              "VPMOVDB(Z|Z128|Z256)rr",
                                              "VPMOVDW(Z|Z128|Z256)rr",
                                              "VPMOVQB(Z|Z128|Z256)rr",
def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
                                              "VPMOVUSQB(Z|Z128|Z256)rr",
                                              "VPMOVUSQD(Z|Z128|Z256)rr",
                                              "VPMOVUSWB(Z|Z128|Z256)rr",
                                              "VPMOVWB(Z|Z128|Z256)rr")>;
 
 def ICXWriteResGroup54 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
                                              "IST_F(16|32)m",
                                              "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
 
 def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>;
 
 def ICXWriteResGroup56 : SchedWriteRes<[]> {
   let Latency = 0;
   let NumMicroOps = 4;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
 }
 def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>;
 
 def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 
 def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort01]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
                                              "MMX_CVT(T?)PS2PIrr",
                                              "VCVTDQ2PDZ128rr",
                                              "VCVTPD2DQZ128rr",
                                              "(V?)CVT(T?)PD2DQrr",
                                              "VCVTPD2UDQZ128rr",
                                              "VCVTPS2PDZ128rr",
def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
                                              "VCVTUDQ2PDZ128rr",
                                              "VCVTUQQ2PSZ128rr",
                                              "VCVTUSI2SSZrr",
                                              "VCVTUSI(64)?2SDZrr")>;
 
 def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
 
 def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>;
 
 def ICXWriteResGroup65 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort01]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
                                              "VCVTPS2PHZ256mr(b?)",
                                              "VCVTPS2PHZmr(b?)")>;
 
 def ICXWriteResGroup66 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVDW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVQB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVQW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSDB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSDW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSQB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSQD(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSQW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSWB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
 
 def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>;
 
 def ICXWriteResGroup69 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,4];
+  let ReleaseAtCycles = [1,1,4];
 }
 def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>;
 
 def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm,
                                           VPBROADCASTDrm,
                                           VPBROADCASTQrm,
                                           VMOVSHDUPrm,
                                           VMOVSLDUPrm,
                                           VMOVDDUPrm,
                                           MOVSHDUPrm,
                                           MOVSLDUPrm,
                                           MOVDDUPrm)>;
 
 def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
 def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
                                              "VCOMPRESSPS(Z|Z128|Z256)rr",
                                              "VPCOMPRESSD(Z|Z128|Z256)rr",
                                              "VPCOMPRESSQ(Z|Z128|Z256)rr",
                                              "VPERMW(Z|Z128|Z256)rr")>;
 
 def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm,
                                           MMX_PADDSWrm,
                                           MMX_PADDUSBrm,
                                           MMX_PADDUSWrm,
                                           MMX_PAVGBrm,
                                           MMX_PAVGWrm,
                                           MMX_PCMPEQBrm,
def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm,
                                           MMX_PSUBSBrm,
                                           MMX_PSUBSWrm,
                                           MMX_PSUBUSBrm,
                                           MMX_PSUBUSWrm)>;
 
 def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>;
 def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
 
 def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm",
                                              "MOVBE(16|32|64)rm")>;
 
 def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
 def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
 
 def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
 def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
 
 def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort01]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
                                              "VCVTSI642SSZrr",
                                              "VCVTUSI642SSZrr")>;
 
 def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
 
 def ICXWriteResGroup86 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
                                              "SHL(8|16|32|64)m(1|i)",
                                              "SHR(8|16|32|64)m(1|i)")>;
 
 def ICXWriteResGroup87 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm",
                                              "PUSH(16|32|64)rmm")>;
 
 def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,5];
+  let ReleaseAtCycles = [1,5];
 }
 def: InstRW<[ICXWriteResGroup88], (instrs STD)>;
 
 def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> {
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
 def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
                                           VBROADCASTI128,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
                                           VMOVSHDUPYrm,
                                           VMOVSLDUPYrm,
                                           VPBROADCASTDYrm,
                                           VPBROADCASTQYrm)>;
 
 def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
 
 def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)",
                                               "VPBROADCAST(B|W)(Z128)?rm",
                                              "(V?)INSERTPS(Z?)rm",
                                              "(V?)PALIGNR(Z128)?rmi",
                                              "(V?)PERMIL(PD|PS)(Z128)?m(b?)i",
                                              "(V?)PERMIL(PD|PS)(Z128)?rm",
                                              "(V?)UNPCK(L|H)(PD|PS)(Z128)?rm")>;
 
 def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort01]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
                                              "VCVTPD2DQ(Y|Z256)rr",
                                              "VCVTPD2UDQZ256rr",
                                              "VCVTPS2PD(Y|Z256)rr",
                                              "VCVTPS2QQZ256rr",
                                              "VCVTPS2UQQZ256rr",
                                              "VCVTQQ2PSZ256rr",
                                              "VCVTTPD2DQ(Y|Z256)rr",
                                              "VCVTTPD2UDQZ256rr",
                                              "VCVTTPS2QQZ256rr",
                                              "VCVTTPS2UQQZ256rr",
                                              "VCVTUDQ2PDZ256rr",
                                              "VCVTUQQ2PSZ256rr")>;
 
 def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
                                            VCVTPD2DQZrr,
                                            VCVTPD2UDQZrr,
                                            VCVTPS2PDZrr,
                                            VCVTPS2QQZrr,
                                            VCVTPS2UQQZrr,
                                            VCVTQQ2PSZrr,
                                            VCVTTPD2DQZrr,
                                            VCVTTPD2UDQZrr,
                                            VCVTTPS2QQZrr,
                                            VCVTTPS2UQQZrr,
                                            VCVTUDQ2PDZrr,
                                            VCVTUQQ2PSZrr)>;
 
 def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
                                           VPBLENDDrmi)>;
 def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd],
                                   (instregex "VBLENDMPDZ128rm(b?)",
                                              "VBLENDMPSZ128rm(b?)",
                                              "VBROADCASTI32X2Z128rm(b?)",
                                              "VBROADCASTSSZ128rm(b?)",
def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd],
                                              "VPSUB(B|D|Q|W)Z128rm(b?)",
                                              "(V?)PSUB(B|D|Q|W)rm",
                                              "VPTERNLOGDZ128rm(b?)i",
                                              "VPTERNLOGQZ128rm(b?)i")>;
 
 def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm,
                                           MMX_PACKSSWBrm,
                                           MMX_PACKUSWBrm)>;
 
 def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr",
                                              "VPERMI2W256rr",
                                              "VPERMI2Wrr",
                                              "VPERMT2W128rr",
                                              "VPERMT2W256rr",
                                              "VPERMT2Wrr")>;
 
 def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64,
                                           SCASB, SCASL, SCASQ, SCASW)>;
 
 def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort01]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
                                               "VCVT(T?)SS2USI64Zrr")>;
 
 def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>;
 
 def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
 
 def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>;
 
 def ICXWriteResGroup106 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
                                               "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
                                               "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
                                               "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
 
 def ICXWriteResGroup107 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
                                               "ROR(8|16|32|64)m(1|i)")>;
 
 def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
 
 def ICXWriteResGroup108 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
 
 def ICXWriteResGroup109 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1,1];
 }
 def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
 def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>;
 
 def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [1,2,2,2];
+  let ReleaseAtCycles = [1,2,2,2];
 }
 def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
                                            VPSCATTERQQZ128mr,
                                            VSCATTERDPDZ128mr,
                                            VSCATTERQPDZ128mr)>;
 
 def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [1,3,1,2];
+  let ReleaseAtCycles = [1,3,1,2];
 }
 def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>;
 
 def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 11;
-  let ResourceCycles = [1,4,4,2];
+  let ReleaseAtCycles = [1,4,4,2];
 }
 def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
                                            VPSCATTERQQZ256mr,
                                            VSCATTERDPDZ256mr,
                                            VSCATTERQPDZ256mr)>;
 
 def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 19;
-  let ResourceCycles = [1,8,8,2];
+  let ReleaseAtCycles = [1,8,8,2];
 }
 def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr,
                                            VPSCATTERQQZmr,
                                            VSCATTERDPDZmr,
                                            VSCATTERQPDZmr)>;
 
 def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 36;
-  let ResourceCycles = [1,16,1,16,2];
+  let ReleaseAtCycles = [1,16,1,16,2];
 }
 def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
 
 def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm",
                                               "PEXT(32|64)rm")>;
 
 def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
                                               "VPBROADCASTB(Z|Z256)rm(b?)",
                                               "VPBROADCASTW(Z|Z256)rm(b?)",
                                               "(V?)PALIGNR(Y|Z256)rmi",
                                               "(V?)PERMIL(PD|PS)(Y|Z256)m(b?)i",
                                               "(V?)PERMIL(PD|PS)(Y|Z256)rm",
                                               "(V?)UNPCK(L|H)(PD|PS)(Y|Z256)rm")>;
 def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm,
                                            VPBROADCASTWYrm,
                                            VPMOVSXBDYrm,
                                            VPMOVSXBQYrm,
                                            VPMOVSXWQYrm)>;
 
 def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
                                            VPBLENDDYrmi)>;
 def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd],
                                    (instregex "VBLENDMPD(Z|Z256)rm(b?)",
                                               "VBLENDMPS(Z|Z256)rm(b?)",
                                               "VBROADCASTF32X2Z256rm(b?)",
                                               "VBROADCASTF32X2Zrm(b?)",
def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd],
                                               "VPSUB(B|D|Q|W)Yrm",
                                               "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
                                               "VPTERNLOGD(Z|Z256)rm(b?)i",
                                               "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
 
 def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
   let Latency = 8;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
 
 def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
                                               "RCR(8|16|32|64)m(1|i)")>;
 
 def ICXWriteResGroup128 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,3];
 }
 def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
                                               "ROR(8|16|32|64)mCL",
                                               "SAR(8|16|32|64)mCL",
                                               "SHL(8|16|32|64)mCL",
                                               "SHR(8|16|32|64)mCL")>;
 
 def ICXWriteResGroup130 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,2,1];
+  let ReleaseAtCycles = [1,1,1,2,1];
 }
 def: SchedAlias<WriteADCRMW, ICXWriteResGroup130>;
 
 def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,2,1,2,2];
+  let ReleaseAtCycles = [1,2,1,2,2];
 }
 def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
                                            VPSCATTERQDZ256mr,
                                            VSCATTERQPSZ128mr,
                                            VSCATTERQPSZ256mr)>;
 
 def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 12;
-  let ResourceCycles = [1,4,1,4,2];
+  let ReleaseAtCycles = [1,4,1,4,2];
 }
 def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
                                            VSCATTERDPSZ128mr)>;
 
 def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 20;
-  let ResourceCycles = [1,8,1,8,2];
+  let ReleaseAtCycles = [1,8,1,8,2];
 }
 def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
                                            VSCATTERDPSZ256mr)>;
 
 def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 36;
-  let ResourceCycles = [1,16,1,16,2];
+  let ReleaseAtCycles = [1,16,1,16,2];
 }
 def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
 
 def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
 
 def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm,
                                            VPMOVSXDQYrm,
                                            VPMOVSXWDYrm,
                                            VPMOVZXWDYrm)>;
 def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
                                               "VFPCLASSSDZrm(b?)",
                                               "VFPCLASSSSZrm(b?)",
def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
                                               "VPMAXSQZ128rm(b?)",
                                               "VPMAXUQZ128rm(b?)",
                                               "VPMINSQZ128rm(b?)",
                                               "VPMINUQZ128rm(b?)")>;
 
 def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
                                                 "VCMP(SD|SS)Zrm",
                                                 "VFPCLASSPDZ128rm(b?)",
                                                 "VFPCLASSPSZ128rm(b?)",
                                                 "VPCMPBZ128rmi(b?)",
                                                 "VPCMPDZ128rmi(b?)",
                                                 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
                                                 "VPTESTNMBZ128rm(b?)",
                                                 "VPTESTNMDZ128rm(b?)",
                                                 "VPTESTNMQZ128rm(b?)",
                                                 "VPTESTNMWZ128rm(b?)")>;
 
 def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort01]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
                                               "(V?)CVTPS2PDrm")>;
 
 def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> {
   let Latency = 9;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm",
                                               "(V?)PHSUBSWrm")>;
 
 def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm",
                                               "LSL(16|32|64)rm")>;
 
 def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>;
 def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                               "ILD_F(16|32|64)m",
                                               "VALIGND(Z|Z256)rm(b?)i",
                                               "VALIGNQ(Z|Z256)rm(b?)i",
                                               "VPMAXSQ(Z|Z256)rm(b?)",
                                               "VPMAXUQ(Z|Z256)rm(b?)",
                                               "VPMINSQ(Z|Z256)rm(b?)",
                                               "VPMINUQ(Z|Z256)rm(b?)")>;
 
 def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
                                                 "VCMPPS(Z|Z256)rm(b?)i",
                                                 "VFPCLASSPD(Z|Z256)rm(b?)",
                                                 "VFPCLASSPS(Z|Z256)rm(b?)",
                                                 "VPCMPB(Z|Z256)rmi(b?)",
                                                 "VPCMPD(Z|Z256)rmi(b?)",
                                                 "VPCMPEQB(Z|Z256)rm(b?)",
def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
                                                 "VPTESTM(B|D|Q|W)Z256rm(b?)",
                                                 "VPTESTM(B|D|Q|W)Zrm(b?)",
                                                 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
                                                 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
 
 def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort01]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
                                               "VCVTDQ2PSZ128rm(b?)",
                                               "(V?)CVTDQ2PSrm",
                                               "VCVTPD2QQZ128rm(b?)",
                                               "VCVTPD2UQQZ128rm(b?)",
                                               "VCVTPH2PSZ128rm(b?)",
                                               "VCVTPS2DQZ128rm(b?)",
def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
                                               "VCVTUDQ2PDZ128rm(b?)",
                                               "VCVTUDQ2PSZ128rm(b?)",
                                               "VCVTUQQ2PDZ128rm(b?)",
                                               "VCVTUQQ2PSZ128rm(b?)")>;
 
 def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
                                               "VEXPANDPSZ128rm(b?)",
                                               "VPEXPANDDZ128rm(b?)",
                                               "VPEXPANDQZ128rm(b?)")>;
 
 def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> {
   let Latency = 10;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm,
                                            VPHSUBSWYrm)>;
 
 def ICXWriteResGroup157 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 10;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,1,1,3];
 }
 def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
 
 def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
 
 def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort01]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm,
                                            VCVTPS2PDYrm)>;
 def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
                                               "VCVTPH2PS(Z|Z256)rm(b?)",
                                               "VCVTPS2PD(Z|Z256)rm(b?)",
                                               "VCVTQQ2PD(Z|Z256)rm(b?)",
                                               "VCVTQQ2PSZ256rm(b?)",
                                               "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PS2DQYrm",
                                               "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PS2QQZ256rm(b?)",
                                               "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PS2UQQZ256rm(b?)",
                                               "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
                                               "VCVTUQQ2PD(Z|Z256)rm(b?)",
                                               "VCVTUQQ2PSZ256rm(b?)")>;
 
 def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
                                               "VEXPANDPD(Z|Z256)rm(b?)",
                                               "VEXPANDPS(Z|Z256)rm(b?)",
                                               "VPEXPANDD(Z|Z256)rm(b?)",
                                               "VPEXPANDQ(Z|Z256)rm(b?)")>;
 
 def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
 
 def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2DQrm,
                                            CVTTPD2DQrm,
                                            MMX_CVTPD2PIrm,
                                            MMX_CVTTPD2PIrm)>;
 
 def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
   let Latency = 11;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
 
 def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
   let Latency = 11;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,3,2];
+  let ReleaseAtCycles = [2,3,2];
 }
 def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
                                               "RCR(16|32|64)rCL")>;
 
 def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 11;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,5,1,2];
+  let ReleaseAtCycles = [1,5,1,2];
 }
 def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>;
 
 def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
   let Latency = 11;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,9];
+  let ReleaseAtCycles = [2,9];
 }
 def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
 
 def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
 
 def ICXWriteResGroup174z : SchedWriteRes<[ICXPort0]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>;
 
 def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
 
 def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort01]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
                                               "VCVT(T?)SS2USI64Zrm(b?)")>;
 
 def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
                                               "VCVT(T?)PS2UQQZrm(b?)")>;
 
 def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
                                               "VPERMWZ256rm(b?)",
                                               "VPERMWZrm(b?)")>;
 
 def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
 
 def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
   let Latency = 13;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
                                               "VPERMT2W128rm(b?)")>;
 
 def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
 
 def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
                                               "VCVTPD2UDQZrm(b?)",
                                               "VCVTQQ2PSZrm(b?)",
                                               "VCVTTPD2DQZrm(b?)",
                                               "VCVTTPD2UDQZrm(b?)",
                                               "VCVTUQQ2PSZrm(b?)")>;
 
 def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
   let Latency = 14;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
                                               "VPERMI2Wrm(b?)",
                                               "VPERMT2W256rm(b?)",
                                               "VPERMT2Wrm(b?)")>;
 
 def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 14;
   let NumMicroOps = 10;
-  let ResourceCycles = [2,4,1,3];
+  let ReleaseAtCycles = [2,4,1,3];
 }
 def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>;
 
 def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> {
   let Latency = 15;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
 
 def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
   let Latency = 15;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,2,2,1,2];
+  let ReleaseAtCycles = [1,2,2,1,2];
 }
 def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
 
 def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort78,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 15;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,1,1,5,1,1];
+  let ReleaseAtCycles = [1,1,1,5,1,1];
 }
 def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
 
 def ICXWriteResGroup199 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 16;
   let NumMicroOps = 14;
-  let ResourceCycles = [1,1,1,4,2,5];
+  let ReleaseAtCycles = [1,1,1,4,2,5];
 }
 def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>;
 
 def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> {
   let Latency = 12;
   let NumMicroOps = 34;
-  let ResourceCycles = [1, 4, 5];
+  let ReleaseAtCycles = [1, 4, 5];
 }
 def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>;
 
 def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> {
   let Latency = 17;
   let NumMicroOps = 15;
-  let ResourceCycles = [2,1,2,4,2,4];
+  let ReleaseAtCycles = [2,1,2,4,2,4];
 }
 def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>;
 
 def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> {
   let Latency = 21;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
 
 def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,5];
+  let ReleaseAtCycles = [1,1,1,5];
 }
 def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>;
 
 def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort78,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 18;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,1,1,4,1,2];
+  let ReleaseAtCycles = [2,1,1,4,1,2];
 }
 def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
 
 def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> {
   let Latency = 22;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
 
 def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort0]> {
   let Latency = 22;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
 
 def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> {
   let Latency = 20;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
 
 def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
   let Latency = 17;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
                                            VGATHERDPDZ128rm, VPGATHERDQZ128rm,
                                            VGATHERQPDZ128rm, VPGATHERQQZ128rm)>;
 
 def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
   let Latency = 19;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,4,1,1];
+  let ReleaseAtCycles = [1,4,1,1];
 }
 def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
                                            VGATHERQPDZ256rm, VPGATHERQQZ256rm,
                                            VGATHERDPSZ128rm, VPGATHERDDZ128rm,
                                            VGATHERDPDZ256rm, VPGATHERDQZ256rm)>;
 
 def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
   let Latency = 21;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,8,1,1];
+  let ReleaseAtCycles = [1,8,1,1];
 }
 def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
                                            VGATHERDPDZrm,    VPGATHERDQZrm,
                                            VGATHERQPDZrm,    VPGATHERQQZrm,
                                            VGATHERQPSZrm,    VPGATHERQDZrm)>;
 
 def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
   let Latency = 25;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,16,1,1];
+  let ReleaseAtCycles = [1,16,1,1];
 }
 def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
 
 def ICXWriteResGroup219 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort6,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 20;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,1,1,1,2];
 }
 def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>;
 
 def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> {
   let Latency = 20;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,2,7];
+  let ReleaseAtCycles = [1,2,7];
 }
 def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>;
 
 def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> {
   let Latency = 22;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
 
 def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> {
   let Latency = 18;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
                                             VGATHERQPDrm, VPGATHERQQrm,
                                             VGATHERQPSrm, VPGATHERQDrm)>;
 
 def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> {
   let Latency = 20;
   let NumMicroOps = 5; // 2 uops peform multiple loads
-  let ResourceCycles = [1,4,1,1];
+  let ReleaseAtCycles = [1,4,1,1];
 }
 def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
                                             VGATHERDPSrm,  VPGATHERDDrm,
                                             VGATHERQPDYrm, VPGATHERQQYrm,
                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
 
 def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> {
   let Latency = 22;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,8,1,1];
+  let ReleaseAtCycles = [1,8,1,1];
 }
 def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
 
 def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> {
   let Latency = 22;
   let NumMicroOps = 14;
-  let ResourceCycles = [5,5,4];
+  let ReleaseAtCycles = [5,5,4];
 }
 def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
                                               "VPCONFLICTQZ256rr")>;
 
 def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 23;
   let NumMicroOps = 19;
-  let ResourceCycles = [2,1,4,1,1,4,6];
+  let ReleaseAtCycles = [2,1,4,1,1,4,6];
 }
 def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>;
 
 def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
   let Latency = 25;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
 
 def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> {
   let Latency = 27;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
 
 def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
   let Latency = 29;
   let NumMicroOps = 15;
-  let ResourceCycles = [5,5,1,4];
+  let ReleaseAtCycles = [5,5,1,4];
 }
 def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
 
 def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
   let Latency = 30;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
 
 def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,3,4,10];
+  let ReleaseAtCycles = [1,5,3,4,10];
 }
 def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri",
                                               "IN(8|16|32)rr")>;
 
 def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,2,1,4,10];
+  let ReleaseAtCycles = [1,5,2,1,4,10];
 }
 def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir",
                                               "OUT(8|16|32)rr")>;
 
 def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> {
   let Latency = 37;
   let NumMicroOps = 21;
-  let ResourceCycles = [9,7,5];
+  let ReleaseAtCycles = [9,7,5];
 }
 def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
                                               "VPCONFLICTQZrr")>;
 
 def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> {
   let Latency = 37;
   let NumMicroOps = 31;
-  let ResourceCycles = [1,8,1,21];
+  let ReleaseAtCycles = [1,8,1,21];
 }
 def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>;
 
 def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort49,ICXPort5,ICXPort6,ICXPort23,ICXPort78,ICXPort15,ICXPort0156]> {
   let Latency = 40;
   let NumMicroOps = 18;
-  let ResourceCycles = [1,1,2,3,1,1,1,8];
+  let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
 }
 def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>;
 
 def ICXWriteResGroup253 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort0156]> {
   let Latency = 41;
   let NumMicroOps = 39;
-  let ResourceCycles = [1,10,1,1,26];
+  let ReleaseAtCycles = [1,10,1,1,26];
 }
 def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>;
 
 def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> {
   let Latency = 42;
   let NumMicroOps = 22;
-  let ResourceCycles = [2,20];
+  let ReleaseAtCycles = [2,20];
 }
 def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>;
 
 def ICXWriteResGroup255 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort0156]> {
   let Latency = 42;
   let NumMicroOps = 40;
-  let ResourceCycles = [1,11,1,1,26];
+  let ReleaseAtCycles = [1,11,1,1,26];
 }
 def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>;
 def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
 
 def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
   let Latency = 44;
   let NumMicroOps = 22;
-  let ResourceCycles = [9,7,1,5];
+  let ReleaseAtCycles = [9,7,1,5];
 }
 def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
                                               "VPCONFLICTQZrm(b?)")>;
 
 def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> {
   let Latency = 62;
   let NumMicroOps = 64;
-  let ResourceCycles = [2,8,5,10,39];
+  let ReleaseAtCycles = [2,8,5,10,39];
 }
 def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>;
 
 def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 63;
   let NumMicroOps = 88;
-  let ResourceCycles = [4,4,31,1,2,1,45];
+  let ReleaseAtCycles = [4,4,31,1,2,1,45];
 }
 def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>;
 
 def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> {
   let Latency = 63;
   let NumMicroOps = 90;
-  let ResourceCycles = [4,2,33,1,2,1,47];
+  let ReleaseAtCycles = [4,2,33,1,2,1,47];
 }
 def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>;
 
 def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> {
   let Latency = 67;
   let NumMicroOps = 35;
-  let ResourceCycles = [17,11,7];
+  let ReleaseAtCycles = [17,11,7];
 }
 def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
 
 def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
   let Latency = 74;
   let NumMicroOps = 36;
-  let ResourceCycles = [17,11,1,7];
+  let ReleaseAtCycles = [17,11,1,7];
 }
 def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
 
 def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> {
   let Latency = 75;
   let NumMicroOps = 15;
-  let ResourceCycles = [6,3,6];
+  let ReleaseAtCycles = [6,3,6];
 }
 def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>;
 
 def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort49,ICXPort5,ICXPort6,ICXPort78,ICXPort06,ICXPort0156]> {
   let Latency = 106;
   let NumMicroOps = 100;
-  let ResourceCycles = [9,1,11,16,1,11,21,30];
+  let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
 }
 def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>;
 
 def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
   let Latency = 140;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>;
 
 def: InstRW<[WriteZero], (instrs CLC)>;
 
 
 // Instruction variants handled by the renamer. These might not need execution
 // ports in certain conditions.

 ]>;
 def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
                                                VPCMPGTDYrr,
                                                VPCMPGTWYrr)>;
 
 def ICXWritePSUB : SchedWriteRes<[ICXPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [ICXWritePSUB]>
 ]>;
 
 def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
                                                PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
                                                PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
                                                PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
                                                VPSUBBYrr, VPSUBBZ256rr,
                                                VPSUBDYrr, VPSUBDZ256rr,
                                                VPSUBQYrr, VPSUBQZ256rr,
                                                VPSUBWYrr, VPSUBWZ256rr,
                                                VPSUBBZrr,
                                                VPSUBDZrr,
                                                VPSUBQZrr,
                                                VPSUBWZrr)>;
 def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [ICXWritePCMPGTQ]>
 ]>;
 def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
                                                   VPCMPGTQYrr)>;
 
 
 // CMOVs that use both Z and C flag require an extra uop.
 def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> {
   let Latency = 7;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
   let NumMicroOps = 3;
 }
 
 def ICXCMOVA_CMOVBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [ICXWriteCMOVA_CMOVBErr]>,
   SchedVar<NoSchedPred,                             [WriteCMOV]>
 ]>;
 
 def ICXCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [ICXWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[ICXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 // SETCCs that use both Z and C flag require an extra uop.
 def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort06]> {
   let Latency = 3;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
   let NumMicroOps = 4;
 }
 
 def ICXSETA_SETBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [ICXWriteSETA_SETBEr]>,
   SchedVar<NoSchedPred,                         [WriteSETCC]>
 ]>;
 

llvm/lib/Target/X86/X86SchedSandyBridge.td

 // folded loads.
 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [1], int UOps = 1,
                           int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
 

 ////////////////////////////////////////////////////////////////////////////////
 // String instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 // Packed Compare Implicit Length Strings, Return Mask
 def : WriteRes<WritePCmpIStrM, [SBPort0]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
   let Latency = 17;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
   let Latency = 11;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
   let Latency = 17;
-  let ResourceCycles = [7, 1];
+  let ReleaseAtCycles = [7, 1];
 }
 
 // Packed Compare Implicit Length Strings, Return Index
 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
   let Latency = 17;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
   let Latency = 10;
-  let ResourceCycles = [7, 1];
+  let ReleaseAtCycles = [7, 1];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK,    [SBPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSK,  [SBPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; }
 def : WriteRes<WriteMMXMOVMSK,  [SBPort0]> { let Latency = 1; }
 
 // AES Instructions.
 def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 
 def : WriteRes<WriteAESIMC, [SBPort5]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
   let Latency = 18;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 
 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
   let Latency = 8;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
   let Latency = 14;
-  let ResourceCycles = [10, 1];
+  let ReleaseAtCycles = [10, 1];
 }
 
 // Carry-less multiplication instructions.
 def : WriteRes<WriteCLMul, [SBPort015]> {
   let Latency = 14;
-  let ResourceCycles = [18];
+  let ReleaseAtCycles = [18];
 }
 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
   let Latency = 20;
-  let ResourceCycles = [17, 1];
+  let ReleaseAtCycles = [17, 1];
 }
 
 // Load/store MXCSR.
 // FIXME: This is probably wrong. Only STMXCSR should require Port4.
-def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ReleaseAtCycles = [1,1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ReleaseAtCycles = [1,1,1,1]; }
 
 def : WriteRes<WriteSystem,     [SBPort015]> { let Latency = 100; }
 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
 def : WriteRes<WriteNop, []>;
 
 // AVX2/FMA is not supported on that architecture, but we should define the basic
 // scheduling resources anyway.
 defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>;
 defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>;
 defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>;
 defm : SBWriteResPair<WriteVPMOV256, [SBPort5], 1, [1], 1, 7>;
 defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>;
 defm : SBWriteResPair<WriteFMA,  [SBPort01],  5>;
 defm : SBWriteResPair<WriteFMAX, [SBPort01],  5>;
 defm : SBWriteResPair<WriteFMAY, [SBPort01],  5>;
 defm : SBWriteResPair<WriteFMAZ, [SBPort01],  5>;  // Unsupported = 1
 
 // Remaining SNB instrs.
 
 def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
                                         COM_FST0r,
                                         UCOM_FPr,
                                         UCOM_Fr)>;
 
 def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
                                         LD_Frr, ST_Frr, ST_FPrr)>;
 def: InstRW<[SBWriteResGroup2], (instrs RET64)>;
 
 def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
 
 def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
                                         MMX_PABSDrr,
                                         MMX_PABSWrr,
                                         MMX_PADDQrr,
                                         MMX_PALIGNRrri,
                                         MMX_PSIGNBrr,
                                         MMX_PSIGNDrr,
                                         MMX_PSIGNWrr)>;
 
 def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SBWriteResGroup11], (instrs SCASB,
                                          SCASL,
                                          SCASQ,
                                          SCASW)>;
 
 def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>;
 
 def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup15], (instrs CWD,
                                          FNSTSW16r)>;
 
 def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
                                          MMX_MOVDQ2Qrr)>;
 
 def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>;
 
 def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
   let Latency = 3;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
 
 def SBWriteResGroup23 : SchedWriteRes<[SBPort05,SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SBWriteResGroup23], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                          RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def SBWriteResGroup24 : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
   let Latency = 3;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,4,2];
+  let ReleaseAtCycles = [1,1,4,2];
 }
 def: InstRW<[SBWriteResGroup24], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def SBWriteResGroup24b : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
   let Latency = 4;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,4,2];
+  let ReleaseAtCycles = [1,1,4,2];
 }
 def: InstRW<[SBWriteResGroup24b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>;
 
 def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 
 def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>;
 
 def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
 
 def SBWriteResGroup30 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
   let Latency = 3;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,3,4];
+  let ReleaseAtCycles = [1,3,4];
 }
 def: InstRW<[SBWriteResGroup30], (instrs LOOP)>;
 
 def SBWriteResGroup31 : SchedWriteRes<[SBPort1,SBPort5,SBPort015,SBPort05]> {
   let Latency = 4;
   let NumMicroOps = 12;
-  let ResourceCycles = [1,3,6,2];
+  let ReleaseAtCycles = [1,3,6,2];
 }
 def: InstRW<[SBWriteResGroup31], (instrs LOOPE, LOOPNE)>;
 
 def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> {
   let Latency = 5;
   let NumMicroOps = 8;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)rCL",
                                             "RCR(8|16|32|64)rCL")>;
 
 def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
 
 def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SBWriteResGroup35], (instrs CLI)>;
 
 def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>;
 def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
 
 def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>;
 def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
                                             "(V?)EXTRACTPSmr")>;
 
 def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>;
 
 def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
 
 def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
                                             "PUSHF(16|64)")>;
 
 def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
 
 def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
 
 def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup48], (instrs VBROADCASTSSrm)>;
 def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
                                             "(V?)MOV64toPQIrm",
                                             "(V?)MOVDDUPrm",
                                             "(V?)MOVDI2PDIrm",
                                             "(V?)MOVQI2PQIrm",
                                             "(V?)MOVSDrm",
                                             "(V?)MOVSHDUPrm",
                                             "(V?)MOVSLDUPrm",
                                             "(V?)MOVSSrm")>;
 
 def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
 
 def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
                                          MMX_PABSDrm,
                                          MMX_PABSWrm,
                                          MMX_PALIGNRrmi,
                                          MMX_PSIGNBrm,
                                          MMX_PSIGNDrm,
                                          MMX_PSIGNWrm)>;
 
 def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>;
 
 def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
                                             "ST_FP(32|64|80)m")>;
 
 def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
                                          VBROADCASTSSYrm,
                                          VMOVDDUPYrm,
                                          VMOVSHDUPYrm,
                                          VMOVSLDUPYrm)>;
 
 def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>;
 
 def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQrm)>;
 
 def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>;
 
 def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>;
 
 def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup64], (instrs FARJMP64m)>;
 
 def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>;
 
 def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
                                             "STR(16|32|64)r")>;
 
 def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>;
 def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
 
 def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
                                             "SHL(8|16|32|64)m(1|i)",
                                             "SHR(8|16|32|64)m(1|i)")>;
 
 def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
   let Latency = 8;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
 
 def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
 }
 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>;
 
 def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [2,3];
+  let ReleaseAtCycles = [2,3];
 }
 def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
                                          CMPSL,
                                          CMPSQ,
                                          CMPSW)>;
 
 def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,2];
+  let ReleaseAtCycles = [1,2,2];
 }
 def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>;
 
 def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,2];
+  let ReleaseAtCycles = [1,2,2];
 }
 def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
                                             "ROR(8|16|32|64)m(1|i)")>;
 
 def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,2];
+  let ReleaseAtCycles = [1,2,2];
 }
 def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
 def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
 
 def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SBWriteResGroup87], (instrs FARCALL64m)>;
 
 def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
   let Latency = 9;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>;
 
 def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
   let Latency = 9;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
                                             "IST_FP(16|32|64)m")>;
 
 def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
   let Latency = 9;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,2,3];
+  let ReleaseAtCycles = [1,2,3];
 }
 def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
                                               "ROR(8|16|32|64)mCL",
                                               "SAR(8|16|32|64)mCL",
                                               "SHL(8|16|32|64)mCL",
                                               "SHR(8|16|32|64)mCL")>;
 
 def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
   let Latency = 9;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,3];
+  let ReleaseAtCycles = [1,2,3];
 }
 def: SchedAlias<WriteADCRMW, SBWriteResGroup98>;
 
 def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
   let Latency = 9;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,2,1];
+  let ReleaseAtCycles = [1,2,2,1];
 }
 def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
                                                       SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
 
 def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
   let Latency = 9;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,2,1,1];
+  let ReleaseAtCycles = [1,1,2,1,1];
 }
 def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW
 
 def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                              "ILD_F(16|32|64)m")>;
 
 def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>;
 
 def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>;
 
 def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
   let Latency = 11;
   let NumMicroOps = 11;
-  let ResourceCycles = [7,4];
+  let ReleaseAtCycles = [7,4];
 }
 def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
                                              "RCR(8|16|32|64)m")>;
 
 def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>;
 
 def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
 
 def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>;
 
 def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
   let Latency = 31;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>;
 
 def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
   let Latency = 34;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
 
 def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> {
   let Latency = 9;
   let NumMicroOps = 20;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>;
 
 def SBWriteResGroupVzeroupper : SchedWriteRes<[]> {
   let Latency = 1;
   let NumMicroOps = 4;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
 }
 def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>;
 
 def: InstRW<[WriteZero], (instrs CLC)>;
 
 // Instruction variants handled by the renamer. These might not need execution
 // ports in certain conditions.
 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
                                               PSUBWrr, VPSUBWrr,
                                               PCMPGTBrr, VPCMPGTBrr,
                                               PCMPGTDrr, VPCMPGTDrr,
                                               PCMPGTWrr, VPCMPGTWrr)>;
 
 def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [SBWritePCMPGTQ]>
 ]>;
 def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>;
 
 // CMOVs that use both Z and C flag require an extra uop.
 def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> {
   let Latency = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
   let NumMicroOps = 3;
 }
 
 def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
   let Latency = 8;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
   let NumMicroOps = 4;
 }
 
 def SBCMOVA_CMOVBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SBWriteCMOVA_CMOVBErr]>,
   SchedVar<NoSchedPred,                             [WriteCMOV]>
 ]>;
 
 def SBCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 // SETCCs that use both Z and C flag require an extra uop.
 def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
   let Latency = 3;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
   let NumMicroOps = 4;
 }
 
 def SBSETA_SETBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>,
   SchedVar<NoSchedPred,                         [WriteSETCC]>
 ]>;
 

llvm/lib/Target/X86/X86SchedSapphireRapids.td

 // folded loads.
 multiclass SPRWriteResPair<X86FoldableSchedWrite SchedRW,
                            list<ProcResourceKind> ExePorts,
                            int Lat, list<int> Res = [1], int UOps = 1,
                            int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([SPRPort02_03_11], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 //===----------------------------------------------------------------------===//
 // The following definitons are infered by smg.
 //===----------------------------------------------------------------------===//
 

 def : WriteRes<WriteFSign, [SPRPort00]>;
 defm : SPRWriteResPair<WriteFSqrt, [SPRPort00], 12, [1], 1, 7>;
 defm : SPRWriteResPair<WriteFSqrt64, [SPRPort00], 18, [1]>;
 defm : SPRWriteResPair<WriteFSqrt64X, [SPRPort00], 18, [1], 1, 6>;
 defm : SPRWriteResPair<WriteFSqrt64Y, [SPRPort00], 18, [1], 1, 3>;
 // Warning: negtive load latency.
 defm : SPRWriteResPair<WriteFSqrt64Z, [SPRPort00, SPRPort00_05], 32, [2, 1], 3, -1>;
 def : WriteRes<WriteFSqrt80, [SPRPortInvalid, SPRPort00]> {
-  let ResourceCycles = [7, 1];
+  let ReleaseAtCycles = [7, 1];
   let Latency = 21;
 }
 defm : SPRWriteResPair<WriteFSqrtX, [SPRPort00], 12, [1], 1, 7>;
 defm : SPRWriteResPair<WriteFSqrtY, [SPRPort00], 12, [1], 1, 8>;
 defm : SPRWriteResPair<WriteFSqrtZ, [SPRPort00, SPRPort00_05], 20, [2, 1], 3, 7>;
 defm : X86WriteRes<WriteFStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
 defm : X86WriteResUnsupported<WriteFStoreNT>;
 defm : X86WriteRes<WriteFStoreNTX, [SPRPort04_09, SPRPort07_08], 518, [1, 1], 2>;

 def SPRWriteResGroup0 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup0], (instregex "^AA(D|N)D64mr$",
                                              "^A(X?)OR64mr$")>;
 
 def SPRWriteResGroup1 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1, 1];
   let Latency = 12;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
 
 def SPRWriteResGroup2 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup2], (instregex "^RORX(32|64)mi$")>;
 def : InstRW<[SPRWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
                                                                                                                                         "^AD(C|O)X(32|64)rm$")>;
 
 def SPRWriteResGroup3 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
   let Latency = 13;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
 
 def SPRWriteResGroup4 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1, 1];
   let Latency = 13;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
 
 def SPRWriteResGroup5 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;

 def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)rm$",
                                                                "^VPERM(I|T)2(D|Q|PS)128rm((b|k|bk|kz)?)$",
                                                                "^VPERM(I|T)2(D|Q|PS)128rmbkz$",
                                                                "^VPERM(I|T)2PD128rm((b|k|bk|kz)?)$",
                                                                "^VPERM(I|T)2PD128rmbkz$")>;
 def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instrs VPERMBZ128rm)>;
 
 def SPRWriteResGroup11 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup11], (instregex "^ADD_FI(16|32)m$",
                                               "^SUB(R?)_FI(16|32)m$")>;
 def : InstRW<[SPRWriteResGroup11, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
 def : InstRW<[SPRWriteResGroup11, ReadAfterVecYLd], (instregex "^VPEXPAND(B|W)Z(128|256)rmk(z?)$",
                                                                "^VPEXPAND(B|W)Zrmk(z?)$")>;

 def : InstRW<[SPRWriteResGroup15, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
 
 def SPRWriteResGroup16 : SchedWriteRes<[SPRPort01_05_10]> {
   let Latency = 2;
 }
 def : InstRW<[SPRWriteResGroup16], (instregex "^ANDN(32|64)rr$")>;
 
 def SPRWriteResGroup17 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [5, 2, 1, 1];
+  let ReleaseAtCycles = [5, 2, 1, 1];
   let Latency = 10;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup17], (instrs BT64mr)>;
 
 def SPRWriteResGroup18 : SchedWriteRes<[SPRPort01]> {
   let Latency = 3;
 }
 def : InstRW<[SPRWriteResGroup18], (instregex "^BT((C|R|S)?)64rr$",
                                               "^P(DEP|EXT)(32|64)rr$")>;
 
 def SPRWriteResGroup19 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [4, 2, 1, 1, 1, 1];
+  let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
   let Latency = 17;
   let NumMicroOps = 10;
 }
 def : InstRW<[SPRWriteResGroup19], (instregex "^BT(C|R|S)64mr$")>;
 
 def SPRWriteResGroup20 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
   let Latency = 7;
   let NumMicroOps = 5;

 
 def SPRWriteResGroup28 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup28], (instrs CLFLUSHOPT)>;
 
 def SPRWriteResGroup29 : SchedWriteRes<[SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup29], (instrs CLI)>;
 
 def SPRWriteResGroup30 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort05]> {
-  let ResourceCycles = [6, 1, 3];
+  let ReleaseAtCycles = [6, 1, 3];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 10;
 }
 def : InstRW<[SPRWriteResGroup30], (instrs CLTS)>;
 
 def SPRWriteResGroup31 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup31], (instregex "^MOV16o(16|32|64)a$")>;
 def : InstRW<[SPRWriteResGroup31], (instrs CLWB)>;
 
 def SPRWriteResGroup32 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
-  let ResourceCycles = [5, 2];
+  let ReleaseAtCycles = [5, 2];
   let Latency = 6;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup32], (instregex "^CMPS(B|L|Q|W)$")>;
 
 def SPRWriteResGroup33 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
+  let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
   let Latency = 32;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup33], (instrs CMPXCHG16B)>;
 
 def SPRWriteResGroup34 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [4, 7, 2, 1, 1, 1];
+  let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
   let Latency = 25;
   let NumMicroOps = 16;
 }
 def : InstRW<[SPRWriteResGroup34], (instrs CMPXCHG8B)>;
 
 def SPRWriteResGroup35 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 1, 1, 1];
+  let ReleaseAtCycles = [1, 2, 1, 1, 1];
   let Latency = 13;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup35], (instrs CMPXCHG8rm)>;
 
 def SPRWriteResGroup36 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
+  let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
   let Latency = 18;
   let NumMicroOps = 26;
 }
 def : InstRW<[SPRWriteResGroup36], (instrs CPUID)>;
 
 def SPRWriteResGroup37 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
   let Latency = 12;
   let NumMicroOps = 3;
def : InstRW<[SPRWriteResGroup39], (instregex "^VCVT(T?)PS2(U?)QQZ256rr((k|kz)?)$",
                                               "^VCVT(U?)QQ2PSZ256rr((k|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup39, ReadInt2Fpu], (instrs CVTSI2SSrr)>;
 def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI2SSrr_Int$",
                                                                         "^VCVT(U?)SI2SSZrr$",
                                                                         "^VCVT(U?)SI2SSZrr(b?)_Int$")>;
 def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instrs VCVTSI2SSrr)>;
 
 def SPRWriteResGroup40 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 8;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup40, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
 def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$",
                                                                         "^VCVT(U?)SI642SSZrr$",
                                                                         "^VCVT(U?)SI642SSZrr(b?)_Int$")>;
 def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;

 
 def SPRWriteResGroup52 : SchedWriteRes<[SPRPort04, SPRPort04_09]>;
 def : InstRW<[SPRWriteResGroup52], (instregex "^ENQCMD(S?)(16|32|64)$",
                                               "^PUSHA(16|32)$",
                                               "^ST_F(32|64)m$")>;
 def : InstRW<[SPRWriteResGroup52], (instrs PUSHF32)>;
 
 def SPRWriteResGroup53 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
+  let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
   let Latency = 126;
   let NumMicroOps = 57;
 }
 def : InstRW<[SPRWriteResGroup53], (instrs ENTER)>;
 
 def SPRWriteResGroup54 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
def SPRWriteResGroup58 : SchedWriteRes<[SPRPort04, SPRPort04_09]> {
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup58], (instregex "^(V?)MASKMOVDQU((64)?)$",
                                               "^ST_FP(32|64|80)m$")>;
 def : InstRW<[SPRWriteResGroup58], (instrs FBSTPm,
                                            VMPTRSTm)>;
 
 def SPRWriteResGroup59 : SchedWriteRes<[SPRPort00_05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup59], (instrs FDECSTP)>;
 
 def SPRWriteResGroup60 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 11;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup60], (instregex "^FICOM(P?)(16|32)m$")>;
 def : InstRW<[SPRWriteResGroup60, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z((256)?)rm((k|kz)?)$",
                                                                "^VPEXPAND(B|D|Q|W)Z((256)?)rm$",
                                                                "^VPEXPAND(D|Q)Z((256)?)rmk(z?)$")>;
 
 def SPRWriteResGroup61 : SchedWriteRes<[SPRPort00_05]>;
 def : InstRW<[SPRWriteResGroup61], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$",
                                               "^VP(ADD|SUB)(B|D|Q|W)Zrr$",
                                               "^VP(ADD|SUB)(D|Q)Zrrk(z?)$",
                                               "^VPTERNLOG(D|Q)Zrri((k|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup61], (instrs FINCSTP,
                                            FNOP)>;
 
 def SPRWriteResGroup62 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup62], (instrs FLDCW16m)>;
 
 def SPRWriteResGroup63 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 5, 10, 39, 8];
+  let ReleaseAtCycles = [2, 5, 10, 39, 8];
   let Latency = 62;
   let NumMicroOps = 64;
 }
 def : InstRW<[SPRWriteResGroup63], (instrs FLDENVm)>;
 
 def SPRWriteResGroup64 : SchedWriteRes<[SPRPort00_01_05_06]> {
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let Latency = 4;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup64], (instrs FNCLEX)>;
 
 def SPRWriteResGroup65 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [6, 3, 6];
+  let ReleaseAtCycles = [6, 3, 6];
   let Latency = 75;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup65], (instrs FNINIT)>;
 
 def SPRWriteResGroup66 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort06]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup66], (instrs FNSTCW16m)>;
 
 def SPRWriteResGroup67 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup67], (instrs FNSTSW16r)>;
 
 def SPRWriteResGroup68 : SchedWriteRes<[SPRPort00, SPRPort04, SPRPort04_09]> {
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup68], (instrs FNSTSWm)>;
 
 def SPRWriteResGroup69 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_06, SPRPort01, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
-  let ResourceCycles = [9, 11, 21, 1, 30, 11, 16, 1];
+  let ReleaseAtCycles = [9, 11, 21, 1, 30, 11, 16, 1];
   let Latency = 106;
   let NumMicroOps = 100;
 }
 def : InstRW<[SPRWriteResGroup69], (instrs FSTENVm)>;
 
 def SPRWriteResGroup70 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
-  let ResourceCycles = [4, 1, 2, 1, 47, 33, 2];
+  let ReleaseAtCycles = [4, 1, 2, 1, 47, 33, 2];
   let Latency = 63;
   let NumMicroOps = 90;
 }
 def : InstRW<[SPRWriteResGroup70], (instrs FXRSTOR)>;
 
 def SPRWriteResGroup71 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
-  let ResourceCycles = [4, 1, 2, 1, 45, 31, 4];
+  let ReleaseAtCycles = [4, 1, 2, 1, 45, 31, 4];
   let Latency = 63;
   let NumMicroOps = 88;
 }
 def : InstRW<[SPRWriteResGroup71], (instrs FXRSTOR64)>;
 
 def SPRWriteResGroup72 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
+  let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 110;
 }
 def : InstRW<[SPRWriteResGroup72], (instregex "^FXSAVE((64)?)$")>;
 
 def SPRWriteResGroup73 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
   let Latency = 12;
   let NumMicroOps = 2;
def : InstRW<[SPRWriteResGroup74], (instregex "^(V?)GF2P8MULBrr$",
                                               "^VM(AX|IN)CSHZrr$",
                                               "^VM(AX|IN|UL)PHZ(128|256)rr$",
                                               "^VM(AX|IN|UL)SHZrr$",
                                               "^VM(AX|IN|UL)SHZrr(b?)_Int$")>;
 def : InstRW<[SPRWriteResGroup74], (instrs VCVTSH2SSZrr,
                                            VGF2P8MULBYrr)>;
 
 def SPRWriteResGroup75 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
+  let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];
   let Latency = 35;
   let NumMicroOps = 87;
 }
 def : InstRW<[SPRWriteResGroup75], (instrs IN16ri)>;
 
 def SPRWriteResGroup76 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
+  let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];
   let Latency = 35;
   let NumMicroOps = 87;
 }
 def : InstRW<[SPRWriteResGroup76], (instrs IN16rr)>;
 
 def SPRWriteResGroup77 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
+  let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];
   let Latency = 35;
   let NumMicroOps = 94;
 }
 def : InstRW<[SPRWriteResGroup77], (instrs IN32ri)>;
 
 def SPRWriteResGroup78 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
+  let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];
   let NumMicroOps = 99;
 }
 def : InstRW<[SPRWriteResGroup78], (instrs IN32rr)>;
 
 def SPRWriteResGroup79 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
+  let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];
   let Latency = 35;
   let NumMicroOps = 87;
 }
 def : InstRW<[SPRWriteResGroup79], (instrs IN8ri)>;
 
 def SPRWriteResGroup80 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
+  let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];
   let Latency = 35;
   let NumMicroOps = 86;
 }
 def : InstRW<[SPRWriteResGroup80], (instrs IN8rr)>;
 
 def SPRWriteResGroup81 : SchedWriteRes<[SPRPort00_06]> {
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup81], (instrs INC16r_alt)>;
 
 def SPRWriteResGroup82 : SchedWriteRes<[SPRPort02_03_11]> {
   let Latency = 7;
 }
 def : InstRW<[SPRWriteResGroup82], (instregex "^LD_F(32|64|80)m$",
                                               "^(V?)MOV(D|SH|SL)DUPrm$",
                                               "^VBROADCASTSS((Z128)?)rm$",
                                               "^VMOV(D|SH|SL)DUPZ128rm$",
                                               "^VPBROADCAST(D|Q)((Z128)?)rm$")>;
 def : InstRW<[SPRWriteResGroup82], (instrs INC32r_alt,
                                            VBROADCASTI32X2Z128rm)>;
 
 def SPRWriteResGroup83 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
+  let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];
   let Latency = 20;
   let NumMicroOps = 83;
 }
 def : InstRW<[SPRWriteResGroup83], (instrs INSB)>;
 
 def SPRWriteResGroup84 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
+  let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
   let Latency = 20;
   let NumMicroOps = 92;
 }
 def : InstRW<[SPRWriteResGroup84], (instrs INSL)>;
 
 def SPRWriteResGroup85 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
+  let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
   let Latency = 20;
   let NumMicroOps = 86;
 }
 def : InstRW<[SPRWriteResGroup85], (instrs INSW)>;
 
 def SPRWriteResGroup86 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
+  let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 42;
 }
 def : InstRW<[SPRWriteResGroup86], (instrs INVLPG)>;
 
 def SPRWriteResGroup87 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort05]> {
   let Latency = 4;
   let NumMicroOps = 3;
def : InstRW<[SPRWriteResGroup96], (instregex "^K((OR)?)TEST(B|D|Q|W)rr$",
                                               "^VPS(L|R)LVWZrrk(z?)$",
                                               "^VPS(L|R)LWZrik(z?)$",
                                               "^VPSRAVWZrrk(z?)$",
                                               "^VPSRAWZrik(z?)$",
                                               "^VPSUBUS(B|W)Zrrk(z?)$")>;
 def : InstRW<[SPRWriteResGroup96], (instrs VMOVSDto64Zrr)>;
 
 def SPRWriteResGroup97 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [8, 2, 14, 3, 1];
+  let ReleaseAtCycles = [8, 2, 14, 3, 1];
   let Latency = 198;
   let NumMicroOps = 81;
 }
 def : InstRW<[SPRWriteResGroup97], (instrs LAR16rm)>;
 
 def SPRWriteResGroup98 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
   let Latency = 66;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup98], (instrs LAR16rr)>;
 
 def SPRWriteResGroup99 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
+  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
   let Latency = 71;
   let NumMicroOps = 85;
 }
 def : InstRW<[SPRWriteResGroup99], (instrs LAR32rm)>;
 
 def SPRWriteResGroup100 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
   let Latency = 65;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup100], (instregex "^LAR(32|64)rr$")>;
 
 def SPRWriteResGroup101 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
+  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
   let Latency = 71;
   let NumMicroOps = 87;
 }
 def : InstRW<[SPRWriteResGroup101], (instrs LAR64rm)>;
 
 def SPRWriteResGroup102 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup102], (instrs LEA16r)>;
 
 def SPRWriteResGroup103 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 6;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup103], (instregex "^LODS(B|W)$",
                                                "^SCAS(B|L|Q|W)$")>;
 def : InstRW<[SPRWriteResGroup103], (instrs LEAVE)>;
 
 def SPRWriteResGroup104 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup104], (instrs LEAVE64)>;
 
 def SPRWriteResGroup105 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
+  let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 14;
 }
 def : InstRW<[SPRWriteResGroup105], (instrs LGDT64m)>;
 
 def SPRWriteResGroup106 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
+  let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 14;
 }
 def : InstRW<[SPRWriteResGroup106], (instrs LIDT64m)>;
 
 def SPRWriteResGroup107 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [5, 3, 2, 1, 1];
+  let ReleaseAtCycles = [5, 3, 2, 1, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 12;
 }
 def : InstRW<[SPRWriteResGroup107], (instrs LLDT16m)>;
 
 def SPRWriteResGroup108 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 4, 3, 1, 1, 1];
+  let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 11;
 }
 def : InstRW<[SPRWriteResGroup108], (instrs LLDT16r)>;
 
 def SPRWriteResGroup109 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
+  let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 27;
 }
 def : InstRW<[SPRWriteResGroup109], (instrs LMSW16m)>;
 
 def SPRWriteResGroup110 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [5, 7, 1, 2, 5, 2];
+  let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup110], (instrs LMSW16r)>;
 
 def SPRWriteResGroup111 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup111], (instregex "^LODS(L|Q)$")>;
 
 def SPRWriteResGroup112 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [2, 4, 1];
+  let ReleaseAtCycles = [2, 4, 1];
   let Latency = 3;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup112], (instrs LOOP)>;
 
 def SPRWriteResGroup113 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [4, 6, 1];
+  let ReleaseAtCycles = [4, 6, 1];
   let Latency = 3;
   let NumMicroOps = 11;
 }
 def : InstRW<[SPRWriteResGroup113], (instrs LOOPE)>;
 
 def SPRWriteResGroup114 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [4, 6, 1];
+  let ReleaseAtCycles = [4, 6, 1];
   let Latency = 2;
   let NumMicroOps = 11;
 }
 def : InstRW<[SPRWriteResGroup114], (instrs LOOPNE)>;
 
 def SPRWriteResGroup115 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup115], (instrs LRET64)>;
 
 def SPRWriteResGroup116 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 5, 3, 3, 1];
+  let ReleaseAtCycles = [1, 5, 3, 3, 1];
   let Latency = 70;
   let NumMicroOps = 13;
 }
 def : InstRW<[SPRWriteResGroup116], (instregex "^LSL(16|32|64)rm$")>;
 
 def SPRWriteResGroup117 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 4, 4, 3, 2, 1];
+  let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];
   let Latency = 63;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup117], (instregex "^LSL(16|32|64)rr$")>;
 
 def SPRWriteResGroup118 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
   let Latency = 24;
   let NumMicroOps = 3;

 
 def SPRWriteResGroup123 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup123], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
 
 def SPRWriteResGroup124 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup124], (instregex "^MMX_MASKMOVQ((64)?)$")>;
 
 def SPRWriteResGroup125 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let Latency = 18;
   let NumMicroOps = 2;

 
 def SPRWriteResGroup128 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
 
 def SPRWriteResGroup129 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
 def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
 
 def SPRWriteResGroup130 : SchedWriteRes<[SPRPort05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 4;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup130], (instregex "^MMX_PACKSS(DW|WB)rr$",
                                                "^VPMOV(D|Q|W|SQ|SW)BZrr$",
                                                "^VPMOV((S|US)?)(D|Q)WZrr$",
                                                "^VPMOV(U?)S(DB|QD)Zrr$",
                                                "^VPMOV(U?)SQDZrrk(z?)$",
def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(32|64)x4Zrm((k|kz)?)$",
                                                                 "^VP(ADD|SUB)(B|D|Q|W)Zrm$",
                                                                 "^VP(ADD|SUB)(D|Q)Zrm(b|k|kz)$",
                                                                 "^VP(ADD|SUB)(D|Q)Zrmbk(z?)$",
                                                                 "^VPTERNLOG(D|Q)Zrm(bi|ik)$",
                                                                 "^VPTERNLOG(D|Q)Zrmbik(z?)$",
                                                                 "^VPTERNLOG(D|Q)Zrmi((kz)?)$")>;
 
 def SPRWriteResGroup132 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 11;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup132, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
 
 def SPRWriteResGroup133 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup133], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
 
 def SPRWriteResGroup134 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
   let Latency = 9;
   let NumMicroOps = 2;

 def : InstRW<[SPRWriteResGroup141], (instrs MOVZX32rr8_NOREX)>;
 
 def SPRWriteResGroup142 : SchedWriteRes<[SPRPort02_03_11]> {
   let Latency = 5;
 }
 def : InstRW<[SPRWriteResGroup142], (instrs MOV64ao32)>;
 
 def SPRWriteResGroup143 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
+  let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
   let Latency = 217;
   let NumMicroOps = 48;
 }
 def : InstRW<[SPRWriteResGroup143], (instrs MOV64dr)>;
 
 def SPRWriteResGroup144 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup144], (instrs MOV64o32a)>;
 
 def SPRWriteResGroup145 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort05]> {
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup145], (instrs MOV64rc)>;
 
 def SPRWriteResGroup146 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort05]> {
-  let ResourceCycles = [3, 4, 8, 4, 2, 3];
+  let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];
   let Latency = 181;
   let NumMicroOps = 24;
 }
 def : InstRW<[SPRWriteResGroup146], (instrs MOV64rd)>;
 
 def SPRWriteResGroup147 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
   let NumMicroOps = 2;
 }

 
 def SPRWriteResGroup158 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let Latency = 518;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup158], (instrs MOVNTImr)>;
 
 def SPRWriteResGroup159 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [4, 1, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1, 1];
   let Latency = 8;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup159], (instrs MOVSB)>;
 
 def SPRWriteResGroup160 : SchedWriteRes<[SPRPort00_01_05]>;
 def : InstRW<[SPRWriteResGroup160], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
                                                "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
                                                "^VMOV(A|U)P(D|S)Z(128|256)rrk(z?)((_REV)?)$",
                                                "^VMOVDQ(A|U)(32|64)Z128rrk(z?)((_REV)?)$",
                                                "^VMOVS(D|H|S)Zrr((_REV)?)$",
                                                "^VMOVS(D|S)Zrrk(z?)((_REV)?)$",
                                                "^VP(ADD|SUB)(B|D|Q|W)Yrr$",
                                                "^VP(ADD|SUB)(B|D|Q|W)Z(128|256)rr$",
                                                "^VP(ADD|SUB)(D|Q)Z(128|256)rrk(z?)$",
                                                "^VPMOVM2(D|Q)Z128rr$",
                                                "^VPTERNLOG(D|Q)Z(128|256)rri((k|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup160], (instrs VPBLENDDrri)>;
 
 def SPRWriteResGroup161 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [4, 1, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1, 1];
   let Latency = 7;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup161], (instregex "^MOVS(L|Q|W)$")>;
 
 def SPRWriteResGroup162 : SchedWriteRes<[SPRPort02_03_11]> {
   let Latency = 6;
 }
def : InstRW<[SPRWriteResGroup167], (instregex "^MUL_F(P?)rST0$",
                                                "^VCVT(T?)PS2(U?)DQZrrbkz$",
                                                "^VM(AX|IN)(C?)PSZrr((k|kz)?)$",
                                                "^VM(AX|IN)PSZrrb((k|kz)?)$",
                                                "^VPLZCNT(D|Q)Zrr((k|kz)?)$",
                                                "^VPMADD52(H|L)UQZr((k|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup167], (instrs MUL_FST0r)>;
 
 def SPRWriteResGroup168 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort05, SPRPort06]> {
-  let ResourceCycles = [7, 1, 2];
+  let ReleaseAtCycles = [7, 1, 2];
   let Latency = 20;
   let NumMicroOps = 10;
 }
 def : InstRW<[SPRWriteResGroup168], (instrs MWAITrr)>;
 
 def SPRWriteResGroup169 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
+  let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
   let Latency = 35;
   let NumMicroOps = 79;
 }
 def : InstRW<[SPRWriteResGroup169], (instrs OUT16ir)>;
 
 def SPRWriteResGroup170 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
+  let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];
   let Latency = 35;
   let NumMicroOps = 79;
 }
 def : InstRW<[SPRWriteResGroup170], (instrs OUT16rr)>;
 
 def SPRWriteResGroup171 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
+  let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
   let Latency = 35;
   let NumMicroOps = 85;
 }
 def : InstRW<[SPRWriteResGroup171], (instrs OUT32ir)>;
 
 def SPRWriteResGroup172 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
+  let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];
   let Latency = 35;
   let NumMicroOps = 85;
 }
 def : InstRW<[SPRWriteResGroup172], (instrs OUT32rr)>;
 
 def SPRWriteResGroup173 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
+  let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
   let Latency = 35;
   let NumMicroOps = 73;
 }
 def : InstRW<[SPRWriteResGroup173], (instrs OUT8ir)>;
 
 def SPRWriteResGroup174 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
+  let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];
   let Latency = 35;
   let NumMicroOps = 73;
 }
 def : InstRW<[SPRWriteResGroup174], (instrs OUT8rr)>;
 
 def SPRWriteResGroup175 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
+  let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 80;
 }
 def : InstRW<[SPRWriteResGroup175], (instrs OUTSB)>;
 
 def SPRWriteResGroup176 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
+  let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 89;
 }
 def : InstRW<[SPRWriteResGroup176], (instrs OUTSL)>;
 
 def SPRWriteResGroup177 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
+  let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 83;
 }
 def : InstRW<[SPRWriteResGroup177], (instrs OUTSW)>;
 
 def SPRWriteResGroup178 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 2;
def SPRWriteResGroup182 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup182], (instregex "^(V?)PEXTR(D|Q)mr$",
                                                "^VPEXTR(D|Q)Zmr$",
                                                "^VPMOVQDZ128mr(k?)$")>;
 
 def SPRWriteResGroup183 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 9;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup183, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
 
 def SPRWriteResGroup184 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup184], (instregex "^(V?)PH(ADD|SUB)SWrr$",
                                                "^VPH(ADD|SUB)SWYrr$")>;
 
 def SPRWriteResGroup185 : SchedWriteRes<[SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup185], (instregex "^POP(16|32|64)rmm$",
                                                "^PUSH(16|32)rmm$")>;
 
 def SPRWriteResGroup186 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [6, 2, 1, 1];
+  let ReleaseAtCycles = [6, 2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 10;
 }
 def : InstRW<[SPRWriteResGroup186], (instrs POPF16)>;
 
 def SPRWriteResGroup187 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup187], (instrs POPF64)>;
 
 def SPRWriteResGroup188 : SchedWriteRes<[SPRPort02_03_11]> {
   let Latency = 0;
 }
 def : InstRW<[SPRWriteResGroup188], (instregex "^PREFETCHT(0|1|2)$")>;
 def : InstRW<[SPRWriteResGroup188], (instrs PREFETCHNTA)>;
 
 def SPRWriteResGroup189 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort06]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup189], (instregex "^PTWRITE((64)?)m$")>;
 
 def SPRWriteResGroup190 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort06]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup190], (instrs PTWRITE64r)>;
 
 def SPRWriteResGroup191 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort06]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup191], (instrs PTWRITEr)>;
 
 def SPRWriteResGroup192 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let NumMicroOps = 2;
 }

 def : InstRW<[SPRWriteResGroup194], (instrs PUSHF64)>;
 
 def SPRWriteResGroup195 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> {
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup195], (instregex "^PUSH(F|G)S64$")>;
 
 def SPRWriteResGroup196 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [2, 3, 2];
+  let ReleaseAtCycles = [2, 3, 2];
   let Latency = 8;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup196], (instregex "^RC(L|R)(16|32|64)rCL$")>;
 
 def SPRWriteResGroup197 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup197, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
 
 def SPRWriteResGroup198 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [1, 5, 2];
+  let ReleaseAtCycles = [1, 5, 2];
   let Latency = 20;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup198, WriteRMW], (instrs RCL8mCL)>;
 
 def SPRWriteResGroup199 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [2, 5, 2];
+  let ReleaseAtCycles = [2, 5, 2];
   let Latency = 7;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup199], (instrs RCL8rCL)>;
 
 def SPRWriteResGroup200 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [2, 4, 3];
+  let ReleaseAtCycles = [2, 4, 3];
   let Latency = 20;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup200, WriteRMW], (instrs RCR8mCL)>;
 
 def SPRWriteResGroup201 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [3, 4, 3];
+  let ReleaseAtCycles = [3, 4, 3];
   let Latency = 9;
   let NumMicroOps = 10;
 }
 def : InstRW<[SPRWriteResGroup201], (instrs RCR8rCL)>;
 
 def SPRWriteResGroup202 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort01_05_10, SPRPort05]> {
-  let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
+  let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 54;
 }
 def : InstRW<[SPRWriteResGroup202], (instrs RDMSR)>;
 
 def SPRWriteResGroup203 : SchedWriteRes<[SPRPort01]> {
   let Latency = SapphireRapidsModel.MaxLatency;
 }
 def : InstRW<[SPRWriteResGroup203], (instrs RDPID64)>;
 
 def SPRWriteResGroup204 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup204], (instrs RDPKRUr)>;
 
 def SPRWriteResGroup205 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
-  let ResourceCycles = [9, 6, 2, 1];
+  let ReleaseAtCycles = [9, 6, 2, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 18;
 }
 def : InstRW<[SPRWriteResGroup205], (instrs RDPMC)>;
 
 def SPRWriteResGroup206 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
   let Latency = 1386;
   let NumMicroOps = 25;
 }
 def : InstRW<[SPRWriteResGroup206], (instrs RDRAND16r)>;
 
 def SPRWriteResGroup207 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 25;
 }
 def : InstRW<[SPRWriteResGroup207], (instregex "^RDRAND(32|64)r$")>;
 
 def SPRWriteResGroup208 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
+  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
   let Latency = 1381;
   let NumMicroOps = 25;
 }
 def : InstRW<[SPRWriteResGroup208], (instrs RDSEED16r)>;
 
 def SPRWriteResGroup209 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
+  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 25;
 }
 def : InstRW<[SPRWriteResGroup209], (instregex "^RDSEED(32|64)r$")>;
 
 def SPRWriteResGroup210 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
-  let ResourceCycles = [5, 6, 3, 1];
+  let ReleaseAtCycles = [5, 6, 3, 1];
   let Latency = 18;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup210], (instrs RDTSC)>;
 
 def SPRWriteResGroup211 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort05]> {
-  let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
+  let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];
   let Latency = 42;
   let NumMicroOps = 21;
 }
 def : InstRW<[SPRWriteResGroup211], (instrs RDTSCP)>;
 
 def SPRWriteResGroup212 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup212], (instrs RET64)>;
 
 def SPRWriteResGroup213 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup213], (instregex "^RETI(16|32|64)$")>;
 
 def SPRWriteResGroup214 : SchedWriteRes<[]>;
 def : InstRW<[SPRWriteResGroup214], (instrs REX64_PREFIX)>;
 
 def SPRWriteResGroup215 : SchedWriteRes<[SPRPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup215, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
 
 def SPRWriteResGroup216 : SchedWriteRes<[SPRPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup216], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
 
 def SPRWriteResGroup217 : SchedWriteRes<[SPRPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 13;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup217, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
                                                          "^(RO|SH)L8mCL$",
                                                          "^(RO|SA|SH)R8mCL$")>;
 
 def SPRWriteResGroup218 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 15;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup218], (instregex "^(V?)ROUNDP(D|S)m$")>;
 def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S)m((_Int)?)$",
                                                                 "^VRNDSCALEP(D|S)Z128rm(bi|ik)$",
                                                                 "^VRNDSCALEP(D|S)Z128rmbik(z?)$",
                                                                 "^VRNDSCALEP(D|S)Z128rmi((kz)?)$",
                                                                 "^VRNDSCALES(D|S)Zm$",
                                                                 "^VRNDSCALES(D|S)Zm_Int((k|kz)?)$")>;
 
 def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 8;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)r$",
                                                "^(V?)ROUND(PS|SD)r$",
                                                "^(V?)ROUNDS(D|S)r_Int$",
                                                "^VRNDSCALEP(D|S)Z(128|256)rri((k|kz)?)$",
                                                "^VRNDSCALES(D|S)Zr$",
                                                "^VRNDSCALES(D|S)Zr(b?)_Int((k|kz)?)$",
                                                "^VROUNDP(D|S)Yr$")>;
 
 def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 4;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup220], (instrs SAHF)>;
 
 def SPRWriteResGroup221 : SchedWriteRes<[SPRPort00_06]> {
   let Latency = 13;
 }

 
 def SPRWriteResGroup223 : SchedWriteRes<[SPRPort00_06]> {
   let Latency = 3;
 }
 def : InstRW<[SPRWriteResGroup223], (instregex "^S(A|H)RX(32|64)rr$",
                                                "^SHLX(32|64)rr$")>;
 
 def SPRWriteResGroup224 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 2, 1, 1, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup224], (instrs SERIALIZE)>;
 
 def SPRWriteResGroup225 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup225], (instrs SFENCE)>;
 
 def SPRWriteResGroup226 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 2, 2];
+  let ReleaseAtCycles = [1, 2, 2, 2];
   let Latency = 21;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup226], (instregex "^S(G|I)DT64m$")>;
 
 def SPRWriteResGroup227 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
   let Latency = 9;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup227, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
 
 def SPRWriteResGroup228 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup228], (instrs SHA1MSG1rr)>;
 
 def SPRWriteResGroup229 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 2, 1, 2, 1];
+  let ReleaseAtCycles = [2, 2, 1, 2, 1];
   let Latency = 13;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup229, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
 
 def SPRWriteResGroup230 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05]> {
-  let ResourceCycles = [2, 2, 1, 2];
+  let ReleaseAtCycles = [2, 2, 1, 2];
   let Latency = 6;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup230], (instrs SHA1MSG2rr)>;
 
 def SPRWriteResGroup231 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 4;

 
 def SPRWriteResGroup234 : SchedWriteRes<[SPRPort05]> {
   let Latency = 6;
 }
 def : InstRW<[SPRWriteResGroup234], (instrs SHA1RNDS4rri,
                                             SHA256RNDS2rr)>;
 
 def SPRWriteResGroup235 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [3, 2, 1, 1, 1];
+  let ReleaseAtCycles = [3, 2, 1, 1, 1];
   let Latency = 12;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup235, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
 
 def SPRWriteResGroup236 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [3, 2, 1, 1];
+  let ReleaseAtCycles = [3, 2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup236], (instrs SHA256MSG1rr)>;
 
 def SPRWriteResGroup237 : SchedWriteRes<[SPRPort05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup237], (instregex "^VPMOV(D|Q|W|SQ|SW)BZrrk(z?)$",
                                                "^VPMOV((S|US)?)(D|Q)WZrrk(z?)$",
                                                "^VPMOV(U?)SDBZrrk(z?)$",
                                                "^VPMOVUS(Q|W)BZrrk(z?)$")>;
 def : InstRW<[SPRWriteResGroup237], (instrs SHA256MSG2rr)>;

 
 def SPRWriteResGroup243 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup243], (instrs STD)>;
 
 def SPRWriteResGroup244 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [1, 4, 1];
+  let ReleaseAtCycles = [1, 4, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup244], (instrs STI)>;
 
 def SPRWriteResGroup245 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 8;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup245], (instrs STOSB)>;
 
 def SPRWriteResGroup246 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 7;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup246], (instregex "^STOS(L|Q|W)$")>;
 
 def SPRWriteResGroup247 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
   let Latency = 5;
   let NumMicroOps = 2;
def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$",
                                                                 "^VPMULTISHIFTQBZ((256)?)rm(b?)$",
                                                                 "^VPUNPCK(H|L)(BW|WD)Zrmk(z?)$")>;
 def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
 def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rmik(z?)$",
                                                                 "^VPCLMULQDQ(Y|Z)rm$")>;
 def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rm)>;
 
 def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)Yrm$")>;
 def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrm)>;
 
 def SPRWriteResGroup260 : SchedWriteRes<[SPRPort00_01_05]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rr$",
                                                "^VBLENDVP(D|SY)rr$",
                                                "^VPBLENDVB(Y?)rr$")>;
 
 def SPRWriteResGroup261 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 9;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
 def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
 
 def SPRWriteResGroup262 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
   let Latency = 9;

 
 def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
   let Latency = 10;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup264, ReadAfterVecLd], (instregex "^V(U?)COMISHZrm((_Int)?)$")>;
 
 def SPRWriteResGroup265 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup265], (instregex "^VCOMPRESSP(D|S)Z(128|256)mr$",
                                                "^VCOMPRESSP(D|S)Zmr$",
                                                "^VPCOMPRESS(D|Q)Z(128|256)mr$",
                                                "^VPCOMPRESS(D|Q)Zmr$",
                                                "^VPMOV(D|Q|W|SQ|SW)BZmr$",
                                                "^VPMOV((S|US)?)(D|Q)WZmr$",
                                                "^VPMOV(U?)S(DB|QD)Zmr$",
                                                "^VPMOVUS(Q|W)BZmr$")>;
 
 def SPRWriteResGroup266 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 15;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup266], (instregex "^VCOMPRESSP(D|S)Z(128|256)mrk$",
                                                "^VCOMPRESSP(D|S)Zmrk$",
                                                "^VPCOMPRESS(D|Q)Z(128|256)mrk$",
                                                "^VPCOMPRESS(D|Q)Zmrk$",
                                                "^VPMOV(D|Q|W|SQ|SW)BZmrk$",
                                                "^VPMOV((S|US)?)(D|Q)WZmrk$",
                                                "^VPMOV(U?)S(DB|QD)Zmrk$",
                                                "^VPMOVUS(Q|W)BZmrk$")>;
 
 def SPRWriteResGroup267 : SchedWriteRes<[SPRPort05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 3;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup267], (instregex "^VCOMPRESSP(D|S)Z(128|256)rr$",
                                                "^VCOMPRESSP(D|S)Zrr$",
                                                "^VEXPANDP(D|S)Z(128|256)rr$",
                                                "^VEXPANDP(D|S)Zrr$",
                                                "^VPCOMPRESS(B|D|Q|W)Z(128|256)rr$",

 
 def SPRWriteResGroup276 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
   let Latency = 14;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup276], (instregex "^VCVT(U?)DQ2PHZ256rrk(z?)$")>;
 
 def SPRWriteResGroup277 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 17;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup277], (instregex "^VCVT(U?)DQ2PHZrm(b?)$")>;
 
 def SPRWriteResGroup278 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 21;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup278], (instregex "^VCVT(U?)DQ2PHZrm(bk|kz)$",
                                                "^VCVT(U?)DQ2PHZrm(k|bkz)$")>;
 
 def SPRWriteResGroup279 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 9;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup279], (instregex "^VCVT(U?)DQ2PHZrr(b?)$")>;
 
 def SPRWriteResGroup280 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 14;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup280], (instregex "^VCVT(U?)DQ2PHZrr(bk|kz)$",
                                                "^VCVT(U?)DQ2PHZrr(k|bkz)$")>;
 
 def SPRWriteResGroup281 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1];
   let Latency = 15;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup281, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(b?)$")>;
 
 def SPRWriteResGroup282 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1];
   let Latency = 17;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup282, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(bk|kz)$",
                                                                 "^VCVTNE2PS2BF16Z128rm(k|bkz)$")>;
 
 def SPRWriteResGroup283 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 8;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup283], (instregex "^VCVTNE2PS2BF16Z(128|256)rr$")>;
 
 def SPRWriteResGroup284 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup284], (instregex "^VCVTNE2PS2BF16Z(128|256)rrk(z?)$")>;
 
 def SPRWriteResGroup285 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1];
   let Latency = 16;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup285, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(b?)$")>;
 
 def SPRWriteResGroup286 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1, 1];
   let Latency = 18;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup286, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(bk|kz)$",
                                                                 "^VCVTNE2PS2BF16Z256rm(k|bkz)$")>;
 
 def SPRWriteResGroup287 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 16;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(b?)$",
                                                                 "^VDPBF16PSZm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instrs VDPBF16PSZmbkz)>;
 
 def SPRWriteResGroup288 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 18;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup288, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(bk|kz)$",
                                                                 "^VCVTNE2PS2BF16Zrm(k|bkz)$")>;
 
 def SPRWriteResGroup289 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 8;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup289], (instregex "^VDPBF16PSZr((k|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup289], (instrs VCVTNE2PS2BF16Zrr)>;
 
 def SPRWriteResGroup290 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup290], (instregex "^VCVTNE2PS2BF16Zrrk(z?)$")>;
 
 def SPRWriteResGroup291 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
   let Latency = 8;
   let NumMicroOps = 3;

 def SPRWriteResGroup294 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
   let Latency = 18;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup294], (instregex "^VCVTNEPS2BF16Z256rm(bk|kz)$",
                                                "^VCVTNEPS2BF16Z256rm(k|bkz)$")>;
 
 def SPRWriteResGroup295 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 16;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup295], (instregex "^VCVTNEPS2BF16Zrm(b?)$")>;
 
 def SPRWriteResGroup296 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 18;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup296], (instregex "^VCVTNEPS2BF16Zrm(bk|kz)$",
                                                "^VCVTNEPS2BF16Zrm(k|bkz)$")>;
 
 def SPRWriteResGroup297 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 8;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup297], (instrs VCVTNEPS2BF16Zrr)>;
 
 def SPRWriteResGroup298 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 10;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup298], (instregex "^VCVTNEPS2BF16Zrrk(z?)$")>;
 
 def SPRWriteResGroup299 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
   let Latency = 15;
   let NumMicroOps = 3;

 def : InstRW<[SPRWriteResGroup300], (instregex "^VCVT(T?)P(D|H)2(U?)DQZrm(b?)$",
                                                "^VCVT(T?)PD2(U?)DQZrm(bk|kz)$",
                                                "^VCVT(T?)PD2(U?)DQZrm(k|bkz)$",
                                                "^VCVTPH2PSXZrm(b?)$",
                                                "^VCVT(U?)QQ2PSZrm((b|k|bk|kz)?)$",
                                                "^VCVT(U?)QQ2PSZrmbkz$")>;
 
 def SPRWriteResGroup301 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 1, 2];
   let Latency = 19;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup301], (instregex "^VCVTPD2PHZ128rm(b?)$")>;
 
 def SPRWriteResGroup302 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 1, 2];
   let Latency = 22;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup302], (instregex "^VCVTPD2PHZ128rm(bk|kz)$",
                                                "^VCVTPD2PHZ128rm(k|bkz)$")>;
 
 def SPRWriteResGroup303 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 12;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup303], (instrs VCVTPD2PHZ128rr)>;
 
 def SPRWriteResGroup304 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 15;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup304], (instregex "^VCVTPD2PHZ128rrk(z?)$")>;
 
 def SPRWriteResGroup305 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 2];
   let Latency = 21;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup305], (instregex "^VCVTPD2PHZ256rm(b?)$")>;
 
 def SPRWriteResGroup306 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 2];
   let Latency = 24;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup306], (instregex "^VCVTPD2PHZ256rm(bk|kz)$",
                                                "^VCVTPD2PHZ256rm(k|bkz)$")>;
 
 def SPRWriteResGroup307 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 13;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup307], (instrs VCVTPD2PHZ256rr)>;
 
 def SPRWriteResGroup308 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 16;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup308], (instregex "^VCVTPD2PHZ256rrk(z?)$")>;
 
 def SPRWriteResGroup309 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 2];
   let Latency = 23;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup309], (instregex "^VCVTP(D2PH|H2PD)Zrm(b?)$")>;
 
 def SPRWriteResGroup310 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 2];
   let Latency = 26;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup310], (instregex "^VCVTP(D2PH|H2PD)Zrm(bk|kz)$",
                                                "^VCVTP(D2PH|H2PD)Zrm(k|bkz)$")>;
 
 def SPRWriteResGroup311 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 15;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup311], (instregex "^VCVTP(D2PH|H2PD)Zrr(b?)$")>;
 
 def SPRWriteResGroup312 : SchedWriteRes<[SPRPort00, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 18;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup312], (instregex "^VCVTP(D2PH|H2PD)Zrr(bk|kz)$",
                                                "^VCVTP(D2PH|H2PD)Zrr(k|bkz)$")>;
 
 def SPRWriteResGroup313 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
   let Latency = 11;
def SPRWriteResGroup321 : SchedWriteRes<[SPRPort00, SPRPort05]> {
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup321], (instregex "^VCVT(T?)PH2(U?)DQZrr(bk|kz)$",
                                                "^VCVT(T?)PH2(U?)DQZrr(k|bkz)$",
                                                "^VCVTP(H2PS|S2PH)XZrr(bk|kz)$",
                                                "^VCVTP(H2PS|S2PH)XZrr(k|bkz)$")>;
 
 def SPRWriteResGroup322 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 1, 2];
   let Latency = 23;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup322], (instregex "^VCVTPH2PDZ128rm(b?)$")>;
 
 def SPRWriteResGroup323 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 1, 2];
   let Latency = 26;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup323], (instregex "^VCVTPH2PDZ128rm(bk|kz)$",
                                                "^VCVTPH2PDZ128rm(k|bkz)$")>;
 
 def SPRWriteResGroup324 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 2];
   let Latency = 16;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup324], (instrs VCVTPH2PDZ128rr)>;
 
 def SPRWriteResGroup325 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1, 2];
+  let ReleaseAtCycles = [2, 1, 1, 2];
   let Latency = 19;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup325], (instregex "^VCVTPH2PDZ128rrk(z?)$")>;
 
 def SPRWriteResGroup326 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 22;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup326], (instregex "^VCVTPH2PDZ256rm(b?)$")>;
 
 def SPRWriteResGroup327 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 25;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup327], (instregex "^VCVTPH2PDZ256rm(bk|kz)$",
                                                "^VCVTPH2PDZ256rm(k|bkz)$")>;
 
 def SPRWriteResGroup328 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 15;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup328], (instrs VCVTPH2PDZ256rr)>;
 
 def SPRWriteResGroup329 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 18;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup329], (instregex "^VCVTPH2PDZ256rrk(z?)$")>;
 
 def SPRWriteResGroup330 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
   let Latency = 9;
   let NumMicroOps = 2;
def SPRWriteResGroup332 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup332], (instregex "^VCVT(T?)PS2(U?)QQZrm((b|k|bk|kz)?)$",
                                                "^VCVT(T?)PS2(U?)QQZrmbkz$")>;
 def : InstRW<[SPRWriteResGroup332], (instrs VCVTPH2PSZrm)>;
 def : InstRW<[SPRWriteResGroup332, ReadAfterVecYLd], (instregex "^VPERMWZrmk(z?)$")>;
 
 def SPRWriteResGroup333 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2, 1, 1, 1];
+  let ReleaseAtCycles = [1, 2, 1, 1, 1];
   let Latency = 17;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup333], (instregex "^VCVT(T?)PH2(U?)QQZ128rm((b|k|bk|kz)?)$",
                                                "^VCVT(T?)PH2(U?)QQZ128rmbkz$")>;
 
 def SPRWriteResGroup334 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup334], (instregex "^VCVT(T?)PH2(U?)QQZ(128|256)rr((k|kz)?)$")>;
 
 def SPRWriteResGroup335 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2, 1, 1, 1];
+  let ReleaseAtCycles = [1, 2, 1, 1, 1];
   let Latency = 18;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup335], (instregex "^VCVT(T?)PH2(U?)QQZ256rm((b|k|bk|kz)?)$",
                                                "^VCVT(T?)PH2(U?)QQZ256rmbkz$")>;
 
 def SPRWriteResGroup336 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
   let Latency = 16;

 
 def SPRWriteResGroup347 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup347], (instregex "^VCVT(U?)QQ2PHZ256rrk(z?)$")>;
 
 def SPRWriteResGroup348 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 1, 2];
   let Latency = 18;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup348], (instregex "^VCVT(U?)QQ2PHZrm(b?)$")>;
 
 def SPRWriteResGroup349 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 1, 2];
   let Latency = 20;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup349], (instregex "^VCVT(U?)QQ2PHZrm(bk|kz)$",
                                                "^VCVT(U?)QQ2PHZrm(k|bkz)$")>;
 
 def SPRWriteResGroup350 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup350], (instregex "^VCVT(U?)QQ2PHZrr(b?)$")>;
 
 def SPRWriteResGroup351 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup351], (instregex "^VCVT(U?)QQ2PHZrr(bk|kz)$",
                                                "^VCVT(U?)QQ2PHZrr(k|bkz)$")>;
 
 def SPRWriteResGroup352 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 2, 1, 1, 1];
   let Latency = 18;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup352, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm((_Int)?)$")>;
 
 def SPRWriteResGroup353 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 2, 1, 1, 1];
+  let ReleaseAtCycles = [2, 2, 1, 1, 1];
   let Latency = 21;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup353, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm_Intk(z?)$")>;
 
 def SPRWriteResGroup354 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 11;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup354], (instregex "^VCVTSD2SHZrr(b?)_Int$")>;
 def : InstRW<[SPRWriteResGroup354], (instrs VCVTSD2SHZrr)>;
 
 def SPRWriteResGroup355 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 14;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup355], (instregex "^VCVTSD2SHZrr(b?)_Intk(z?)$")>;
 
 def SPRWriteResGroup356 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 18;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup356, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm((_Int)?)$")>;
 
 def SPRWriteResGroup357 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 20;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup357, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm_Intk(z?)$")>;
 
 def SPRWriteResGroup358 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 10;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup358], (instregex "^VCVTSH2SDZrr(b?)_Int$")>;
 def : InstRW<[SPRWriteResGroup358], (instrs VCVTSH2SDZrr)>;
 
 def SPRWriteResGroup359 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup359], (instregex "^VCVTSH2SDZrr(b?)_Intk(z?)$")>;
 
 def SPRWriteResGroup360 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_11]> {
   let Latency = 13;
   let NumMicroOps = 3;
def : InstRW<[SPRWriteResGroup367], (instregex "^VDBPSADBWZ(128|256)rrik(z?)$",
                                                "^VPERMBZrrk(z?)$",
                                                "^VPMOV(S|Z)XBWZ((256)?)rrk(z?)$",
                                                "^VPMULTISHIFTQBZ(128|256)rrk(z?)$",
                                                "^VPMULTISHIFTQBZrrk(z?)$",
                                                "^VPOPCNT(B|W)Z(128|256)rrk(z?)$",
                                                "^VPOPCNT(B|W)Zrrk(z?)$")>;
 
 def SPRWriteResGroup368 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 36;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup368, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(b?)$")>;
 
 def SPRWriteResGroup369 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 38;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup369, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(bk|kz)$",
                                                                 "^VDIVPHZ128rm(k|bkz)$")>;
 
 def SPRWriteResGroup370 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 31;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup370], (instregex "^VDIVPHZ(128|256)rr$")>;
 
 def SPRWriteResGroup371 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 33;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup371], (instregex "^VDIVPHZ(128|256)rrk$",
                                                "^VSQRTPHZ(128|256)r$")>;
 def : InstRW<[SPRWriteResGroup371], (instrs VDIVPHZ128rrkz)>;
 
 def SPRWriteResGroup372 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 37;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup372, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(b?)$")>;
 
 def SPRWriteResGroup373 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 39;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup373, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(bk|kz)$",
                                                                 "^VDIVPHZ256rm(k|bkz)$")>;
 def : InstRW<[SPRWriteResGroup373, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(b?)$")>;
 
 def SPRWriteResGroup374 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 11;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup374], (instrs VDIVPHZ256rrkz)>;
 
 def SPRWriteResGroup375 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [4, 2, 1, 1, 1];
+  let ReleaseAtCycles = [4, 2, 1, 1, 1];
   let Latency = 49;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup375, ReadAfterVecYLd], (instregex "^VDIVPHZrm(b?)$")>;
 
 def SPRWriteResGroup376 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [4, 2, 1, 1, 1];
+  let ReleaseAtCycles = [4, 2, 1, 1, 1];
   let Latency = 51;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup376, ReadAfterVecYLd], (instregex "^VDIVPHZrm(bk|kz)$",
                                                                 "^VDIVPHZrm(k|bkz)$")>;
 
 def SPRWriteResGroup377 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [4, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1];
   let Latency = 41;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup377], (instregex "^VDIVPHZrr(b?)$")>;
 
 def SPRWriteResGroup378 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [4, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1];
   let Latency = 43;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup378], (instregex "^VDIVPHZrr(bk|kz)$",
                                                "^VDIVPHZrr(k|bkz)$")>;
 
 def SPRWriteResGroup379 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 17;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup379], (instrs VDIVPSZrr)>;
 
 def SPRWriteResGroup380 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
   let Latency = 21;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instregex "^VDIVSHZrm_Int((k|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instrs VDIVSHZrm)>;
 
 def SPRWriteResGroup381 : SchedWriteRes<[SPRPort00]> {
   let Latency = 14;
 }
 def : InstRW<[SPRWriteResGroup381], (instrs VDIVSHZrr_Int,
                                             VSQRTSHZr_Int)>;
 
 def SPRWriteResGroup382 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 15;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instregex "^VDPBF16PSZ128m((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instrs VDPBF16PSZ128mbkz)>;
 
 def SPRWriteResGroup383 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
-  let ResourceCycles = [2, 2];
+  let ReleaseAtCycles = [2, 2];
   let Latency = 8;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup383], (instregex "^VDPBF16PSZ(128|256)r((k|kz)?)$")>;
 
 def SPRWriteResGroup384 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [2, 1, 2];
+  let ReleaseAtCycles = [2, 1, 2];
   let Latency = 16;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instregex "^VDPBF16PSZ256m((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instrs VDPBF16PSZ256mbkz)>;
 
 def SPRWriteResGroup385 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [6, 7, 18];
+  let ReleaseAtCycles = [6, 7, 18];
   let Latency = 81;
   let NumMicroOps = 31;
 }
 def : InstRW<[SPRWriteResGroup385], (instrs VERRm)>;
 
 def SPRWriteResGroup386 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [6, 7, 17];
+  let ReleaseAtCycles = [6, 7, 17];
   let Latency = 74;
   let NumMicroOps = 30;
 }
 def : InstRW<[SPRWriteResGroup386], (instrs VERRr)>;
 
 def SPRWriteResGroup387 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [5, 8, 21];
+  let ReleaseAtCycles = [5, 8, 21];
   let Latency = 81;
   let NumMicroOps = 34;
 }
 def : InstRW<[SPRWriteResGroup387], (instrs VERWm)>;
 
 def SPRWriteResGroup388 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
-  let ResourceCycles = [5, 8, 20];
+  let ReleaseAtCycles = [5, 8, 20];
   let Latency = 74;
   let NumMicroOps = 33;
 }
 def : InstRW<[SPRWriteResGroup388], (instrs VERWr)>;
 
 def SPRWriteResGroup389 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 10;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup389, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z128rm((k|kz)?)$",
                                                                 "^VPEXPAND(B|D|Q|W)Z128rm$",
                                                                 "^VPEXPAND(D|Q)Z128rmk(z?)$")>;
 
 def SPRWriteResGroup390 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 16;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup390], (instregex "^VF(C?)MADDCPHZ(128|256)m(b?)$",
                                                "^VROUNDP(D|S)Ym$")>;
 def : InstRW<[SPRWriteResGroup390, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZm$",
                                                                 "^VF(C?)MULCPHZ128rm(b?)$",
                                                                 "^VF(C?)MULCSHZrm$",
                                                                 "^VRNDSCALEPHZ128rm(b?)i$",
                                                                 "^VRNDSCALESHZm((_Int)?)$",
                                                                 "^VSCALEFPHZ128rm(b?)$")>;
 def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(b?)$",
                                                                 "^VRNDSCALEP(D|H|S)Z256rm(b?)i$",
                                                                 "^VRNDSCALEP(D|S)Z256rm(b?)ik(z?)$",
                                                                 "^VSCALEFPHZ256rm(b?)$")>;
 def : InstRW<[SPRWriteResGroup390, ReadAfterVecLd], (instrs VSCALEFSHZrm)>;
 
 def SPRWriteResGroup391 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 21;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup391], (instregex "^VF(C?)MADDCPHZ(128|256)m(bk|kz)$",
                                                "^VF(C?)MADDCPHZ(128|256)m(k|bkz)$")>;
 def : InstRW<[SPRWriteResGroup391, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZmk(z?)$",
                                                                 "^VF(C?)MULCPHZ128rm(bk|kz)$",
                                                                 "^VF(C?)MULCPHZ128rm(k|bkz)$",
                                                                 "^VF(C?)MULCSHZrmk(z?)$")>;
 def : InstRW<[SPRWriteResGroup391, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(bk|kz)$",
                                                                 "^VF(C?)MULCPHZ256rm(k|bkz)$")>;
 
 def SPRWriteResGroup392 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup392], (instregex "^VF(C?)MADDCPHZ(128|256)r$",
                                                "^VF(C?)MADDCSHZr(b?)$",
                                                "^VF(C?)MULCPHZ(128|256)rr$",
                                                "^VF(C?)MULCSHZrr(b?)$",
                                                "^VRNDSCALEPHZ(128|256)rri$",
                                                "^VRNDSCALESHZr(b?)_Int$",
                                                "^VSCALEFPHZ(128|256)rr$")>;
 def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZr,
                                             VSCALEFSHZrr,
                                             VSCALEFSHZrrb_Int)>;
 
 def SPRWriteResGroup393 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 15;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup393], (instregex "^VF(C?)MADDCPHZ(128|256)rk(z?)$",
                                                "^VF(C?)MADDCSHZr(bk|kz)$",
                                                "^VF(C?)MADDCSHZr(k|bkz)$",
                                                "^VF(C?)MULCPHZ(128|256)rrk(z?)$",
                                                "^VF(C?)MULCSHZrr(bk|kz)$",
                                                "^VF(C?)MULCSHZrr(k|bkz)$")>;
 
 def SPRWriteResGroup394 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 16;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup394], (instregex "^VF(C?)MADDCPHZm(b?)$")>;
 def : InstRW<[SPRWriteResGroup394, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(b?)$",
                                                                 "^VRNDSCALEP(D|H|S)Zrm(b?)i$",
                                                                 "^VRNDSCALEP(D|S)Zrm(b?)ik(z?)$",
                                                                 "^VSCALEFPHZrm(b?)$")>;
 
 def SPRWriteResGroup395 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 21;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup395], (instregex "^VF(C?)MADDCPHZm(bk|kz)$",
                                                "^VF(C?)MADDCPHZm(k|bkz)$")>;
 def : InstRW<[SPRWriteResGroup395, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(bk|kz)$",
                                                                 "^VF(C?)MULCPHZrm(k|bkz)$")>;
 
 def SPRWriteResGroup396 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup396], (instregex "^VF(C?)MADDCPHZr(b?)$",
                                                "^VF(C?)MULCPHZrr(b?)$",
                                                "^VRNDSCALEPHZrri(b?)$",
                                                "^VSCALEFPHZrr(b?)$")>;
 
 def SPRWriteResGroup397 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 15;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup397], (instregex "^VF(C?)MADDCPHZr(bk|kz)$",
                                                "^VF(C?)MADDCPHZr(k|bkz)$",
                                                "^VF(C?)MULCPHZrr(bk|kz)$",
                                                "^VF(C?)MULCPHZrr(k|bkz)$")>;
 
 def SPRWriteResGroup398 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2, 4];
+  let ReleaseAtCycles = [1, 1, 2, 4];
   let Latency = 29;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
                                                                               "^VPGATHER(D|Q)QYrm$")>;
 def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
                                                                            VPGATHERQDYrm)>;
 
 def SPRWriteResGroup399 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 20;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ128rm$",
                                                                               "^VPGATHER(D|Q)QZ128rm$")>;
 def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ128rm,
                                                                            VPGATHERQDZ128rm)>;
 
 def SPRWriteResGroup400 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 2, 4];
+  let ReleaseAtCycles = [1, 2, 4];
   let Latency = 28;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ256rm$",
                                                                               "^VPGATHER(D|Q)QZ256rm$")>;
 def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ256rm,
                                                                            VPGATHERQDZ256rm)>;
 
 def SPRWriteResGroup401 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 8, 2];
+  let ReleaseAtCycles = [1, 8, 2];
   let Latency = 28;
   let NumMicroOps = 11;
 }
 def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZrm$",
                                                                               "^VPGATHER(D|Q)QZrm$")>;
 def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZrm,
                                                                            VPGATHERQDZrm)>;
 
 def SPRWriteResGroup402 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 1, 2];
   let Latency = 20;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
                                                                               "^VPGATHER(D|Q)Qrm$")>;
 def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
                                                                            VPGATHERQDrm)>;
 
 def SPRWriteResGroup403 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2, 8];
+  let ReleaseAtCycles = [1, 1, 2, 8];
   let Latency = 30;
   let NumMicroOps = 12;
 }
 def : InstRW<[SPRWriteResGroup403, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
                                                                            VPGATHERDDYrm)>;
 
 def SPRWriteResGroup404 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 2, 4];
+  let ReleaseAtCycles = [1, 2, 4];
   let Latency = 27;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup404, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ128rm,
                                                                            VPGATHERDDZ128rm)>;
 
 def SPRWriteResGroup405 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 2, 8];
+  let ReleaseAtCycles = [1, 2, 8];
   let Latency = 29;
   let NumMicroOps = 11;
 }
 def : InstRW<[SPRWriteResGroup405, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ256rm,
                                                                            VPGATHERDDZ256rm)>;
 
 def SPRWriteResGroup406 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 16, 2];
+  let ReleaseAtCycles = [1, 16, 2];
   let Latency = 30;
   let NumMicroOps = 19;
 }
 def : InstRW<[SPRWriteResGroup406, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZrm,
                                                                            VPGATHERDDZrm)>;
 
 def SPRWriteResGroup407 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 1, 2, 4];
+  let ReleaseAtCycles = [1, 1, 2, 4];
   let Latency = 28;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup407, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
                                                                            VPGATHERDDrm)>;
 
 def SPRWriteResGroup408 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
   let Latency = 15;

 
 def SPRWriteResGroup413 : SchedWriteRes<[SPRPort00]> {
   let Latency = 10;
 }
 def : InstRW<[SPRWriteResGroup413], (instregex "^VGF2P8AFFINE((INV)?)QBZrrikz$")>;
 def : InstRW<[SPRWriteResGroup413], (instrs VGF2P8MULBZrrkz)>;
 
 def SPRWriteResGroup414 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup414], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
 
 def SPRWriteResGroup415 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup415], (instrs VLDMXCSR)>;
 
 def SPRWriteResGroup416 : SchedWriteRes<[SPRPort01, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
-  let ResourceCycles = [1, 1, 1, 8, 1, 1, 2, 3];
+  let ReleaseAtCycles = [1, 1, 1, 8, 1, 1, 2, 3];
   let Latency = 40;
   let NumMicroOps = 18;
 }
 def : InstRW<[SPRWriteResGroup416], (instrs VMCLEARm)>;
 
 def SPRWriteResGroup417 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
   let Latency = 11;
   let NumMicroOps = 2;

 }
 def : InstRW<[SPRWriteResGroup418], (instregex "^VMOVDQU(8|16)Z(128|256)rrk(z?)((_REV)?)$",
                                                "^VMOVSHZrrk(z?)((_REV)?)$",
                                                "^VP(ADD|SUB)(B|W)Z(128|256)rrk(z?)$",
                                                "^VPBLENDM(B|W)Z(128|256)rrk(z?)$",
                                                "^VPMOVM2(B|W)Z(128|256)rr$")>;
 
 def SPRWriteResGroup419 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 2, 2];
+  let ReleaseAtCycles = [1, 2, 2];
   let Latency = 12;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup419], (instrs VMOVDQU8Zmrk)>;
 
 def SPRWriteResGroup420 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let Latency = 477;
   let NumMicroOps = 2;

 
 def SPRWriteResGroup430 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
   let Latency = 471;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup430], (instrs VMOVNTPSZmr)>;
 
 def SPRWriteResGroup431 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [3, 1, 8];
+  let ReleaseAtCycles = [3, 1, 8];
   let Latency = 10;
   let NumMicroOps = 12;
 }
 def : InstRW<[SPRWriteResGroup431, ReadAfterVecXLd], (instregex "^VP2INTERSECTDZ128rm(b?)$")>;
 def : InstRW<[SPRWriteResGroup431, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZ256rm(b?)$")>;
 
 def SPRWriteResGroup432 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [4, 8];
+  let ReleaseAtCycles = [4, 8];
   let Latency = 10;
   let NumMicroOps = 12;
 }
 def : InstRW<[SPRWriteResGroup432], (instrs VP2INTERSECTDZ128rr,
                                             VP2INTERSECTQZ256rr)>;
 
 def SPRWriteResGroup433 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 8, 7, 2, 1, 11];
+  let ReleaseAtCycles = [1, 8, 7, 2, 1, 11];
   let Latency = 27;
   let NumMicroOps = 30;
 }
 def : InstRW<[SPRWriteResGroup433, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZ256rm(b?)$")>;
 
 def SPRWriteResGroup434 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
-  let ResourceCycles = [1, 8, 8, 2, 11];
+  let ReleaseAtCycles = [1, 8, 8, 2, 11];
   let Latency = 27;
   let NumMicroOps = 30;
 }
 def : InstRW<[SPRWriteResGroup434], (instrs VP2INTERSECTDZ256rr)>;
 
 def SPRWriteResGroup435 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [13, 9, 1, 23];
+  let ReleaseAtCycles = [13, 9, 1, 23];
   let Latency = 40;
   let NumMicroOps = 46;
 }
 def : InstRW<[SPRWriteResGroup435, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZrm(b?)$")>;
 
 def SPRWriteResGroup436 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [13, 10, 23];
+  let ReleaseAtCycles = [13, 10, 23];
   let Latency = 40;
   let NumMicroOps = 46;
 }
 def : InstRW<[SPRWriteResGroup436], (instrs VP2INTERSECTDZrr)>;
 
 def SPRWriteResGroup437 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 4];
+  let ReleaseAtCycles = [1, 4];
   let Latency = 6;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup437, ReadAfterVecXLd], (instregex "^VP2INTERSECTQZ128rm(b?)$")>;
 
 def SPRWriteResGroup438 : SchedWriteRes<[SPRPort05]> {
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let Latency = 6;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup438], (instrs VP2INTERSECTQZ128rr)>;
 
 def SPRWriteResGroup439 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [8, 7, 1, 14];
+  let ReleaseAtCycles = [8, 7, 1, 14];
   let Latency = 29;
   let NumMicroOps = 30;
 }
 def : InstRW<[SPRWriteResGroup439, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZrm(b?)$")>;
 
 def SPRWriteResGroup440 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [8, 8, 14];
+  let ReleaseAtCycles = [8, 8, 14];
   let Latency = 30;
   let NumMicroOps = 30;
 }
 def : InstRW<[SPRWriteResGroup440], (instrs VP2INTERSECTQZrr)>;
 
 def SPRWriteResGroup441 : SchedWriteRes<[SPRPort00_01]> {
   let Latency = 3;
 }

 def : InstRW<[SPRWriteResGroup443], (instregex "^VPBROADCASTM(B2Q|W2D)Z(128|256)rr$",
                                                "^VPBROADCASTM(B2Q|W2D)Zrr$",
                                                "^VP(ERM|SRA)WZrrk(z?)$",
                                                "^VPSHUFBITQMBZ(128|256)rr$",
                                                "^VPS(L|R)LWZrrk(z?)$")>;
 def : InstRW<[SPRWriteResGroup443], (instrs VPSHUFBITQMBZrr)>;
 
 def SPRWriteResGroup444 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 1, 2, 1];
+  let ReleaseAtCycles = [1, 1, 1, 2, 1];
   let Latency = 12;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup444], (instregex "^VPCOMPRESS(B|W)Z(128|256)mr$")>;
 def : InstRW<[SPRWriteResGroup444], (instrs VPCOMPRESSWZmr)>;
 
 def SPRWriteResGroup445 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 1, 2, 1];
+  let ReleaseAtCycles = [1, 1, 1, 2, 1];
   let Latency = 14;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup445], (instregex "^VPCOMPRESS(B|W)Z(128|256)mrk$")>;
 def : InstRW<[SPRWriteResGroup445], (instrs VPCOMPRESSWZmrk)>;
 
 def SPRWriteResGroup446 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 2, 2, 2];
+  let ReleaseAtCycles = [1, 1, 2, 2, 2];
   let Latency = 12;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup446], (instrs VPCOMPRESSBZmr)>;
 
 def SPRWriteResGroup447 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 2, 2, 2];
+  let ReleaseAtCycles = [1, 1, 2, 2, 2];
   let Latency = 14;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup447], (instrs VPCOMPRESSBZmrk)>;
 
 def SPRWriteResGroup448 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [5, 4, 1, 5];
+  let ReleaseAtCycles = [5, 4, 1, 5];
   let Latency = 17;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup448], (instregex "^VPCONFLICTDZ128rm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup448], (instrs VPCONFLICTDZ128rmbkz)>;
 
 def SPRWriteResGroup449 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [5, 5, 5];
+  let ReleaseAtCycles = [5, 5, 5];
   let Latency = 12;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup449], (instregex "^VPCONFLICTDZ128rr((k|kz)?)$")>;
 
 def SPRWriteResGroup450 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 5, 1, 1, 9];
+  let ReleaseAtCycles = [7, 5, 1, 1, 9];
   let Latency = 24;
   let NumMicroOps = 23;
 }
 def : InstRW<[SPRWriteResGroup450], (instregex "^VPCONFLICTDZ256rm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup450], (instrs VPCONFLICTDZ256rmbkz)>;
 
 def SPRWriteResGroup451 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [7, 6, 1, 9];
+  let ReleaseAtCycles = [7, 6, 1, 9];
   let Latency = 17;
   let NumMicroOps = 23;
 }
 def : InstRW<[SPRWriteResGroup451], (instregex "^VPCONFLICTDZ256rr((k|kz)?)$")>;
 
 def SPRWriteResGroup452 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [11, 8, 1, 17];
+  let ReleaseAtCycles = [11, 8, 1, 17];
   let Latency = 33;
   let NumMicroOps = 37;
 }
 def : InstRW<[SPRWriteResGroup452], (instregex "^VPCONFLICTDZrm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup452], (instrs VPCONFLICTDZrmbkz)>;
 
 def SPRWriteResGroup453 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [11, 9, 17];
+  let ReleaseAtCycles = [11, 9, 17];
   let Latency = 26;
   let NumMicroOps = 37;
 }
 def : InstRW<[SPRWriteResGroup453], (instregex "^VPCONFLICTDZrr((kz)?)$")>;
 
 def SPRWriteResGroup454 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [11, 9, 17];
+  let ReleaseAtCycles = [11, 9, 17];
   let Latency = 25;
   let NumMicroOps = 37;
 }
 def : InstRW<[SPRWriteResGroup454], (instrs VPCONFLICTDZrrk)>;
 
 def SPRWriteResGroup455 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 11;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup455], (instregex "^VPCONFLICTQZ128rm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup455], (instrs VPCONFLICTQZ128rmbkz)>;
 def : InstRW<[SPRWriteResGroup455, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B128rm$")>;
 
 def SPRWriteResGroup456 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 4;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup456], (instregex "^VPCONFLICTQZ128rr((k|kz)?)$")>;
 
 def SPRWriteResGroup457 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [5, 4, 1, 5];
+  let ReleaseAtCycles = [5, 4, 1, 5];
   let Latency = 20;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup457], (instregex "^VPCONFLICTQZ256rm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup457], (instrs VPCONFLICTQZ256rmbkz)>;
 
 def SPRWriteResGroup458 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [5, 5, 5];
+  let ReleaseAtCycles = [5, 5, 5];
   let Latency = 13;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup458], (instregex "^VPCONFLICTQZ256rr((k|kz)?)$")>;
 
 def SPRWriteResGroup459 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [7, 5, 1, 9];
+  let ReleaseAtCycles = [7, 5, 1, 9];
   let Latency = 23;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup459], (instregex "^VPCONFLICTQZrm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup459], (instrs VPCONFLICTQZrmbkz)>;
 
 def SPRWriteResGroup460 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [7, 6, 9];
+  let ReleaseAtCycles = [7, 6, 9];
   let Latency = 17;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup460], (instregex "^VPCONFLICTQZrr((kz)?)$")>;
 
 def SPRWriteResGroup461 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [7, 6, 9];
+  let ReleaseAtCycles = [7, 6, 9];
   let Latency = 16;
   let NumMicroOps = 22;
 }
 def : InstRW<[SPRWriteResGroup461], (instrs VPCONFLICTQZrrk)>;
 
 def SPRWriteResGroup462 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 13;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B128rmk(z?)$")>;
 def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instrs VPERMT2W128rm)>;
 
 def SPRWriteResGroup463 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup463], (instregex "^VPERM(I|T)2B(128|256)rr$")>;
 
 def SPRWriteResGroup464 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup464], (instregex "^VPERM(I|T)2B(128|256)rrk(z?)$",
                                                "^VPERM(I|T)2W(128|256)rr$")>;
 
 def SPRWriteResGroup465 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup465, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B256rm$")>;
 
 def SPRWriteResGroup466 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 14;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B256rmk(z?)$")>;
 def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instrs VPERMI2W128rm,
                                                              VPERMT2W256rm)>;
 
 def SPRWriteResGroup467 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 12;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup467, ReadAfterVecYLd], (instregex "^VPERM(I|T)2Brm$")>;
 
 def SPRWriteResGroup468 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 14;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instregex "^VPERM(I|T)2Brmk(z?)$")>;
 def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instrs VPERMT2Wrm)>;
 
 def SPRWriteResGroup469 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 5;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup469], (instregex "^VPERM(I|T)2Brr$")>;
 
 def SPRWriteResGroup470 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup470], (instregex "^VPERM(I|T)2Brrk(z?)$",
                                                "^VPERM(I|T)2Wrr$")>;
 
 def SPRWriteResGroup471 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 16;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup471, ReadAfterVecYLd], (instregex "^VPERMI2W128rmk(z?)$",
                                                                 "^VPERMT2W256rmk(z?)$")>;
 
 def SPRWriteResGroup472 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 9;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup472], (instregex "^VPERM(I|T)2W(128|256)rrk(z?)$")>;
 
 def SPRWriteResGroup473 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 15;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instregex "^VPERMT2W128rmk(z?)$")>;
 def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instrs VPERMI2W256rm)>;
 
 def SPRWriteResGroup474 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 17;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup474, ReadAfterVecYLd], (instregex "^VPERMI2W256rmk(z?)$")>;
 
 def SPRWriteResGroup475 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 15;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup475, ReadAfterVecYLd], (instrs VPERMI2Wrm)>;
 
 def SPRWriteResGroup476 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 17;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup476, ReadAfterVecYLd], (instregex "^VPERMI2Wrmk(z?)$")>;
 
 def SPRWriteResGroup477 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let Latency = 9;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup477], (instregex "^VPERM(I|T)2Wrrk(z?)$")>;
 
 def SPRWriteResGroup478 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let Latency = 16;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup478, ReadAfterVecYLd], (instregex "^VPERMT2Wrmk(z?)$")>;
 
 def SPRWriteResGroup479 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
   let Latency = 10;
   let NumMicroOps = 3;

 
 def SPRWriteResGroup483 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
   let Latency = 11;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup483, ReadAfterVecYLd], (instrs VPERMWZrm)>;
 
 def SPRWriteResGroup484 : SchedWriteRes<[SPRPort05]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 8;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup484], (instregex "^VPEXPAND(B|W)Z(128|256)rrk(z?)$",
                                                "^VPEXPAND(B|W)Zrrk(z?)$")>;
 
 def SPRWriteResGroup485 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [1, 2, 1];
+  let ReleaseAtCycles = [1, 2, 1];
   let Latency = 10;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup485, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
 
 def SPRWriteResGroup486 : SchedWriteRes<[SPRPort00_01]> {
   let Latency = 7;
 }

 
 def SPRWriteResGroup496 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
   let Latency = 14;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup496], (instregex "^VPMOVQDZ((256)?)mrk$")>;
 
 def SPRWriteResGroup497 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 23;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instregex "^VPMULLQZ128rm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instrs VPMULLQZ128rmbkz)>;
 def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instregex "^VPMULLQZ256rm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instrs VPMULLQZ256rmbkz)>;
 
 def SPRWriteResGroup498 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 15;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup498], (instregex "^VPMULLQZ(128|256)rr((k|kz)?)$")>;
 
 def SPRWriteResGroup499 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 23;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instregex "^VPMULLQZrm((b|k|bk|kz)?)$")>;
 def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instrs VPMULLQZrmbkz)>;
 
 def SPRWriteResGroup500 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 15;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup500], (instregex "^VPMULLQZrr((k|kz)?)$")>;
 
 def SPRWriteResGroup501 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 1, 4, 4];
+  let ReleaseAtCycles = [1, 1, 1, 4, 4];
   let Latency = 12;
   let NumMicroOps = 11;
 }
 def : InstRW<[SPRWriteResGroup501], (instregex "^VPSCATTER(D|Q)QZ256mr$",
                                                "^VSCATTER(D|Q)PDZ256mr$")>;
 def : InstRW<[SPRWriteResGroup501], (instrs VPSCATTERDDZ128mr,
                                             VPSCATTERQDZ256mr,
                                             VSCATTERDPSZ128mr,
                                             VSCATTERQPSZ256mr)>;
 
 def SPRWriteResGroup502 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 1, 8, 8];
+  let ReleaseAtCycles = [1, 1, 1, 8, 8];
   let Latency = 12;
   let NumMicroOps = 19;
 }
 def : InstRW<[SPRWriteResGroup502], (instrs VPSCATTERDDZ256mr,
                                             VSCATTERDPSZ256mr)>;
 
 def SPRWriteResGroup503 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 16, 16];
+  let ReleaseAtCycles = [2, 1, 16, 16];
   let Latency = 19;
   let NumMicroOps = 35;
 }
 def : InstRW<[SPRWriteResGroup503], (instrs VPSCATTERDDZmr,
                                             VSCATTERDPSZmr)>;
 
 def SPRWriteResGroup504 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [1, 1, 1, 2, 2];
+  let ReleaseAtCycles = [1, 1, 1, 2, 2];
   let Latency = 12;
   let NumMicroOps = 7;
 }
 def : InstRW<[SPRWriteResGroup504], (instregex "^VPSCATTER(D|Q)QZ128mr$",
                                                "^VSCATTER(D|Q)PDZ128mr$")>;
 def : InstRW<[SPRWriteResGroup504], (instrs VPSCATTERQDZ128mr,
                                             VSCATTERQPSZ128mr)>;
 
 def SPRWriteResGroup505 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
-  let ResourceCycles = [2, 1, 8, 8];
+  let ReleaseAtCycles = [2, 1, 8, 8];
   let Latency = 12;
   let NumMicroOps = 19;
 }
 def : InstRW<[SPRWriteResGroup505], (instregex "^VPSCATTER(D|Q)QZmr$",
                                                "^VSCATTER(D|Q)PDZmr$")>;
 def : InstRW<[SPRWriteResGroup505], (instrs VPSCATTERQDZmr,
                                             VSCATTERQPSZmr)>;
 

 def SPRWriteResGroup522 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
   let Latency = 4;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup522], (instregex "^VPS(L|R)LWZ128rrk(z?)$",
                                                "^VPSRAWZ128rrk(z?)$")>;
 
 def SPRWriteResGroup523 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 16;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup523, ReadAfterVecYLd], (instregex "^VR(CP|SQRT)PHZm(bk|kz)$",
                                                                 "^VR(CP|SQRT)PHZm(k|bkz)$")>;
 
 def SPRWriteResGroup524 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 9;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup524], (instregex "^VRCPPHZrk(z?)$")>;
 
 def SPRWriteResGroup525 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 20;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)i$")>;
 def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instrs VREDUCESHZrmi)>;
 def : InstRW<[SPRWriteResGroup525, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)i$")>;
 
 def SPRWriteResGroup526 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 22;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup526, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)ik(z?)$",
                                                                 "^VREDUCESHZrmik(z?)$")>;
 def : InstRW<[SPRWriteResGroup526, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)ik(z?)$")>;
 
 def SPRWriteResGroup527 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup527], (instregex "^VREDUCEPHZ(128|256)rri$",
                                                "^VREDUCESHZrri(b?)$")>;
 
 def SPRWriteResGroup528 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 16;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup528], (instregex "^VREDUCEPHZ(128|256)rrik(z?)$",
                                                "^VREDUCESHZrri(bk|kz)$",
                                                "^VREDUCESHZrri(k|bkz)$")>;
 
 def SPRWriteResGroup529 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 20;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup529, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)i$")>;
 
 def SPRWriteResGroup530 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let Latency = 22;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup530, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)ik(z?)$")>;
 
 def SPRWriteResGroup531 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup531], (instregex "^VREDUCEPHZrri(b?)$")>;
 
 def SPRWriteResGroup532 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let Latency = 16;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup532], (instregex "^VREDUCEPHZrri(bk|kz)$",
                                                "^VREDUCEPHZrri(k|bkz)$")>;
 
 def SPRWriteResGroup533 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 8;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup533], (instregex "^VRNDSCALEP(D|S)Zrri((b|k|bk|kz)?)$",
                                                "^VRNDSCALEP(D|S)Zrribkz$")>;
 
 def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 17;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup534, ReadAfterVecXLd], (instregex "^VRNDSCALEPHZ128rm(b?)ik(z?)$",
                                                                 "^VRNDSCALESHZm_Intk(z?)$",
                                                                 "^VSCALEFPHZ128rm(bk|kz)$",
                                                                 "^VSCALEFPHZ128rm(k|bkz)$")>;
 def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ256rm(b?)ik(z?)$",
                                                                 "^VSCALEFPHZ256rm(bk|kz)$",
                                                                 "^VSCALEFPHZ256rm(k|bkz)$")>;
 def : InstRW<[SPRWriteResGroup534, ReadAfterVecLd], (instregex "^VSCALEFSHZrmk(z?)$")>;
 
 def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 11;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$",
                                                "^VRNDSCALESHZr(b?)_Intk(z?)$",
                                                "^VSCALEFPHZ(128|256)rrk(z?)$",
                                                "^VSCALEFSHZrrb_Intk(z?)$",
                                                "^VSCALEFSHZrrk(z?)$")>;
 
 def SPRWriteResGroup536 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 17;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup536, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZrm(b?)ik(z?)$",
                                                                 "^VSCALEFPHZrm(bk|kz)$",
                                                                 "^VSCALEFPHZrm(k|bkz)$")>;
 
 def SPRWriteResGroup537 : SchedWriteRes<[SPRPort00]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 11;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup537], (instregex "^VRNDSCALEPHZrri(bk|kz)$",
                                                "^VRNDSCALEPHZrri(k|bkz)$",
                                                "^VSCALEFPHZrr(bk|kz)$",
                                                "^VSCALEFPHZrr(k|bkz)$")>;
 
 def SPRWriteResGroup538 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup538], (instregex "^VRSQRT14P(D|S)Zr$")>;
 def : InstRW<[SPRWriteResGroup538], (instrs VRSQRT14PSZrk,
                                             VRSQRTPHZr)>;
 
 def SPRWriteResGroup539 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
   let Latency = 25;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup539], (instrs VSQRTPDYm)>;
 def : InstRW<[SPRWriteResGroup539, ReadAfterVecYLd], (instregex "^VSQRTPDZ256m(b?)$")>;
 
 def SPRWriteResGroup540 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
   let Latency = 20;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup540, ReadAfterVecXLd], (instregex "^VSQRTPDZ128m(bk|kz)$",
                                                                 "^VSQRTPDZ128m(k|bkz)$")>;
 def : InstRW<[SPRWriteResGroup540, ReadAfterVecLd], (instregex "^VSQRTSDZm_Intk(z?)$")>;
 
 def SPRWriteResGroup541 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 38;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup541, ReadAfterVecYLd], (instrs VSQRTPDZm)>;
 
 def SPRWriteResGroup542 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 39;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup542, ReadAfterVecYLd], (instrs VSQRTPDZmb)>;
 
 def SPRWriteResGroup543 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 31;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup543], (instrs VSQRTPDZr)>;
 
 def SPRWriteResGroup544 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 41;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup544, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(bk|kz)$",
                                                                 "^VSQRTPHZ128m(k|bkz)$")>;
 
 def SPRWriteResGroup545 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 35;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup545], (instregex "^VSQRTPHZ(128|256)rk$")>;
 def : InstRW<[SPRWriteResGroup545], (instrs VSQRTPHZ256rkz)>;
 
 def SPRWriteResGroup546 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 12;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup546], (instrs VSQRTPHZ128rkz)>;
 
 def SPRWriteResGroup547 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 40;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup547, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(b?)$")>;
 
 def SPRWriteResGroup548 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1, 1];
+  let ReleaseAtCycles = [2, 1, 1];
   let Latency = 42;
   let NumMicroOps = 4;
 }
 def : InstRW<[SPRWriteResGroup548, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(bk|kz)$",
                                                                 "^VSQRTPHZ256m(k|bkz)$")>;
 
 def SPRWriteResGroup549 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [4, 2, 1, 1, 1];
+  let ReleaseAtCycles = [4, 2, 1, 1, 1];
   let Latency = 53;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup549, ReadAfterVecYLd], (instregex "^VSQRTPHZm(b?)$")>;
 
 def SPRWriteResGroup550 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
-  let ResourceCycles = [4, 2, 1, 1, 1];
+  let ReleaseAtCycles = [4, 2, 1, 1, 1];
   let Latency = 55;
   let NumMicroOps = 9;
 }
 def : InstRW<[SPRWriteResGroup550, ReadAfterVecYLd], (instregex "^VSQRTPHZm(bk|kz)$",
                                                                 "^VSQRTPHZm(k|bkz)$")>;
 
 def SPRWriteResGroup551 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [4, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1];
   let Latency = 45;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup551], (instregex "^VSQRTPHZr(b?)$")>;
 
 def SPRWriteResGroup552 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
-  let ResourceCycles = [4, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1];
   let Latency = 47;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup552], (instregex "^VSQRTPHZr(bk|kz)$",
                                                "^VSQRTPHZr(k|bkz)$")>;
 
 def SPRWriteResGroup553 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 19;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup553], (instrs VSQRTPSZr)>;
 
 def SPRWriteResGroup554 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10]> {
-  let ResourceCycles = [1, 2, 3, 3, 1];
+  let ReleaseAtCycles = [1, 2, 3, 3, 1];
   let Latency = 12;
   let NumMicroOps = 10;
 }
 def : InstRW<[SPRWriteResGroup554], (instrs VZEROALL)>;
 
 def SPRWriteResGroup555 : SchedWriteRes<[SPRPort00_01_05_06]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup555], (instrs WAIT)>;
 
 def SPRWriteResGroup556 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
+  let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 144;
 }
 def : InstRW<[SPRWriteResGroup556], (instrs WRMSR)>;
 
 def SPRWriteResGroup557 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
-  let ResourceCycles = [2, 1, 4, 1];
+  let ReleaseAtCycles = [2, 1, 4, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 8;
 }
 def : InstRW<[SPRWriteResGroup557], (instrs WRPKRUr)>;
 
 def SPRWriteResGroup558 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 12;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup558, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
 
 def SPRWriteResGroup559 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let Latency = 13;
   let NumMicroOps = 2;
 }
 def : InstRW<[SPRWriteResGroup559, WriteRMW], (instrs XADD8rm)>;
 
 def SPRWriteResGroup560 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
-  let ResourceCycles = [4, 1];
+  let ReleaseAtCycles = [4, 1];
   let Latency = 39;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup560, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
 
 def SPRWriteResGroup561 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
-  let ResourceCycles = [5, 1];
+  let ReleaseAtCycles = [5, 1];
   let Latency = 39;
   let NumMicroOps = 6;
 }
 def : InstRW<[SPRWriteResGroup561, WriteRMW], (instrs XCHG64rm)>;
 
 def SPRWriteResGroup562 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
-  let ResourceCycles = [4, 1];
+  let ReleaseAtCycles = [4, 1];
   let Latency = 40;
   let NumMicroOps = 5;
 }
 def : InstRW<[SPRWriteResGroup562, WriteRMW], (instrs XCHG8rm)>;
 
 def SPRWriteResGroup563 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_05, SPRPort01, SPRPort05, SPRPort06]> {
-  let ResourceCycles = [2, 4, 2, 1, 2, 4];
+  let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
   let Latency = 17;
   let NumMicroOps = 15;
 }
 def : InstRW<[SPRWriteResGroup563], (instrs XCH_F)>;
 
 def SPRWriteResGroup564 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01]> {
-  let ResourceCycles = [7, 3, 8, 5];
+  let ReleaseAtCycles = [7, 3, 8, 5];
   let Latency = 4;
   let NumMicroOps = 23;
 }
 def : InstRW<[SPRWriteResGroup564], (instrs XGETBV)>;
 
 def SPRWriteResGroup565 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup565], (instrs XLAT)>;
 
 def SPRWriteResGroup566 : SchedWriteRes<[SPRPort01, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
-  let ResourceCycles = [1, 21, 1, 8];
+  let ReleaseAtCycles = [1, 21, 1, 8];
   let Latency = 37;
   let NumMicroOps = 31;
 }
 def : InstRW<[SPRWriteResGroup566], (instregex "^XRSTOR((S|64)?)$")>;
 def : InstRW<[SPRWriteResGroup566], (instrs XRSTORS64)>;
 
 def SPRWriteResGroup567 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
   let Latency = 42;
   let NumMicroOps = 140;
 }
 def : InstRW<[SPRWriteResGroup567], (instrs XSAVE)>;
 
 def SPRWriteResGroup568 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
   let Latency = 41;
   let NumMicroOps = 140;
 }
 def : InstRW<[SPRWriteResGroup568], (instrs XSAVE64)>;
 
 def SPRWriteResGroup569 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
+  let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
   let Latency = 42;
   let NumMicroOps = 151;
 }
 def : InstRW<[SPRWriteResGroup569], (instrs XSAVEC)>;
 
 def SPRWriteResGroup570 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
+  let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
   let Latency = 42;
   let NumMicroOps = 152;
 }
 def : InstRW<[SPRWriteResGroup570], (instrs XSAVEC64)>;
 
 def SPRWriteResGroup571 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
+  let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
   let Latency = 42;
   let NumMicroOps = 155;
 }
 def : InstRW<[SPRWriteResGroup571], (instrs XSAVEOPT)>;
 
 def SPRWriteResGroup572 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
+  let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
   let Latency = 42;
   let NumMicroOps = 156;
 }
 def : InstRW<[SPRWriteResGroup572], (instrs XSAVEOPT64)>;
 
 def SPRWriteResGroup573 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
+  let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
   let Latency = 42;
   let NumMicroOps = 184;
 }
 def : InstRW<[SPRWriteResGroup573], (instrs XSAVES)>;
 
 def SPRWriteResGroup574 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
-  let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
+  let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
   let Latency = 42;
   let NumMicroOps = 186;
 }
 def : InstRW<[SPRWriteResGroup574], (instrs XSAVES64)>;
 
 def SPRWriteResGroup575 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort05]> {
-  let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
+  let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
   let Latency = 5;
   let NumMicroOps = 54;
 }
 def : InstRW<[SPRWriteResGroup575], (instrs XSETBV)>;
 
 def SPRWriteResGroup576 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let Latency = SapphireRapidsModel.MaxLatency;
   let NumMicroOps = 3;
 }
 def : InstRW<[SPRWriteResGroup576], (instrs XTEST)>;
 
 }

llvm/lib/Target/X86/X86SchedSkylakeClient.td

 // folded loads.
 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [1], int UOps = 1,
                           int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3/7 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 

 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 
 // Vector insert/extract operations.
 def : WriteRes<WriteVecInsert, [SKLPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 
 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {

 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 
 // Strings instructions.
 
 // Packed Compare Implicit Length Strings, Return Mask
 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
   let Latency = 19;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
   let Latency = 25;
   let NumMicroOps = 10;
-  let ResourceCycles = [4,3,1,1,1];
+  let ReleaseAtCycles = [4,3,1,1,1];
 }
 
 // Packed Compare Implicit Length Strings, Return Index
 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [4,3,1];
+  let ReleaseAtCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 
 // AES instructions.
 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 
 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
   let Latency = 20;
   let NumMicroOps = 11;
-  let ResourceCycles = [3,6,2];
+  let ReleaseAtCycles = [3,6,2];
 }
 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
   let Latency = 25;
   let NumMicroOps = 11;
-  let ResourceCycles = [3,6,1,1];
+  let ReleaseAtCycles = [3,6,1,1];
 }
 
 // Carry-less multiplication instructions.
 def : WriteRes<WriteCLMul, [SKLPort5]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 // Catch-all for expensive system instructions.
 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 
 // AVX2.
 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 
 // Old microcoded instructions that nobody use.
 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 
 // Fence instructions.
 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
 
 // Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 
 // Nop, not very useful expect it provides a model for nops!
 def : WriteRes<WriteNop, []>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Horizontal add/sub  instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 
 // Remaining instrs.
 
 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
                                             "MMX_PADDUS(B|W)rr",
                                             "MMX_PAVG(B|W)rr",
                                             "MMX_PCMPEQ(B|D|W)rr",
                                             "MMX_PCMPGT(B|D|W)rr",
                                             "MMX_P(MAX|MIN)SWrr",
                                             "MMX_P(MAX|MIN)UBrr",
                                             "MMX_PSUBS(B|W)rr",
                                             "MMX_PSUBUS(B|W)rr")>;
 
 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
                                             "UCOM_F(P?)r")>;
 
 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 
 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 
 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 
 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 
 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
                                             "VPBLENDD(Y?)rri")>;
 
 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m,
                                           SIDT64m,
                                           SMSW16m,
                                           STRm,
                                           SYSCALL)>;
 
 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
   let Latency = 1;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
 
 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 
 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
                                           MMX_MOVDQ2Qrr)>;
 
 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
                                           WAIT,
                                           XGETBV)>;
 
 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 
 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 
 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
                                           JCXZ, JECXZ, JRCXZ,
                                           ADC8i8, SBB8i8,
                                           ADC16i16, SBB16i16,
                                           ADC32i32, SBB32i32,
                                           ADC64i32, SBB64i32)>;
 
 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 
 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 
 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
                                           STOSB, STOSL, STOSQ, STOSW)>;
 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 
 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
                                              "PEXT(32|64)rr")>;
 
 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
                                              "VPBROADCAST(B|W)rr")>;
 
 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 
 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 
 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
                                              "(V?)PHSUBSW(Y?)rr")>;
 
 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
                                           MMX_PACKSSWBrr,
                                           MMX_PACKUSWBrr)>;
 
 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 
 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
 
 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                           RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
   let Latency = 5;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
   let Latency = 6;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 
 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 
 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 
 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 
 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
                                              "IST_F(16|32)m")>;
 
 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 
 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 
 def SKLWriteResGroup56 : SchedWriteRes<[]> {
   let Latency = 0;
   let NumMicroOps = 4;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
 }
 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 
 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 
 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort01]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>;
 
 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 
 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 
 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,4];
+  let ReleaseAtCycles = [1,1,4];
 }
 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
 
 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
                                           VPBROADCASTDrm,
                                           VPBROADCASTQrm)>;
 def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
                                              "(V?)MOVSLDUPrm",
                                              "(V?)MOVDDUPrm")>;
 
 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;
 
 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
                                           MMX_PADDSWrm,
                                           MMX_PADDUSBrm,
                                           MMX_PADDUSWrm,
                                           MMX_PAVGBrm,
                                           MMX_PAVGWrm,
                                           MMX_PCMPEQBrm,
def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
                                           MMX_PSUBSBrm,
                                           MMX_PSUBSWrm,
                                           MMX_PSUBUSBrm,
                                           MMX_PSUBUSWrm)>;
 
 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;
 def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
 
 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
                                              "MOVBE(16|32|64)rm")>;
 
 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
 
 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
 
 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
 
 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
                                              "SHL(8|16|32|64)m(1|i)",
                                              "SHR(8|16|32|64)m(1|i)")>;
 
 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
                                              "PUSH(16|32|64)rmm")>;
 
 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
   let Latency = 6;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,5];
+  let ReleaseAtCycles = [1,5];
 }
 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
 
 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
 def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
                                           VBROADCASTI128,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
                                           VMOVSHDUPYrm,
                                           VMOVSLDUPYrm,
                                           VPBROADCASTDYrm,
                                           VPBROADCASTQYrm)>;
 
 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
                                              "(V?)PMOV(SX|ZX)BQrm",
                                              "(V?)PMOV(SX|ZX)BWrm",
                                              "(V?)PMOV(SX|ZX)DQrm",
                                              "(V?)PMOV(SX|ZX)WDrm",
                                              "(V?)PMOV(SX|ZX)WQrm")>;
 
 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
                                           VINSERTI128rm,
                                           VPBLENDDrmi)>;
 def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
                                   (instregex "(V?)PADD(B|D|Q|W)rm",
                                              "(V?)PSUB(B|D|Q|W)rm")>;
 
 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
                                           MMX_PACKSSWBrm,
                                           MMX_PACKUSWBrm)>;
 
 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
                                           SCASB, SCASL, SCASQ, SCASW)>;
 
 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;
 
 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
 
 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
 
 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
                                               "ROR(8|16|32|64)m(1|i)")>;
 
 def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
 
 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
 
 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
 def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
 
 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [1,3,1,2];
+  let ReleaseAtCycles = [1,3,1,2];
 }
 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
 
 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
                                               "PEXT(32|64)rm")>;
 
 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
 def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
                                            VPBROADCASTWYrm,
                                            VPMOVSXBDYrm,
                                            VPMOVSXBQYrm,
                                            VPMOVSXWQYrm)>;
 
 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
 def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
                                    (instregex "VPADD(B|D|Q|W)Yrm",
                                               "VPSUB(B|D|Q|W)Yrm")>;
 
 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
   let Latency = 8;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
 
 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
                                               "RCR(8|16|32|64)m(1|i)")>;
 
 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,3];
 }
 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
                                               "ROR(8|16|32|64)mCL",
                                               "SAR(8|16|32|64)mCL",
                                               "SHL(8|16|32|64)mCL",
                                               "SHR(8|16|32|64)mCL")>;
 
 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,2,1];
+  let ReleaseAtCycles = [1,1,1,2,1];
 }
 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
 
 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>;
 
 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
                                            VPCMPGTQrm,
                                            VPMOVSXBWYrm,
                                            VPMOVSXDQYrm,
                                            VPMOVSXWDYrm,
                                            VPMOVZXWDYrm)>;
 
 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>;
 
 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
   let Latency = 9;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
                                               "(V?)PHSUBSWrm")>;
 
 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
                                               "LSL(16|32|64)rm")>;
 
 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                               "ILD_F(16|32|64)m")>;
 def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
 
 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>;
 
 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
   let Latency = 10;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
                                            VPHSUBSWYrm)>;
 
 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 10;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,1,1,3];
 }
 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
 
 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
 
 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
 
 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
   let Latency = 11;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,3,2];
+  let ReleaseAtCycles = [2,3,2];
 }
 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
                                               "RCR(16|32|64)rCL")>;
 
 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 11;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,5,1,2];
+  let ReleaseAtCycles = [1,5,1,2];
 }
 def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
 
 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
   let Latency = 11;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,9];
+  let ReleaseAtCycles = [2,9];
 }
 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
 
 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
 
 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
 
 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 14;
   let NumMicroOps = 10;
-  let ResourceCycles = [2,4,1,3];
+  let ReleaseAtCycles = [2,4,1,3];
 }
 def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
 
 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
   let Latency = 15;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
 
 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 15;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,1,1,5,1,1];
+  let ReleaseAtCycles = [1,1,1,5,1,1];
 }
 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
 
 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 16;
   let NumMicroOps = 14;
-  let ResourceCycles = [1,1,1,4,2,5];
+  let ReleaseAtCycles = [1,1,1,4,2,5];
 }
 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
 
 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
   let Latency = 16;
   let NumMicroOps = 16;
-  let ResourceCycles = [16];
+  let ReleaseAtCycles = [16];
 }
 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
 
 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
   let Latency = 17;
   let NumMicroOps = 15;
-  let ResourceCycles = [2,1,2,4,2,4];
+  let ReleaseAtCycles = [2,1,2,4,2,4];
 }
 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
 
 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,5];
+  let ReleaseAtCycles = [1,1,1,5];
 }
 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
 
 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 18;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,1,1,4,1,2];
+  let ReleaseAtCycles = [2,1,1,4,1,2];
 }
 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
 
 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
   let Latency = 20;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
 
 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 20;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,1,1,1,2];
 }
 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
 
 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
   let Latency = 20;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,2,7];
+  let ReleaseAtCycles = [1,2,7];
 }
 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
 
 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 22;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
 
 def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
   let Latency = 18;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
                                             VGATHERQPDrm, VPGATHERQQrm,
                                             VGATHERQPSrm, VPGATHERQDrm)>;
 
 def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
   let Latency = 20;
   let NumMicroOps = 5; // 2 uops peform multiple loads
-  let ResourceCycles = [1,4,1,1];
+  let ReleaseAtCycles = [1,4,1,1];
 }
 def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
                                             VGATHERDPSrm,  VPGATHERDDrm,
                                             VGATHERQPDYrm, VPGATHERQQYrm,
                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
 
 def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
   let Latency = 22;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,8,1,1];
+  let ReleaseAtCycles = [1,8,1,1];
 }
 def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm,  VPGATHERDDYrm)>;
 
 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 23;
   let NumMicroOps = 19;
-  let ResourceCycles = [2,1,4,1,1,4,6];
+  let ReleaseAtCycles = [2,1,4,1,1,4,6];
 }
 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
 
 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
   let Latency = 25;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
 
 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 27;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
 
 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
   let Latency = 30;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
 
 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,3,4,10];
+  let ReleaseAtCycles = [1,5,3,4,10];
 }
 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
                                               "IN(8|16|32)rr")>;
 
 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,2,1,4,10];
+  let ReleaseAtCycles = [1,5,2,1,4,10];
 }
 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
                                               "OUT(8|16|32)rr")>;
 
 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
   let Latency = 37;
   let NumMicroOps = 31;
-  let ResourceCycles = [1,8,1,21];
+  let ReleaseAtCycles = [1,8,1,21];
 }
 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
 
 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
   let Latency = 40;
   let NumMicroOps = 18;
-  let ResourceCycles = [1,1,2,3,1,1,1,8];
+  let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
 }
 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
 
 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
   let Latency = 41;
   let NumMicroOps = 39;
-  let ResourceCycles = [1,10,1,1,26];
+  let ReleaseAtCycles = [1,10,1,1,26];
 }
 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
 
 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
   let Latency = 42;
   let NumMicroOps = 22;
-  let ResourceCycles = [2,20];
+  let ReleaseAtCycles = [2,20];
 }
 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
 
 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
   let Latency = 42;
   let NumMicroOps = 40;
-  let ResourceCycles = [1,11,1,1,26];
+  let ReleaseAtCycles = [1,11,1,1,26];
 }
 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
 
 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
   let Latency = 46;
   let NumMicroOps = 44;
-  let ResourceCycles = [1,11,1,1,30];
+  let ReleaseAtCycles = [1,11,1,1,30];
 }
 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
 
 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
   let Latency = 62;
   let NumMicroOps = 64;
-  let ResourceCycles = [2,8,5,10,39];
+  let ReleaseAtCycles = [2,8,5,10,39];
 }
 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
 
 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 63;
   let NumMicroOps = 88;
-  let ResourceCycles = [4,4,31,1,2,1,45];
+  let ReleaseAtCycles = [4,4,31,1,2,1,45];
 }
 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
 
 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
   let Latency = 63;
   let NumMicroOps = 90;
-  let ResourceCycles = [4,2,33,1,2,1,47];
+  let ReleaseAtCycles = [4,2,33,1,2,1,47];
 }
 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
 
 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
   let Latency = 75;
   let NumMicroOps = 15;
-  let ResourceCycles = [6,3,6];
+  let ReleaseAtCycles = [6,3,6];
 }
 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
 
 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
   let Latency = 106;
   let NumMicroOps = 100;
-  let ResourceCycles = [9,1,11,16,1,11,21,30];
+  let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
 }
 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
 
 def: InstRW<[WriteZero], (instrs CLC)>;
 
 
 // Instruction variants handled by the renamer. These might not need execution
 // ports in certain conditions.

 ]>;
 def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
                                                VPCMPGTDYrr,
                                                VPCMPGTWYrr)>;
 
 def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [SKLWritePSUB]>
 ]>;
 def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
                                                PSUBDrr, VPSUBDrr,
                                                PSUBQrr, VPSUBQrr,
                                                PSUBWrr, VPSUBWrr,
                                                VPSUBBYrr,
                                                VPSUBDYrr,
                                                VPSUBQYrr,
                                                VPSUBWYrr)>;
 
 def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [SKLWritePCMPGTQ]>
 ]>;
 def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
                                                   VPCMPGTQYrr)>;
 
 
 // CMOVs that use both Z and C flag require an extra uop.
 def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
   let Latency = 7;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
   let NumMicroOps = 3;
 }
 
 def SKLCMOVA_CMOVBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,
   SchedVar<NoSchedPred,                             [WriteCMOV]>
 ]>;
 
 def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 // SETCCs that use both Z and C flag require an extra uop.
 def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
   let Latency = 3;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
   let NumMicroOps = 4;
 }
 
 def SKLSETA_SETBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
   SchedVar<NoSchedPred,                         [WriteSETCC]>
 ]>;
 

llvm/lib/Target/X86/X86SchedSkylakeServer.td

 // folded loads.
 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [1], int UOps = 1,
                           int LoadLat = 5, int LoadUOps = 1> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
   // the latency (default = 5).
   def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3/7 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
 

 defm : SKXWriteResPair<WriteVarVecShift,  [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
 
 // Vector insert/extract operations.
 def : WriteRes<WriteVecInsert, [SKXPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 
 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {

 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
 
 // Strings instructions.
 
 // Packed Compare Implicit Length Strings, Return Mask
 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
   let Latency = 19;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
   let Latency = 25;
   let NumMicroOps = 10;
-  let ResourceCycles = [4,3,1,1,1];
+  let ReleaseAtCycles = [4,3,1,1,1];
 }
 
 // Packed Compare Implicit Length Strings, Return Index
 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
   let Latency = 16;
   let NumMicroOps = 4;
-  let ResourceCycles = [3,1];
+  let ReleaseAtCycles = [3,1];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [4,3,1];
+  let ReleaseAtCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
-  let ResourceCycles = [4,3,1,1];
+  let ReleaseAtCycles = [4,3,1,1];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK,    [SKXPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSK,  [SKXPort0]> { let Latency = 2; }
 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
 def : WriteRes<WriteMMXMOVMSK,  [SKXPort0]> { let Latency = 2; }
 
 // AES instructions.
 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 
 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
   let Latency = 20;
   let NumMicroOps = 11;
-  let ResourceCycles = [3,6,2];
+  let ReleaseAtCycles = [3,6,2];
 }
 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
   let Latency = 25;
   let NumMicroOps = 11;
-  let ResourceCycles = [3,6,1,1];
+  let ReleaseAtCycles = [3,6,1,1];
 }
 
 // Carry-less multiplication instructions.
 def : WriteRes<WriteCLMul, [SKXPort5]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 
 // Catch-all for expensive system instructions.
 def : WriteRes<WriteSystem,     [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 
 // AVX2.
 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 
 // Old microcoded instructions that nobody use.
 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 
 // Fence instructions.
 def : WriteRes<WriteFence,  [SKXPort23, SKXPort4]>;
 
 // Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 
 // Nop, not very useful expect it provides a model for nops!
 def : WriteRes<WriteNop, []>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Horizontal add/sub  instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : SKXWriteResPair<WriteFHAdd,  [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
 defm : SKXWriteResPair<WritePHAdd,  [SKXPort5,SKXPort05],  3, [2,1], 3, 5>;
 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
 
 // Remaining instrs.
 
 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
                                             "KANDN(B|D|Q|W)rr",
                                             "KMOV(B|D|Q|W)kk",
                                             "KNOT(B|D|Q|W)rr",
                                             "KOR(B|D|Q|W)rr",
                                             "KXNOR(B|D|Q|W)rr",
                                             "KXOR(B|D|Q|W)rr",
def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
                                             "VPMOVB2M(Z|Z128|Z256)rr",
                                             "VPMOVD2M(Z|Z128|Z256)rr",
                                             "VPMOVQ2M(Z|Z128|Z256)rr",
                                             "VPMOVW2M(Z|Z128|Z256)rr")>;
 
 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
                                             "KMOV(B|D|Q|W)kr",
                                             "UCOM_F(P?)r")>;
 
 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 
 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
 
 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 
 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 
 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
                                             "VBLENDMPS(Z128|Z256)rr",
                                             "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
                                             "(V?)PADD(B|D|Q|W)rr",
                                             "VPBLENDD(Y?)rri",
                                             "VPBLENDMB(Z128|Z256)rr",
                                             "VPBLENDMD(Z128|Z256)rr",
                                             "VPBLENDMQ(Z128|Z256)rr",
                                             "VPBLENDMW(Z128|Z256)rr",
                                             "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
                                             "VPTERNLOGD(Z|Z128|Z256)rri",
                                             "VPTERNLOGQ(Z|Z128|Z256)rri")>;
 
 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup10], (instrs SGDT64m,
                                           SIDT64m,
                                           SMSW16m,
                                           STRm,
                                           SYSCALL)>;
 
 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
   let Latency = 1;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
                                              "ST_FP(32|64|80)m")>;
 
 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 
 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
                                           MMX_MOVDQ2Qrr)>;
 
 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
                                           WAIT,
                                           XGETBV)>;
 
 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
 
 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
 
 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
                                           JCXZ, JECXZ, JRCXZ,
                                           ADC8i8, SBB8i8,
                                           ADC16i16, SBB16i16,
                                           ADC32i32, SBB32i32,
                                           ADC64i32, SBB64i32)>;
 
 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
 
 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 
 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
                                           STOSB, STOSL, STOSQ, STOSW)>;
 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 
 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
   let Latency = 2;
   let NumMicroOps = 5;
-  let ResourceCycles = [2,2,1];
+  let ReleaseAtCycles = [2,2,1];
 }
 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
 
 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
                                              "KORTEST(B|D|Q|W)rr",
                                              "KTEST(B|D|Q|W)rr")>;
 
 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
                                              "PEXT(32|64)rr")>;
 
 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
                                              "VALIGND(Z|Z128|Z256)rri",
                                              "VALIGNQ(Z|Z128|Z256)rri",
                                              "VPBROADCAST(B|W)rr",
                                              "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;
 
 def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
                                              "KSHIFTL(B|D|Q|W)ri",
                                              "KSHIFTR(B|D|Q|W)ri",
                                              "KUNPCK(BW|DQ|WD)rr",
                                              "VCMPPD(Z|Z128|Z256)rri",
                                              "VCMPPS(Z|Z128|Z256)rri",
                                              "VCMP(SD|SS)Zrr",
                                              "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
                                              "VFPCLASS(SD|SS)Zrr",
                                              "VPCMPB(Z|Z128|Z256)rri",
                                              "VPCMPD(Z|Z128|Z256)rri",
                                              "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
                                              "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
                                              "VPCMPQ(Z|Z128|Z256)rri",
                                              "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
                                              "VPCMPW(Z|Z128|Z256)rri",
                                              "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
 
 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
 
 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 
 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
 
 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr,
                                           MMX_PACKSSWBrr,
                                           MMX_PACKUSWBrr)>;
 
 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
 
 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
 
 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                           RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def SKXWriteResGroup44b : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[SKXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def SKXWriteResGroup44c : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 8;
-  let ResourceCycles = [2,4,2];
+  let ReleaseAtCycles = [2,4,2];
 }
 def: InstRW<[SKXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
   let Latency = 3;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
 
 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 
 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
 
 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 
 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
                                              "VCVTPD2UQQ(Z128|Z256)rr",
                                              "VCVTPS2DQ(Y|Z128|Z256)rr",
                                              "(V?)CVTPS2DQrr",
                                              "VCVTPS2UDQ(Z128|Z256)rr",
                                              "VCVTTPD2QQ(Z128|Z256)rr",
                                              "VCVTTPD2UQQ(Z128|Z256)rr",
                                              "VCVTTPS2DQ(Z128|Z256)rr",
                                              "(V?)CVTTPS2DQrr",
                                              "VCVTTPS2UDQ(Z128|Z256)rr")>;
 
 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
   let Latency = 4;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr,
                                            VCVTPD2UQQZrr,
                                            VCVTPS2DQZrr,
                                            VCVTPS2UDQZrr,
                                            VCVTTPD2QQZrr,
                                            VCVTTPD2UQQZrr,
                                            VCVTTPS2DQZrr,
                                            VCVTTPS2UDQZrr)>;
 
 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
                                              "VEXPANDPS(Z|Z128|Z256)rr",
                                              "VPEXPANDD(Z|Z128|Z256)rr",
                                              "VPEXPANDQ(Z|Z128|Z256)rr",
                                              "VPMOVDB(Z|Z128|Z256)rr",
                                              "VPMOVDW(Z|Z128|Z256)rr",
                                              "VPMOVQB(Z|Z128|Z256)rr",
def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
                                              "VPMOVUSQB(Z|Z128|Z256)rr",
                                              "VPMOVUSQD(Z|Z128|Z256)rr",
                                              "VPMOVUSWB(Z|Z128|Z256)rr",
                                              "VPMOVWB(Z|Z128|Z256)rr")>;
 
 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
   let Latency = 4;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
                                              "IST_F(16|32)m",
                                              "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
 
 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
 
 def SKXWriteResGroup56 : SchedWriteRes<[]> {
   let Latency = 0;
   let NumMicroOps = 4;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
 }
 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
 
 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
   let Latency = 4;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
 }
 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 
 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort01]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
                                              "MMX_CVT(T?)PS2PIrr",
                                              "VCVTDQ2PDZ128rr",
                                              "VCVTPD2DQZ128rr",
                                              "(V?)CVT(T?)PD2DQrr",
                                              "VCVTPD2UDQZ128rr",
                                              "VCVTPS2PDZ128rr",
def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
                                              "VCVTUDQ2PDZ128rr",
                                              "VCVTUQQ2PSZ128rr",
                                              "VCVTUSI2SSZrr",
                                              "VCVTUSI(64)?2SDZrr")>;
 
 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
 
 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
 
 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort01]> {
   let Latency = 5;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
                                              "VCVTPS2PHZ256mr(b?)",
                                              "VCVTPS2PHZmr(b?)")>;
 
 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
   let Latency = 5;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVDW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVQB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVQW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSDB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSDW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSQB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSQD(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSQW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVSWB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
                                              "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
                                              "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
 
 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,4];
+  let ReleaseAtCycles = [1,4];
 }
 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
 
 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,4];
+  let ReleaseAtCycles = [1,1,4];
 }
 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
 
 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
   let Latency = 6;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
                                           VPBROADCASTDrm,
                                           VPBROADCASTQrm)>;
 def: InstRW<[SKXWriteResGroup71], (instregex "(V?)MOVSHDUPrm",
                                              "(V?)MOVSLDUPrm",
                                              "(V?)MOVDDUPrm")>;
 
 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
                                              "VCOMPRESSPS(Z|Z128|Z256)rr",
                                              "VPCOMPRESSD(Z|Z128|Z256)rr",
                                              "VPCOMPRESSQ(Z|Z128|Z256)rr",
                                              "VPERMW(Z|Z128|Z256)rr")>;
 
 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,
                                           MMX_PADDSWrm,
                                           MMX_PADDUSBrm,
                                           MMX_PADDUSWrm,
                                           MMX_PAVGBrm,
                                           MMX_PAVGWrm,
                                           MMX_PCMPEQBrm,
def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,
                                           MMX_PSUBSBrm,
                                           MMX_PSUBSWrm,
                                           MMX_PSUBUSBrm,
                                           MMX_PSUBUSWrm)>;
 
 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>;
 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
 
 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
                                              "MOVBE(16|32|64)rm")>;
 
 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
 
 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
 
 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort01]> {
   let Latency = 6;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
                                              "VCVTSI642SSZrr",
                                              "VCVTUSI642SSZrr")>;
 
 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
 
 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
                                              "SHL(8|16|32|64)m(1|i)",
                                              "SHR(8|16|32|64)m(1|i)")>;
 
 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
                                              "PUSH(16|32|64)rmm")>;
 
 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
   let Latency = 6;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,5];
+  let ReleaseAtCycles = [1,5];
 }
 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
 
 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
   let Latency = 7;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
                                           VBROADCASTI128,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
                                           VMOVSHDUPYrm,
                                           VMOVSLDUPYrm,
                                           VPBROADCASTDYrm,
                                           VPBROADCASTQYrm)>;
 
 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
 
 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
                                              "VMOVSSZrm(b?)")>;
 
 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 6;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
                                               "(V?)PMOV(SX|ZX)BQrm",
                                               "(V?)PMOV(SX|ZX)BWrm",
                                               "(V?)PMOV(SX|ZX)DQrm",
                                               "(V?)PMOV(SX|ZX)WDrm",
                                               "(V?)PMOV(SX|ZX)WQrm")>;
 
 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort01]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
                                              "VCVTPD2DQ(Y|Z256)rr",
                                              "VCVTPD2UDQZ256rr",
                                              "VCVTPS2PD(Y|Z256)rr",
                                              "VCVTPS2QQZ256rr",
                                              "VCVTPS2UQQZ256rr",
                                              "VCVTQQ2PSZ256rr",
                                              "VCVTTPD2DQ(Y|Z256)rr",
                                              "VCVTTPD2UDQZ256rr",
                                              "VCVTTPS2QQZ256rr",
                                              "VCVTTPS2UQQZ256rr",
                                              "VCVTUDQ2PDZ256rr",
                                              "VCVTUQQ2PSZ256rr")>;
 
 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
                                            VCVTPD2DQZrr,
                                            VCVTPD2UDQZrr,
                                            VCVTPS2PDZrr,
                                            VCVTPS2QQZrr,
                                            VCVTPS2UQQZrr,
                                            VCVTQQ2PSZrr,
                                            VCVTTPD2DQZrr,
                                            VCVTTPD2UDQZrr,
                                            VCVTTPS2QQZrr,
                                            VCVTTPS2UQQZrr,
                                            VCVTUDQ2PDZrr,
                                            VCVTUQQ2PSZrr)>;
 
 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
                                           VPBLENDDrmi)>;
 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
                                   (instregex "VBLENDMPDZ128rm(b?)",
                                              "VBLENDMPSZ128rm(b?)",
                                              "VBROADCASTI32X2Z128rm(b?)",
                                              "VBROADCASTSSZ128rm(b?)",
def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
                                              "VPSUB(B|D|Q|W)Z128rm(b?)",
                                              "(V?)PSUB(B|D|Q|W)rm",
                                              "VPTERNLOGDZ128rm(b?)i",
                                              "VPTERNLOGQZ128rm(b?)i")>;
 
 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm,
                                           MMX_PACKSSWBrm,
                                           MMX_PACKUSWBrm)>;
 
 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
                                              "VPERMI2W256rr",
                                              "VPERMI2Wrr",
                                              "VPERMT2W128rr",
                                              "VPERMT2W256rr",
                                              "VPERMT2Wrr")>;
 
 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
                                           SCASB, SCASL, SCASQ, SCASW)>;
 
 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort01]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
                                               "VCVT(T?)SS2USI64Zrr")>;
 
 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
 
 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
 
 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>;
 
 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
   let Latency = 7;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
                                               "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
                                               "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
                                               "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
 
 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
                                               "ROR(8|16|32|64)m(1|i)")>;
 
 def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
 
 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
 
 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,1,1];
+  let ReleaseAtCycles = [1,1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;
 
 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [1,2,2,2];
+  let ReleaseAtCycles = [1,2,2,2];
 }
 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
                                            VPSCATTERQQZ128mr,
                                            VSCATTERDPDZ128mr,
                                            VSCATTERQPDZ128mr)>;
 
 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 7;
-  let ResourceCycles = [1,3,1,2];
+  let ReleaseAtCycles = [1,3,1,2];
 }
 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
 
 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 11;
-  let ResourceCycles = [1,4,4,2];
+  let ReleaseAtCycles = [1,4,4,2];
 }
 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
                                            VPSCATTERQQZ256mr,
                                            VSCATTERDPDZ256mr,
                                            VSCATTERQPDZ256mr)>;
 
 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 19;
-  let ResourceCycles = [1,8,8,2];
+  let ReleaseAtCycles = [1,8,8,2];
 }
 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
                                            VPSCATTERQQZmr,
                                            VSCATTERDPDZmr,
                                            VSCATTERQPDZmr)>;
 
 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 36;
-  let ResourceCycles = [1,16,1,16,2];
+  let ReleaseAtCycles = [1,16,1,16,2];
 }
 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
 
 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
                                               "PEXT(32|64)rm")>;
 
 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
                                               "VPBROADCASTB(Z|Z256)rm(b?)",
                                               "VPBROADCASTW(Z|Z256)rm(b?)")>;
 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
                                            VPBROADCASTWYrm,
                                            VPMOVSXBDYrm,
                                            VPMOVSXBQYrm,
                                            VPMOVSXWQYrm)>;
 
 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
                                            VPBLENDDYrmi)>;
 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
                                    (instregex "VBLENDMPD(Z|Z256)rm(b?)",
                                               "VBLENDMPS(Z|Z256)rm(b?)",
                                               "VBROADCASTF32X2Z256rm(b?)",
                                               "VBROADCASTF32X2Zrm(b?)",
def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
                                               "VPSUB(B|D|Q|W)Yrm",
                                               "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
                                               "VPTERNLOGD(Z|Z256)rm(b?)i",
                                               "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
 
 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
   let Latency = 8;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1];
+  let ReleaseAtCycles = [1,2,1];
 }
 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
 
 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,2];
 }
 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
                                               "RCR(8|16|32|64)m(1|i)")>;
 
 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,3];
 }
 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
                                               "ROR(8|16|32|64)mCL",
                                               "SAR(8|16|32|64)mCL",
                                               "SHL(8|16|32|64)mCL",
                                               "SHR(8|16|32|64)mCL")>;
 
 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 6;
-  let ResourceCycles = [1,1,1,2,1];
+  let ReleaseAtCycles = [1,1,1,2,1];
 }
 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
 
 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,2,1,2,2];
+  let ReleaseAtCycles = [1,2,1,2,2];
 }
 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
                                            VPSCATTERQDZ256mr,
                                            VSCATTERQPSZ128mr,
                                            VSCATTERQPSZ256mr)>;
 
 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 12;
-  let ResourceCycles = [1,4,1,4,2];
+  let ReleaseAtCycles = [1,4,1,4,2];
 }
 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
                                            VSCATTERDPSZ128mr)>;
 
 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 20;
-  let ResourceCycles = [1,8,1,8,2];
+  let ReleaseAtCycles = [1,8,1,8,2];
 }
 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
                                            VSCATTERDPSZ256mr)>;
 
 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 36;
-  let ResourceCycles = [1,16,1,16,2];
+  let ReleaseAtCycles = [1,16,1,16,2];
 }
 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
 
 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
 
 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
                                            VPMOVSXDQYrm,
                                            VPMOVSXWDYrm,
                                            VPMOVZXWDYrm)>;
 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
                                               "VFPCLASSSDZrm(b?)",
                                               "VFPCLASSSSZrm(b?)",
def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
                                               "VPMAXSQZ128rm(b?)",
                                               "VPMAXUQZ128rm(b?)",
                                               "VPMINSQZ128rm(b?)",
                                               "VPMINUQZ128rm(b?)")>;
 
 def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
                                                 "VCMP(SD|SS)Zrm",
                                                 "VFPCLASSPDZ128rm(b?)",
                                                 "VFPCLASSPSZ128rm(b?)",
                                                 "VPCMPBZ128rmi(b?)",
                                                 "VPCMPDZ128rmi(b?)",
                                                 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
                                                 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
                                                 "VPCMPQZ128rmi(b?)",
                                                 "VPCMPU(B|D|Q|W)Z128rmi(b?)",
                                                 "VPCMPWZ128rmi(b?)",
                                                 "VPTESTMBZ128rm(b?)",
                                                 "VPTESTMDZ128rm(b?)",
                                                 "VPTESTMQZ128rm(b?)",
                                                 "VPTESTMWZ128rm(b?)",
                                                 "VPTESTNMBZ128rm(b?)",
                                                 "VPTESTNMDZ128rm(b?)",
                                                 "VPTESTNMQZ128rm(b?)",
                                                 "VPTESTNMWZ128rm(b?)")>;
 
 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort01]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
                                               "(V?)CVTPS2PDrm")>;
 
 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
   let Latency = 9;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
                                               "(V?)PHSUBSWrm")>;
 
 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
   let Latency = 9;
   let NumMicroOps = 5;
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
                                               "LSL(16|32|64)rm")>;
 
 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                               "ILD_F(16|32|64)m",
                                               "VALIGND(Z|Z256)rm(b?)i",
                                               "VALIGNQ(Z|Z256)rm(b?)i",
                                               "VPMAXSQ(Z|Z256)rm(b?)",
                                               "VPMAXUQ(Z|Z256)rm(b?)",
                                               "VPMINSQ(Z|Z256)rm(b?)",
                                               "VPMINUQ(Z|Z256)rm(b?)")>;
 
 def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
                                                 "VCMPPS(Z|Z256)rm(b?)i",
                                                 "VFPCLASSPD(Z|Z256)rm(b?)",
                                                 "VFPCLASSPS(Z|Z256)rm(b?)",
                                                 "VPCMPB(Z|Z256)rmi(b?)",
                                                 "VPCMPD(Z|Z256)rmi(b?)",
                                                 "VPCMPEQB(Z|Z256)rm(b?)",
def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
                                                 "VPTESTM(B|D|Q|W)Z256rm(b?)",
                                                 "VPTESTM(B|D|Q|W)Zrm(b?)",
                                                 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
                                                 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
 
 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort01]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
                                               "VCVTDQ2PSZ128rm(b?)",
                                               "(V?)CVTDQ2PSrm",
                                               "VCVTPD2QQZ128rm(b?)",
                                               "VCVTPD2UQQZ128rm(b?)",
                                               "VCVTPH2PSZ128rm(b?)",
                                               "VCVTPS2DQZ128rm(b?)",
def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
                                               "VCVTUDQ2PDZ128rm(b?)",
                                               "VCVTUDQ2PSZ128rm(b?)",
                                               "VCVTUQQ2PDZ128rm(b?)",
                                               "VCVTUQQ2PSZ128rm(b?)")>;
 
 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 10;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
                                               "VEXPANDPSZ128rm(b?)",
                                               "VPEXPANDDZ128rm(b?)",
                                               "VPEXPANDQZ128rm(b?)")>;
 
 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
   let Latency = 10;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
                                            VPHSUBSWYrm)>;
 
 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 10;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,3];
+  let ReleaseAtCycles = [1,1,1,1,1,3];
 }
 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
 
 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
 
 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort01]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
                                            VCVTPS2PDYrm)>;
 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
                                               "VCVTPH2PS(Z|Z256)rm(b?)",
                                               "VCVTPS2PD(Z|Z256)rm(b?)",
                                               "VCVTQQ2PD(Z|Z256)rm(b?)",
                                               "VCVTQQ2PSZ256rm(b?)",
                                               "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PS2DQYrm",
                                               "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PS2QQZ256rm(b?)",
                                               "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
                                               "VCVT(T?)PS2UQQZ256rm(b?)",
                                               "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
                                               "VCVTUQQ2PD(Z|Z256)rm(b?)",
                                               "VCVTUQQ2PSZ256rm(b?)")>;
 
 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
                                               "VEXPANDPD(Z|Z256)rm(b?)",
                                               "VEXPANDPS(Z|Z256)rm(b?)",
                                               "VPEXPANDD(Z|Z256)rm(b?)",
                                               "VPEXPANDQ(Z|Z256)rm(b?)")>;
 
 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
 
 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
   let Latency = 11;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2DQrm,
                                            CVTTPD2DQrm,
                                            MMX_CVTPD2PIrm,
                                            MMX_CVTTPD2PIrm)>;
 
 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
   let Latency = 11;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
 
 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
   let Latency = 11;
   let NumMicroOps = 7;
-  let ResourceCycles = [2,3,2];
+  let ReleaseAtCycles = [2,3,2];
 }
 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
                                               "RCR(16|32|64)rCL")>;
 
 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 11;
   let NumMicroOps = 9;
-  let ResourceCycles = [1,5,1,2];
+  let ReleaseAtCycles = [1,5,1,2];
 }
 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
 
 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
   let Latency = 11;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,9];
+  let ReleaseAtCycles = [2,9];
 }
 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
 
 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
 
 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
   let Latency = 15;
   let NumMicroOps = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
 
 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
 
 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort01]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
                                               "VCVT(T?)SS2USI64Zrm(b?)")>;
 
 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
   let Latency = 12;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
                                               "VCVT(T?)PS2UQQZrm(b?)")>;
 
 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
                                               "VPERMWZ256rm(b?)",
                                               "VPERMWZrm(b?)")>;
 
 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
   let Latency = 13;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
 
 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
   let Latency = 13;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
                                               "VPERMT2W128rm(b?)")>;
 
 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
 
 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
   let Latency = 14;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
                                               "VCVTPD2UDQZrm(b?)",
                                               "VCVTQQ2PSZrm(b?)",
                                               "VCVTTPD2DQZrm(b?)",
                                               "VCVTTPD2UDQZrm(b?)",
                                               "VCVTUQQ2PSZrm(b?)")>;
 
 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
   let Latency = 14;
   let NumMicroOps = 4;
-  let ResourceCycles = [2,1,1];
+  let ReleaseAtCycles = [2,1,1];
 }
 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
                                               "VPERMI2Wrm(b?)",
                                               "VPERMT2W256rm(b?)",
                                               "VPERMT2Wrm(b?)")>;
 
 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 14;
   let NumMicroOps = 10;
-  let ResourceCycles = [2,4,1,3];
+  let ReleaseAtCycles = [2,4,1,3];
 }
 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
 
 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
   let Latency = 15;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
 
 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
   let Latency = 15;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,2,2,1,2];
+  let ReleaseAtCycles = [1,2,2,1,2];
 }
 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
 
 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 15;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,1,1,5,1,1];
+  let ReleaseAtCycles = [1,1,1,5,1,1];
 }
 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
 
 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 16;
   let NumMicroOps = 14;
-  let ResourceCycles = [1,1,1,4,2,5];
+  let ReleaseAtCycles = [1,1,1,4,2,5];
 }
 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
 
 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
   let Latency = 12;
   let NumMicroOps = 34;
-  let ResourceCycles = [1, 4, 5];
+  let ReleaseAtCycles = [1, 4, 5];
 }
 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
 
 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
   let Latency = 17;
   let NumMicroOps = 15;
-  let ResourceCycles = [2,1,2,4,2,4];
+  let ReleaseAtCycles = [2,1,2,4,2,4];
 }
 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
 
 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> {
   let Latency = 21;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
 
 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
   let Latency = 18;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,5];
+  let ReleaseAtCycles = [1,1,1,5];
 }
 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
 
 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 18;
   let NumMicroOps = 11;
-  let ResourceCycles = [2,1,1,4,1,2];
+  let ReleaseAtCycles = [2,1,1,4,1,2];
 }
 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
 
 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> {
   let Latency = 22;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
 
 def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> {
   let Latency = 22;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
 
 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
   let Latency = 20;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
 
 def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
   let Latency = 17;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
                                            VGATHERDPDZ128rm, VPGATHERDQZ128rm,
                                            VGATHERQPDZ128rm, VPGATHERQQZ128rm)>;
 
 def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
   let Latency = 19;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,4,1,1];
+  let ReleaseAtCycles = [1,4,1,1];
 }
 def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
                                            VGATHERQPDZ256rm, VPGATHERQQZ256rm,
                                            VGATHERDPSZ128rm, VPGATHERDDZ128rm,
                                            VGATHERDPDZ256rm, VPGATHERDQZ256rm)>;
 
 def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
   let Latency = 21;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,8,1,1];
+  let ReleaseAtCycles = [1,8,1,1];
 }
 def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
                                            VGATHERDPDZrm,    VPGATHERDQZrm,
                                            VGATHERQPDZrm,    VPGATHERQQZrm,
                                            VGATHERQPSZrm,    VPGATHERQDZrm)>;
 
 def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
   let Latency = 25;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,16,1,1];
+  let ReleaseAtCycles = [1,16,1,1];
 }
 def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
 
 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 20;
   let NumMicroOps = 8;
-  let ResourceCycles = [1,1,1,1,1,1,2];
+  let ReleaseAtCycles = [1,1,1,1,1,1,2];
 }
 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
 
 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
   let Latency = 20;
   let NumMicroOps = 10;
-  let ResourceCycles = [1,2,7];
+  let ReleaseAtCycles = [1,2,7];
 }
 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
 
 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 22;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
 
 def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
   let Latency = 18;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,2,1,1];
+  let ReleaseAtCycles = [1,2,1,1];
 }
 def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
                                             VGATHERQPDrm, VPGATHERQQrm,
                                             VGATHERQPSrm, VPGATHERQDrm)>;
 
 def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
   let Latency = 20;
   let NumMicroOps = 5; // 2 uops peform multiple loads
-  let ResourceCycles = [1,4,1,1];
+  let ReleaseAtCycles = [1,4,1,1];
 }
 def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
                                             VGATHERDPSrm,  VPGATHERDDrm,
                                             VGATHERQPDYrm, VPGATHERQQYrm,
                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
 
 def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
   let Latency = 22;
   let NumMicroOps = 5; // 2 uops perform multiple loads
-  let ResourceCycles = [1,8,1,1];
+  let ReleaseAtCycles = [1,8,1,1];
 }
 def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
 
 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
   let Latency = 22;
   let NumMicroOps = 14;
-  let ResourceCycles = [5,5,4];
+  let ReleaseAtCycles = [5,5,4];
 }
 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
                                               "VPCONFLICTQZ256rr")>;
 
 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 23;
   let NumMicroOps = 19;
-  let ResourceCycles = [2,1,4,1,1,4,6];
+  let ReleaseAtCycles = [2,1,4,1,1,4,6];
 }
 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
 
 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
   let Latency = 25;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
 
 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 27;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
+  let ReleaseAtCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
 
 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
   let Latency = 29;
   let NumMicroOps = 15;
-  let ResourceCycles = [5,5,1,4];
+  let ReleaseAtCycles = [5,5,1,4];
 }
 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
 
 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
   let Latency = 30;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
+  let ReleaseAtCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
 
 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,3,4,10];
+  let ReleaseAtCycles = [1,5,3,4,10];
 }
 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
                                               "IN(8|16|32)rr")>;
 
 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 35;
   let NumMicroOps = 23;
-  let ResourceCycles = [1,5,2,1,4,10];
+  let ReleaseAtCycles = [1,5,2,1,4,10];
 }
 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
                                               "OUT(8|16|32)rr")>;
 
 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
   let Latency = 37;
   let NumMicroOps = 21;
-  let ResourceCycles = [9,7,5];
+  let ReleaseAtCycles = [9,7,5];
 }
 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
                                               "VPCONFLICTQZrr")>;
 
 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
   let Latency = 37;
   let NumMicroOps = 31;
-  let ResourceCycles = [1,8,1,21];
+  let ReleaseAtCycles = [1,8,1,21];
 }
 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
 
 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
   let Latency = 40;
   let NumMicroOps = 18;
-  let ResourceCycles = [1,1,2,3,1,1,1,8];
+  let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
 }
 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
 
 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
   let Latency = 41;
   let NumMicroOps = 39;
-  let ResourceCycles = [1,10,1,1,26];
+  let ReleaseAtCycles = [1,10,1,1,26];
 }
 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
 
 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
   let Latency = 42;
   let NumMicroOps = 22;
-  let ResourceCycles = [2,20];
+  let ReleaseAtCycles = [2,20];
 }
 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
 
 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
   let Latency = 42;
   let NumMicroOps = 40;
-  let ResourceCycles = [1,11,1,1,26];
+  let ReleaseAtCycles = [1,11,1,1,26];
 }
 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
 
 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
   let Latency = 44;
   let NumMicroOps = 22;
-  let ResourceCycles = [9,7,1,5];
+  let ReleaseAtCycles = [9,7,1,5];
 }
 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
                                               "VPCONFLICTQZrm(b?)")>;
 
 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
   let Latency = 62;
   let NumMicroOps = 64;
-  let ResourceCycles = [2,8,5,10,39];
+  let ReleaseAtCycles = [2,8,5,10,39];
 }
 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
 
 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 63;
   let NumMicroOps = 88;
-  let ResourceCycles = [4,4,31,1,2,1,45];
+  let ReleaseAtCycles = [4,4,31,1,2,1,45];
 }
 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
 
 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 63;
   let NumMicroOps = 90;
-  let ResourceCycles = [4,2,33,1,2,1,47];
+  let ReleaseAtCycles = [4,2,33,1,2,1,47];
 }
 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
 
 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
   let Latency = 67;
   let NumMicroOps = 35;
-  let ResourceCycles = [17,11,7];
+  let ReleaseAtCycles = [17,11,7];
 }
 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
 
 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
   let Latency = 74;
   let NumMicroOps = 36;
-  let ResourceCycles = [17,11,1,7];
+  let ReleaseAtCycles = [17,11,1,7];
 }
 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
 
 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
   let Latency = 75;
   let NumMicroOps = 15;
-  let ResourceCycles = [6,3,6];
+  let ReleaseAtCycles = [6,3,6];
 }
 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
 
 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 106;
   let NumMicroOps = 100;
-  let ResourceCycles = [9,1,11,16,1,11,21,30];
+  let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
 }
 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
 
 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
   let Latency = 140;
   let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
 
 def: InstRW<[WriteZero], (instrs CLC)>;
 
 
 // Instruction variants handled by the renamer. These might not need execution
 // ports in certain conditions.

 ]>;
 def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
                                                VPCMPGTDYrr,
                                                VPCMPGTWYrr)>;
 
 def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
   let Latency = 1;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [SKXWritePSUB]>
 ]>;
 
 def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
                                                PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
                                                PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
                                                PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
                                                VPSUBBYrr, VPSUBBZ256rr,
                                                VPSUBDYrr, VPSUBDZ256rr,
                                                VPSUBQYrr, VPSUBQZ256rr,
                                                VPSUBWYrr, VPSUBWZ256rr,
                                                VPSUBBZrr,
                                                VPSUBDZrr,
                                                VPSUBQZrr,
                                                VPSUBWZrr)>;
 def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
   let Latency = 3;
   let NumMicroOps = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 
 def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
     SchedVar<NoSchedPred,                          [SKXWritePCMPGTQ]>
 ]>;
 def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
                                                   VPCMPGTQYrr)>;
 
 
 // CMOVs that use both Z and C flag require an extra uop.
 def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
   let Latency = 7;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
   let NumMicroOps = 3;
 }
 
 def SKXCMOVA_CMOVBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,
   SchedVar<NoSchedPred,                             [WriteCMOV]>
 ]>;
 
 def SKXCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 // SETCCs that use both Z and C flag require an extra uop.
 def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
   let Latency = 3;
-  let ResourceCycles = [1,1,2];
+  let ReleaseAtCycles = [1,1,2];
   let NumMicroOps = 4;
 }
 
 def SKXSETA_SETBErr :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
   SchedVar<NoSchedPred,                         [WriteSETCC]>
 ]>;
 

llvm/lib/Target/X86/X86Schedule.td

 // This SchedRead describes a bypass delay caused by data being moved from the
 // integer unit to the floating point unit.
 def ReadInt2Fpu : SchedRead;
 
 // Instructions with both a load and a store folded are modeled as a folded
 // load + WriteRMW.
 def WriteRMW : SchedWrite;
 
-// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
+// Helper to set SchedWrite ExePorts/Latency/ReleaseAtCycles/NumMicroOps.
 multiclass X86WriteRes<SchedWrite SchedRW,
                        list<ProcResourceKind> ExePorts,
                        int Lat, list<int> Res, int UOps> {
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 }
 
 // Most instructions can fold loads, so almost every SchedWrite comes in two
 // variants: With and without a folded load.
 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
 // with a folded load.

llvm/lib/Target/X86/X86ScheduleAtom.td

multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
                             int RRLat = 1, int RMLat = 1,
                             list<int> RRRes = [1],
                             list<int> RMRes = [1],
                             int RRUOps = 1,
                             int RMUOps = 1> {
   // Register variant.
   def : WriteRes<SchedRW, RRPorts> {
     let Latency = RRLat;
-    let ResourceCycles = RRRes;
+    let ReleaseAtCycles = RRRes;
     let NumMicroOps = RRUOps;
   }
 
   // Memory variant.
   def : WriteRes<SchedRW.Folded, RMPorts> {
     let Latency = RMLat;
-    let ResourceCycles = RMRes;
+    let ReleaseAtCycles = RMRes;
     let NumMicroOps = RMUOps;
   }
 }
 
 // A folded store needs a cycle on Port0 for the store data.
 def : WriteRes<WriteRMW, [AtomPort0]>;
 
 ////////////////////////////////////////////////////////////////////////////////

 defm : X86WriteResPairUnsupported<WriteCRC32>;
 
 defm : AtomWriteResPair<WriteCMOV,  [AtomPort01], [AtomPort0]>;
 defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move.
 
 def  : WriteRes<WriteSETCC, [AtomPort01]>;
 def  : WriteRes<WriteSETCCStore, [AtomPort01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def  : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 defm : X86WriteRes<WriteBitTest,         [AtomPort1],  1, [1], 1>;
 defm : X86WriteRes<WriteBitTestImmLd,    [AtomPort0],  1, [1], 1>;
 defm : X86WriteRes<WriteBitTestRegLd,    [AtomPort01], 9, [9], 1>;
 defm : X86WriteRes<WriteBitTestSet,      [AtomPort1],  1, [1], 1>;
 //defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1],  1, [1], 1>;
 //defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1],  1, [1], 1>;
 

 defm : X86WriteResPairUnsupported<WritePCmpIStrM>;
 defm : X86WriteResPairUnsupported<WritePCmpEStrI>;
 defm : X86WriteResPairUnsupported<WritePCmpEStrM>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // MOVMSK Instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
-def  : WriteRes<WriteFMOVMSK,    [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
-def  : WriteRes<WriteVecMOVMSK,  [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
+def  : WriteRes<WriteFMOVMSK,    [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
+def  : WriteRes<WriteVecMOVMSK,  [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
 defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
-def  : WriteRes<WriteMMXMOVMSK,  [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
+def  : WriteRes<WriteMMXMOVMSK,  [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
 
 ////////////////////////////////////////////////////////////////////////////////
 // AES instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : X86WriteResPairUnsupported<WriteAESIMC>;
 defm : X86WriteResPairUnsupported<WriteAESKeyGen>;
 defm : X86WriteResPairUnsupported<WriteAESDecEnc>;

 
 ////////////////////////////////////////////////////////////////////////////////
 // Special Cases.
 ////////////////////////////////////////////////////////////////////////////////
 
 // Port0
 def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : InstRW<[AtomWrite0_1], (instrs XAM_F, LD_Frr,
                                      MOVSX64rr32)>;
 def : SchedAlias<WriteALURMW, AtomWrite0_1>;
 def : SchedAlias<WriteADCRMW, AtomWrite0_1>;
 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
                                         "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;
 
 // Port1
 def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
 def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>;
 
 def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
   let Latency = 5;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
 }
 def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,
                                      MMX_CVTPS2PIrr, MMX_CVTTPS2PIrr)>;
 
 // Port0 and Port1
 def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
   let Latency = 1;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
 }
 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
                                        POP16rmr, POP32rmr, POP64rmr,
                                        PUSH16r, PUSH32r, PUSH64r,
                                        PUSH16i, PUSH32i,
                                        PUSH16rmr, PUSH32rmr, PUSH64rmr,
                                        PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
                                        XCH_F)>;
 def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",
                                           "IRET(16|32|64)?")>;
 
 def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
   let Latency = 5;
-  let ResourceCycles = [5, 5];
+  let ReleaseAtCycles = [5, 5];
 }
 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIrm, MMX_CVTTPS2PIrm)>;
 def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
 
 def AtomWrite0_1_7 : SchedWriteRes<[AtomPort0,AtomPort1]> {
   let Latency = 7;
-  let ResourceCycles = [6,6];
+  let ReleaseAtCycles = [6,6];
 }
 def : InstRW<[AtomWrite0_1_7], (instregex "CVTSI642SDrm(_Int)?")>;
 
 def AtomWrite0_1_7_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {
   let Latency = 7;
-  let ResourceCycles = [8,8];
+  let ReleaseAtCycles = [8,8];
   let NumMicroOps = 4;
 }
 def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrr(_Int)?")>;
 
 def AtomWrite0_1_8_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {
   let Latency = 8;
-  let ResourceCycles = [8,8];
+  let ReleaseAtCycles = [8,8];
   let NumMicroOps = 4;
 }
 def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrm(_Int)?")>;
 
 def AtomWrite0_1_9 : SchedWriteRes<[AtomPort0,AtomPort1]> {
   let Latency = 9;
-  let ResourceCycles = [9,9];
+  let ReleaseAtCycles = [9,9];
   let NumMicroOps = 4;
 }
 def : InstRW<[AtomWrite0_1_9], (instregex "CVT(T)?SS2SI64rr(_Int)?")>;
 
 def AtomWrite0_1_10 : SchedWriteRes<[AtomPort0,AtomPort1]> {
   let Latency = 10;
-  let ResourceCycles = [11,11];
+  let ReleaseAtCycles = [11,11];
   let NumMicroOps = 5;
 }
 def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>;
 
 // Port0 or Port1
 def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
 }
 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
                                       LFENCE,
                                       STOSB, STOSL, STOSQ, STOSW,
                                       MOVSSrr, MOVSSrr_REV)>;
 
 def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
                                       PUSH16rmm, PUSH32rmm, PUSH64rmm,
                                       LODSB, LODSL, LODSQ, LODSW,
                                       SCASB, SCASL, SCASQ, SCASW)>;
 def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",
                                          "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",
                                          "MMX_P(ADD|SUB)Qrr",
                                          "MOV(S|Z)X16rr8",
                                          "MOV(UPS|UPD|DQU)mr",
                                          "MASKMOVDQU(64)?",
                                          "P(ADD|SUB)Qrr")>;
 def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>;
 
 def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
   let Latency = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
                                       CMPSB, CMPSL, CMPSQ, CMPSW,
                                       MOVSB, MOVSL, MOVSQ, MOVSW,
                                       POP16rmm, POP32rmm, POP64rmm)>;
 def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
                                          "XCHG(8|16|32|64)rm",
                                          "PH(ADD|SUB)Drr",
                                          "MOV(S|Z)X16rm8",
                                          "MMX_P(ADD|SUB)Qrm",
                                          "MOV(UPS|UPD|DQU)rm",
                                          "P(ADD|SUB)Qrm")>;
 
 def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
   let Latency = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
                                       JCXZ, JECXZ, JRCXZ,
                                       LD_F80m)>;
 def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",
                                          "(MMX_)?PEXTRWrr(_REV)?")>;
 
 def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
   let Latency = 5;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
 }
 def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;
 def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;
 
 def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
   let Latency = 6;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
 }
 def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,
                                       SHLD16rrCL, SHRD16rrCL,
                                       SHLD16rri8, SHRD16rri8,
                                       SHLD16mrCL, SHRD16mrCL,
                                       SHLD16mri8, SHRD16mri8)>;
 def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m",
                                          "MMX_PH(ADD|SUB)S?Wrm")>;
 
 def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
   let Latency = 7;
-  let ResourceCycles = [7];
+  let ReleaseAtCycles = [7];
 }
 def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;
 
 def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
   let Latency = 8;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def : InstRW<[AtomWrite01_8], (instrs LOOPE,
                                       PUSHA16, PUSHA32,
                                       SHLD64rrCL, SHRD64rrCL,
                                       FNSTCW16m)>;
 
 def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
   let Latency = 9;
-  let ResourceCycles = [9];
+  let ReleaseAtCycles = [9];
 }
 def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
                                       PUSHF16, PUSHF32, PUSHF64,
                                       SHLD64mrCL, SHRD64mrCL,
                                       SHLD64mri8, SHRD64mri8,
                                       SHLD64rri8, SHRD64rri8,
                                       CMPXCHG8rr)>;
 def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F")>;
 
 def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
   let Latency = 10;
-  let ResourceCycles = [10];
+  let ReleaseAtCycles = [10];
 }
 def : SchedAlias<WriteFLDC, AtomWrite01_10>;
 
 def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
   let Latency = 11;
-  let ResourceCycles = [11];
+  let ReleaseAtCycles = [11];
 }
 def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
 def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>;
 
 def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
   let Latency = 13;
-  let ResourceCycles = [13];
+  let ReleaseAtCycles = [13];
 }
 def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
 
 def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
   let Latency = 14;
-  let ResourceCycles = [14];
+  let ReleaseAtCycles = [14];
 }
 def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
 
 def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
   let Latency = 17;
-  let ResourceCycles = [17];
+  let ReleaseAtCycles = [17];
 }
 def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
 
 def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
   let Latency = 18;
-  let ResourceCycles = [18];
+  let ReleaseAtCycles = [18];
 }
 def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
 
 def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
   let Latency = 20;
-  let ResourceCycles = [20];
+  let ReleaseAtCycles = [20];
 }
 def : InstRW<[AtomWrite01_20], (instrs DAS)>;
 
 def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
   let Latency = 21;
-  let ResourceCycles = [21];
+  let ReleaseAtCycles = [21];
 }
 def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
 
 def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
   let Latency = 22;
-  let ResourceCycles = [22];
+  let ReleaseAtCycles = [22];
 }
 def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
 
 def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
   let Latency = 23;
-  let ResourceCycles = [23];
+  let ReleaseAtCycles = [23];
 }
 def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
 
 def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
   let Latency = 25;
-  let ResourceCycles = [25];
+  let ReleaseAtCycles = [25];
 }
 def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
 
 def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
   let Latency = 26;
-  let ResourceCycles = [26];
+  let ReleaseAtCycles = [26];
 }
 def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
 
 def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
   let Latency = 29;
-  let ResourceCycles = [29];
+  let ReleaseAtCycles = [29];
 }
 def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
 
 def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
   let Latency = 30;
-  let ResourceCycles = [30];
+  let ReleaseAtCycles = [30];
 }
 def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
 
 def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
   let Latency = 32;
-  let ResourceCycles = [32];
+  let ReleaseAtCycles = [32];
 }
 def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
 
 def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
   let Latency = 45;
-  let ResourceCycles = [45];
+  let ReleaseAtCycles = [45];
 }
 def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>;
 
 def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
   let Latency = 46;
-  let ResourceCycles = [46];
+  let ReleaseAtCycles = [46];
 }
 def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
 
 def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
   let Latency = 48;
-  let ResourceCycles = [48];
+  let ReleaseAtCycles = [48];
 }
 def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
 
 def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
   let Latency = 55;
-  let ResourceCycles = [55];
+  let ReleaseAtCycles = [55];
 }
 def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
 
 def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
   let Latency = 59;
-  let ResourceCycles = [59];
+  let ReleaseAtCycles = [59];
 }
 def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
 
 def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
   let Latency = 63;
-  let ResourceCycles = [63];
+  let ReleaseAtCycles = [63];
 }
 def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
 
 def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
   let Latency = 68;
-  let ResourceCycles = [68];
+  let ReleaseAtCycles = [68];
 }
 def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
 
 def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
   let Latency = 71;
-  let ResourceCycles = [71];
+  let ReleaseAtCycles = [71];
 }
 def : InstRW<[AtomWrite01_71], (instrs FPREM1,
                                        INVLPG, INVLPGA32, INVLPGA64)>;
 
 def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
   let Latency = 72;
-  let ResourceCycles = [72];
+  let ReleaseAtCycles = [72];
 }
 def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
 
 def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
   let Latency = 74;
-  let ResourceCycles = [74];
+  let ReleaseAtCycles = [74];
 }
 def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
 
 def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
   let Latency = 77;
-  let ResourceCycles = [77];
+  let ReleaseAtCycles = [77];
 }
 def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
 
 def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
   let Latency = 78;
-  let ResourceCycles = [78];
+  let ReleaseAtCycles = [78];
 }
 def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
 
 def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
   let Latency = 79;
-  let ResourceCycles = [79];
+  let ReleaseAtCycles = [79];
 }
 def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$",
                                           "LRETI?(16|32|64)")>;
 
 def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
   let Latency = 92;
-  let ResourceCycles = [92];
+  let ReleaseAtCycles = [92];
 }
 def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
 
 def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
   let Latency = 94;
-  let ResourceCycles = [94];
+  let ReleaseAtCycles = [94];
 }
 def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
 
 def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
   let Latency = 99;
-  let ResourceCycles = [99];
+  let ReleaseAtCycles = [99];
 }
 def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
 
 def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
   let Latency = 121;
-  let ResourceCycles = [121];
+  let ReleaseAtCycles = [121];
 }
 def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
 
 def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
   let Latency = 127;
-  let ResourceCycles = [127];
+  let ReleaseAtCycles = [127];
 }
 def : InstRW<[AtomWrite01_127], (instrs INT)>;
 
 def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
   let Latency = 130;
-  let ResourceCycles = [130];
+  let ReleaseAtCycles = [130];
 }
 def : InstRW<[AtomWrite01_130], (instrs INT3)>;
 
 def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
   let Latency = 140;
-  let ResourceCycles = [140];
+  let ReleaseAtCycles = [140];
 }
 def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
 
 def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
   let Latency = 141;
-  let ResourceCycles = [141];
+  let ReleaseAtCycles = [141];
 }
 def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
 
 def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
   let Latency = 146;
-  let ResourceCycles = [146];
+  let ReleaseAtCycles = [146];
 }
 def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
 
 def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
   let Latency = 147;
-  let ResourceCycles = [147];
+  let ReleaseAtCycles = [147];
 }
 def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
 
 def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
   let Latency = 168;
-  let ResourceCycles = [168];
+  let ReleaseAtCycles = [168];
 }
 def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
 
 def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
   let Latency = 174;
-  let ResourceCycles = [174];
+  let ReleaseAtCycles = [174];
 }
 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
 
 def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
   let Latency = 183;
-  let ResourceCycles = [183];
+  let ReleaseAtCycles = [183];
 }
 def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
 
 def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
   let Latency = 202;
-  let ResourceCycles = [202];
+  let ReleaseAtCycles = [202];
 }
 def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;
 
 } // SchedModel

llvm/lib/Target/X86/X86ScheduleBdVer2.td

 // as two micro-ops when dispatched by the schedulers.
 // This multiclass defines the resource usage for variants with and without
 // folded loads.
 multiclass PdWriteRes<SchedWrite SchedRW,
                       list<ProcResourceKind> ExePorts, int Lat = 1,
                       list<int> Res = [], int UOps = 1> {
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 }
 
 multiclass __pdWriteResPair<X86FoldableSchedWrite SchedRW,
                             list<ProcResourceKind> ExePorts, int Lat,
                             list<int> Res, int UOps,
                             int LoadLat, int LoadRes, int LoadUOps> {

 
 // A folded store needs a cycle on the PdStore for the store data.
 def : WriteRes<WriteRMW, [PdStore]>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Loads, stores, and moves, not folded with other operations.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteLoad,    [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
+def : WriteRes<WriteLoad,    [PdLoad]> { let Latency = 5; let ReleaseAtCycles = [2]; }
 def : WriteRes<WriteStore,   [PdStore]>;
 def : WriteRes<WriteStoreNT, [PdStore]>;
-def : WriteRes<WriteMove,    [PdEX01]> { let ResourceCycles = [2]; }
+def : WriteRes<WriteMove,    [PdEX01]> { let ReleaseAtCycles = [2]; }
 defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>;
 
 // Load/store MXCSR.
 // FIXME: These are copy and pasted from WriteLoad/Store.
 def : WriteRes<WriteLDMXCSR, [PdLoad]> { let Latency = 5; }
-def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
+def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ReleaseAtCycles = [18]; }
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
 ////////////////////////////////////////////////////////////////////////////////

 
 def PdWriteXLAT : SchedWriteRes<[PdEX01]> {
   let Latency = 6;
 }
 def : InstRW<[PdWriteXLAT], (instrs XLAT)>;
 
 def PdWriteLARrr : SchedWriteRes<[PdEX01]> {
   let Latency = 184;
-  let ResourceCycles = [375];
+  let ReleaseAtCycles = [375];
   let NumMicroOps = 45;
 }
 def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
                                         "LSL(16|32|64)rr")>;
 
 // Nops don't have dependencies, so there's no actual latency, but we set this
 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
-def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
+def : WriteRes<WriteNop, [PdEX01]> { let ReleaseAtCycles = [2]; }
 
 ////////////////////////////////////////////////////////////////////////////////
 // Arithmetic.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : PdWriteResExPair<WriteALU,     [PdEX01], 1, [2]>;
 
 def PdWriteALURMW : SchedWriteRes<[PdLoad, PdEX01, PdStore]> {
   let Latency = 6;
-  let ResourceCycles = [3, 2, 1];
+  let ReleaseAtCycles = [3, 2, 1];
   let NumMicroOps = 1;
 }
 def : SchedAlias<WriteALURMW, PdWriteALURMW>;
 
 def PdWriteLXADD : SchedWriteRes<[PdEX01]> {
   let Latency = 6;
-  let ResourceCycles = [88];
+  let ReleaseAtCycles = [88];
   let NumMicroOps = 4;
 }
 def : InstRW<[PdWriteLXADD], (instrs LXADD8, LXADD16, LXADD32, LXADD64)>;
 
 def PdWriteBMI1 : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteBMI1],
              (instrs BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr,
                      BLCIC32rr, BLCIC64rr, BLCMSK32rr, BLCMSK64rr,
                      BLCS32rr, BLCS64rr, BLSFILL32rr, BLSFILL64rr,
                      BLSIC32rr, BLSIC64rr, T1MSKC32rr, T1MSKC64rr,
                      TZMSK32rr, TZMSK64rr)>;
 
 def PdWriteBMI1m : SchedWriteRes<[PdLoad, PdEX01]> {
   let Latency = 6;
-  let ResourceCycles = [3, 3];
+  let ReleaseAtCycles = [3, 3];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteBMI1m],
              (instrs BLCFILL32rm, BLCFILL64rm, BLCI32rm, BLCI64rm,
                      BLCIC32rm, BLCIC64rm, BLCMSK32rm, BLCMSK64rm,
                      BLCS32rm, BLCS64rm, BLSFILL32rm, BLSFILL64rm,
                      BLSIC32rm, BLSIC64rm, T1MSKC32rm, T1MSKC64rm,
                      TZMSK32rm, TZMSK64rm)>;
 
 defm : PdWriteResExPair<WriteADC,    [PdEX01],                  1,  [2]>;
 
 def PdWriteADCSBB64ri32 : SchedWriteRes<[PdEX01]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
 }
 def : InstRW<[PdWriteADCSBB64ri32], (instrs ADC64ri32, SBB64ri32)>;
 
 defm : PdWriteRes<WriteBSWAP32,      [PdEX01]>;
 defm : PdWriteRes<WriteBSWAP64,      [PdEX01]>;
 defm : PdWriteRes<WriteCMPXCHG,      [PdEX1],                   3,  [3],        5>;
 defm : PdWriteRes<WriteCMPXCHGRMW,   [PdEX1, PdStore, PdLoad],  3,  [44, 1, 1], 2>;
 defm : PdWriteRes<WriteXCHG,         [PdEX1],                   1,  [],         2>;
 
 def PdWriteCMPXCHG8rr : SchedWriteRes<[PdEX1]> {
   let Latency = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 3;
 }
 def : InstRW<[PdWriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
 
 def PdWriteCMPXCHG8rm : SchedWriteRes<[PdEX1]> {
   let Latency = 3;
-  let ResourceCycles = [23];
+  let ReleaseAtCycles = [23];
   let NumMicroOps = 5;
 }
 def : InstRW<[PdWriteCMPXCHG8rm], (instrs CMPXCHG8rm)>;
 
 def PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm : SchedWriteRes<[PdEX1]> {
   let Latency = 3;
-  let ResourceCycles = [21];
+  let ReleaseAtCycles = [21];
   let NumMicroOps = 6;
 }
 def : InstRW<[PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm],
              (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
 
 def PdWriteCMPXCHG8B : SchedWriteRes<[PdEX1]> {
   let Latency = 3;
-  let ResourceCycles = [26];
+  let ReleaseAtCycles = [26];
   let NumMicroOps = 18;
 }
 def : InstRW<[PdWriteCMPXCHG8B], (instrs CMPXCHG8B)>;
 
 def PdWriteCMPXCHG16B : SchedWriteRes<[PdEX1]> {
   let Latency = 3;
-  let ResourceCycles = [69];
+  let ReleaseAtCycles = [69];
   let NumMicroOps = 22;
 }
 def : InstRW<[PdWriteCMPXCHG16B], (instrs CMPXCHG16B)>;
 
 def PdWriteXADDm : SchedWriteRes<[PdEX1]> {
   let Latency = 6;
-  let ResourceCycles = [20];
+  let ReleaseAtCycles = [20];
   let NumMicroOps = 4;
 }
 def : InstRW<[PdWriteXADDm], (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm)>;
 
 defm : PdWriteResExPair<WriteIMul8,     [PdEX1, PdMul],          4,  [1, 4]>;
 defm : PdWriteResExPair<WriteIMul16,    [PdEX1, PdMul],          4,  [1, 5],    2>;
 defm : PdWriteResExPair<WriteIMul16Imm, [PdEX1, PdMul],          5,  [1, 5],    2>;
 defm : PdWriteResExPair<WriteIMul16Reg, [PdEX1, PdMul],          4,  [1, 2]>;

 defm : PdWriteResExPair<WriteIDiv16,  [PdEX1, PdDiv],           15,  [1, 17],   2>;
 defm : PdWriteResExPair<WriteIDiv32,  [PdEX1, PdDiv],           14,  [1, 25],   2>;
 defm : PdWriteResExPair<WriteIDiv64,  [PdEX1, PdDiv],           14,  [1, 14],   2>;
 
 defm : PdWriteResExPair<WriteCRC32,   [PdEX01],                  2,  [4],       3>;
 
 def PdWriteCRC32r32r16 : SchedWriteRes<[PdEX01]> {
   let Latency = 5;
-  let ResourceCycles = [10];
+  let ReleaseAtCycles = [10];
   let NumMicroOps = 5;
 }
 def : InstRW<[PdWriteCRC32r32r16], (instrs CRC32r32r16)>;
 
 def PdWriteCRC32r32r32 : SchedWriteRes<[PdEX01]> {
   let Latency = 6;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 7;
 }
 def : InstRW<[PdWriteCRC32r32r32], (instrs CRC32r32r32)>;
 
 def PdWriteCRC32r64r64 : SchedWriteRes<[PdEX01]> {
   let Latency = 10;
-  let ResourceCycles = [17];
+  let ReleaseAtCycles = [17];
   let NumMicroOps = 11;
 }
 def : InstRW<[PdWriteCRC32r64r64], (instrs CRC32r64r64)>;
 
 defm : PdWriteResExPair<WriteCMOV,    [PdEX01]>; // Conditional move.
 
 def PdWriteCMOVm : SchedWriteRes<[PdLoad, PdEX01]> {
   let Latency = 5;
-  let ResourceCycles = [3, 3];
+  let ReleaseAtCycles = [3, 3];
   let NumMicroOps = 2;
 }
 
 def PdWriteCMOVmVar : SchedWriteVariant<[
   SchedVar<MCSchedPredicate<CheckImmOperand_s<7, "X86::COND_BE">>, [PdWriteCMOVm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<7, "X86::COND_A">>,  [PdWriteCMOVm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<7, "X86::COND_L">>,  [PdWriteCMOVm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<7, "X86::COND_GE">>, [PdWriteCMOVm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<7, "X86::COND_LE">>, [PdWriteCMOVm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<7, "X86::COND_G">>,  [PdWriteCMOVm]>,
   SchedVar<NoSchedPred, [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[PdWriteCMOVmVar], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
 defm : PdWriteRes<WriteFCMOV,        [PdFPU0, PdFPFMA]>; // x87 conditional move.
 
 def : WriteRes<WriteSETCC,           [PdEX01]>; // Setcc.
 def : WriteRes<WriteSETCCStore,      [PdEX01, PdStore]>;
 
 def PdWriteSETGEmSETGmSETLEmSETLm : SchedWriteRes<[PdEX01]> {
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def PdSETGEmSETGmSETLEmSETLm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_GE">>, [PdWriteSETGEmSETGmSETLEmSETLm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_G">>,  [PdWriteSETGEmSETGmSETLEmSETLm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_LE">>, [PdWriteSETGEmSETGmSETLEmSETLm]>,
   SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_L">>,  [PdWriteSETGEmSETGmSETLEmSETLm]>,
   SchedVar<NoSchedPred,                                            [WriteSETCCStore]>
 ]>;
 def : InstRW<[PdSETGEmSETGmSETLEmSETLm], (instrs SETCCm)>;
 
 defm : PdWriteRes<WriteLAHFSAHF,      [PdEX01],          2,  [4],       2>;
 
 def PdWriteLAHF : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 4;
 }
 def : InstRW<[PdWriteLAHF], (instrs LAHF)>;
 
 def PdWriteSAHF : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteSAHF], (instrs SAHF)>;
 
 defm : PdWriteRes<WriteBitTest,          [PdEX01],         1, [2],      1>;
 defm : PdWriteRes<WriteBitTestImmLd,     [PdEX01, PdLoad], 5, [2,  3],  1>;
 defm : PdWriteRes<WriteBitTestRegLd,     [PdEX01, PdLoad], 5, [7,  2],  7>;
 defm : PdWriteRes<WriteBitTestSet,       [PdEX01],         2, [2],      2>;
 defm : PdWriteRes<WriteBitTestSetImmLd,  [PdEX01, PdLoad], 6, [1,  1],  4>;
 defm : PdWriteRes<WriteBitTestSetRegLd,  [PdEX01, PdLoad], 6, [1,  1], 10>;
 
 def PdWriteBTSIm : SchedWriteRes<[PdEX01, PdLoad]> {
   let Latency = 7;
-  let ResourceCycles = [42, 1];
+  let ReleaseAtCycles = [42, 1];
   let NumMicroOps = 4;
 }
 def : SchedAlias<WriteBitTestSetImmRMW, PdWriteBTSIm>;
 def PdWriteBTSRm : SchedWriteRes<[PdEX01, PdLoad]> {
   let Latency = 7;
-  let ResourceCycles = [44, 1];
+  let ReleaseAtCycles = [44, 1];
   let NumMicroOps = 10;
 }
 def : SchedAlias<WriteBitTestSetRegRMW, PdWriteBTSRm>;
 
 // This is for simple LEAs with one or two input operands.
-def : WriteRes<WriteLEA,              [PdEX01]> { let ResourceCycles = [2]; }
+def : WriteRes<WriteLEA,              [PdEX01]> { let ReleaseAtCycles = [2]; }
 
 // This write is used for slow LEA instructions.
 def PdWrite3OpsLEA : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // On Piledriver, a slow LEA is either a 3Ops LEA (base, index, offset),
 // or an LEA with a `Scale` value different than 1.
 def PdSlowLEAPredicate : MCSchedPredicate<
   CheckAny<[
     // A 3-operand LEA (base, index, offset).
     IsThreeOperandsLEAFn,
     // An LEA with a "Scale" different than 1.
     CheckAll<[
       CheckIsImmOperand<2>,
       CheckNot<CheckImmOperand<2, 1>>
     ]>
   ]>
 >;
 
 def PdWriteLEA : SchedWriteVariant<[
     SchedVar<PdSlowLEAPredicate, [PdWrite3OpsLEA]>,
     SchedVar<NoSchedPred,        [WriteLEA]>
 ]>;
 
 def : InstRW<[PdWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
 
 def PdWriteLEA16r : SchedWriteRes<[PdEX01]> {
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteLEA16r], (instrs LEA16r)>;
 
 // Bit counts.
 defm : PdWriteResExPair<WriteBSF,     [PdEX01],          3,  [6],     6, 2>;
 defm : PdWriteResExPair<WriteBSR,     [PdEX01],          4,  [8],     7, 2>;
 defm : PdWriteResExPair<WritePOPCNT,  [PdEX01],          4,  [4]>;
 defm : PdWriteResExPair<WriteLZCNT,   [PdEX0],           2,  [2],     2>;
 defm : PdWriteResExPair<WriteTZCNT,   [PdEX0],           2,  [2],     2>;
 
 // BMI1 BEXTR, BMI2 BZHI
 defm : PdWriteResExPair<WriteBEXTR,   [PdEX01],          2,  [2],    2>;
 defm : PdWriteResExPair<WriteBLS,     [PdEX01],          2,  [2],    2>;
 defm : PdWriteResExPair<WriteBZHI,    [PdEX01]>;
 
 def PdWriteBEXTRI : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteBEXTRI], (instrs BEXTRI32ri, BEXTRI64ri)>;
 
 def PdWriteBEXTRIm : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteBEXTRIm], (instrs BEXTRI32mi, BEXTRI64mi)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Integer shifts and rotates.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : PdWriteResExPair<WriteShift,    [PdEX01], 1, [2]>;
 defm : PdWriteResExPair<WriteShiftCL,  [PdEX01]>;
 defm : PdWriteResExPair<WriteRotate,   [PdEX01], 1, [2]>;
 defm : PdWriteResExPair<WriteRotateCL, [PdEX01]>;
 
 def PdWriteRCL8rCL : SchedWriteRes<[PdEX01]> {
   let Latency = 12;
-  let ResourceCycles = [24];
+  let ReleaseAtCycles = [24];
   let NumMicroOps = 26;
 }
 def : InstRW<[PdWriteRCL8rCL], (instrs RCL8rCL)>;
 
 def PdWriteRCR8ri : SchedWriteRes<[PdEX01]> {
   let Latency = 12;
-  let ResourceCycles = [23];
+  let ReleaseAtCycles = [23];
   let NumMicroOps = 23;
 }
 def : InstRW<[PdWriteRCR8ri], (instrs RCR8ri)>;
 
 def PdWriteRCR8rCL : SchedWriteRes<[PdEX01]> {
   let Latency = 11;
-  let ResourceCycles = [22];
+  let ReleaseAtCycles = [22];
   let NumMicroOps = 24;
 }
 def : InstRW<[PdWriteRCR8rCL], (instrs RCR8rCL)>;
 
 def PdWriteRCL16rCL : SchedWriteRes<[PdEX01]> {
   let Latency = 10;
-  let ResourceCycles = [20];
+  let ReleaseAtCycles = [20];
   let NumMicroOps = 22;
 }
 def : InstRW<[PdWriteRCL16rCL], (instrs RCL16rCL)>;
 
 def PdWriteRCR16ri : SchedWriteRes<[PdEX01]> {
   let Latency = 10;
-  let ResourceCycles = [19];
+  let ReleaseAtCycles = [19];
   let NumMicroOps = 19;
 }
 def : InstRW<[PdWriteRCR16ri], (instrs RCR16ri)>;
 
 def PdWriteRCL3264rCL : SchedWriteRes<[PdEX01]> {
   let Latency = 7;
-  let ResourceCycles = [14];
+  let ReleaseAtCycles = [14];
   let NumMicroOps = 17;
 }
 def : InstRW<[PdWriteRCL3264rCL], (instrs RCL32rCL, RCL64rCL)>;
 
 def PdWriteRCR3264rCL : SchedWriteRes<[PdEX01]> {
   let Latency = 7;
-  let ResourceCycles = [13];
+  let ReleaseAtCycles = [13];
   let NumMicroOps = 16;
 }
 def : InstRW<[PdWriteRCR3264rCL], (instrs RCR32rCL, RCR64rCL)>;
 
 def PdWriteRCR32riRCR64ri : SchedWriteRes<[PdEX01]> {
   let Latency = 7;
-  let ResourceCycles = [14];
+  let ReleaseAtCycles = [14];
   let NumMicroOps = 15;
 }
 def : InstRW<[PdWriteRCR32riRCR64ri], (instrs RCR32ri, RCR64ri)>;
 
 
 def PdWriteRCR16rCL : SchedWriteRes<[PdEX01]> {
   let Latency = 9;
-  let ResourceCycles = [18];
+  let ReleaseAtCycles = [18];
   let NumMicroOps = 20;
 }
 def : InstRW<[PdWriteRCR16rCL], (instrs RCR16rCL)>;
 
 def PdWriteRCL16ri : SchedWriteRes<[PdEX01]> {
   let Latency = 11;
-  let ResourceCycles = [21];
+  let ReleaseAtCycles = [21];
   let NumMicroOps = 21;
 }
 def : InstRW<[PdWriteRCL16ri], (instrs RCL16ri)>;
 
 def PdWriteRCL3264ri : SchedWriteRes<[PdEX01]> {
   let Latency = 8;
-  let ResourceCycles = [15];
+  let ReleaseAtCycles = [15];
   let NumMicroOps = 16;
 }
 def : InstRW<[PdWriteRCL3264ri], (instrs RCL32ri, RCL64ri)>;
 
 def PdWriteRCL8ri : SchedWriteRes<[PdEX01]> {
   let Latency = 13;
-  let ResourceCycles = [25];
+  let ReleaseAtCycles = [25];
   let NumMicroOps = 25;
 }
 def : InstRW<[PdWriteRCL8ri], (instrs RCL8ri)>;
 
 // SHLD/SHRD.
 defm : PdWriteRes<WriteSHDrri,       [PdEX01],         3, [6], 6>;
 defm : PdWriteRes<WriteSHDrrcl,      [PdEX01],         3, [8], 7>;
 
 def PdWriteSHLD16rrCLSHLD32rrCLSHRD32rrCL : SchedWriteRes<[PdEX01]> {
   let Latency = 3;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 7;
 }
 def : InstRW<[PdWriteSHLD16rrCLSHLD32rrCLSHRD32rrCL], (instrs SHLD16rrCL,
                                                               SHLD32rrCL,
                                                               SHRD32rrCL)>;
 
 defm : PdWriteRes<WriteSHDmri,       [PdLoad, PdEX01], 4, [1, 22], 8>;
 defm : PdWriteRes<WriteSHDmrcl,      [PdLoad, PdEX01], 4, [1, 22], 8>;

 defm : PdWriteRes<WriteFMaskedLoadY,       [PdLoad, PdFPU01, PdFPFMA], 6, [3, 2, 4], 2>;
 
 defm : PdWriteRes<WriteFStore,             [PdStore, PdFPU23, PdFPSTO], 2, [1,  3, 1]>;
 defm : PdWriteRes<WriteFStoreX,            [PdStore, PdFPU23, PdFPSTO], 1, [1,  3, 1]>;
 defm : PdWriteRes<WriteFStoreY,            [PdStore, PdFPU23, PdFPSTO], 1, [1, 36, 2], 4>;
 
 def PdWriteMOVHPm : SchedWriteRes<[PdStore, PdFPU23,  PdFPSTO]> {
   let Latency = 2;
-  let ResourceCycles = [1, 3, 1];
+  let ReleaseAtCycles = [1, 3, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteMOVHPm], (instrs MOVHPDmr, MOVHPSmr, VMOVHPDmr, VMOVHPSmr)>;
 
 def PdWriteVMOVUPDYmrVMOVUPSYmr : SchedWriteRes<[PdStore, PdFPU1,  PdFPSTO]> {
   let NumMicroOps = 8;
 }
 def : InstRW<[PdWriteVMOVUPDYmrVMOVUPSYmr], (instrs VMOVUPDYmr, VMOVUPSYmr)>;

 
 defm : PdWriteResXMMPair<WriteFAdd,         [PdFPU0, PdFPFMA],  5>;
 defm : PdWriteResXMMPair<WriteFAddX,        [PdFPU0, PdFPFMA],  5>;
 defm : PdWriteResYMMPair<WriteFAddY,        [PdFPU0, PdFPFMA],  5, [1, 2]>;
 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 
 def PdWriteX87Add: SchedWriteRes<[PdLoad, PdFPU0, PdFPFMA]> {
   let Latency = 5;
-  let ResourceCycles = [3, 1, 10];
+  let ReleaseAtCycles = [3, 1, 10];
 }
 def : InstRW<[PdWriteX87Add], (instrs ADD_FI16m,  ADD_FI32m,  ADD_F32m,  ADD_F64m,
                                       SUB_FI16m,  SUB_FI32m,  SUB_F32m,  SUB_F64m,
                                       SUBR_FI16m, SUBR_FI32m, SUBR_F32m, SUBR_F64m)>;
 
 defm : PdWriteResXMMPair<WriteFAdd64,       [PdFPU0, PdFPFMA],  5>;
 defm : PdWriteResXMMPair<WriteFAdd64X,      [PdFPU0, PdFPFMA],  5>;
 defm : PdWriteResYMMPair<WriteFAdd64Y,      [PdFPU0, PdFPFMA],  5, [1, 2]>;

 
 defm : PdWriteResXMMPair<WriteFMul,         [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResXMMPair<WriteFMulX,        [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResYMMPair<WriteFMulY,        [PdFPU1, PdFPFMA],  5, [1, 2]>;
 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 
 def PdWriteX87Mul: SchedWriteRes<[PdLoad, PdFPU1, PdFPFMA]> {
   let Latency = 5;
-  let ResourceCycles = [3, 1, 10];
+  let ReleaseAtCycles = [3, 1, 10];
 }
 def : InstRW<[PdWriteX87Mul], (instrs MUL_FI16m, MUL_FI32m, MUL_F32m, MUL_F64m)>;
 
 defm : PdWriteResXMMPair<WriteFMul64,       [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResXMMPair<WriteFMul64X,      [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResYMMPair<WriteFMul64Y,      [PdFPU1, PdFPFMA],  5, [1, 2]>;
 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 
 defm : PdWriteResXMMPair<WriteFMA,          [PdFPU, PdFPFMA], 5, [1, 3]>;
 defm : PdWriteResXMMPair<WriteFMAX,         [PdFPU, PdFPFMA], 5, [1, 3]>;
 defm : PdWriteResYMMPair<WriteFMAY,         [PdFPU, PdFPFMA], 5, [1, 3]>;
 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 
 defm : PdWriteResXMMPair<WriteDPPD,         [PdFPU1, PdFPFMA], 15, [1, 10], 15, 2>;
 
 defm : PdWriteResXMMPair<WriteDPPS,         [PdFPU1, PdFPFMA], 25, [1, 14],  16, 2>;
 defm : PdWriteResYMMPair<WriteDPPSY,        [PdFPU1, PdFPFMA], 27, [2, 25], /*or 29*/ 25, 4>;
 
 def PdWriteVDPPSrri : SchedWriteRes<[PdFPU1, PdFPFMA]> {
   let Latency = 27;
-  let ResourceCycles = [1, 14];
+  let ReleaseAtCycles = [1, 14];
   let NumMicroOps = 17;
 }
 def : InstRW<[PdWriteVDPPSrri], (instrs VDPPSrri)>;
 
 defm : PdWriteResXMMPair<WriteFRcp,         [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResXMMPair<WriteFRcpX,        [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResYMMPair<WriteFRcpY,        [PdFPU1, PdFPFMA],  5, [2, 1]>;
 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 
 defm : PdWriteResXMMPair<WriteFRsqrt,       [PdFPU1, PdFPFMA],  5, [1, 2]>;
 defm : PdWriteResXMMPair<WriteFRsqrtX,      [PdFPU1, PdFPFMA],  5>;
 defm : PdWriteResYMMPair<WriteFRsqrtY,      [PdFPU1, PdFPFMA],  5, [2, 2]>;
 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 
 defm : PdWriteResXMMPair<WriteFDiv,         [PdFPU1, PdFPFMA], 9, [1, 9]>;
 defm : PdWriteResXMMPair<WriteFDivX,        [PdFPU1, PdFPFMA], 9, [1, 9]>;
 defm : PdWriteResYMMPair<WriteFDivY,        [PdFPU1, PdFPFMA], 9, [2, 18]>;
 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 
 def PdWriteX87Div: SchedWriteRes<[PdLoad, PdFPU0, PdFPFMA]> {
   let Latency = 9;
-  let ResourceCycles = [3, 1, 18];
+  let ReleaseAtCycles = [3, 1, 18];
 }
 def : InstRW<[PdWriteX87Div], (instrs DIV_FI16m,  DIV_FI32m,
                                       DIVR_FI16m, DIVR_FI32m,
                                       DIV_F32m,   DIV_F64m,
                                       DIVR_F32m,  DIVR_F64m)>;
 
 defm : PdWriteResXMMPair<WriteFDiv64,       [PdFPU1, PdFPFMA], 9, [1, 9]>;
 defm : PdWriteResXMMPair<WriteFDiv64X,      [PdFPU1, PdFPFMA], 9, [1, 9]>;

 defm : PdWriteResXMMPair<WriteFSign,        [PdFPU1, PdFPFMA],  1, [1, 4]>;
 
 defm : PdWriteResXMMPair<WriteFRnd,         [PdFPU1, PdFPSTO],  4, []>;
 defm : PdWriteResYMMPair<WriteFRndY,        [PdFPU1, PdFPSTO],  4, [2, 1], 2>;
 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 
 def PdWriteVFRCZP : SchedWriteRes<[PdFPU1, PdFPSTO]> {
   let Latency = 10;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteVFRCZP], (instrs VFRCZPDrr, VFRCZPSrr)>;
 
 def PdWriteVFRCZS : SchedWriteRes<[PdFPU1, PdFPSTO]> {
   let Latency = 10;
-  let ResourceCycles = [10, 1];
+  let ReleaseAtCycles = [10, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteVFRCZS], (instrs VFRCZSDrr, VFRCZSSrr)>;
 
 def PdWriteVFRCZm : SchedWriteRes<[PdFPU1, PdFPSTO]> {
   let Latency = 15;
-  let ResourceCycles = [2, 1];
+  let ReleaseAtCycles = [2, 1];
   let NumMicroOps = 3;
 }
 def : InstRW<[PdWriteVFRCZm], (instrs VFRCZPDrm, VFRCZPSrm,
                                       VFRCZSDrm, VFRCZSSrm)>;
 
 def PdWriteVFRCZY : SchedWriteRes<[PdFPU1, PdFPSTO]> {
   let Latency = 10;
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let NumMicroOps = 4;
 }
 def : InstRW<[PdWriteVFRCZY], (instrs VFRCZPSYrr, VFRCZPDYrr)>;
 
 def PdWriteVFRCZYm : SchedWriteRes<[PdFPU1, PdFPSTO]> {
   let Latency = 15;
-  let ResourceCycles = [4, 1];
+  let ReleaseAtCycles = [4, 1];
   let NumMicroOps = 8;
 }
 def : InstRW<[PdWriteVFRCZYm], (instrs VFRCZPSYrm, VFRCZPDYrm)>;
 
 defm : PdWriteResXMMPair<WriteFLogic,       [PdFPU23, PdFPMAL],  2>;
 defm : PdWriteResYMMPair<WriteFLogicY,      [PdFPU23, PdFPMAL],  2, [2, 2]>;
 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 
 defm : PdWriteResXMMPair<WriteFTest,        [PdFPU0, PdFPFMA, PdEX0],  1, [], 2>;
 defm : PdWriteResYMMPair<WriteFTestY,       [PdFPU01, PdFPFMA, PdEX0], 1, [4, 4, 1], 4, 2>;
 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 
 defm : PdWriteResXMMPair<WriteFShuffle,     [PdFPU01, PdFPFMA],  2, [1, 2]>;
 defm : PdWriteResYMMPair<WriteFShuffleY,    [PdFPU01, PdFPFMA],  2, [2, 4], 2>;
 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 
 def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
   let Latency = 7;
-  let ResourceCycles = [1, 3];
+  let ReleaseAtCycles = [1, 3];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
 
 defm : PdWriteResXMMPair<WriteFVarShuffle,  [PdFPU1, PdFPXBR],  3>;
 defm : PdWriteResYMMPair<WriteFVarShuffleY, [PdFPU1, PdFPXBR],  3, [2, 2], 2>;
 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 
 defm : PdWriteResXMMPair<WriteFBlend,       [PdFPU23, PdFPMAL],  2>;
 defm : PdWriteResYMMPair<WriteFBlendY,      [PdFPU23, PdFPMAL],  2, [2, 2], 2>;
 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 
 defm : PdWriteResXMMPair<WriteFVarBlend,    [PdFPU1, PdFPXBR],  2>;
 defm : PdWriteResYMMPair<WriteFVarBlendY,   [PdFPU1, PdFPXBR],  2, [2, 2], 2>;
 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 
 defm : PdWriteResXMMPair<WriteFShuffle256,  [PdFPU01, PdFPFMA],  2, [1, 3], 2>;
 defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
 
 def PdWriteVEXTRACTF128rr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
   let Latency = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[PdWriteVEXTRACTF128rr], (instrs VEXTRACTF128rr)>;
 
 def PdWriteVEXTRACTF128mr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
   let Latency = 7;
-  let ResourceCycles = [1, 4];
+  let ReleaseAtCycles = [1, 4];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteVEXTRACTF128mr], (instrs VEXTRACTF128mr)>;
 
 def PdWriteVPERM2F128rr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
   let Latency = 4;
-  let ResourceCycles = [1, 6];
+  let ReleaseAtCycles = [1, 6];
   let NumMicroOps = 8;
 }
 def : InstRW<[PdWriteVPERM2F128rr], (instrs VPERM2F128rr)>;
 
 def PdWriteVPERM2F128rm : SchedWriteRes<[PdFPU01, PdFPFMA]> {
   let Latency = 8; // 4 + 4
-  let ResourceCycles = [1, 8];
+  let ReleaseAtCycles = [1, 8];
   let NumMicroOps = 10;
 }
 def : InstRW<[PdWriteVPERM2F128rm], (instrs VPERM2F128rm)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Conversions.
 ////////////////////////////////////////////////////////////////////////////////
 

 defm : PdWriteResYMMPair<WriteCvtI2PSY,  [PdFPU0, PdFPCVT, PdFPSTO], 4, [1, 2, 1]>;
 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 
 defm : PdWriteResXMMPair<WriteCvtI2SD,   [PdFPU0, PdFPCVT, PdFPSTO], 4, [], 2>;
 // FIXME: .Folded version is one NumMicroOp *less*..
 
 def PdWriteCVTSI642SDrr_CVTSI642SSrr_CVTSI2SDr_CVTSI2SSrr : SchedWriteRes<[PdFPU0, PdFPCVT, PdFPSTO]> {
   let Latency = 13;
-  let ResourceCycles = [1, 3, 1];
+  let ReleaseAtCycles = [1, 3, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteCVTSI642SDrr_CVTSI642SSrr_CVTSI2SDr_CVTSI2SSrr], (instrs CVTSI642SDrr, CVTSI642SSrr, CVTSI2SDrr, CVTSI2SSrr)>;
 
 defm : PdWriteResXMMPair<WriteCvtI2PD,   [PdFPU0, PdFPCVT, PdFPSTO], 8, [],     2>;
 defm : PdWriteResYMMPair<WriteCvtI2PDY,  [PdFPU0, PdFPCVT, PdFPSTO], 8, [1, 2, 1], 4, 1>;
 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 

 
 defm : PdWriteResXMMPair<WriteVarShuffle,    [PdFPU1, PdFPXBR], 3>;
 defm : PdWriteResXMMPair<WriteVarShuffleX,   [PdFPU1, PdFPXBR], 3>;
 defm : X86WriteResPairUnsupported<WriteVarShuffleY>;
 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 
 def PdWriteVPPERM : SchedWriteRes<[PdFPU1, PdFPXBR]> {
   let Latency = 2;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
 }
 def : InstRW<[PdWriteVPPERM], (instrs VPPERMrrr, VPPERMrrr_REV)>;
 
 def PdWriteVPPERMLd : SchedWriteRes<[PdFPU1, PdFPXBR, PdLoad]> {
   let Latency = 7;
-  let ResourceCycles = [1, 1, 3];
+  let ReleaseAtCycles = [1, 1, 3];
 }
 def : InstRW<[PdWriteVPPERMLd], (instrs VPPERMrrm, VPPERMrmr)>;
 
 defm : PdWriteResXMMPair<WriteBlend,         [PdFPU23, PdFPMAL], 2>;
 defm : X86WriteResPairUnsupported<WriteBlendY>;
 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 
 defm : PdWriteResXMMPair<WriteVarBlend,      [PdFPU1, PdFPXBR], 2>;

 defm : PdWriteRes<WriteVecInsert,    [PdFPU01, PdFPMAL], 2, [1, 3], 2>;
 defm : PdWriteRes<WriteVecInsertLd,  [PdFPU01, PdFPMAL, PdLoad], 6, [1, 4, 3], 2>;
 
 defm : PdWriteRes<WriteVecExtract,   [PdFPU0, PdFPFMA, PdEX0], 12, [1, 3, 1], 2>;
 defm : PdWriteRes<WriteVecExtractSt, [PdFPU1, PdFPSTO, PdStore], 13, [2, 1, 1], 2>;
 
 def PdWriteEXTRQ : SchedWriteRes<[PdFPU01, PdFPMAL]> {
   let Latency = 3;
-  let ResourceCycles = [1, 3];
+  let ReleaseAtCycles = [1, 3];
 }
 def : InstRW<[PdWriteEXTRQ], (instrs EXTRQ, EXTRQI)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // SSE42 String instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : PdWriteResXMMPair<WritePCmpIStrI, [PdFPU1, PdFPFMA, PdEX0], 11, [1, 6, 1], 7, 1>;

 ////////////////////////////////////////////////////////////////////////////////
 // Carry-less multiplication instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : PdWriteResXMMPair<WriteCLMul, [PdFPU0, PdFPMMA], 12, [1, 7], 5, 1>;
 
 def PdWriteVPCLMULQDQrr : SchedWriteRes<[PdFPU0, PdFPMMA]> {
   let Latency = 12;
-  let ResourceCycles = [1, 7];
+  let ReleaseAtCycles = [1, 7];
   let NumMicroOps = 6;
 }
 def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // SSE4A instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 def PdWriteINSERTQ : SchedWriteRes<[PdFPU01, PdFPMAL]> {
   let Latency = 3;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[PdWriteINSERTQ], (instrs INSERTQ)>;
 
 def PdWriteINSERTQI : SchedWriteRes<[PdFPU01, PdFPMAL]> {
   let Latency = 3;
-  let ResourceCycles = [1, 3];
+  let ReleaseAtCycles = [1, 3];
 }
 def : InstRW<[PdWriteINSERTQI], (instrs INSERTQI)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // AVX instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 def PdWriteVBROADCASTYLd : SchedWriteRes<[PdLoad, PdFPU01, PdFPFMA]> {
   let Latency = 6;
-  let ResourceCycles = [1, 2, 4];
+  let ReleaseAtCycles = [1, 2, 4];
   let NumMicroOps = 2;
 }
 def : InstRW<[PdWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm,
                                                           VBROADCASTSSYrm)>;
 
 def PdWriteVZEROALL : SchedWriteRes<[]> {
   let Latency = 90;
   let NumMicroOps = 32;

llvm/lib/Target/X86/X86ScheduleBtVer2.td

 // folded loads.
 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
                             list<ProcResourceKind> ExePorts,
                             int Lat, list<int> Res = [], int UOps = 1,
                             int LoadUOps = 0> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
   // latency.
   def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
     let Latency = !add(Lat, 3);
-    let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
+    let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
                             list<ProcResourceKind> ExePorts,
                             int Lat, list<int> Res = [], int UOps = 1,
                             int LoadUOps = 0> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
   // latency.
   def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
     let Latency = !add(Lat, 5);
-    let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
+    let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
                             list<ProcResourceKind> ExePorts,
                             int Lat, list<int> Res = [2], int UOps = 2,
                             int LoadUOps = 0> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses 2 cycles on JLAGU and adds 5 cycles to the
   // latency.
   def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
     let Latency = !add(Lat, 5);
-    let ResourceCycles = !listconcat([2], Res);
+    let ReleaseAtCycles = !listconcat([2], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // Instructions that have local forwarding disabled have an extra +1cy latency.
 
 // A folded store needs a cycle on the SAGU for the store data, most RMW
 // instructions don't need an extra uop.  ALU RMW operations don't seem to

 def : WriteRes<WriteFence,  [JSAGU]>;
 
 // Nops don't have dependencies, so there's no actual latency, but we set this
 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
 def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
 
 def JWriteCMPXCHG8rr : SchedWriteRes<[JALU01]> {
   let Latency = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 3;
 }
 
 def JWriteLOCK_CMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 16;
-  let ResourceCycles = [3,16,16];
+  let ReleaseAtCycles = [3,16,16];
   let NumMicroOps = 5;
 }
 
 def JWriteLOCK_CMPXCHGrm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 17;
-  let ResourceCycles = [3,17,17];
+  let ReleaseAtCycles = [3,17,17];
   let NumMicroOps = 6;
 }
 
 def JWriteCMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 11;
-  let ResourceCycles = [3,1,1];
+  let ReleaseAtCycles = [3,1,1];
   let NumMicroOps = 5;
 }
 
 def JWriteCMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 11;
-  let ResourceCycles = [3,1,1];
+  let ReleaseAtCycles = [3,1,1];
   let NumMicroOps = 18;
 }
 
 def JWriteCMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 32;
-  let ResourceCycles = [6,1,1];
+  let ReleaseAtCycles = [6,1,1];
   let NumMicroOps = 28;
 }
 
 def JWriteLOCK_CMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 19;
-  let ResourceCycles = [3,19,19];
+  let ReleaseAtCycles = [3,19,19];
   let NumMicroOps = 18;
 }
 
 def JWriteLOCK_CMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 38;
-  let ResourceCycles = [6,38,38];
+  let ReleaseAtCycles = [6,38,38];
   let NumMicroOps = 28;
 }
 
 def JWriteCMPXCHGVariant :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsAtomicCompareAndSwap8B>,  [JWriteLOCK_CMPXCHG8B]>,
   SchedVar<MCSchedPredicate<IsAtomicCompareAndSwap16B>, [JWriteLOCK_CMPXCHG16B]>,
   SchedVar<MCSchedPredicate<IsAtomicCompareAndSwap_8>,  [JWriteLOCK_CMPXCHG8rm]>,
   SchedVar<MCSchedPredicate<IsAtomicCompareAndSwap>,    [JWriteLOCK_CMPXCHGrm]>,
def : InstRW<[JWriteCMPXCHGVariant,
               // Ignore reads contributed by the memory operand.
               ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
               // Add a read-advance to every implicit register read.
               ReadAfterLd, ReadAfterLd, ReadAfterLd, ReadAfterLd], (instrs LCMPXCHG8B, LCMPXCHG16B,
                                                                            CMPXCHG8B, CMPXCHG16B)>;
 
 def JWriteLOCK_ALURMW : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
   let Latency = 19;
-  let ResourceCycles = [1,19,19];
+  let ReleaseAtCycles = [1,19,19];
   let NumMicroOps = 1;
 }
 
 def JWriteLOCK_ALURMWVariant :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<CheckLockPrefix>, [JWriteLOCK_ALURMW]>,
   SchedVar<NoSchedPred,                       [WriteALURMW]>
 ]>;
 def : InstRW<[JWriteLOCK_ALURMWVariant], (instrs INC8m, INC16m, INC32m, INC64m,
                                                  DEC8m, DEC16m, DEC32m, DEC64m,
                                                  NOT8m, NOT16m, NOT32m, NOT64m,
                                                  NEG8m, NEG16m, NEG32m, NEG64m)>;
 
 def JWriteXCHG8rr_XADDrr : SchedWriteRes<[JALU01]> {
   let Latency = 2;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 3;
 }
 def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
                                                       XADD32rr, XADD64rr)>;
 
 // This write defines the latency of the in/out register operand of a non-atomic
 // XADDrm. This is the first of a pair of writes that model non-atomic
 // XADDrm instructions (the second write definition is JWriteXADDrm_LdSt_Part).
 //
 // We need two writes because the instruction latency differs from the output
 // register operand latency. In particular, the first write describes the first
 // (and only) output register operand of the instruction.  However, the
 // instruction latency is set to the MAX of all the write latencies. That's why
 // a second write is needed in this case (see example below).
 //
 // Example:
 //     XADD %ecx, (%rsp)      ## Instruction latency: 11cy
 //                            ## ECX write Latency: 3cy
 //
 // Register ECX becomes available in 3 cycles. That is because the value of ECX
 // is exchanged with the value read from the stack pointer, and the load-to-use
 // latency is assumed to be 3cy.
 def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
   let Latency = 3;  // load-to-use latency
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 3;
 }
 
 // This write defines the latency of the in/out register operand of an atomic
 // XADDrm. This is the first of a sequence of two writes used to model atomic
 // XADD instructions. The second write of the sequence is JWriteXCHGrm_LdSt_Part.
 //
 //
 // Example:
 //    LOCK XADD %ecx, (%rsp)     ## Instruction Latency: 16cy
 //                               ## ECX write Latency: 11cy
 //
 // The value of ECX becomes available only after 11cy from the start of
 // execution. This write is used to specifically set that operand latency. 
 def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
   let Latency = 11;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 3;
 }
 
 // This write defines the latency of the in/out register operand of an atomic
 // XCHGrm. This write is the first of a sequence of two writes that describe
 // atomic XCHG operations. We need two writes because the instruction latency
 // differs from the output register write latency.  We want to make sure that
 // the output register operand becomes visible after 11cy. However, we want to
 // set the instruction latency to 16cy.
 def JWriteXCHGrm_XCHG_Part : SchedWriteRes<[JALU01]> {
   let Latency = 11;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 
 def JWriteXADDrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
   let Latency = 11;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 1;
 }
 
 def JWriteXCHGrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
   let Latency = 16;
-  let ResourceCycles = [16, 16];
+  let ReleaseAtCycles = [16, 16];
   let NumMicroOps = 1;
 }
 
 def JWriteXADDrm_Part1 : SchedWriteVariant<[
   SchedVar<MCSchedPredicate<CheckLockPrefix>, [JWriteLOCK_XADDrm_XCHG_Part]>,
   SchedVar<NoSchedPred,                       [JWriteXADDrm_XCHG_Part]>
 ]>;
 

 defm : JWriteResFpuPair<WriteCLMul,       [JFPU0, JVIMUL], 2>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // SSE4A instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
   let Latency = 2;
-  let ResourceCycles = [1, 4];
+  let ReleaseAtCycles = [1, 4];
 }
 def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // AVX instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 def JWriteVecExtractF128: SchedWriteRes<[JFPU01, JFPX]>;
 def : InstRW<[JWriteVecExtractF128], (instrs VEXTRACTF128rr)>;
 
 def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
   let Latency = 6;
-  let ResourceCycles = [1, 2, 4];
+  let ReleaseAtCycles = [1, 2, 4];
   let NumMicroOps = 2;
 }
 def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
                                             VBROADCASTSSYrm,
                                             VBROADCASTF128)>;
 
 def JWriteJVZEROALL: SchedWriteRes<[]> {
   let Latency = 90;
   let NumMicroOps = 73;
 }
 def : InstRW<[JWriteJVZEROALL], (instrs VZEROALL)>;
 
 def JWriteJVZEROUPPER: SchedWriteRes<[]> {
   let Latency = 46;
   let NumMicroOps = 37;
 }
 def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>;
 
 ///////////////////////////////////////////////////////////////////////////////
 //  SSE2/AVX Store Selected Bytes of Double Quadword - (V)MASKMOVDQ
 ///////////////////////////////////////////////////////////////////////////////
 
 def JWriteMASKMOVDQU: SchedWriteRes<[JFPU0, JFPA, JFPU1, JSTC, JLAGU, JSAGU, JALU01]> {
   let Latency = 34;
-  let ResourceCycles = [1, 1, 2, 2, 2, 16, 42];
+  let ReleaseAtCycles = [1, 1, 2, 2, 2, 16, 42];
   let NumMicroOps = 63;
 }
 def : InstRW<[JWriteMASKMOVDQU], (instrs MASKMOVDQU, MASKMOVDQU64,
                                          VMASKMOVDQU, VMASKMOVDQU64)>;
 
 ///////////////////////////////////////////////////////////////////////////////
 //  SchedWriteVariant definitions.
 ///////////////////////////////////////////////////////////////////////////////
def JWriteLEA : SchedWriteVariant<[
     SchedVar<JSlowLEAPredicate, [JWrite3OpsLEA]>,
     SchedVar<NoSchedPred,       [WriteLEA]>
 ]>;
 
 def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
 
 def JSlowLEA16r : SchedWriteRes<[JALU01]> {
   let Latency = 3;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
 }
 
 def : InstRW<[JSlowLEA16r], (instrs LEA16r)>;
 
 ///////////////////////////////////////////////////////////////////////////////
 // Dependency breaking instructions.
 ///////////////////////////////////////////////////////////////////////////////
 

llvm/lib/Target/X86/X86ScheduleSLM.td

 // folded loads.
 multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
                            list<ProcResourceKind> ExePorts,
                            int Lat, list<int> Res = [1], int UOps = 1,
                            int LoadUOps = 0, int LoadLat = 3> {
   // Register variant is using a single cycle on ExePort.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
   // the latency (default = 3).
   def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !listconcat([1], Res);
+    let ReleaseAtCycles = !listconcat([1], Res);
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // A folded store needs a cycle on MEC_RSV for the store data (using the same uop),
 // but it does not need an extra port cycle to recompute the address.
 def : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; }
 

 defm : SLMWriteResPair<WriteJump,   [SLM_IEC_RSV1],  1>;
 defm : SLMWriteResPair<WriteCRC32,  [SLM_IEC_RSV1],  3>;
 
 defm : SLMWriteResPair<WriteCMOV,  [SLM_IEC_RSV01], 2, [2]>;
 defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move.
 def  : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
 def  : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
   // FIXME Latency and NumMicrOps?
-  let ResourceCycles = [2,1];
+  let ReleaseAtCycles = [2,1];
 }
 defm : X86WriteRes<WriteLAHFSAHF,        [SLM_IEC_RSV01], 1, [1], 1>;
 defm : X86WriteRes<WriteBitTest,         [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;
 defm : X86WriteRes<WriteBitTestImmLd,    [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 1>;
 defm : X86WriteRes<WriteBitTestRegLd,    [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 7>;
 defm : X86WriteRes<WriteBitTestSet,      [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;
 defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 1>;
 defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 8>;

 defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0],  1>;
 
 def  : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> {
   let NumMicroOps = 2;
 }
 def  : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
   let Latency = 4;
   let NumMicroOps = 5;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 
 ////////////////////////////////////////////////////////////////////////////////
 // Horizontal add/sub  instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : SLMWriteResPair<WriteFHAdd,   [SLM_FPC_RSV1],  6, [6], 4, 1>;
 defm : X86WriteResPairUnsupported<WriteFHAddY>;

 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
 def : WriteRes<WriteNop, []>;
 
 // Remaining SLM instrs.
 
 def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
   let Latency = 4;
   let NumMicroOps = 2;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
 }
 def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
                                            MMX_PSUBQrr, PSUBQrr,
                                            PCMPEQQrr)>;
 
 def SLMWriteResGroup2rr : SchedWriteRes<[SLM_FPC_RSV0]> {
   let Latency = 5;
   let NumMicroOps = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def: InstRW<[SLMWriteResGroup2rr], (instrs PCMPGTQrr)>;
 
 def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
   let Latency = 7;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,8];
+  let ReleaseAtCycles = [1,8];
 }
 
 def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
                                            MMX_PSUBQrm, PSUBQrm,
                                            PCMPEQQrm)>;
 
 def SLMWriteResGroup2rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def: InstRW<[SLMWriteResGroup2rm], (instrs PCMPGTQrm)>;
 
 ///////////////////////////////////////////////////////////////////////////////
 // Dependency breaking instructions.
 ///////////////////////////////////////////////////////////////////////////////
 
 def : IsZeroIdiomFunction<[

llvm/lib/Target/X86/X86ScheduleZnver1.td

 // This multiclass is for folded loads for integer units.
 multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [], int UOps = 1,
                           int LoadLat = 4, int LoadUOps = 1> {
   // Register variant takes 1-cycle on Execution Port.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on ZnAGU
   // adds LoadLat cycles to the latency (default = 4).
   def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
+    let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // This multiclass is for folded loads for floating point units.
 multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [], int UOps = 1,
                           int LoadLat = 7, int LoadUOps = 0> {
   // Register variant takes 1-cycle on Execution Port.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on ZnAGU
   // adds LoadLat cycles to the latency (default = 7).
   def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
+    let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // WriteRMW is set for instructions with Memory write
 // operation in codegen
 def : WriteRes<WriteRMW, [ZnAGU]>;
 

 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 defm : ZnWriteResFpuPair<WritePHMINPOS,   [ZnFPU0],  4>;
 
 // Vector insert/extract operations.
 defm : ZnWriteResFpuPair<WriteVecInsert,   [ZnFPU],   1>;
 
 def : WriteRes<WriteVecExtract, [ZnFPU12, ZnFPU2]> {
   let Latency = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : WriteRes<WriteVecExtractSt, [ZnAGU, ZnFPU12, ZnFPU2]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2, 3];
+  let ReleaseAtCycles = [1, 2, 3];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK, [ZnFPU2]>;
 def : WriteRes<WriteMMXMOVMSK, [ZnFPU2]>;
 def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>;
 
 def : WriteRes<WriteVecMOVMSKY, [ZnFPU2]> {
   let NumMicroOps = 2;
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // AES Instructions.
 defm : ZnWriteResFpuPair<WriteAESDecEnc, [ZnFPU01], 4>;
 defm : ZnWriteResFpuPair<WriteAESIMC,    [ZnFPU01], 4>;
 defm : ZnWriteResFpuPair<WriteAESKeyGen, [ZnFPU01], 4>;
 
 def : WriteRes<WriteFence,  [ZnAGU]>;

 // FCOMI(P) FUCOMI(P).
 // m.
 def : InstRW<[ZnWriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 
 def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]>
 {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 
 // FICOM(P).
 def : InstRW<[ZnWriteFPU03], (instregex "FICOM(P?)(16|32)m")>;
 
 // FTST.
 def : InstRW<[ZnWriteFPU0Lat1], (instregex "TST_F")>;
 

 def : InstRW<[ZnWriteFPU01], (instrs VPBLENDDrri)>;
 // ymm
 def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>;
 
 // v,v,m,i
 def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> {
   let NumMicroOps = 2;
   let Latency = 8;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> {
   let NumMicroOps = 2;
   let Latency = 9;
-  let ResourceCycles = [1, 3];
+  let ReleaseAtCycles = [1, 3];
 }
 def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>;
 def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
 
 // MASKMOVQ.
 def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
 
 // MASKMOVDQU.
 def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>;
 
 // VPMASKMOVD.
 // ymm
 def : InstRW<[WriteMicrocoded],
                                (instregex "VPMASKMOVD(Y?)rm")>;
 // m, v,v.
 def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
 
 // VPBROADCAST B/W.
 // x, m8/16.
 def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[ZnWriteVPBROADCAST128Ld],
                                      (instregex "VPBROADCAST(B|W)rm")>;
 
 // y, m8/16
 def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[ZnWriteVPBROADCAST256Ld],
                                      (instregex "VPBROADCAST(B|W)Yrm")>;
 
 // VPGATHER.
 def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>;
 
 //-- Arithmetic instructions --//

 // x <- x,m.
 def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
   let Latency = 8;
 }
 // ymm.
 def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
 def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
 
 //=== Floating Point XMM and YMM Instructions ===//
 //-- Move instructions --//
 
 // VPERM2F128 / VPERM2I128.

 def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
                                          VBROADCASTI128)>;
 
 // EXTRACTPS.
 // r32,x,i.
 def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> {
   let Latency = 2;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
 
 def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [5, 1, 2];
+  let ReleaseAtCycles = [5, 1, 2];
 }
 // m32,x,i.
 def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
 
 // VEXTRACTF128 / VEXTRACTI128.
 // x,y,i.
 def : InstRW<[ZnWriteFPU013], (instrs VEXTRACTF128rr,
                                       VEXTRACTI128rr)>;
 
 // m128,y,i.
 def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr,
                                        VEXTRACTI128mr)>;
 
 def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> {
   let Latency = 9;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 // VINSERTF128 / VINSERTI128.
 // y,y,x,i.
 def : InstRW<[ZnWriteVINSERT128r], (instrs VINSERTF128rr,
                                            VINSERTI128rr)>;
 def : InstRW<[ZnWriteVINSERT128Ld], (instrs VINSERTF128rm,
                                             VINSERTI128rm)>;
 
 // VGATHER.
 def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>;
 
 //-- Conversion instructions --//
 def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> {
   let Latency = 4;
 }
 def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // CVTPD2PS.
 // x,x.
 def : SchedAlias<WriteCvtPD2PS,  ZnWriteCVTPD2PSr>;
 // y,y.
 def : SchedAlias<WriteCvtPD2PSY, ZnWriteCVTPD2PSYr>;
 // z,z.
 defm : X86WriteResUnsupported<WriteCvtPD2PSZ>;
 
 def ZnWriteCVTPD2PSLd: SchedWriteRes<[ZnAGU,ZnFPU3]> {
   let Latency = 11;
 }
 // x,m128.
 def : SchedAlias<WriteCvtPD2PSLd, ZnWriteCVTPD2PSLd>;
 
 // x,m256.
 def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def : SchedAlias<WriteCvtPD2PSYLd, ZnWriteCVTPD2PSYLd>;
 // z,m512
 defm : X86WriteResUnsupported<WriteCvtPD2PSZLd>;
 
 // CVTSD2SS.
 // x,x.
 // Same as WriteCVTPD2PSr
def ZnWriteCVTSS2SDr : SchedWriteRes<[ZnFPU3]> {
   let Latency = 4;
 }
 def : SchedAlias<WriteCvtSS2SD, ZnWriteCVTSS2SDr>;
 
 // x,m32.
 def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
   let Latency = 11;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : SchedAlias<WriteCvtSS2SDLd, ZnWriteCVTSS2SDLd>;
 
 def ZnWriteCVTDQ2PDr: SchedWriteRes<[ZnFPU12,ZnFPU3]> {
   let Latency = 5;
 }
 // CVTDQ2PD.
 // x,x.

 //-- SHA instructions --//
 // SHA256MSG2
 def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
 
 // SHA1MSG1, SHA256MSG1
 // x,x.
 def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
 // x,m.
 def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
   let Latency = 9;
-  let ResourceCycles = [1,2];
+  let ReleaseAtCycles = [1,2];
 }
 def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;
 
 // SHA1MSG2
 // x,x.
 def ZnWriteSHA1MSG2r : SchedWriteRes<[ZnFPU12]> ;
 def : InstRW<[ZnWriteSHA1MSG2r], (instrs SHA1MSG2rr)>;
 // x,m.

llvm/lib/Target/X86/X86ScheduleZnver2.td

 // This multiclass is for folded loads for integer units.
 multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [], int UOps = 1,
                           int LoadLat = 4, int LoadUOps = 1> {
   // Register variant takes 1-cycle on Execution Port.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on Zn2AGU
   // adds LoadLat cycles to the latency (default = 4).
   def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
+    let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // This multiclass is for folded loads for floating point units.
 multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
                           list<ProcResourceKind> ExePorts,
                           int Lat, list<int> Res = [], int UOps = 1,
                           int LoadLat = 7, int LoadUOps = 0> {
   // Register variant takes 1-cycle on Execution Port.
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 
   // Memory variant also uses a cycle on Zn2AGU
   // adds LoadLat cycles to the latency (default = 7).
   def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
     let Latency = !add(Lat, LoadLat);
-    let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
+    let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
     let NumMicroOps = !add(UOps, LoadUOps);
   }
 }
 
 // WriteRMW is set for instructions with Memory write
 // operation in codegen
 def : WriteRes<WriteRMW, [Zn2AGU]>;
 

 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 defm : Zn2WriteResFpuPair<WritePHMINPOS,   [Zn2FPU0],  4>;
 
 // Vector insert/extract operations.
 defm : Zn2WriteResFpuPair<WriteVecInsert,   [Zn2FPU],   1>;
 
 def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
   let Latency = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2, 3];
+  let ReleaseAtCycles = [1, 2, 3];
 }
 
 // MOVMSK Instructions.
 def : WriteRes<WriteFMOVMSK, [Zn2FPU2]>;
 def : WriteRes<WriteMMXMOVMSK, [Zn2FPU2]>;
 def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
 
 def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
   let NumMicroOps = 2;
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
 }
 
 // AES Instructions.
 defm : Zn2WriteResFpuPair<WriteAESDecEnc, [Zn2FPU01], 4>;
 defm : Zn2WriteResFpuPair<WriteAESIMC,    [Zn2FPU01], 4>;
 defm : Zn2WriteResFpuPair<WriteAESKeyGen, [Zn2FPU01], 4>;
 
 def : WriteRes<WriteFence,  [Zn2AGU]>;

 // FCOMI(P) FUCOMI(P).
 // m.
 def : InstRW<[Zn2WriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 
 def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
 {
   let Latency = 12;
   let NumMicroOps = 2;
-  let ResourceCycles = [1,3];
+  let ReleaseAtCycles = [1,3];
 }
 
 // FICOM(P).
 def : InstRW<[Zn2WriteFPU03], (instregex "FICOM(P?)(16|32)m")>;
 
 // FTST.
 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "TST_F")>;
 

 def : InstRW<[Zn2WriteFPU01], (instrs VPBLENDDrri)>;
 // ymm
 def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
 
 // v,v,m,i
 def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
   let NumMicroOps = 2;
   let Latency = 8;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
   let NumMicroOps = 2;
   let Latency = 9;
-  let ResourceCycles = [1, 3];
+  let ReleaseAtCycles = [1, 3];
 }
 def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
 def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
 
 // MASKMOVQ.
 def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
 
 // MASKMOVDQU.
 def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>;
 
 // VPMASKMOVD.
 // ymm
 def : InstRW<[WriteMicrocoded],
                                (instregex "VPMASKMOVD(Y?)rm")>;
 // m, v,v.
 def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
 
 // VPBROADCAST B/W.
 // x, m8/16.
 def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[Zn2WriteVPBROADCAST128Ld],
                                      (instregex "VPBROADCAST(B|W)rm")>;
 
 // y, m8/16
 def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
   let Latency = 8;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[Zn2WriteVPBROADCAST256Ld],
                                      (instregex "VPBROADCAST(B|W)Yrm")>;
 
 // VPGATHER.
 def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>;
 
 //-- Arithmetic instructions --//

 def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
                                           VBROADCASTI128)>;
 
 // EXTRACTPS.
 // r32,x,i.
 def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
   let Latency = 2;
   let NumMicroOps = 2; 
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
 
 def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
   let Latency = 5;
   let NumMicroOps = 2;
-  let ResourceCycles = [5, 1, 2];
+  let ReleaseAtCycles = [5, 1, 2];
 }
 // m32,x,i.
 def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
 
 // VEXTRACTF128 / VEXTRACTI128.
 // x,y,i.
 def : InstRW<[Zn2WriteFPU013], (instrs VEXTRACTF128rr,
                                        VEXTRACTI128rr)>;
 
 // m128,y,i.
 def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr,
                                         VEXTRACTI128mr)>;
 
 def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
   let Latency = 2;
-//  let ResourceCycles = [2];
+//  let ReleaseAtCycles = [2];
 }
 def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 // VINSERTF128 / VINSERTI128.
 // y,y,x,i.
 def : InstRW<[Zn2WriteVINSERT128r], (instrs VINSERTF128rr,
def Zn2WriteCVTSS2SDr : SchedWriteRes<[Zn2FPU3]> {
   let Latency = 3;
 }
 def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
 
 // x,m32.
 def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
   let Latency = 10;
   let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
 }
 def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;
 
 def Zn2WriteCVTDQ2PDr: SchedWriteRes<[Zn2FPU12,Zn2FPU3]> {
   let Latency = 3;
 }
 // CVTDQ2PD.
 // x,x.

llvm/lib/Target/X86/X86ScheduleZnver3.td

 // as two micro-ops when dispatched by the schedulers.
 // This multiclass defines the resource usage for variants with and without
 // folded loads.
 
 multiclass __zn3WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
                          int Lat = 1, list<int> Res = [], int UOps = 1> {
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 }
 
 multiclass __zn3WriteResPair<X86FoldableSchedWrite SchedRW,
                              list<ProcResourceKind> ExePorts, int Lat,
                              list<int> Res, int UOps, int LoadLat, int LoadUOps,
                              ProcResourceKind AGU, int LoadRes> {

 defm : Zn3WriteResInt<WriteLoad, [Zn3AGU012, Zn3Load], !add(Znver3Model.LoadLatency, 1), [1, 1], 1>;
 
 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 defm : Zn3WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver3Model.LoadLatency, 1), [], 0>;
 
 def Zn3WriteMOVSlow : SchedWriteRes<[Zn3AGU012, Zn3Load]> {
   let Latency = !add(Znver3Model.LoadLatency, 1);
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
 
 defm : Zn3WriteResInt<WriteStore, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatency, [1, 2], 1>;
 defm : Zn3WriteResInt<WriteStoreNT, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatency, [1, 2], 1>;
 defm : Zn3WriteResInt<WriteMove, [Zn3ALU0123], 1, [4], 1>;
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 def Zn3WriteMOVBE16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
   let Latency = Znver3Model.LoadLatency;
-  let ResourceCycles = [1, 1, 4];
+  let ReleaseAtCycles = [1, 1, 4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteMOVBE16rm], (instrs MOVBE16rm)>;
 
 def Zn3WriteMOVBEmr : SchedWriteRes<[Zn3ALU0123, Zn3AGU012, Zn3Store]> {
   let Latency = Znver3Model.StoreLatency;
-  let ResourceCycles = [4, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
 
 // Arithmetic.
 defm : Zn3WriteResIntPair<WriteALU, [Zn3ALU0123], 1, [1], 1>; // Simple integer ALU op.
 
 def Zn3WriteALUSlow : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
                                         AND8i8, AND16i16, AND32i32, AND64i32,
                                          OR8i8,  OR16i16,  OR32i32,  OR64i32,
                                         SUB8i8, SUB16i16, SUB32i32, SUB64i32,
                                         XOR8i8, XOR16i16, XOR32i32, XOR64i32)>;
 
 def Zn3WriteMoveExtend : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
 
 def Zn3WriteMaterialize32bitImm: SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
 
 def Zn3WritePDEP_PEXT : SchedWriteRes<[Zn3ALU1]> {
   let Latency = 3;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
                                           PEXT32rr, PEXT64rr)>;
 
 defm : Zn3WriteResIntPair<WriteADC, [Zn3ALU0123], 1, [4], 1>; // Integer ALU + flags op.
 
 def Zn3WriteADC8mr_SBB8mr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123, Zn3Store]> {
   let Latency = 1;
-  let ResourceCycles = [1, 1, 7, 1];
+  let ReleaseAtCycles = [1, 1, 7, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
 
 // This is for simple LEAs with one or two input operands.
 defm : Zn3WriteResInt<WriteLEA, [Zn3AGU012], 1, [1], 1>;     // LEA instructions can't fold loads.
 
 // This write is used for slow LEA instructions.
 def Zn3Write3OpsLEA : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 2;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 // On Znver3, a slow LEA is either a 3Ops LEA (base, index, offset),
 // or an LEA with a `Scale` value different than 1.
 def Zn3SlowLEAPredicate : MCSchedPredicate<
   CheckAny<[
     // A 3-operand LEA (base, index, offset).
def Zn3WriteLEA : SchedWriteVariant<[
     SchedVar<Zn3SlowLEAPredicate, [Zn3Write3OpsLEA]>,
     SchedVar<NoSchedPred,         [WriteLEA]>
 ]>;
 
 def : InstRW<[Zn3WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
 
 def Zn3SlowLEA16r : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 2; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[Zn3SlowLEA16r], (instrs LEA16r)>;
 
 // Integer multiplication
 defm : Zn3WriteResIntPair<WriteIMul8, [Zn3Multiplier], 3, [3], 1>; // Integer 8-bit multiplication.
 defm : Zn3WriteResIntPair<WriteIMul16, [Zn3Multiplier], 3, [3], 3, /*LoadUOps=*/1>; // Integer 16-bit multiplication.

 
 defm : Zn3WriteResInt<WriteBSWAP32, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 32-bit Swap.
 defm : Zn3WriteResInt<WriteBSWAP64, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 64-bit Swap.
 
 defm : Zn3WriteResIntPair<WriteCMPXCHG, [Zn3ALU0123], 3, [12], 5>; // Compare and set, compare and swap.
 
 def Zn3WriteCMPXCHG8rr : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 3;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 3;
 }
 def : InstRW<[Zn3WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
 
 defm : Zn3WriteResInt<WriteCMPXCHGRMW, [Zn3ALU0123], 3, [12], 6>;     // Compare and set, compare and swap.
 
 def Zn3WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
-  let ResourceCycles = [1, 1, 12];
+  let ReleaseAtCycles = [1, 1, 12];
   let NumMicroOps = !add(Zn3WriteCMPXCHG8rr.NumMicroOps, 2);
 }
 def : InstRW<[Zn3WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
 
 def Zn3WriteCMPXCHG8B : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 3; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [24];
+  let ReleaseAtCycles = [24];
   let NumMicroOps = 19;
 }
 def : InstRW<[Zn3WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
 
 def Zn3WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 4; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [59];
+  let ReleaseAtCycles = [59];
   let NumMicroOps = 28;
 }
 def : InstRW<[Zn3WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
 
 def Zn3WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
 
 def Zn3WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = 5;
 }
 def : InstRW<[Zn3WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
 
 def Zn3WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
 
 // Integer division.
 // FIXME: uops for 8-bit division measures as 2. for others it's a guess.
 // FIXME: latency for 8-bit division measures as 10. for others it's a guess.
 defm : Zn3WriteResIntPair<WriteDiv8, [Zn3Divider], 10, [10], 2>;
 defm : Zn3WriteResIntPair<WriteDiv16, [Zn3Divider], 11, [11], 2>;
 defm : Zn3WriteResIntPair<WriteDiv32, [Zn3Divider], 13, [13], 2>;
 defm : Zn3WriteResIntPair<WriteDiv64, [Zn3Divider], 17, [17], 2>;
 defm : Zn3WriteResIntPair<WriteIDiv8, [Zn3Divider], 10, [10], 2>;
 defm : Zn3WriteResIntPair<WriteIDiv16, [Zn3Divider], 11, [11], 2>;
 defm : Zn3WriteResIntPair<WriteIDiv32, [Zn3Divider], 13, [13], 2>;
 defm : Zn3WriteResIntPair<WriteIDiv64, [Zn3Divider], 17, [17], 2>;
 
 defm : Zn3WriteResIntPair<WriteBSF, [Zn3ALU1], 3, [3], 6, /*LoadUOps=*/2>; // Bit scan forward.
 defm : Zn3WriteResIntPair<WriteBSR, [Zn3ALU1], 4, [4], 6, /*LoadUOps=*/2>; // Bit scan reverse.
 
 defm : Zn3WriteResIntPair<WritePOPCNT, [Zn3ALU0123], 1, [1], 1>; // Bit population count.
 
 def Zn3WritePOPCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WritePOPCNT16rr], (instrs POPCNT16rr)>;
 
 defm : Zn3WriteResIntPair<WriteLZCNT, [Zn3ALU0123], 1, [1], 1>; // Leading zero count.
 
 def Zn3WriteLZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteLZCNT16rr], (instrs LZCNT16rr)>;
 
 defm : Zn3WriteResIntPair<WriteTZCNT, [Zn3ALU12], 2, [1], 2>; // Trailing zero count.
 
 def Zn3WriteTZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
   let Latency = 2;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteTZCNT16rr], (instrs TZCNT16rr)>;
 
 defm : Zn3WriteResIntPair<WriteCMOV, [Zn3ALU03], 1, [1], 1>; // Conditional move.
 defm : Zn3WriteResInt<WriteFCMOV, [Zn3ALU0123], 7, [28], 7>; // FIXME: not from llvm-exegesis // X87 conditional move.
 defm : Zn3WriteResInt<WriteSETCC, [Zn3ALU03], 1, [2], 1>; // Set register based on condition code.
 defm : Zn3WriteResInt<WriteSETCCStore, [Zn3ALU03, Zn3AGU012, Zn3Store], 2, [2, 1, 1], 2>; // FIXME: latency not from llvm-exegesis

 
 // Integer shifts and rotates.
 defm : Zn3WriteResIntPair<WriteShift, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 defm : Zn3WriteResIntPair<WriteShiftCL, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 defm : Zn3WriteResIntPair<WriteRotate, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 
 def Zn3WriteRotateR1 : SchedWriteRes<[Zn3ALU12]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                          RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def Zn3WriteRotateM1 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn3WriteRotateR1.NumMicroOps, 1);
 }
 def : InstRW<[Zn3WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
                                          RCR8m1, RCR16m1, RCR32m1, RCR64m1)>;
 
 def Zn3WriteRotateRightRI : SchedWriteRes<[Zn3ALU12]> {
   let Latency = 3;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 7;
 }
 def : InstRW<[Zn3WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def Zn3WriteRotateRightMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRI.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn3WriteRotateRightRI.NumMicroOps, 3);
 }
 def : InstRW<[Zn3WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
 
 def Zn3WriteRotateLeftRI : SchedWriteRes<[Zn3ALU12]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 9;
 }
 def : InstRW<[Zn3WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def Zn3WriteRotateLeftMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRI.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn3WriteRotateLeftRI.NumMicroOps, 2);
 }
 def : InstRW<[Zn3WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
 
 defm : Zn3WriteResIntPair<WriteRotateCL, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 
 def Zn3WriteRotateRightRCL : SchedWriteRes<[Zn3ALU12]> {
   let Latency = 3;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 7;
 }
 def : InstRW<[Zn3WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
 
 def Zn3WriteRotateRightMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRCL.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn3WriteRotateRightRCL.NumMicroOps, 2);
 }
 def : InstRW<[Zn3WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
 
 def Zn3WriteRotateLeftRCL : SchedWriteRes<[Zn3ALU12]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 9;
 }
 def : InstRW<[Zn3WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
 
 def Zn3WriteRotateLeftMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRCL.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn3WriteRotateLeftRCL.NumMicroOps, 2);
 }
 def : InstRW<[Zn3WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
 
 // Double shift instructions.
 defm : Zn3WriteResInt<WriteSHDrri, [Zn3ALU12], 2, [3], 4>;
 defm : Zn3WriteResInt<WriteSHDrrcl, [Zn3ALU12], 2, [3], 5>;
 defm : Zn3WriteResInt<WriteSHDmri, [Zn3AGU012, Zn3Load, Zn3ALU12], !add(Znver3Model.LoadLatency, 2), [1, 1, 4], 6>;

 defm : Zn3WriteResXMM<WriteFLoadX, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResYMM<WriteFLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteFMaskedLoad, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResYMM<WriteFMaskedLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteFStore, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 
 def Zn3WriteWriteFStoreMMX : SchedWriteRes<[Zn3FPSt, Zn3Store]> {
   let Latency = 2; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteWriteFStoreMMX], (instrs MOVHPDmr,  MOVHPSmr,
                                                VMOVHPDmr, VMOVHPSmr)>;
 
 defm : Zn3WriteResXMM<WriteFStoreX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResYMM<WriteFStoreY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteFStoreNT, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteFStoreNTX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResYMM<WriteFStoreNTY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 
 defm : Zn3WriteResXMM<WriteFMaskedStore32, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
 defm : Zn3WriteResXMM<WriteFMaskedStore64, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [4, 1], 10>;
 defm : Zn3WriteResYMM<WriteFMaskedStore32Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [12, 1], 42>;
 defm : Zn3WriteResYMM<WriteFMaskedStore64Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
 
 defm : Zn3WriteResXMMPair<WriteFAdd, [Zn3FPFAdd01], 3, [1], 1>;  // Floating point add/sub.
 
 def Zn3WriteX87Arith : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 24];
+  let ReleaseAtCycles = [1, 1, 24];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
                                          SUB_FI16m, SUB_FI32m,
                                          SUBR_FI16m, SUBR_FI32m,
                                          MUL_FI16m, MUL_FI32m)>;
 
 def Zn3WriteX87Div : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 62];
+  let ReleaseAtCycles = [1, 1, 62];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
                                        DIVR_FI16m, DIVR_FI32m)>;
 
 defm : Zn3WriteResXMMPair<WriteFAddX, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub (XMM).
 defm : Zn3WriteResYMMPair<WriteFAddY, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub (YMM).
 defm : X86WriteResPairUnsupported<WriteFAddZ>; // Floating point add/sub (ZMM).

 defm : Zn3WriteResYMM<WriteVecLoadNTY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteVecMaskedLoad, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResYMM<WriteVecMaskedLoadY, [Zn3FPLd01, Zn3Load], !add(Znver3Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteVecStore, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteVecStoreX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 
 def Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn3FPFMisc0]> {
   let Latency = 4;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
 
 def Zn3WriteVEXTRACTI128mr : SchedWriteRes<[Zn3FPFMisc0, Zn3FPSt, Zn3Store]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
-  let ResourceCycles = [1, 1, 1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
 }
 def : InstRW<[Zn3WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
 
 def Zn3WriteVINSERTF128rmr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPFMisc0]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
-  let ResourceCycles = [1, 1, 1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn3WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
 
 defm : Zn3WriteResYMM<WriteVecStoreY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteVecStoreNT, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResYMM<WriteVecStoreNTY, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [1, 1], 1>;
 defm : Zn3WriteResXMM<WriteVecMaskedStore32, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
 defm : Zn3WriteResXMM<WriteVecMaskedStore64, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [4, 1], 10>;
 defm : Zn3WriteResYMM<WriteVecMaskedStore32Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [12, 1], 42>;
 defm : Zn3WriteResYMM<WriteVecMaskedStore64Y, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency, [6, 1], 18>;
 
 defm : Zn3WriteResXMM<WriteVecMoveToGpr, [Zn3FPLd01], 1, [2], 1>;
 defm : Zn3WriteResXMM<WriteVecMoveFromGpr, [Zn3FPLd01], 1, [2], 1>;
 
 def Zn3WriteMOVMMX : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
   let Latency = 1;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
 
 def Zn3WriteMOVMMXSlow : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
   let Latency = 1;
-  let ResourceCycles = [1, 4];
+  let ReleaseAtCycles = [1, 4];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
 
 defm : Zn3WriteResXMMPair<WriteVecALU, [Zn3FPVAdd0123], 1, [1], 1>;  // Vector integer ALU op, no logicals.
 
 def Zn3WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
   let Latency = 3;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
 
 def Zn3WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
   let Latency = 3;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
 
 defm : Zn3WriteResXMMPair<WriteVecALUX, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (XMM).
 
 def Zn3WriteVecALUXSlow : SchedWriteRes<[Zn3FPVAdd01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
                                             PADDSBrr, PADDSWrr, PADDUSBrr, PADDUSWrr,
                                             PAVGBrr, PAVGWrr,
                                             PSIGNBrr, PSIGNDrr, PSIGNWrr,
                                             VPABSBrr, VPABSDrr, VPABSWrr,
                                             VPADDSBrr, VPADDSWrr, VPADDUSBrr, VPADDUSWrr,
                                             VPAVGBrr, VPAVGWrr,
                                             VPCMPEQQrr,
                                             VPSIGNBrr, VPSIGNDrr, VPSIGNWrr,
                                             PSUBSBrr, PSUBSWrr, PSUBUSBrr, PSUBUSWrr, VPSUBSBrr, VPSUBSWrr, VPSUBUSBrr, VPSUBUSWrr)>;
 
 def Zn3WriteVecALUXMMX : SchedWriteRes<[Zn3FPVAdd01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteVecALUXMMX], (instrs MMX_PABSBrr, MMX_PABSDrr, MMX_PABSWrr,
                                            MMX_PSIGNBrr, MMX_PSIGNDrr, MMX_PSIGNWrr,
                                            MMX_PADDSBrr, MMX_PADDSWrr, MMX_PADDUSBrr, MMX_PADDUSWrr,
                                            MMX_PAVGBrr, MMX_PAVGWrr,
                                            MMX_PSUBSBrr, MMX_PSUBSWrr, MMX_PSUBUSBrr, MMX_PSUBUSWrr)>;
 
 defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (YMM).
 
 def Zn3WriteVecALUYSlow : SchedWriteRes<[Zn3FPVAdd01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
                                             VPADDSBYrr, VPADDSWYrr, VPADDUSBYrr, VPADDUSWYrr,
                                             VPSUBSBYrr, VPSUBSWYrr, VPSUBUSBYrr, VPSUBUSWYrr,
                                             VPAVGBYrr, VPAVGWYrr,
                                             VPCMPEQQYrr,
                                             VPSIGNBYrr, VPSIGNDYrr, VPSIGNWYrr)>;

 // Conversion between integer and float.
 defm : Zn3WriteResXMMPair<WriteCvtSD2I, [Zn3FPFCvt01], 2, [2], 2>;  // Double -> Integer.
 defm : Zn3WriteResXMMPair<WriteCvtPD2I, [Zn3FPFCvt01], 3, [1], 1>; // Double -> Integer (XMM).
 defm : Zn3WriteResYMMPair<WriteCvtPD2IY, [Zn3FPFCvt01], 6, [2], 2>; // Double -> Integer (YMM).
 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; // Double -> Integer (ZMM).
 
 def Zn3WriteCvtPD2IMMX : SchedWriteRes<[Zn3FPFCvt01]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteCvtPD2IMMX], (instrs MMX_CVTPD2PIrm, MMX_CVTTPD2PIrm, MMX_CVTPD2PIrr, MMX_CVTTPD2PIrr)>;
 
 defm : Zn3WriteResXMMPair<WriteCvtSS2I, [Zn3FPFCvt01], 2, [2], 2>;  // Float -> Integer.
 
 defm : Zn3WriteResXMMPair<WriteCvtPS2I, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Integer (XMM).
 defm : Zn3WriteResYMMPair<WriteCvtPS2IY, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Integer (YMM).
 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; // Float -> Integer (ZMM).
 
 defm : Zn3WriteResXMMPair<WriteCvtI2SD, [Zn3FPFCvt01], 3, [2], 2, /*LoadUOps=*/-1>;  // Integer -> Double.
 defm : Zn3WriteResXMMPair<WriteCvtI2PD, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Double (XMM).
 defm : Zn3WriteResYMMPair<WriteCvtI2PDY, [Zn3FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>; // Integer -> Double (YMM).
 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; // Integer -> Double (ZMM).
 
 def Zn3WriteCvtI2PDMMX : SchedWriteRes<[Zn3FPFCvt01]> {
   let Latency = 2;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteCvtI2PDMMX], (instrs MMX_CVTPI2PDrm, MMX_CVTPI2PDrr)>;
 
 defm : Zn3WriteResXMMPair<WriteCvtI2SS, [Zn3FPFCvt01], 3, [2], 2, /*LoadUOps=*/-1>;  // Integer -> Float.
 defm : Zn3WriteResXMMPair<WriteCvtI2PS, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Float (XMM).
 defm : Zn3WriteResYMMPair<WriteCvtI2PSY, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Float (YMM).
 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; // Integer -> Float (ZMM).
 
 def Zn3WriteCvtI2PSMMX : SchedWriteRes<[Zn3FPFCvt01]> {
   let Latency = 3;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteCvtI2PSMMX], (instrs MMX_CVTPI2PSrr)>;
 
 defm : Zn3WriteResXMMPair<WriteCvtSS2SD, [Zn3FPFCvt01], 3, [1], 1>;  // Float -> Double size conversion.
 defm : Zn3WriteResXMMPair<WriteCvtPS2PD, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Double size conversion (XMM).
 defm : Zn3WriteResYMMPair<WriteCvtPS2PDY, [Zn3FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>; // Float -> Double size conversion (YMM).
 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; // Float -> Double size conversion (ZMM).

 defm : Zn3WriteResYMM<WriteCvtPS2PHYSt, [Zn3FPFCvt01, Zn3FPSt, Zn3Store], !add(6, Znver3Model.StoreLatency), [2, 1, 1], 3>; // Float -> Half + store size conversion (YMM).
 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; // Float -> Half + store size conversion (ZMM).
 
 // CRC32 instruction.
 defm : Zn3WriteResIntPair<WriteCRC32, [Zn3ALU1], 3, [1], 1>;
 
 def Zn3WriteSHA1MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
 
 def Zn3WriteSHA1MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG1rr.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn3WriteSHA1MSG1rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn3WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
 
 def Zn3WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
 
 def Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn3WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
 }
 def : InstRW<[Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
 
 def Zn3WriteSHA256MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 2;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
 
 def Zn3Writerm_SHA256MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG1rr.Latency);
-  let ResourceCycles = [1, 1, 3];
+  let ReleaseAtCycles = [1, 1, 3];
   let NumMicroOps = !add(Zn3WriteSHA256MSG1rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn3Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
 
 def Zn3WriteSHA256MSG2rr : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 3;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 def : InstRW<[Zn3WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
 
 def Zn3WriteSHA256MSG2rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG2rr.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn3WriteSHA256MSG2rr.NumMicroOps, 1);
 }
 def : InstRW<[Zn3WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
 
 def Zn3WriteSHA1RNDS4rri : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 6;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
 
 def Zn3WriteSHA256RNDS2rr : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
 
 // Strings instructions.
 // Packed Compare Implicit Length Strings, Return Mask
 defm : Zn3WriteResXMMPair<WritePCmpIStrM, [Zn3FPVAdd0123], 6, [8], 3, /*LoadUOps=*/1>;
 // Packed Compare Explicit Length Strings, Return Mask

 defm : Zn3WriteResInt<WriteLDMXCSR, [Zn3AGU012, Zn3Load, Zn3ALU0123], !add(Znver3Model.LoadLatency, 1), [1, 1, 6], 1>; // FIXME: latency not from llvm-exegesis
 defm : Zn3WriteResInt<WriteSTMXCSR, [Zn3ALU0123, Zn3AGU012, Zn3Store], !add(1, Znver3Model.StoreLatency), [60, 1, 1], 2>; // FIXME: latency not from llvm-exegesis
 
 // Catch-all for expensive system instructions.
 defm : Zn3WriteResInt<WriteSystem, [Zn3ALU0123], 100, [100], 100>;
 
 def Zn3WriteVZEROUPPER : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 0; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteVZEROUPPER], (instrs VZEROUPPER)>;
 
 def Zn3WriteVZEROALL : SchedWriteRes<[Zn3FPU0123]> {
   let Latency = 10; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [24];
+  let ReleaseAtCycles = [24];
   let NumMicroOps = 18;
 }
 def : InstRW<[Zn3WriteVZEROALL], (instrs VZEROALL)>;
 
 // AVX2.
 defm : Zn3WriteResYMMPair<WriteFShuffle256, [Zn3FPVShuf], 2, [1], 1, /*LoadUOps=*/2>; // Fp 256-bit width vector shuffles.
 defm : Zn3WriteResYMMPair<WriteFVarShuffle256, [Zn3FPVShuf], 7, [1], 2, /*LoadUOps=*/1>; // Fp 256-bit width variable shuffles.
 defm : Zn3WriteResYMMPair<WriteShuffle256, [Zn3FPVShuf], 2, [1], 1>; // 256-bit width vector shuffles.
 
 def Zn3WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn3FPVShuf]> {
   let Latency = 3;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
 
 def Zn3WriteVPERM2F128rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERM2I128rr_VPERM2F128rr.Latency);
-  let ResourceCycles = [1, 1, 1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = !add(Zn3WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn3WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
 
 def Zn3WriteVPERMPSYrm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
   let Latency = !add(Znver3Model.LoadLatency, 7);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = 3;
 }
 def : InstRW<[Zn3WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
 
 def Zn3WriteVPERMYri : SchedWriteRes<[Zn3FPVShuf]> {
   let Latency = 6;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
 
 def Zn3WriteVPERMPDYmi : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn3WriteVPERMYri.NumMicroOps, 1);
 }
 def : InstRW<[Zn3WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
 
 def Zn3WriteVPERMDYm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
   let Latency = !add(Znver3Model.LoadLatency, 5);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteVPERMDYm], (instrs VPERMQYmi, VPERMDYrm)>;
 
 defm : Zn3WriteResYMMPair<WriteVPMOV256, [Zn3FPVShuf01], 4, [3], 2, /*LoadUOps=*/-1>; // 256-bit width packed vector width-changing move.
 defm : Zn3WriteResYMMPair<WriteVarShuffle256, [Zn3FPVShuf], 5, [1], 2, /*LoadUOps=*/1>; // 256-bit width vector variable shuffles.
 defm : Zn3WriteResXMMPair<WriteVarVecShift, [Zn3FPVShift01], 1, [1], 1>; // Variable vector shifts.
 defm : Zn3WriteResYMMPair<WriteVarVecShiftY, [Zn3FPVShift01], 1, [1], 1>; // Variable vector shifts (YMM).
 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; // Variable vector shifts (ZMM).
 
 // Old microcoded instructions that nobody use.
 defm : Zn3WriteResInt<WriteMicrocoded, [Zn3ALU0123], 100, [100], 100>;
 
 // Fence instructions.
 defm : Zn3WriteResInt<WriteFence, [Zn3ALU0123], 1, [100], 1>;
 
 def Zn3WriteLFENCE : SchedWriteRes<[Zn3LSU]> {
   let Latency = 1;
-  let ResourceCycles = [30];
+  let ReleaseAtCycles = [30];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteLFENCE], (instrs LFENCE)>;
 
 def Zn3WriteSFENCE : SchedWriteRes<[Zn3LSU]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteSFENCE], (instrs SFENCE)>;
 
 // Nop, not very useful expect it provides a model for nops!
 defm : Zn3WriteResInt<WriteNop, [Zn3ALU0123], 0, [1], 1>; // FIXME: latency not from llvm-exegesis
 
 
 ///////////////////////////////////////////////////////////////////////////////
 // Zero Cycle Move
 ///////////////////////////////////////////////////////////////////////////////
 
 def Zn3WriteZeroLatency : SchedWriteRes<[]> {
   let Latency = 0;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn3WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
                                                MOV64rr, MOV64rr_REV,
                                                MOVSX32rr32)>;
 
 def Zn3WriteSwapRenameable : SchedWriteRes<[]> {
   let Latency = 0;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
                                                XCHG64rr, XCHG64ar)>;
 
 defm : Zn3WriteResInt<WriteXCHG, [Zn3ALU0123], 0, [8], 2>;        // Compare+Exchange - TODO RMW support.
 
 defm : Zn3WriteResXMM<WriteFMove, [Zn3FPVMisc0123], 1, [1], 1>; // Empty sched class

llvm/lib/Target/X86/X86ScheduleZnver4.td

 // as two micro-ops when dispatched by the schedulers.
 // This multiclass defines the resource usage for variants with and without
 // folded loads.
 
 multiclass __Zn4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
                          int Lat = 1, list<int> Res = [], int UOps = 1> {
   def : WriteRes<SchedRW, ExePorts> {
     let Latency = Lat;
-    let ResourceCycles = Res;
+    let ReleaseAtCycles = Res;
     let NumMicroOps = UOps;
   }
 }
 
 multiclass __Zn4WriteResPair<X86FoldableSchedWrite SchedRW,
                              list<ProcResourceKind> ExePorts, int Lat,
                              list<int> Res, int UOps, int LoadLat, int LoadUOps,
                              ProcResourceKind AGU, int LoadRes> {

 defm : Zn4WriteResInt<WriteLoad, [Zn4AGU012, Zn4Load], !add(Znver4Model.LoadLatency, 1), [1, 1], 1>;
 
 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 defm : Zn4WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver4Model.LoadLatency, 1), [], 0>;
 
 def Zn4WriteMOVSlow : SchedWriteRes<[Zn4AGU012, Zn4Load]> {
   let Latency = !add(Znver4Model.LoadLatency, 1);
-  let ResourceCycles = [3, 1];
+  let ReleaseAtCycles = [3, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
 
 defm : Zn4WriteResInt<WriteStore, [Zn4AGU012, Zn4Store], Znver4Model.StoreLatency, [1, 2], 1>;
 defm : Zn4WriteResInt<WriteStoreNT, [Zn4AGU012, Zn4Store], Znver4Model.StoreLatency, [1, 2], 1>;
 defm : Zn4WriteResInt<WriteMove, [Zn4ALU0123], 1, [4], 1>;
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 def Zn4WriteMOVBE16rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
   let Latency = Znver4Model.LoadLatency;
-  let ResourceCycles = [1, 1, 4];
+  let ReleaseAtCycles = [1, 1, 4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteMOVBE16rm], (instrs MOVBE16rm)>;
 
 def Zn4WriteMOVBEmr : SchedWriteRes<[Zn4ALU0123, Zn4AGU012, Zn4Store]> {
   let Latency = Znver4Model.StoreLatency;
-  let ResourceCycles = [4, 1, 1];
+  let ReleaseAtCycles = [4, 1, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
 
 // Arithmetic.
 defm : Zn4WriteResIntPair<WriteALU, [Zn4ALU0123], 1, [1], 1>; // Simple integer ALU op.
 
 def Zn4WriteALUSlow : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
                                         AND8i8, AND16i16, AND32i32, AND64i32,
                                          OR8i8,  OR16i16,  OR32i32,  OR64i32,
                                         SUB8i8, SUB16i16, SUB32i32, SUB64i32,
                                         XOR8i8, XOR16i16, XOR32i32, XOR64i32)>;
 
 def Zn4WriteMoveExtend : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
 
 def Zn4WriteMaterialize32bitImm: SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
 
 def Zn4WritePDEP_PEXT : SchedWriteRes<[Zn4ALU1]> {
   let Latency = 3;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
                                           PEXT32rr, PEXT64rr)>;
 
 defm : Zn4WriteResIntPair<WriteADC, [Zn4ALU0123], 1, [4], 1>; // Integer ALU + flags op.
 
 def Zn4WriteADC8mr_SBB8mr : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123, Zn4Store]> {
   let Latency = 1;
-  let ResourceCycles = [1, 1, 7, 1];
+  let ReleaseAtCycles = [1, 1, 7, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
 
 // This is for simple LEAs with one or two input operands.
 defm : Zn4WriteResInt<WriteLEA, [Zn4AGU012], 1, [1], 1>;     // LEA instructions can't fold loads.
 
 // This write is used for slow LEA instructions.
 def Zn4Write3OpsLEA : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 2;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 // On Znver4, a slow LEA is either a 3Ops LEA (base, index, offset),
 // or an LEA with a `Scale` value different than 1.
 def Zn4SlowLEAPredicate : MCSchedPredicate<
   CheckAny<[
     // A 3-operand LEA (base, index, offset).
def Zn4WriteLEA : SchedWriteVariant<[
     SchedVar<Zn4SlowLEAPredicate, [Zn4Write3OpsLEA]>,
     SchedVar<NoSchedPred,         [WriteLEA]>
 ]>;
 
 def : InstRW<[Zn4WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
 
 def Zn4SlowLEA16r : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 2; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 2;
 }
 
 def : InstRW<[Zn4SlowLEA16r], (instrs LEA16r)>;
 
 // Integer multiplication
 defm : Zn4WriteResIntPair<WriteIMul8, [Zn4Multiplier], 3, [3], 1>; // Integer 8-bit multiplication.
 defm : Zn4WriteResIntPair<WriteIMul16, [Zn4Multiplier], 3, [3], 3, /*LoadUOps=*/1>; // Integer 16-bit multiplication.

 
 defm : Zn4WriteResInt<WriteBSWAP32, [Zn4ALU0123], 1, [1], 1>; // Byte Order (Endianness) 32-bit Swap.
 defm : Zn4WriteResInt<WriteBSWAP64, [Zn4ALU0123], 1, [1], 1>; // Byte Order (Endianness) 64-bit Swap.
 
 defm : Zn4WriteResIntPair<WriteCMPXCHG, [Zn4ALU0123], 3, [12], 5>; // Compare and set, compare and swap.
 
 def Zn4WriteCMPXCHG8rr : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 3;
-  let ResourceCycles = [12];
+  let ReleaseAtCycles = [12];
   let NumMicroOps = 3;
 }
 def : InstRW<[Zn4WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
 
 defm : Zn4WriteResInt<WriteCMPXCHGRMW, [Zn4ALU0123], 3, [12], 6>;     // Compare and set, compare and swap.
 
 def Zn4WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteCMPXCHG8rr.Latency);
-  let ResourceCycles = [1, 1, 12];
+  let ReleaseAtCycles = [1, 1, 12];
   let NumMicroOps = !add(Zn4WriteCMPXCHG8rr.NumMicroOps, 2);
 }
 def : InstRW<[Zn4WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
 
 def Zn4WriteCMPXCHG8B : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 3; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [24];
+  let ReleaseAtCycles = [24];
   let NumMicroOps = 19;
 }
 def : InstRW<[Zn4WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
 
 def Zn4WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 4; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [59];
+  let ReleaseAtCycles = [59];
   let NumMicroOps = 28;
 }
 def : InstRW<[Zn4WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
 
 def Zn4WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
 
 def Zn4WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = 5;
 }
 def : InstRW<[Zn4WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
 
 def Zn4WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
 
 // Integer division.
 // FIXME: uops for 8-bit division measures as 2. for others it's a guess.
 // FIXME: latency for 8-bit division measures as 10. for others it's a guess.
 defm : Zn4WriteResIntPair<WriteDiv8, [Zn4Divider], 10, [10], 2>;
 defm : Zn4WriteResIntPair<WriteDiv16, [Zn4Divider], 11, [11], 2>;
 defm : Zn4WriteResIntPair<WriteDiv32, [Zn4Divider], 13, [13], 2>;
 defm : Zn4WriteResIntPair<WriteDiv64, [Zn4Divider], 17, [17], 2>;
 defm : Zn4WriteResIntPair<WriteIDiv8, [Zn4Divider], 10, [10], 2>;
 defm : Zn4WriteResIntPair<WriteIDiv16, [Zn4Divider], 11, [11], 2>;
 defm : Zn4WriteResIntPair<WriteIDiv32, [Zn4Divider], 13, [13], 2>;
 defm : Zn4WriteResIntPair<WriteIDiv64, [Zn4Divider], 17, [17], 2>;
 
 defm : Zn4WriteResIntPair<WriteBSF, [Zn4ALU1], 1, [1], 6, /*LoadUOps=*/1>; // Bit scan forward.
 defm : Zn4WriteResIntPair<WriteBSR, [Zn4ALU1], 1, [1], 6, /*LoadUOps=*/1>; // Bit scan reverse.
 
 defm : Zn4WriteResIntPair<WritePOPCNT, [Zn4ALU0123], 1, [1], 1>; // Bit population count.
 
 def Zn4WritePOPCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WritePOPCNT16rr], (instrs POPCNT16rr)>;
 
 defm : Zn4WriteResIntPair<WriteLZCNT, [Zn4ALU0123], 1, [1], 1>; // Leading zero count.
 
 def Zn4WriteLZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 1;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteLZCNT16rr], (instrs LZCNT16rr)>;
 
 defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 2, [1], 2>; // Trailing zero count.
 
 def Zn4WriteTZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
   let Latency = 2;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteTZCNT16rr], (instrs TZCNT16rr)>;
 
 defm : Zn4WriteResIntPair<WriteCMOV, [Zn4ALU03], 1, [1], 1>; // Conditional move.
 defm : Zn4WriteResInt<WriteFCMOV, [Zn4ALU0123], 7, [28], 7>; // FIXME: not from llvm-exegesis // X87 conditional move.
 defm : Zn4WriteResInt<WriteSETCC, [Zn4ALU03], 1, [2], 1>; // Set register based on condition code.
 defm : Zn4WriteResInt<WriteSETCCStore, [Zn4ALU03, Zn4AGU012, Zn4Store], 2, [2, 1, 1], 2>; // FIXME: latency not from llvm-exegesis

 
 // Integer shifts and rotates.
 defm : Zn4WriteResIntPair<WriteShift, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 defm : Zn4WriteResIntPair<WriteShiftCL, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 defm : Zn4WriteResIntPair<WriteRotate, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 
 def Zn4WriteRotateR1 : SchedWriteRes<[Zn4ALU12]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
                                          RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 
 def Zn4WriteRotateM1 : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateR1.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn4WriteRotateR1.NumMicroOps, 1);
 }
 def : InstRW<[Zn4WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
                                          RCR8m1, RCR16m1, RCR32m1, RCR64m1)>;
 
 def Zn4WriteRotateRightRI : SchedWriteRes<[Zn4ALU12]> {
   let Latency = 3;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 7;
 }
 def : InstRW<[Zn4WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 
 def Zn4WriteRotateRightMI : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateRightRI.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn4WriteRotateRightRI.NumMicroOps, 3);
 }
 def : InstRW<[Zn4WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
 
 def Zn4WriteRotateLeftRI : SchedWriteRes<[Zn4ALU12]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 9;
 }
 def : InstRW<[Zn4WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 
 def Zn4WriteRotateLeftMI : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateLeftRI.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn4WriteRotateLeftRI.NumMicroOps, 2);
 }
 def : InstRW<[Zn4WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
 
 defm : Zn4WriteResIntPair<WriteRotateCL, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
 
 def Zn4WriteRotateRightRCL : SchedWriteRes<[Zn4ALU12]> {
   let Latency = 3;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 7;
 }
 def : InstRW<[Zn4WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
 
 def Zn4WriteRotateRightMCL : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateRightRCL.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn4WriteRotateRightRCL.NumMicroOps, 2);
 }
 def : InstRW<[Zn4WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
 
 def Zn4WriteRotateLeftRCL : SchedWriteRes<[Zn4ALU12]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 9;
 }
 def : InstRW<[Zn4WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
 
 def Zn4WriteRotateLeftMCL : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateLeftRCL.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn4WriteRotateLeftRCL.NumMicroOps, 2);
 }
 def : InstRW<[Zn4WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
 
 // Double shift instructions.
 defm : Zn4WriteResInt<WriteSHDrri, [Zn4ALU12], 2, [3], 4>;
 defm : Zn4WriteResInt<WriteSHDrrcl, [Zn4ALU12], 2, [3], 5>;
 defm : Zn4WriteResInt<WriteSHDmri, [Zn4AGU012, Zn4Load, Zn4ALU12], !add(Znver4Model.LoadLatency, 2), [1, 1, 4], 6>;

 defm : Zn4WriteResXMM<WriteFLoadX, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResYMM<WriteFLoadY, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteFMaskedLoad, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResYMM<WriteFMaskedLoadY, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteFStore, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 
 def Zn4WriteWriteFStoreMMX : SchedWriteRes<[Zn4FPSt, Zn4Store]> {
   let Latency = 2; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteWriteFStoreMMX], (instrs MOVHPDmr,  MOVHPSmr,
                                                VMOVHPDmr, VMOVHPSmr)>;
 
 defm : Zn4WriteResXMM<WriteFStoreX, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResYMM<WriteFStoreY, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteFStoreNT, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteFStoreNTX, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResYMM<WriteFStoreNTY, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 
 defm : Zn4WriteResXMM<WriteFMaskedStore32, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [6, 1], 18>;
 defm : Zn4WriteResXMM<WriteFMaskedStore64, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [4, 1], 10>;
 defm : Zn4WriteResYMM<WriteFMaskedStore32Y, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [12, 1], 42>;
 defm : Zn4WriteResYMM<WriteFMaskedStore64Y, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [6, 1], 18>;
 
 defm : Zn4WriteResXMMPair<WriteFAdd, [Zn4FPFAdd01], 3, [1], 1>;  // Floating point add/sub.
 
 def Zn4WriteX87Arith : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 24];
+  let ReleaseAtCycles = [1, 1, 24];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
                                          SUB_FI16m, SUB_FI32m,
                                          SUBR_FI16m, SUBR_FI32m,
                                          MUL_FI16m, MUL_FI32m)>;
 
 def Zn4WriteX87Div : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1, 1, 62];
+  let ReleaseAtCycles = [1, 1, 62];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
                                        DIVR_FI16m, DIVR_FI32m)>;
 
 defm : Zn4WriteResXMMPair<WriteFAddX, [Zn4FPFAdd01], 3, [1], 1>; // Floating point add/sub (XMM).
 defm : Zn4WriteResYMMPair<WriteFAddY, [Zn4FPFAdd01], 3, [1], 1>; // Floating point add/sub (YMM).
 defm : Zn4WriteResZMMPair<WriteFAddZ, [Zn4FPFAdd01], 3, [2], 1>; // Floating point add/sub (ZMM).

 defm : Zn4WriteResYMM<WriteVecLoadNTY, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteVecMaskedLoad, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResYMM<WriteVecMaskedLoadY, [Zn4FPLd01, Zn4Load], !add(Znver4Model.VecLoadLatency, 1), [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteVecStore, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteVecStoreX, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 
 def Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn4FPFMisc0]> {
   let Latency = 4;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
 
 def Zn4WriteVEXTRACTI128mr : SchedWriteRes<[Zn4FPFMisc0, Zn4FPSt, Zn4Store]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
-  let ResourceCycles = [1, 1, 1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = !add(Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
 }
 def : InstRW<[Zn4WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
 
 def Zn4WriteVINSERTF128rmr : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPFMisc0]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
-  let ResourceCycles = [1, 1, 1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = !add(Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn4WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
 
 defm : Zn4WriteResYMM<WriteVecStoreY, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteVecStoreNT, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResYMM<WriteVecStoreNTY, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [1, 1], 1>;
 defm : Zn4WriteResXMM<WriteVecMaskedStore32, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [6, 1], 18>;
 defm : Zn4WriteResXMM<WriteVecMaskedStore64, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [4, 1], 10>;
 defm : Zn4WriteResYMM<WriteVecMaskedStore32Y, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [12, 1], 42>;
 defm : Zn4WriteResYMM<WriteVecMaskedStore64Y, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency, [6, 1], 18>;
 
 defm : Zn4WriteResXMM<WriteVecMoveToGpr, [Zn4FPLd01], 1, [2], 1>;
 defm : Zn4WriteResXMM<WriteVecMoveFromGpr, [Zn4FPLd01], 1, [2], 1>;
 
 def Zn4WriteMOVMMX : SchedWriteRes<[Zn4FPLd01, Zn4FPFMisc0123]> {
   let Latency = 1;
-  let ResourceCycles = [1, 2];
+  let ReleaseAtCycles = [1, 2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
 
 def Zn4WriteMOVMMXSlow : SchedWriteRes<[Zn4FPLd01, Zn4FPFMisc0123]> {
   let Latency = 1;
-  let ResourceCycles = [1, 4];
+  let ReleaseAtCycles = [1, 4];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
 
 defm : Zn4WriteResXMMPair<WriteVecALU, [Zn4FPVAdd0123], 1, [1], 1>;  // Vector integer ALU op, no logicals.
 
 def Zn4WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn4FPVShuf01, Zn4FPLd01]> {
   let Latency = 3;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
 
 def Zn4WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn4FPVShuf01, Zn4FPLd01]> {
   let Latency = 3;
-  let ResourceCycles = [1, 1];
+  let ReleaseAtCycles = [1, 1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
 
 defm : Zn4WriteResXMMPair<WriteVecALUX, [Zn4FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (XMM).
 
 def Zn4WriteVecALUXSlow : SchedWriteRes<[Zn4FPVAdd01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
                                             PADDSBrr, PADDSWrr, PADDUSBrr, PADDUSWrr,
                                             PAVGBrr, PAVGWrr,
                                             PSIGNBrr, PSIGNDrr, PSIGNWrr,
                                             VPABSBrr, VPABSDrr, VPABSWrr,
                                             VPADDSBrr, VPADDSWrr, VPADDUSBrr, VPADDUSWrr,
                                             VPAVGBrr, VPAVGWrr,
                                             VPCMPEQQrr,
                                             VPSIGNBrr, VPSIGNDrr, VPSIGNWrr,
                                             PSUBSBrr, PSUBSWrr, PSUBUSBrr, PSUBUSWrr, VPSUBSBrr, VPSUBSWrr, VPSUBUSBrr, VPSUBUSWrr)>;
 
 def Zn4WriteVecOpMask : SchedWriteRes<[Zn4FPOpMask01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVecOpMask], (instrs   KADDBrr, KADDDrr, KADDQrr, KADDWrr,
                                             KANDBrr, KANDDrr, KANDQrr, KANDWrr,
                                             KANDNBrr, KANDNDrr, KANDNQrr, KANDNWrr,
                                             KMOVBkk, KMOVDkk, KMOVQkk, KMOVWkk,
                                             KMOVBrk, KMOVDrk, KMOVQrk, KMOVWrk,
                                             KNOTBrr, KNOTDrr, KNOTQrr, KNOTWrr,
                                             KORBrr, KORDrr, KORQrr, KORWrr,
                                             KORTESTBrr, KORTESTDrr, KORTESTQrr, KORTESTWrr,
                                             KTESTBrr, KTESTDrr, KTESTQrr, KTESTWrr,
                                             KUNPCKBWrr, KUNPCKDQrr, KUNPCKWDrr,
                                             KXNORBrr, KXNORDrr, KXNORQrr, KXNORWrr,
                                             KXORBrr, KXORDrr, KXORQrr, KXORWrr)>;
 
 def Zn4WriteVecOpMaskMemMov : SchedWriteRes<[Zn4FPOpMask4]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVecOpMaskMemMov], (instrs KMOVBmk, KMOVDmk, KMOVQmk, KMOVWmk)>;
 
 def Zn4WriteVecOpMaskKRMov : SchedWriteRes<[Zn4FPOpMask4]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVecOpMaskKRMov], (instrs KMOVBkr, KMOVDkr, KMOVQkr, KMOVWkr)>;
 
 def Zn4WriteVecALU2Slow : SchedWriteRes<[Zn4FPVAdd12]> {
   // TODO: All align instructions are expected to be of 4 cycle latency
   let Latency = 4;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVecALU2Slow], (instrs VALIGNDZrri, VALIGNDZ128rri, VALIGNDZ256rri,
                                             VALIGNQZrri, VALIGNQZ128rri, VALIGNQZ256rri)
                                             >;
 defm : Zn4WriteResYMMPair<WriteVecALUY, [Zn4FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (YMM).
 
 def Zn4WriteVecALUYSlow : SchedWriteRes<[Zn4FPVAdd01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
                                             VPADDSBYrr, VPADDSWYrr, VPADDUSBYrr, VPADDUSWYrr,
                                             VPSUBSBYrr, VPSUBSWYrr, VPSUBUSBYrr, VPSUBUSWYrr,
                                             VPAVGBYrr, VPAVGWYrr,
                                             VPCMPEQQYrr,
                                             VPSIGNBYrr, VPSIGNDYrr, VPSIGNWYrr)>;

 // Conversion between integer and float.
 defm : Zn4WriteResXMMPair<WriteCvtSD2I, [Zn4FPFCvt01], 1, [1], 1>;  // Double -> Integer.
 defm : Zn4WriteResXMMPair<WriteCvtPD2I, [Zn4FPFCvt01], 3, [2], 1>; // Double -> Integer (XMM).
 defm : Zn4WriteResYMMPair<WriteCvtPD2IY, [Zn4FPFCvt01], 3, [2], 2>; // Double -> Integer (YMM).
 defm : Zn4WriteResZMMPair<WriteCvtPD2IZ, [Zn4FPFCvt01], 3, [4], 2>; // Double -> Integer (ZMM).
 
 def Zn4WriteCvtPD2IMMX : SchedWriteRes<[Zn4FPFCvt01]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 defm : Zn4WriteResXMMPair<WriteCvtSS2I, [Zn4FPFCvt01], 5, [5], 2>;  // Float -> Integer.
 
 defm : Zn4WriteResXMMPair<WriteCvtPS2I, [Zn4FPFCvt01], 3, [1], 1>; // Float -> Integer (XMM).
 defm : Zn4WriteResYMMPair<WriteCvtPS2IY, [Zn4FPFCvt01], 4, [1], 1>; // Float -> Integer (YMM).
 defm : Zn4WriteResZMMPair<WriteCvtPS2IZ, [Zn4FPFCvt01], 4, [2], 2>; // Float -> Integer (ZMM).
 
 defm : Zn4WriteResXMMPair<WriteCvtI2SD, [Zn4FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>;  // Integer -> Double.
 defm : Zn4WriteResXMMPair<WriteCvtI2PD, [Zn4FPFCvt01], 3, [1], 1>; // Integer -> Double (XMM).
 defm : Zn4WriteResYMMPair<WriteCvtI2PDY, [Zn4FPFCvt01], 3, [2], 2, /*LoadUOps=*/-1>; // Integer -> Double (YMM).
 defm : Zn4WriteResZMMPair<WriteCvtI2PDZ, [Zn4FPFCvt01], 4, [4], 4, /*LoadUOps=*/-1>; // Integer -> Double (ZMM).
 
 def Zn4WriteCvtI2PDMMX : SchedWriteRes<[Zn4FPFCvt01]> {
   let Latency = 2;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 2;
 }
 
 defm : Zn4WriteResXMMPair<WriteCvtI2SS, [Zn4FPFCvt01], 3, [2], 2, /*LoadUOps=*/-1>;  // Integer -> Float.
 defm : Zn4WriteResXMMPair<WriteCvtI2PS, [Zn4FPFCvt01], 3, [1], 1>; // Integer -> Float (XMM).
 defm : Zn4WriteResYMMPair<WriteCvtI2PSY, [Zn4FPFCvt01], 3, [1], 1>; // Integer -> Float (YMM).
 defm : Zn4WriteResZMMPair<WriteCvtI2PSZ, [Zn4FPFCvt01], 3, [2], 2>; // Integer -> Float (ZMM).
 
 def Zn4WriteCvtI2PSMMX : SchedWriteRes<[Zn4FPFCvt01]> {
   let Latency = 3;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 
 defm : Zn4WriteResXMMPair<WriteCvtSS2SD, [Zn4FPFCvt01], 3, [1], 1>;  // Float -> Double size conversion.
 defm : Zn4WriteResXMMPair<WriteCvtPS2PD, [Zn4FPFCvt01], 3, [1], 1>; // Float -> Double size conversion (XMM).
 defm : Zn4WriteResYMMPair<WriteCvtPS2PDY, [Zn4FPFCvt01], 4, [2], 2, /*LoadUOps=*/-1>; // Float -> Double size conversion (YMM).
 defm : Zn4WriteResZMMPair<WriteCvtPS2PDZ, [Zn4FPFCvt01], 6, [4], 4, /*LoadUOps=*/-1>; // Float -> Double size conversion (ZMM).
 

 defm : Zn4WriteResYMM<WriteCvtPS2PHYSt, [Zn4FPFCvt01, Zn4FPSt, Zn4Store], !add(6, Znver4Model.StoreLatency), [2, 1, 1], 3>; // Float -> Half + store size conversion (YMM).
 defm : Zn4WriteResYMM<WriteCvtPS2PHZSt, [Zn4FPFCvt01, Zn4FPSt, Zn4Store], !add(6, Znver4Model.StoreLatency), [2, 1, 1], 3>; // Float -> Half + store size conversion (ZMM).
 
 // CRC32 instruction.
 defm : Zn4WriteResIntPair<WriteCRC32, [Zn4ALU1], 3, [1], 1>;
 
 def Zn4WriteSHA1MSG1rr : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
 
 def Zn4WriteSHA1MSG1rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA1MSG1rr.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn4WriteSHA1MSG1rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn4WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
 
 def Zn4WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 1;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
 
 def Zn4Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn4WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
 }
 def : InstRW<[Zn4Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
 
 def Zn4WriteSHA256MSG1rr : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 2;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
 
 def Zn4Writerm_SHA256MSG1rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA256MSG1rr.Latency);
-  let ResourceCycles = [1, 1, 3];
+  let ReleaseAtCycles = [1, 1, 3];
   let NumMicroOps = !add(Zn4WriteSHA256MSG1rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn4Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
 
 def Zn4WriteSHA256MSG2rr : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 3;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 4;
 }
 def : InstRW<[Zn4WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
 
 def Zn4WriteSHA256MSG2rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA256MSG2rr.Latency);
-  let ResourceCycles = [1, 1, 8];
+  let ReleaseAtCycles = [1, 1, 8];
   let NumMicroOps = !add(Zn4WriteSHA256MSG2rr.NumMicroOps, 1);
 }
 def : InstRW<[Zn4WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
 
 def Zn4WriteSHA1RNDS4rri : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 6;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
 
 def Zn4WriteSHA256RNDS2rr : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 4;
-  let ResourceCycles = [8];
+  let ReleaseAtCycles = [8];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
 
 // Strings instructions.
 // Packed Compare Implicit Length Strings, Return Mask
 defm : Zn4WriteResXMMPair<WritePCmpIStrM, [Zn4FPVAdd0123], 6, [8], 3, /*LoadUOps=*/1>;
 // Packed Compare Explicit Length Strings, Return Mask

 defm : Zn4WriteResInt<WriteLDMXCSR, [Zn4AGU012, Zn4Load, Zn4ALU0123], !add(Znver4Model.LoadLatency, 1), [1, 1, 6], 1>; // FIXME: latency not from llvm-exegesis
 defm : Zn4WriteResInt<WriteSTMXCSR, [Zn4ALU0123, Zn4AGU012, Zn4Store], !add(1, Znver4Model.StoreLatency), [60, 1, 1], 2>; // FIXME: latency not from llvm-exegesis
 
 // Catch-all for expensive system instructions.
 defm : Zn4WriteResInt<WriteSystem, [Zn4ALU0123], 100, [100], 100>;
 
 def Zn4WriteVZEROUPPER : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 0; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVZEROUPPER], (instrs VZEROUPPER)>;
 
 def Zn4WriteVZEROALL : SchedWriteRes<[Zn4FPU0123]> {
   let Latency = 10; // FIXME: not from llvm-exegesis
-  let ResourceCycles = [24];
+  let ReleaseAtCycles = [24];
   let NumMicroOps = 18;
 }
 def : InstRW<[Zn4WriteVZEROALL], (instrs VZEROALL)>;
 
 // AVX2.
 defm : Zn4WriteResYMMPair<WriteFShuffle256, [Zn4FPVShuf], 2, [1], 1, /*LoadUOps=*/2>; // Fp 256-bit width vector shuffles.
 defm : Zn4WriteResYMMPair<WriteFVarShuffle256, [Zn4FPVShuf], 7, [1], 2, /*LoadUOps=*/1>; // Fp 256-bit width variable shuffles.
 defm : Zn4WriteResYMMPair<WriteShuffle256, [Zn4FPVShuf], 1, [1], 1>; // 256-bit width vector shuffles.
 
 def Zn4WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn4FPVShuf]> {
   let Latency = 3;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
 
 def Zn4WriteVPERM2F128rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERM2I128rr_VPERM2F128rr.Latency);
-  let ResourceCycles = [1, 1, 1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = !add(Zn4WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
 }
 def : InstRW<[Zn4WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
 
 def Zn4WriteVPERMPSYrr : SchedWriteRes<[Zn4FPVShuf]> {
   let Latency = 7;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteVPERMPSYrr], (instrs VPERMPSYrr)>;
 
 def Zn4WriteVPERMPSYrm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMPSYrr.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn4WriteVPERMPSYrr.NumMicroOps, 1);
 }
 def : InstRW<[Zn4WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
 
 def Zn4WriteVPERMYri : SchedWriteRes<[Zn4FPVShuf]> {
   let Latency = 6;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
 
 def Zn4WriteVPERMPDYmi : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMYri.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn4WriteVPERMYri.NumMicroOps, 1);
 }
 def : InstRW<[Zn4WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
 
 def Zn4WriteVPERMDYrr : SchedWriteRes<[Zn4FPVShuf]> {
   let Latency = 5;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteVPERMDYrr], (instrs VPERMDYrr)>;
 
 def Zn4WriteVPERMYm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
   let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMDYrr.Latency);
-  let ResourceCycles = [1, 1, 2];
+  let ReleaseAtCycles = [1, 1, 2];
   let NumMicroOps = !add(Zn4WriteVPERMDYrr.NumMicroOps, 0);
 }
 def : InstRW<[Zn4WriteVPERMYm], (instrs VPERMQYmi, VPERMDYrm)>;
 
 defm : Zn4WriteResYMMPair<WriteVPMOV256, [Zn4FPVShuf01], 4, [3], 2, /*LoadUOps=*/-1>; // 256-bit width packed vector width-changing move.
 defm : Zn4WriteResYMMPair<WriteVarShuffle256, [Zn4FPVShuf01], 1, [1], 2>; // 256-bit width vector variable shuffles.
 defm : Zn4WriteResXMMPair<WriteVarVecShift, [Zn4FPVShift01], 1, [1], 1>; // Variable vector shifts.
 defm : Zn4WriteResYMMPair<WriteVarVecShiftY, [Zn4FPVShift01], 1, [1], 1>; // Variable vector shifts (YMM).
 defm : Zn4WriteResZMMPair<WriteVarVecShiftZ, [Zn4FPVShift01], 1, [2], 2>; // Variable vector shifts (ZMM).
 
 // Old microcoded instructions that nobody use.
 defm : Zn4WriteResInt<WriteMicrocoded, [Zn4ALU0123], 100, [100], 100>;
 
 // Fence instructions.
 defm : Zn4WriteResInt<WriteFence, [Zn4ALU0123], 1, [100], 1>;
 
 def Zn4WriteLFENCE : SchedWriteRes<[Zn4LSU]> {
   let Latency = 1;
-  let ResourceCycles = [30];
+  let ReleaseAtCycles = [30];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteLFENCE], (instrs LFENCE)>;
 
 def Zn4WriteSFENCE : SchedWriteRes<[Zn4LSU]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteSFENCE], (instrs SFENCE)>;
 
 // Nop, not very useful expect it provides a model for nops!
 defm : Zn4WriteResInt<WriteNop, [Zn4ALU0123], 0, [1], 1>; // FIXME: latency not from llvm-exegesis
 
 
 ///////////////////////////////////////////////////////////////////////////////
 // Zero Cycle Move
 ///////////////////////////////////////////////////////////////////////////////
 
 def Zn4WriteZeroLatency : SchedWriteRes<[]> {
   let Latency = 0;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
                                                MOV64rr, MOV64rr_REV,
                                                MOVSX32rr32)>;
 
 def Zn4WriteSwapRenameable : SchedWriteRes<[]> {
   let Latency = 0;
-  let ResourceCycles = [];
+  let ReleaseAtCycles = [];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
                                                XCHG64rr, XCHG64ar)>;
 
 defm : Zn4WriteResInt<WriteXCHG, [Zn4ALU0123], 0, [8], 2>;        // Compare+Exchange - TODO RMW support.
 
 defm : Zn4WriteResXMM<WriteFMoveX, [], 0, [], 1>;
InstructionEquivalenceClass<[
     VMOVDQAYrr, VMOVDQAYrr_REV,
     VMOVDQUYrr, VMOVDQUYrr_REV,
   ], TruePred >
 ]>;
 
 // FIXUP and RANGE Instructions
 def Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr : SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr], (instregex
   "VFIXUPIMM(S|P)(S|D)(Z|Z128|Z256?)rrik", "VFIXUPIMM(S|P)(S|D)(Z?|Z128?|Z256?)rrikz", 
         "VFIXUPIMM(S|P)(S|D)(Z128|Z256?)rri",  "VRANGE(S|P)(S|D)(Z?|Z128?|Z256?)rri(b?)",
   "VRANGE(S|P)(S|D)(Z|Z128|Z256?)rri(b?)k","VRANGE(S|P)(S|D)(Z?|Z128?|Z256?)rri(b?)kz"
   )>;
 
 // SCALE & REDUCE instructions
 def Zn4WriteSCALErr: SchedWriteRes<[Zn4FPFMisc23]> {
   let Latency = 6;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteSCALErr], (instregex
         "V(SCALEF|REDUCE)(S|P)(S|D)(Z?|Z128?|Z256?)(rr|rrb|rrkz|rrik|rrikz|rri)(_Int?|_Intkz?)",
         "(V?)REDUCE(PD|PS|SD|SS)(Z?|Z128?)(rri|rrikz|rrib)"
   )>;
 
 //BF16PS Instructions
 def Zn4WriteBF16: SchedWriteRes<[Zn4FPFMisc23]> {
   let Latency = 6;
-  let ResourceCycles = [6];
+  let ReleaseAtCycles = [6];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn4WriteBF16], (instregex
         "(V?)DPBF16PS(Z?|Z128?|Z256?)(r|rk|rkz)"
   )>;
 
 // BUSD and VPMADD Instructions
 def Zn4WriteBUSDr_VPMADDr: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteBUSDr_VPMADDr], (instregex
   "VPDP(BU|WS)(S|P)(S|D|DS)(Z|Z128|Z256)(r|rk|rkz)",
         "VPMADD52(H|L)UQ(Z|Z128|Z256)(r|rk|rkz)"
   )>;
 
 // SHIFT instructions
 def Zn4WriteSHIFTrr: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteSHIFTrr], (instregex
         "VP(LZCNT|SHLD|SHRD?)(D|Q|W|VD|VQ|VW?)(Z?|Z128?|Z256?)(rr|rk|rrk|rrkz|rri|rrik|rrikz)",
         "(V?)P(SLL|SRL|SRA)(D|Q|W|DQ)(Y?|Z?|Z128?|Z256?)(rr|rrk|rrkz)",
         "(V?)P(SLL|SRL|SRA)DQYri",
         "(V?)P(SLL|SRL)DQ(Z?|Z256?)ri",
         "(V?)P(SHUFB)(Y|Z|Z128|Z256?)(rr|rrk|rrkz)",
         "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z?|Z128?|Z256?)(rr|rrk|rrkz)",
         "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z256?)(ri|rik|rikz)",
         "(V?)P(ROL|ROR)(D|Q)(Z?|Z128?)(ri|rik|rikz)",
   "VPSHUFBITQMBZ128rr", "VFMSUB231SSZr_Intkz"
   )>;
 
 def Zn4WriteSHIFTri: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 1;
-  let ResourceCycles = [1];
+  let ReleaseAtCycles = [1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteSHIFTri], (instregex
         "VP(SLL|SRL|SRA)(D|Q|W)(Z|Z128|Z256?)(ri|rik|rikz)"
   )>;
 
 // ALIGN Instructions
 def Zn4WriteALIGN: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteALIGN], (instregex
         "(V?)PALIGNR(Z?|Z128?|Z256?)(rri|rrik|rrikz)"
   )>;
 
 //PACK Instructions
 def Zn4WritePACK: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WritePACK], (instregex
         "(V?)PACK(SS|US)(DW|WB)(Z?|Z128?|Z256?)(rr|rrk|rrkz)"
   )>;
 
 // MAX and MIN Instructions
 def Zn4WriteFCmp64: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteFCmp64], (instregex
         "(V?)CMP(S|P)(S|D)(rr|rri|rr_Int)",
         "(V?|VP?)(MAX|MIN|MINC|MAXC)(S|P|U)(S|D|Q)(Z?|Z128?|Z256?)(rr|rri|rrk|rrkz)(_Int?)",
         "VP(MAX|MIN)(SQ|UQ)(Z|Z128|Z256)(rr|rrk|rrkz)",
         "(V?)(MAX|MAXC|MIN|MINC)PD(Z|Z128|Z256?)(rr|rrk|rrkz)"
   )>;
 
 // MOV Instructions
 def Zn4MOVS: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4MOVS], (instregex
         "(V?)PMOV(SX|ZX)(BD|BQ|BW|WD|WQ|DQ)(Z128?|Z256?)(rr|rrk|rrkz)",
         "(V?)PMOV(SX|QD|UZ|ZX)(BD|BQ|BW?)(Y|Z128?)(rr|rrk|rrkz)",
         "(V?)PMOV(SX|US|ZX)(DQ|WD|QW|WQ?)(Y|Z128?)(rr|rrk|rrkz)",
         "(V?)VMOVDDUP(Z|Z128|Z256)(rr|rrk|rrkz)",
         "VPMOV(DB|DW|QB|QD|QW|SDB|SDW|SQB|SQD|SQW|SWB|USDB|USDW|USQB|USQD|USWB|WB)(Z128?)(rr|rrk|rrkz)"
   )>;
 
 def Zn4MOVSZ: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4MOVSZ], (instregex
         "(V?)PMOV(SX|ZX)(BD|BQ|BW|WD|WQ|DQ)(Z?)(rr|rrk|rrkz)"
   )>;
 
 def Zn4MOVSrr: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 5;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4MOVSrr], (instregex
         "(V?)PMOV(DB|QB|QW|SDB|SQB|SQW|USDB|USQB|USQW)(Z?)(rr|rrk|rrkz)"
   )>;
 
 
 //VPTEST Instructions
 def Zn4VPTESTZ128: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 3;
-  let ResourceCycles = [3];
+  let ReleaseAtCycles = [3];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4VPTESTZ128], (instregex
         "(V?)PTEST(N?)(MB|MD|MQ|MW)(Z128?)(rrk)"
   )>;
 
 def Zn4VPTESTZ256: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 4;
-  let ResourceCycles = [4];
+  let ReleaseAtCycles = [4];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4VPTESTZ256], (instregex
         "(V?)PTEST(N?)(MB|MD|MQ|MW)(Z256?)(rr|rrk)"
   )>;
 
 def Zn4VPTESTZ: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 5;
-  let ResourceCycles = [5];
+  let ReleaseAtCycles = [5];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4VPTESTZ], (instregex
         "(V?)PTEST(N?)(MB|MD|MQ|MW)(Z?)(rrk)"
   )>;
 
 // CONFLICT Instructions
 def Zn4CONFLICTZ128: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4CONFLICTZ128], (instregex
         "VPCONFLICT(D|Q)(Z128)(rr|rrk|rrkz)"
   )>;
 
 def Zn4CONFLICTrr: SchedWriteRes<[Zn4FPFMisc01,Zn4FPFMisc12,Zn4FPFMisc23]> {
   let Latency = 6;
-  let ResourceCycles = [2,2,2];
+  let ReleaseAtCycles = [2,2,2];
   let NumMicroOps = 4;
 }
 def : InstRW<[Zn4CONFLICTrr], (instregex
         "VPCONFLICT(D|Q)(Z|Z256)(rr|rrkz)"
   )>;
 
 // RSQRT Instructions
 def Zn4VRSQRT14PDZ256: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 5;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4VRSQRT14PDZ256], (instregex
         "VRSQRT14(PD|PS)(Z?|Z128?|Z256?)(r|rr|rk|rrk|rkz|rrkz)"
   )>;
 
 
 // PERM Instructions
 def Zn4PERMILP: SchedWriteRes<[Zn4FPFMisc123]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4PERMILP], (instregex
         "VPERMILP(S|D)(Y|Z|Z128|Z256)(rr|rrk|rrkz)"
   )>;
 
 def Zn4PERMIT2_128: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 3;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4PERMIT2_128], (instregex
         "VPERM(I2|T2)(PS|PD|W)128(rr|rrk|rrkz)",
         "VPERM(I2|T2)(B|D|Q)128(rr|rrk|rrkz)"
   )>;
 
 def Zn4PERMIT2_128rr:SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4PERMIT2_128rr], (instregex
   "V(P?)COMPRESS(B|W|D|Q|PD|PS|SD|SQ)Z128(rr|rrk|rrkz)",
   "VPERM(B|D|Q|W)(Z128?)(rr|rrk|rrkz)"
   )>;
 
 def Zn4PERMIT2_256: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 4;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4PERMIT2_256], (instregex
         "VPERM(I2|T2)(PS|PD|W)256(rr|rrk|rrkz)",
   "VPERMP(S|D)Z256(rr|rrk|rrkz)",
   "V(P?)COMPRESS(B|W|D|Q|PD|PS|SD|SQ)Z256(rr|rrk|rrkz)",
   "VPERM(B|D|Q|W)Z256(rr|rrk|rrkz)",
   "VPERM(I2|Q|T2)(B|D|Q)(Z?)256(rr|rrk|rrkz)",
   "VPEXPAND(B|W)Z256(rr|rrk|rrkz)"
   )>;
 
 def Zn4PERMIT2Z: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 5;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4PERMIT2Z], (instregex
         "VPERM(I2|T2)(PS|PD|W)(rr|rrk|rrkz)",
   "VPERM(B|D|W)Z(rr|rrk|rrkz)",
   "VPERM(I2|Q|T2)(B|D|Q)(Z?)(rr|rrk|rrkz)",
   "V(P?)COMPRESS(B|W|D|Q|PD|PS|SD|SQ)Z(rr|rrk|rrkz)",
   "VPEXPAND(B|W)Z(rr|rrk|rrkz)",
         "VPERMP(S|D)Z(rr|rrk|rrkz)"
   )>;
 
 // ALU SLOW Misc Instructions
 def Zn4VecALUZSlow: SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 2;
-  let ResourceCycles = [2];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4VecALUZSlow], (instrs 
   VPABSBZ128rr,      VPABSBZ128rrk,  VPABSBZ128rrkz,   VPABSDZ128rr, 
   VPABSDZ128rrk,     VPABSDZ128rrkz, VPABSQZ128rr,     VPABSQZ128rrk, 
   VPABSQZ128rrkz,    VPABSWZ128rr,   VPABSWZ128rrk,    VPABSWZ128rrkz, 
   VPADDSBZ128rr,     VPADDSBZ128rrk, VPADDSBZ128rrkz,  VPADDSWZ128rr, 
   VPADDSWZ128rrk,    VPADDSWZ128rrkz,VPADDUSBZ128rr,   VPADDUSBZ128rrk, 

llvm/test/TableGen/AcquireAtCycle.td

 // RUN: llvm-tblgen -gen-subtarget -DCORRECT -I %p/../../include %s 2>&1 | \
 // RUN:   FileCheck %s  --check-prefix=CORRECT
 
 // RUN: not llvm-tblgen -gen-subtarget -DWRONG_SIZE -I %p/../../include %s 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=WRONG_SIZE
 
 // RUN: not llvm-tblgen -gen-subtarget -DWRONG_VALUE -I %p/../../include %s 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=WRONG_VALUE
 
 // RUN: not llvm-tblgen -gen-subtarget -DNEGATIVE_INVALID -I %p/../../include %s 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=NEGATIVE_INVALID
 
-// Make sure that StartAtCycle in WriteRes is used to generate the
+// Make sure that AcquireAtCycle in WriteRes is used to generate the
 // correct data.
 
 include "llvm/Target/Target.td"
 
 def MyTarget : Target;
 
 let BufferSize = 0 in {
 def ResX0 : ProcResource<1>; // X0

 // Check the generated data when there are no semantic issues.
 #ifdef CORRECT
 // CORRECT-LABEL: llvm::MCWriteProcResEntry MyTargetWriteProcResTable[] = {
 // CORRECT-NEXT: { 0, 0, 0 }, // Invalid
 def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
 // CORRECT-NEXT: { 1, 2, 0}, // #1
 // CORRECT-NEXT: { 2, 4, 1}, // #2
 // CORRECT-NEXT: { 3, 3, 2}, // #3
-    let ResourceCycles = [2, 4, 3];
-    let StartAtCycles = [0, 1, 2];
+    let ReleaseAtCycles = [2, 4, 3];
+    let AcquireAtCycles = [0, 1, 2];
 }
 def : WriteRes<WriteInst_B, [ResX2]> {
-// If unspecified, StartAtCycle is set to 0.
+// If unspecified, AcquireAtCycle is set to 0.
 // CORRECT-NEXT: { 3, 1, 0} // #4
-    let ResourceCycles = [1];
+    let ReleaseAtCycles = [1];
 }
 #endif // CORRECT
 
 #ifdef WRONG_SIZE
-// WRONG_SIZE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(StartAtCycles) != size(ProcResources): 2 vs 3
+// WRONG_SIZE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(AcquireAtCycles) != size(ProcResources): 2 vs 3
 def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
-    let ResourceCycles = [2, 4, 3];
-    let StartAtCycles = [0, 1];
+    let ReleaseAtCycles = [2, 4, 3];
+    let AcquireAtCycles = [0, 1];
 }
 #endif
 
 #ifdef WRONG_VALUE
-// WRONG_VALUE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: StartAtCycles < Cycles must hold
+// WRONG_VALUE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: AcquireAtCycles < ReleaseAtCycles must hold
 def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
-    let ResourceCycles = [2, 4, 3];
-    let StartAtCycles = [0, 1, 8];
+    let ReleaseAtCycles = [2, 4, 3];
+    let AcquireAtCycles = [0, 1, 8];
 }
 #endif
 
 #ifdef NEGATIVE_INVALID
-// NEGATIVE_INVALID: StartAtCycle.td:[[@LINE+1]]:1: error: Invalid value: StartAtCycle must be a non-negative value.
+// NEGATIVE_INVALID: AcquireAtCycle.td:[[@LINE+1]]:1: error: Invalid value: AcquireAtCycle must be a non-negative value.
 def : WriteRes<WriteInst_A, [ResX0]> {
-    let ResourceCycles = [2];
-    let StartAtCycles = [-1];
+    let ReleaseAtCycles = [2];
+    let AcquireAtCycles = [-1];
 }
 #endif
 
 def : InstRW<[WriteInst_A], (instrs Inst_A)>;
 def : InstRW<[WriteInst_B], (instrs Inst_B)>;
 }
 
 def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
 

llvm/tools/llvm-exegesis/lib/Analysis.cpp

writeMeasurementValue<kEscapeHtml>(
         OS, MCSchedModel::getReciprocalThroughput(SI, *RSC.SCDesc));
     OS << "</td>";
     // WriteProcRes.
     OS << "<td><ul>";
     for (const auto &WPR : RSC.NonRedundantWriteProcRes) {
       OS << "<li><span class=\"mono\">";
       writeEscaped<kEscapeHtml>(OS,
                                 SM.getProcResource(WPR.ProcResourceIdx)->Name);
-      OS << "</span>: " << WPR.Cycles << "</li>";
+      OS << "</span>: " << WPR.ReleaseAtCycle << "</li>";
     }
     OS << "</ul></td>";
     // Idealized port pressure.
     OS << "<td><ul>";
     for (const auto &Pressure : RSC.IdealizedProcResPressure) {
       OS << "<li><span class=\"mono\">";
       writeEscaped<kEscapeHtml>(
           OS, SI.getSchedModel().getProcResource(Pressure.first)->Name);

llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp

sort(ResourceMaskAndEntries,
          return A.first < B.first;
        });
 
   SmallVector<float, 32> ProcResUnitUsage(NumProcRes);
   for (const ResourceMaskAndEntry &Entry : ResourceMaskAndEntries) {
     const MCWriteProcResEntry *WPR = Entry.second;
     const MCProcResourceDesc *const ProcResDesc =
         SM.getProcResource(WPR->ProcResourceIdx);
-    // TODO: Handle StartAtCycle in llvm-exegesis and llvm-mca. See
+    // TODO: Handle AcquireAtAtCycle in llvm-exegesis and llvm-mca. See
     // https://github.com/llvm/llvm-project/issues/62680 and
     // https://github.com/llvm/llvm-project/issues/62681
-    assert(WPR->StartAtCycle == 0 &&
-           "`llvm-exegesis` does not handle StartAtCycle > 0");
+    assert(WPR->AcquireAtCycle == 0 &&
+           "`llvm-exegesis` does not handle AcquireAtCycle > 0");
     if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
       // This is a ProcResUnit.
-      Result.push_back({WPR->ProcResourceIdx, WPR->Cycles, WPR->StartAtCycle});
-      ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles;
+      Result.push_back(
+          {WPR->ProcResourceIdx, WPR->ReleaseAtCycle, WPR->AcquireAtCycle});
+      ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->ReleaseAtCycle;
     } else {
       // This is a ProcResGroup. First see if it contributes any cycles or if
       // it has cycles just from subunits.
-      float RemainingCycles = WPR->Cycles;
+      float RemainingCycles = WPR->ReleaseAtCycle;
       for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
            SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
            ++SubResIdx) {
         RemainingCycles -= ProcResUnitUsage[*SubResIdx];
       }
       if (RemainingCycles < 0.01f) {
         // The ProcResGroup contributes no cycles of its own.
         continue;
       }
       // The ProcResGroup contributes `RemainingCycles` cycles of its own.
       Result.push_back({WPR->ProcResourceIdx,
                         static_cast<uint16_t>(std::round(RemainingCycles)),
-                        WPR->StartAtCycle});
+                        WPR->AcquireAtCycle});
       // Spread the remaining cycles over all subunits.
       for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
            SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
            ++SubResIdx) {
         ProcResUnitUsage[*SubResIdx] += RemainingCycles / ProcResDesc->NumUnits;
       }
     }
   }
sort(WPRS, [](const MCWriteProcResEntry &A, const MCWriteProcResEntry &B) {
     return A.ProcResourceIdx < B.ProcResourceIdx;
   });
   for (const MCWriteProcResEntry &WPR : WPRS) {
     // Get units for the entry.
     const MCProcResourceDesc *const ProcResDesc =
         SM.getProcResource(WPR.ProcResourceIdx);
     if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
       // This is a ProcResUnit.
-      DensePressure[WPR.ProcResourceIdx] += WPR.Cycles;
+      DensePressure[WPR.ProcResourceIdx] += WPR.ReleaseAtCycle;
     } else {
       // This is a ProcResGroup.
       SmallVector<uint16_t, 32> Subunits(ProcResDesc->SubUnitsIdxBegin,
                                          ProcResDesc->SubUnitsIdxBegin +
                                              ProcResDesc->NumUnits);
-      distributePressure(WPR.Cycles, Subunits, DensePressure);
+      distributePressure(WPR.ReleaseAtCycle, Subunits, DensePressure);
     }
   }
   // Turn dense pressure into sparse pressure by removing zero entries.
   std::vector<std::pair<uint16_t, float>> Pressure;
   for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
     if (DensePressure[I] > 0.0f)
       Pressure.emplace_back(I, DensePressure[I]);
   }

llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp

OS << "\nThroughput Bottlenecks: "
      << "\n  Resource Pressure       [ "
      << format("%.2f", floor((ResourcePressurePerCycle * 100) + 0.5) / 100)
      << "% ]";
 
   if (BPI.PressureIncreaseCycles) {
     ArrayRef<unsigned> Distribution = Tracker.getResourcePressureDistribution();
     const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
     for (unsigned I = 0, E = Distribution.size(); I < E; ++I) {
-      unsigned ResourceCycles = Distribution[I];
-      if (ResourceCycles) {
-        double Frequency = (double)ResourceCycles * 100 / TotalCycles;
+      unsigned ReleaseAtCycles = Distribution[I];
+      if (ReleaseAtCycles) {
+        double Frequency = (double)ReleaseAtCycles * 100 / TotalCycles;
         const MCProcResourceDesc &PRDesc = *SM.getProcResource(I);
         OS << "\n  - " << PRDesc.Name << "  [ "
            << format("%.2f", floor((Frequency * 100) + 0.5) / 100) << "% ]";
       }
     }
   }
 
   OS << "\n  Data Dependencies:      [ "

llvm/tools/llvm-mca/Views/ResourcePressureView.h

 class ResourcePressureView : public InstructionView {
   unsigned LastInstructionIdx;
 
   // Map to quickly obtain the ResourceUsage column index from a processor
   // resource ID.
   llvm::DenseMap<unsigned, unsigned> Resource2VecIndex;
 
   // Table of resources used by instructions.
-  std::vector<ResourceCycles> ResourceUsage;
+  std::vector<ReleaseAtCycles> ResourceUsage;
   unsigned NumResourceUnits;
 
   void printResourcePressurePerIter(llvm::raw_ostream &OS) const;
   void printResourcePressurePerInst(llvm::raw_ostream &OS) const;
 
 public:
   ResourcePressureView(const llvm::MCSubtargetInfo &sti,
                        llvm::MCInstPrinter &Printer,

llvm/tools/llvm-mca/Views/ResourcePressureView.cpp

void ResourcePressureView::onEvent(const HWInstructionEvent &Event) {
 
   // We're only interested in Issue events.
   if (Event.Type != HWInstructionEvent::Issued)
     return;
 
   const auto &IssueEvent = static_cast<const HWInstructionIssuedEvent &>(Event);
   ArrayRef<llvm::MCInst> Source = getSource();
   const unsigned SourceIdx = Event.IR.getSourceIndex() % Source.size();
-  for (const std::pair<ResourceRef, ResourceCycles> &Use :
+  for (const std::pair<ResourceRef, ReleaseAtCycles> &Use :
        IssueEvent.UsedResources) {
     const ResourceRef &RR = Use.first;
     assert(Resource2VecIndex.contains(RR.first));
     unsigned R2VIndex = Resource2VecIndex[RR.first];
     R2VIndex += llvm::countr_zero(RR.second);
     ResourceUsage[R2VIndex + NumResourceUnits * SourceIdx] += Use.second;
     ResourceUsage[R2VIndex + NumResourceUnits * Source.size()] += Use.second;
   }
json::Value ResourcePressureView::toJSON() const {
   // We're dumping the instructions and the ResourceUsage array.
   json::Array ResourcePressureInfo;
 
   // The ResourceUsage matrix is sparse, so we only consider
   // non-zero values.
   ArrayRef<llvm::MCInst> Source = getSource();
   const unsigned Executions = LastInstructionIdx / Source.size() + 1;
   for (const auto &R : enumerate(ResourceUsage)) {
-    const ResourceCycles &RU = R.value();
+    const ReleaseAtCycles &RU = R.value();
     if (RU.getNumerator() == 0)
       continue;
     unsigned InstructionIndex = R.index() / NumResourceUnits;
     unsigned ResourceIndex = R.index() % NumResourceUnits;
     double Usage = RU / Executions;
     ResourcePressureInfo.push_back(
         json::Object({{"InstructionIndex", InstructionIndex},
                       {"ResourceIndex", ResourceIndex},
                       {"ResourceUsage", Usage}}));
   }
 
   json::Object JO({{"ResourcePressureInfo", std::move(ResourcePressureInfo)}});
   return JO;
 }
 } // namespace mca
 } // namespace llvm

llvm/utils/TableGen/SubtargetEmitter.cpp

class SubtargetEmitter {
   void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
                                      raw_ostream &OS);
   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
                               raw_ostream &OS);
   Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
                              const CodeGenProcModel &ProcModel);
   Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
                           const CodeGenProcModel &ProcModel);
-  void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
-                           std::vector<int64_t> &StartAtCycles,
+  void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
+                           std::vector<int64_t> &AcquireAtCycles,
                            const CodeGenProcModel &ProcModel);
   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
                            SchedClassTables &SchedTables);
   void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
   void EmitProcessorModels(raw_ostream &OS);
   void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
   void emitSchedModelHelpersImpl(raw_ostream &OS,
                                  bool OnlyExpandMCInstPredicates = false);
PrintFatalError(ProcModel.ModelDef->getLoc(),
                     Twine("Processor does not define resources for ") +
                     SchedRead.TheDef->getName());
   }
   return ResDef;
 }
 
 // Expand an explicit list of processor resources into a full list of implied
 // resource groups and super resources that cover them.
-void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
-                                           std::vector<int64_t> &Cycles,
-                                           std::vector<int64_t> &StartAtCycles,
-                                           const CodeGenProcModel &PM) {
-  assert(PRVec.size() == Cycles.size() && "failed precondition");
+void SubtargetEmitter::ExpandProcResources(
+    RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
+    std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {
+  assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");
   for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
     Record *PRDef = PRVec[i];
     RecVec SubResources;
     if (PRDef->isSubClassOf("ProcResGroup"))
       SubResources = PRDef->getValueAsListOfDefs("Resources");
     else {
       SubResources.push_back(PRDef);
       PRDef = SchedModels.findProcResUnits(PRDef, PM, PRDef->getLoc());
       for (Record *SubDef = PRDef;
            SubDef->getValueInit("Super")->isComplete();) {
         if (SubDef->isSubClassOf("ProcResGroup")) {
           // Disallow this for simplicitly.
           PrintFatalError(SubDef->getLoc(), "Processor resource group "
                           " cannot be a super resources.");
         }
         Record *SuperDef =
             SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM,
                                          SubDef->getLoc());
         PRVec.push_back(SuperDef);
-        Cycles.push_back(Cycles[i]);
-        StartAtCycles.push_back(StartAtCycles[i]);
+        ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
+        AcquireAtCycles.push_back(AcquireAtCycles[i]);
         SubDef = SuperDef;
       }
     }
     for (Record *PR : PM.ProcResourceDefs) {
       if (PR == PRDef || !PR->isSubClassOf("ProcResGroup"))
         continue;
       RecVec SuperResources = PR->getValueAsListOfDefs("Resources");
       RecIter SubI = SubResources.begin(), SubE = SubResources.end();
       for( ; SubI != SubE; ++SubI) {
         if (!is_contained(SuperResources, *SubI)) {
           break;
         }
       }
       if (SubI == SubE) {
         PRVec.push_back(PR);
-        Cycles.push_back(Cycles[i]);
-        StartAtCycles.push_back(StartAtCycles[i]);
+        ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
+        AcquireAtCycles.push_back(AcquireAtCycles[i]);
       }
     }
   }
 }
 
 // Generate the SchedClass table for this processor and update global
 // tables. Must be called for each processor in order.
 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
for (unsigned W : Writes) {
         SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
         SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
         SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue");
         SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue");
         SCDesc.RetireOOO |= WriteRes->getValueAsBit("RetireOOO");
 
         // Create an entry for each ProcResource listed in WriteRes.
         RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
-        std::vector<int64_t> Cycles =
-          WriteRes->getValueAsListOfInts("ResourceCycles");
+        std::vector<int64_t> ReleaseAtCycles =
+          WriteRes->getValueAsListOfInts("ReleaseAtCycles");
 
-        std::vector<int64_t> StartAtCycles =
-            WriteRes->getValueAsListOfInts("StartAtCycles");
+        std::vector<int64_t> AcquireAtCycles =
+            WriteRes->getValueAsListOfInts("AcquireAtCycles");
 
         // Check consistency of the two vectors carrying the start and
         // stop cycles of the resources.
-        if (!Cycles.empty() && Cycles.size() != PRVec.size()) {
-          // If ResourceCycles is provided, check consistency.
+        if (!ReleaseAtCycles.empty() &&
+            ReleaseAtCycles.size() != PRVec.size()) {
+          // If ReleaseAtCycles is provided, check consistency.
           PrintFatalError(
               WriteRes->getLoc(),
-              Twine("Inconsistent resource cycles: size(ResourceCycles) != "
+              Twine("Inconsistent release at cycles: size(ReleaseAtCycles) != "
                     "size(ProcResources): ")
                   .concat(Twine(PRVec.size()))
                   .concat(" vs ")
-                  .concat(Twine(Cycles.size())));
+                  .concat(Twine(ReleaseAtCycles.size())));
         }
 
-        if (!StartAtCycles.empty() && StartAtCycles.size() != PRVec.size()) {
+        if (!AcquireAtCycles.empty() && AcquireAtCycles.size() != PRVec.size()) {
           PrintFatalError(
               WriteRes->getLoc(),
-              Twine("Inconsistent resource cycles: size(StartAtCycles) != "
+              Twine("Inconsistent resource cycles: size(AcquireAtCycles) != "
                     "size(ProcResources): ")
-                  .concat(Twine(StartAtCycles.size()))
+                  .concat(Twine(AcquireAtCycles.size()))
                   .concat(" vs ")
                   .concat(Twine(PRVec.size())));
         }
 
-        if (Cycles.empty()) {
-          // If ResourceCycles is not provided, default to one cycle
+        if (ReleaseAtCycles.empty()) {
+          // If ReleaseAtCycles is not provided, default to one cycle
           // per resource.
-          Cycles.resize(PRVec.size(), 1);
+          ReleaseAtCycles.resize(PRVec.size(), 1);
         }
 
-        if (StartAtCycles.empty()) {
-          // If StartAtCycles is not provided, reserve the resource
+        if (AcquireAtCycles.empty()) {
+          // If AcquireAtCycles is not provided, reserve the resource
           // starting from cycle 0.
-          StartAtCycles.resize(PRVec.size(), 0);
+          AcquireAtCycles.resize(PRVec.size(), 0);
         }
 
-        assert(StartAtCycles.size() == Cycles.size());
+        assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
 
-        ExpandProcResources(PRVec, Cycles, StartAtCycles, ProcModel);
-        assert(StartAtCycles.size() == Cycles.size());
+        ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
+        assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
 
         for (unsigned PRIdx = 0, PREnd = PRVec.size();
              PRIdx != PREnd; ++PRIdx) {
           MCWriteProcResEntry WPREntry;
           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
           assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
-          WPREntry.Cycles = Cycles[PRIdx];
-          WPREntry.StartAtCycle = StartAtCycles[PRIdx];
-          if (StartAtCycles[PRIdx] > Cycles[PRIdx]) {
-            PrintFatalError(WriteRes->getLoc(),
-                            Twine("Inconsistent resource cycles: StartAtCycles "
-                                  "< Cycles must hold."));
+          WPREntry.ReleaseAtCycle = ReleaseAtCycles[PRIdx];
+          WPREntry.AcquireAtCycle = AcquireAtCycles[PRIdx];
+          if (AcquireAtCycles[PRIdx] > ReleaseAtCycles[PRIdx]) {
+            PrintFatalError(
+                WriteRes->getLoc(),
+                Twine("Inconsistent resource cycles: AcquireAtCycles "
+                      "< ReleaseAtCycles must hold."));
           }
-          if (StartAtCycles[PRIdx] < 0) {
+          if (AcquireAtCycles[PRIdx] < 0) {
             PrintFatalError(WriteRes->getLoc(),
-                            Twine("Invalid value: StartAtCycle "
+                            Twine("Invalid value: AcquireAtCycle "
                                   "must be a non-negative value."));
           }
           // If this resource is already used in this sequence, add the current
           // entry's cycles so that the same resource appears to be used
           // serially, rather than multiple parallel uses. This is important for
           // in-order machine where the resource consumption is a hazard.
           unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
           for( ; WPRIdx != WPREnd; ++WPRIdx) {
             if (WriteProcResources[WPRIdx].ProcResourceIdx
                 == WPREntry.ProcResourceIdx) {
               // TODO: multiple use of the same resources would
               // require either 1. thinking of how to handle multiple
               // intervals for the same resource in
               // `<Target>WriteProcResTable` (see
               // `SubtargetEmitter::EmitSchedClassTables`), or
               // 2. thinking how to merge multiple intervals into a
               // single interval.
-              assert(WPREntry.StartAtCycle == 0 &&
+              assert(WPREntry.AcquireAtCycle == 0 &&
                      "multiple use ofthe same resource is not yet handled");
-              WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
+              WriteProcResources[WPRIdx].ReleaseAtCycle +=
+                  WPREntry.ReleaseAtCycle;
               break;
             }
           }
           if (WPRIdx == WPREnd)
             WriteProcResources.push_back(WPREntry);
         }
       }
       WriteLatencies.push_back(WLEntry);
for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
     }
   }
 }
 
 // Emit SchedClass tables for all processors and associated global tables.
 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
                                             raw_ostream &OS) {
   // Emit global WriteProcResTable.
-  OS << "\n// {ProcResourceIdx, Cycles, StartAtCycle}\n"
+  OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
      << "extern const llvm::MCWriteProcResEntry " << Target
      << "WriteProcResTable[] = {\n"
      << "  { 0,  0,  0 }, // Invalid\n";
   for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
        WPRIdx != WPREnd; ++WPRIdx) {
     MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
     OS << "  {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
-       << format("%2d", WPREntry.Cycles) << ",  "
-       << format("%2d", WPREntry.StartAtCycle) << "}";
+       << format("%2d", WPREntry.ReleaseAtCycle) << ",  "
+       << format("%2d", WPREntry.AcquireAtCycle) << "}";
     if (WPRIdx + 1 < WPREnd)
       OS << ',';
     OS << " // #" << WPRIdx << '\n';
   }
   OS << "}; // " << Target << "WriteProcResTable\n";
 
   // Emit global WriteLatencyTable.
   OS << "\n// {Cycles, WriteResourceID}\n"