PseudoTail should be a software guarded branch in Ziciflp, since its branch
target is known in link time. JALR/C.JR/C.JALR with rs1 as t2 is termed a
software guarded branch. Such branches do not need to land on a lpad instruction.
|60,030 ms||x64 debian > MLIR.Examples/standalone::test.toy|
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#-a-listing-of-standard-risc-v-pseudoinstructions very clearly states that x6 is the register used. What's wrong with t1? x1 and x5 are special as the registers for microarchitectural push/pop hints and, with Zicfilp, repurposed for shadow stack push/pop (somewhat ew), but neither x6 nor x7 are mentioned in the CFI spec that I can see.
Software guarded branches changed to x6 here https://github.com/riscv/riscv-cfi/commit/aaea3077bc4256dd56b07403cd1b88ca46b83c27 but then changed back https://github.com/riscv/riscv-cfi/commit/afbc2d5544f8ceda4a69d4c1ba17efc7c2c639d3
In this comment, Ved says that x6/t1 plays an ABI role in passing information between the PLT header and the dynamic linker.