[RISCV] Add tune features of preferred function/loop align

[wangpc]

Summary

D144048 has added preferred function and loop alignment to
RISCVSubtarget, but now we need to set them manually for
different processors.

Tune features that set preferred function/loop align to
[2, 64] bytes (align 1 is not here since the min align is 2)
are added. These features can be used in processor
definitions.

[craig.topper]

256 seems high. The largest I see on AArch64 is 64?

[wangpc]

Change max align to 64.

[asb]

LGTM. Personally I'd just list out 2, 4, 8, 16, 32, 64 in a list in TableGen rather than introducing the defvar - but I'm happy to defer to your preference on that.

[wangpc]

list out all alignments.

llvm/lib/Target/RISCV/RISCVFeatures.td

def FeatureForcedAtomics : SubtargetFeature<
     "Assume that lock-free native-width atomics are available">;
 def HasAtomicLdSt
     : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
 
 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
     "AllowTaggedGlobals",
     "true", "Use an instruction sequence for taking the address of a global "
     "that allows a memory tag in the upper address bits">;
+
+foreach align = [2, 4, 8, 16, 32, 64] in {
+  def TunePrefFunctionAlignment # align :
+      SubtargetFeature<"pref-func-align-" # align, "PrefFunctionAlignment",
+                       "Align(" # align # ")", "Set preferred function alignment to " # align # " bytes">;
+  def TunePrefLoopAlignment # align :
+      SubtargetFeature<"pref-loop-align-" # align, "PrefLoopAlignment",
+                       "Align(" # align # ")", "Set preferred loop alignment to " # align # " bytes">;
+}

llvm/test/CodeGen/RISCV/align-loops.ll

 ; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
 ; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16
 ; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s -check-prefix=ALIGN_32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-16 | FileCheck %s -check-prefix=ALIGN_16
+; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-32 | FileCheck %s -check-prefix=ALIGN_32
 
 declare void @foo()
 
 define void @test(i32 %n, i32 %m) nounwind {
 ; CHECK-LABEL:    test:
 ; CHECK-NOT:        .p2align
 ; CHECK:            ret
 

llvm/test/CodeGen/RISCV/align.ll

 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32C
+; RUN: llc -mtriple=riscv32 -mattr=+pref-func-align-32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=ALIGN-32
 ; RUN: llc -filetype=obj -mtriple=riscv32 < %s -o %t
 ; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-I
 ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+c < %s -o %t
 ; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-C
 
 ; SEC:   Name   Type     Address  Off      Size     ES Flg Lk Inf Al
 ; SEC-I: .text  PROGBITS 00000000 [[#%x,]] [[#%x,]] 00  AX  0   0  4
 ; SEC-C: .text  PROGBITS 00000000 [[#%x,]] [[#%x,]] 00  AX  0   0  2
 
 define void @foo() {
 ;RV32I: .p2align 2
 ;RV32I: foo:
 ;RV32C: .p2align 1
 ;RV32C: foo:
+;ALIGN-32: .p2align 5
+;ALIGN-32: foo:
 entry:
   ret void
 }