[AArch64][SME] Non-streaming compatible SCVTF emitted with --force-streaming-compatible-sve

[dtemirbulatov]

Summary

For scalar integer to float converts currently we emit NEON version of convert instrction for Streaming Compatible SVE, this change fixes the issue,

[benmxwl-arm]

Thanks Dinar! I've checked out this patch and it fixes our issues downstream.

[sdesmalen]

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll

1126

Sorry, just spotted this after accepting the patch. The name v1i16 seems wrong, because it's just converting an i16 -> f16, not <1 x i16> -> f16. I think you can just remove the v1 from the name.

(same comment for all the other tests below).

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
   // Only optimize when the source and destination types have the same width.
   if (VT.getSizeInBits() != N->getOperand(0).getValueSizeInBits())
     return SDValue();
 
   // If the result of an integer load is only used by an integer-to-float
   // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
   // This eliminates an "integer-to-vector-move" UOP and improves throughput.
   SDValue N0 = N->getOperand(0);
-  if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
+  if (Subtarget->isNeonAvailable() && ISD::isNormalLoad(N0.getNode()) &&
+      N0.hasOneUse() &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
                                LN0->getPointerInfo(), LN0->getAlign(),
                                LN0->getMemOperand()->getFlags());
 
     // Make sure successors of the original load stay after it by updating them

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll

 ; CHECK-NEXT:    scvtf z1.d, p0/m, z1.d
 ; CHECK-NEXT:    stp q0, q1, [x1]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %res = sitofp <4 x i64> %op1 to <4 x double>
   store <4 x double> %res, ptr %b
   ret void
 }
+
+define half @scvtf_v1i16_f16(ptr %0) {
+; CHECK-LABEL: scvtf_v1i16_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldrsh w8, [x0]
+; CHECK-NEXT:    scvtf h0, w8
+; CHECK-NEXT:    ret
+  %2 = load i16, ptr %0, align 64
+  %3 = sitofp i16 %2 to half
+  ret half %3
+}
+
+define float @scvtf_v1i16_f32(ptr %0) {
+; CHECK-LABEL: scvtf_v1i16_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldrsh w8, [x0]
+; CHECK-NEXT:    scvtf s0, w8
+; CHECK-NEXT:    ret
+  %2 = load i16, ptr %0, align 64
+  %3 = sitofp i16 %2 to float
+  ret float %3
+}
+
+define double @scvtf_v1i16_f64(ptr %0) {
+; CHECK-LABEL: scvtf_v1i16_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldrsh w8, [x0]
+; CHECK-NEXT:    scvtf d0, w8
+; CHECK-NEXT:    ret
+  %2 = load i16, ptr %0, align 64
+  %3 = sitofp i16 %2 to double
+  ret double %3
+}
+
+define half @scvtf_v1i32_v1f16(ptr %0) {
+; CHECK-LABEL: scvtf_v1i32_v1f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr w8, [x0]
+; CHECK-NEXT:    scvtf h0, w8
+; CHECK-NEXT:    ret
+  %2 = load i32, ptr %0, align 64
+  %3 = sitofp i32 %2 to half
+  ret half %3
+}
+
+define float @scvtf_v1i32_v1f32(ptr %0) {
+; CHECK-LABEL: scvtf_v1i32_v1f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr w8, [x0]
+; CHECK-NEXT:    scvtf s0, w8
+; CHECK-NEXT:    ret
+  %2 = load i32, ptr %0, align 64
+  %3 = sitofp i32 %2 to float
+  ret float %3
+}
+
+define double @scvtf_v1i32_v1f64(ptr %0) {
+; CHECK-LABEL: scvtf_v1i32_v1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr w8, [x0]
+; CHECK-NEXT:    scvtf d0, w8
+; CHECK-NEXT:    ret
+  %2 = load i32, ptr %0, align 64
+  %3 = sitofp i32 %2 to double
+  ret double %3
+}
+
+define half @scvtf_v1i64_v1f16(ptr %0) {
+; CHECK-LABEL: scvtf_v1i64_v1f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    scvtf h0, x8
+; CHECK-NEXT:    ret
+  %2 = load i64, ptr %0, align 64
+  %3 = sitofp i64 %2 to half
+  ret half %3
+}
+
+define float @scvtf_v1i64_v1f32(ptr %0) {
+; CHECK-LABEL: scvtf_v1i64_v1f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    scvtf s0, x8
+; CHECK-NEXT:    ret
+  %2 = load i64, ptr %0, align 64
+  %3 = sitofp i64 %2 to float
+  ret float %3
+}
+
+define double @scvtf_v1i64_v1f64(ptr %0) {
+; CHECK-LABEL: scvtf_v1i64_v1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    scvtf d0, x8
+; CHECK-NEXT:    ret
+  %2 = load i64, ptr %0, align 64
+  %3 = sitofp i64 %2 to double
+  ret double %3
+}
+
+define half @ucvtf_v1i16_f16(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i16_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    ucvtf h0, w8
+; CHECK-NEXT:    ret
+  %2 = load i16, ptr %0, align 64
+  %3 = uitofp i16 %2 to half
+  ret half %3
+}
+
+define float @ucvtf_v1i16_f32(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i16_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr h0, [x0]
+; CHECK-NEXT:    ucvtf s0, s0
+; CHECK-NEXT:    ret
+  %2 = load i16, ptr %0, align 64
+  %3 = uitofp i16 %2 to float
+  ret float %3
+}
+
+define double @ucvtf_v1i16_f64(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i16_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr h0, [x0]
+; CHECK-NEXT:    ucvtf d0, d0
+; CHECK-NEXT:    ret
+  %2 = load i16, ptr %0, align 64
+  %3 = uitofp i16 %2 to double
+  ret double %3
+}
+
+define half @ucvtf_v1i32_v1f16(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i32_v1f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr w8, [x0]
+; CHECK-NEXT:    ucvtf h0, w8
+; CHECK-NEXT:    ret
+  %2 = load i32, ptr %0, align 64
+  %3 = uitofp i32 %2 to half
+  ret half %3
+}
+
+define float @ucvtf_v1i32_v1f32(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i32_v1f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr w8, [x0]
+; CHECK-NEXT:    ucvtf s0, w8
+; CHECK-NEXT:    ret
+  %2 = load i32, ptr %0, align 64
+  %3 = uitofp i32 %2 to float
+  ret float %3
+}
+
+define double @ucvtf_v1i32_v1f64(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i32_v1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr s0, [x0]
+; CHECK-NEXT:    ucvtf d0, d0
+; CHECK-NEXT:    ret
+  %2 = load i32, ptr %0, align 64
+  %3 = uitofp i32 %2 to double
+  ret double %3
+}
+
+define half @ucvtf_v1i64_v1f16(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i64_v1f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    ucvtf h0, x8
+; CHECK-NEXT:    ret
+  %2 = load i64, ptr %0, align 64
+  %3 = uitofp i64 %2 to half
+  ret half %3
+}
+
+define float @ucvtf_v1i64_v1f32(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i64_v1f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    ucvtf s0, x8
+; CHECK-NEXT:    ret
+  %2 = load i64, ptr %0, align 64
+  %3 = uitofp i64 %2 to float
+  ret float %3
+}
+
+define double @ucvtf_v1i64_v1f64(ptr %0) {
+; CHECK-LABEL: ucvtf_v1i64_v1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr x8, [x0]
+; CHECK-NEXT:    ucvtf d0, x8
+; CHECK-NEXT:    ret
+  %2 = load i64, ptr %0, align 64
+  %3 = uitofp i64 %2 to double
+  ret double %3
+}